JP4888125B2 - Solid-state imaging device, imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging device which are an example of a semiconductor device for physical quantity distribution detection. Specifically, for example, a plurality of unit components that are sensitive to electromagnetic waves input from the outside, such as light and radiation, are arranged, and the physical quantity distribution converted into an electric signal by the unit components is converted into an analog electrical signal. The present invention relates to a mechanism for reading out signals and digital data. In particular, the present invention relates to a mechanism having a function of thinning out and outputting pixels when reading an image signal.

  For example, physical quantities formed by arranging multiple unit components (for example, pixels) that are sensitive to changes in physical quantities, such as electromagnetic waves input from outside such as light and radiation, or pressure (contact etc.) Distribution detection semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In recent years, MOS and CMOS type image sensors that can overcome various problems of CCD image sensors have attracted attention as an example of solid-state imaging devices.

  For example, a CMOS image sensor has an amplifying circuit such as a floating diffusion amplifier for each pixel. When reading a pixel signal, one row in the pixel array unit is selected as an example of address control. A so-called column-parallel output type or column type is often used in which row signals are accessed simultaneously and in units of rows, that is, pixel signals are read from the pixel array unit simultaneously in parallel for all pixels in one row. ing.

  In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  Further, in some solid-state imaging devices, an amplifying solid-state imaging device (APS; Active Pixel Sensor) that has a driving transistor for amplification in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplification type solid-state imaging device including a pixel having a configuration (also referred to as / gain cell). For example, many CMOS solid-state imaging devices have such a configuration.

  In such an amplification type solid-state imaging device, in order to read out a pixel signal to the outside, address control is performed on a pixel unit in which a plurality of unit pixels are arranged, and signals from individual unit pixels are assigned to a predetermined address. The data is read out in order or arbitrarily. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons and holes) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  Here, as a trend of recent solid-state imaging devices, pixel miniaturization and high speed are remarkable. One common problem is sensitivity. The former miniaturization relates to a decrease in the amount of incident light per pixel due to a reduction in the light receiving portion. The latter increase in speed is related to a decrease in the amount of incident light due to a decrease in exposure time.

  For the former, for example, a mechanism for reducing the area occupied by the circuit by sharing a part of the circuit held in each pixel cell by a plurality of pixels and securing the area of the photoelectric conversion unit (hereinafter referred to as “the photoelectric conversion unit”). Is called a pixel sharing method).

JP 2006-054276 A

  In Patent Document 1, one voltage conversion unit is arranged between two photoelectric conversion units that are obliquely adjacent to each other in a two-dimensional array (pixel array unit, imaging unit), and the one voltage conversion unit is converted into two photoelectric conversion units. By configuring so that the conversion unit is shared, the generation of invalid regions around the voltage conversion unit is suppressed, thereby ensuring the area of the photoelectric conversion unit relative to the pixel area, and the photoelectric conversion unit A mechanism has been proposed in which the optical pixel centers are two-dimensionally arranged at equal intervals by being arranged at the optical center of each pixel.

  On the other hand, from the viewpoint of a high-speed method for shortening the readout processing time of pixel signals, pixel signals are not read out from all the pixels of the pixel array unit (imaging unit), but a part thereof, for example, in units of rows or columns There is thinning-out reading that reads out only the pixel signal of the first pixel. It is also conceivable to use this thinning-out reading together with the pixel sharing method.

  However, when thinning-out reading is performed in units of rows or columns (hereinafter, representatively in units of rows), driving conditions for the pixels (transistor driving) are determined depending on whether the thinning-out row is not read out or the readout row is not thinned out. Due to the difference in frequency), various problems occur.

  As an example, there is a phenomenon (referred to as blooming phenomenon) in which the thinned out rows are exposed but are not read out, so that the charge generated in the photoelectric conversion unit overflows and affects the read out rows.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a mechanism that can alleviate a blooming phenomenon that may occur during thinning-out reading and maintain good image quality. In particular, even in combination with the pixel sharing structure, a mechanism in which the influence of the countermeasure against the blooming phenomenon does not adversely affect the operation of the readout row in the shared pixel group or the degree of the adverse effect is small while reducing the blooming phenomenon. The purpose is to provide a mechanism.

  An embodiment of a solid-state imaging device according to the present invention includes a detection unit (typically a photodiode such as a photoelectric conversion unit) that detects a change in a physical quantity by charge, and a pixel that converts charge detected by the detection unit into a pixel signal. A signal generation unit (amplification amplifier having a floating diffusion structure is a typical example), a transfer unit (typically a transfer transistor) that transfers charges detected by the detection unit to the pixel signal generation unit based on an input transfer control potential, and A configuration in which a part of unit pixels having an initialization unit (typically a reset transistor) that initializes the potential of the pixel signal generation unit based on an input initialization control potential is shared by a plurality of unit pixels Read pixel signals of a pixel array unit in which unit pixel groups having a matrix are arranged and a part of unit pixel of the pixel array unit, for example, in units of rows or columns. It was assumed and a drive control unit for controlling the unit pixels in to thinning readout mode.

  Here, in the thinning readout mode, the drive control unit overflows with the detection unit of the thinned unit pixels in consideration of the pixel sharing structure, that is, depending on whether the thinning row is shared with the readout operation row. The blooming countermeasure potential, which is a transfer control potential supplied to the transfer unit of the thinned unit pixel, is controlled so that the charge is easily transferred to the pixel signal generation unit side of the thinned unit pixel. To do.

  By controlling such a blooming countermeasure potential for the transfer unit of the unit pixel to be thinned out, the potential barrier below the transfer electrode of the transfer unit is lowered as compared with the case of supplying a normal inactive level. As a result, unnecessary charges overflowing in the detection unit including the photodiode are easily discharged to the pixel signal generation unit side.

  Here, as a feature of the embodiment of the solid-state imaging device according to the present invention, the supply of the blooming countermeasure potential to the transfer unit of the thinning row is performed depending on whether the thinning row is shared with the reading operation row. Control. Specifically, when the unit pixel to be thinned has a pixel sharing relationship with the unit pixel for the readout operation, the supply of the blooming countermeasure potential is stopped to the transfer unit of the thinned unit pixel, and the inactive side (For example, it may be equal to the potential defining the inactive state).

  In actual operation, the unit pixels to be read are sequentially switched, and accordingly, the supply of the blooming countermeasure potential and the supply of the more inactive potential are switched.

  The invention described in the dependent claims defines further advantageous specific examples of one embodiment of the display device according to the present invention.

  For example, the anti-blooming potential may be a potential on the active level side rather than the inactive level, but from the viewpoint of reliability and dark current, an excessive potential on the active level side is not preferable. . Therefore, in practice, an appropriate potential (intermediate potential) between the inactive level and the active level is preferable.

  Here, as a countermeasure against blooming supplied to the transfer unit of the unit pixel to be thinned out, if a potential corresponding to the intermediate potential has already been used for another purpose, it is preferable to use it. A dedicated anti-blooming potential may be provided between the active level and the inactive level. However, in this case, it is necessary to deal with a circuit that generates the anti-blooming potential. There is an advantage that the circuit configuration can be made compact by using the intermediate potential for the purpose itself as a potential for preventing blooming.

  Here, “for other purposes” means that the transfer control potential for driving the transfer unit itself may be used for other than the countermeasure against blooming, or the initialization control potential for driving the initialization unit. It may be a control potential for driving other unit pixels, and in an extreme case, it is not limited to a control potential for driving unit pixels, but controls other elements constituting the solid-state imaging device. It may be a control potential.

  Alternatively, the blooming countermeasure potential supplied to the transfer unit of the thinned unit pixel may be in a floating state that actually does not have a potential. In this specification, the “blooming countermeasure potential” means not only a potential having a certain magnitude that can suppress a blooming phenomenon but also a floating state that does not have a magnitude as a potential.

  In addition, if unnecessary charge overflowing in the detection unit is discharged to the pixel signal generation unit by controlling the blooming countermeasure potential for the transfer unit of the unit pixel to be thinned out, the processing of the discharged charge is also considered. Should.

  As a first example of the countermeasure, it is preferable that the initialization unit includes a depletion structure transistor. By adopting the depletion structure, even if the control voltage is kept inactive, the leakage current operation is used to automatically discharge unnecessary charges transferred from the detection unit of the initialization unit to the power supply side. can do.

  If the first example is not adopted, the initialization unit of the unit pixel to be thinned out may be controlled to discharge the charge transferred to the pixel signal generation unit by supplying the blooming countermeasure potential to the transfer unit. Good. This operation does not require the interlocking process with the read operation row as in the shutter operation in the normal read operation, and may be performed at an appropriate timing that does not affect the control of the shutter operation row and the read operation row.

  Note that the solid-state imaging device may have a form formed as a single chip, or a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. Also good.

  Further, the present invention can be applied not only to a solid-state imaging device but also to an imaging device. In this case, the same effect as the solid-state imaging device can be obtained as the imaging device. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

  According to one embodiment of the present invention, the transfer control potential supplied to the transfer unit for the unit pixel to be thinned out in the thinning-out reading mode is in a state in which charges overflowing in the detection unit are easily transferred to the pixel signal generation unit side. Set to the blooming countermeasure potential. As a result, unnecessary charges overflowing in the detection unit are easily discharged to the pixel signal generation unit, so that the blooming phenomenon in which the charge generated in the thinned unit pixels overflows and leaks to the adjacent unit pixel of the reading operation. Can be suppressed.

  At this time, considering that the pixel array unit is configured by a unit pixel group having a pixel sharing structure, when the unit pixel to be thinned has a pixel sharing relationship with the unit pixel of the reading operation, the unit pixel to be thinned out Since the supply of the anti-blooming potential is stopped and the potential on the inactive side is supplied to the transfer unit, the signal from the detection unit of the thinned unit pixel to the pixel signal generation unit of the unit pixel of the read operation It is possible to prevent signal level fluctuations due to leakage.

  Even in combination with the pixel sharing structure, while reducing the blooming phenomenon, a mechanism in which the influence of the countermeasure against the blooming phenomenon does not adversely affect the operation of the readout row in the shared pixel group, or a mechanism with a small degree of the adverse effect. realizable.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS solid-state imaging device will be described on the assumption that all pixels are made of NMOS.

  In particular, in the solid-state imaging device according to the present embodiment, a unit pixel group having a pixel sharing structure having a configuration in which some of the unit pixels are shared by a plurality of unit pixels is used as a unit component constituting the pixel array unit. It is characterized in that it is provided.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. Forms are applicable as well.

<Overview of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) which is an embodiment of a solid-state imaging device according to the present invention.

  The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix). The signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit, a digital conversion unit (ADC), etc. are provided in parallel in a column. It is.

  “A CDS processing function unit and a digital conversion unit are provided in parallel in a column” means that a plurality of CDS processing function units substantially parallel to a vertical signal line (an example of a column signal line) 19 in a vertical column This means that a digital conversion unit is provided.

  Each of the plurality of functional units is arranged only on one end side in the column direction with respect to the pixel array unit 10 (output side arranged on the lower side of the drawing) when the device is viewed in plan view. Or one end side in the column direction (output side arranged on the lower side of the figure) and the other end side opposite to the pixel array unit 10 (upper side in the figure). ) May be arranged separately. In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and a digital conversion unit are provided in parallel in a column, a CDS processing function unit and other analog signal processing units, A digital conversion unit is provided for each vertical column, and the vertical column, a CDS processing function unit, a digital conversion unit, and the like that are sequentially read out to the output side are connected in a one-to-one relationship. In addition to the column type (column parallel type), one CDS processing function unit or digital conversion unit is allocated to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns), N A mode in which one CDS processing function unit or digital conversion unit is allocated to N vertical signal lines 19 (vertical columns) every other number (N is a positive integer; N−1 are arranged therebetween). It can also be taken.

  Except for the column type, in any form, since a plurality of vertical signal lines 19 (vertical columns) commonly use one CDS processing function unit and digital conversion unit, they are supplied from the pixel array unit 10 side. A switching circuit (switch) that supplies pixel signals for a plurality of columns to one CDS processing function unit or digital conversion unit is provided. Depending on the subsequent processing, a separate measure such as providing a memory for holding the output signal is required.

  In any case, the signal processing of each pixel signal is read out in units of pixel columns by adopting a form in which one CDS processing function unit or digital conversion unit is assigned to a plurality of vertical signal lines 19 (vertical columns). By performing the processing later, the configuration in each unit pixel can be simplified and the number of pixels of the image sensor can be reduced, the size can be reduced, and the cost can be reduced as compared with the case where the same signal processing is performed in each unit pixel.

  In addition, since a plurality of signal processing units arranged in parallel in a column can simultaneously process pixel signals for one row, one CDS processing function unit or digital conversion unit is provided on the output circuit side or outside the device. Therefore, the signal processing unit can be operated at a low speed as compared with the case where processing is performed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like. In other words, when the power consumption and bandwidth performance are the same, the entire sensor can be operated at high speed.

  In the case of a column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like, and has an advantage that a switching circuit (switch) is unnecessary. In the following embodiments, this column type will be described unless otherwise specified.

  As shown in FIG. 1, in the solid-state imaging device 1 of the present embodiment, a unit pixel group 2 having a pixel sharing structure having a configuration in which some of the unit pixels 3 are shared by a plurality of unit pixels 3 includes rows and A pixel array unit 10, which is also referred to as a pixel unit or an imaging unit arranged in a column, a drive control unit 7 provided outside the pixel array unit 10, and a pixel signal reading unit pixel 3 in the pixel array unit 10 Read current source section 24 for supplying the operating current (read current), a column processing section 26 having a column AD circuit 25 arranged for each vertical column, and supplying a reference signal Vslop for AD conversion to the column processing section 26 The reference signal generation unit 27 and the output circuit 28 are provided. Each of these functional units is provided on the same semiconductor substrate.

  The reference signal Vslop may be any signal as long as it has a linearly changing waveform with a certain slope as a whole. The reference signal Vslop may have a smooth slope shape, or may change in a stepwise manner. You may do.

  The column AD circuit 25 of the present embodiment includes an AD conversion unit that independently converts the reset level Srst and the signal level Ssig, which are reference levels of the pixel signal So, into digital data, an AD conversion result of the reset level Srst, and a signal level Ssig. By executing a difference process between the AD conversion results of the first and second AD conversion results, a function of a difference processing unit for acquiring digital data of a signal component indicated by the difference between the reset level Srst and the signal level Ssig is provided.

  In addition, an AGC (Auto Gain Control) circuit having a signal amplification function or the like can be provided in the same semiconductor region as the column processing unit 26 as needed before or after the column processing unit 26. When AGC is performed before the column processing unit 26, analog amplification is performed. When AGC is performed after the column processing unit 26, digital amplification is performed. If the n-bit digital data is simply amplified, the gradation may be lost. Therefore, it is preferable to perform digital conversion after amplification by analog.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel array unit 10. For example, the drive control unit 7 includes a horizontal scanning circuit (column scanning circuit) 12 having a horizontal decoder 12a and a horizontal driving unit 12b for controlling column addresses and column scanning, a vertical decoder 14a and a vertical decoder for controlling row addresses and row scanning. A vertical scanning circuit (row scanning circuit) 14 having a driving unit 14b and a communication / timing control unit 20 having a function of generating an internal clock are provided.

  Although illustration is omitted, a clock conversion unit that is an example of a high-speed clock generation unit and generates a pulse having a clock frequency faster than the input clock frequency may be provided. The communication / timing control unit 20 generates an internal clock based on the input clock (master clock) CLK0 input via the terminal 5a and the high-speed clock generated by the clock conversion unit.

  By using a signal derived from the high-speed clock generated by the clock converter, AD conversion processing and the like can be operated at high speed. Also, motion extraction and compression processing requiring high-speed calculation can be performed using a high-speed clock. Also, the parallel data output from the column processing unit 26 can be converted into serial data and the video data D1 can be output outside the device. By doing so, it is possible to adopt a configuration in which high-speed operation output is performed with a smaller number of terminals than the number of bits of AD-converted digital data.

  In FIG. 1, for the sake of simplicity, some of the rows and columns are omitted, but in reality, each row or column has several tens to thousands of unit pixels 3 (in fact, unit pixel group 2 ) Is arranged. The unit pixel 3 is typically composed of a photodiode as a light receiving element (charge generation unit) which is an example of a detection unit, and an in-pixel amplifier having an amplification semiconductor element (for example, a transistor).

  The intra-pixel amplifier is not limited as long as it can output the signal charge generated and accumulated in the charge generation unit of the unit pixel 3 as an electric signal, and various configurations can be adopted. A floating diffusion amplifier configuration is used. As an example, a transfer unit having a read selection transistor as an example of a charge readout unit (transfer gate unit / read gate unit) and an initialization unit having a reset transistor as an example of a reset gate unit with respect to the charge generation unit , A vertical selection transistor, and a transistor for amplifying a source follower which is an example of a detection element for detecting a potential change of a floating diffusion (also referred to as a floating node). A configuration can be used (see, eg, FIG. 2A below).

  Alternatively, an amplifying transistor connected to the drain line (DRN) for amplifying a signal voltage corresponding to the signal charge generated by the charge generating unit, a reset transistor for resetting the charge generating unit, and a vertical shift It is also possible to use a transistor composed of three transistors having a read selection transistor (transfer gate portion) scanned from a register via a transfer wiring (TRF).

  Note that the solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter. That is, color separation comprising a combination of a plurality of color filters for capturing a color image on a light receiving surface on which electromagnetic waves (light in this example) of each charge generation unit (photodiode, etc.) in the pixel array unit 10 are incident. Any color filter of the filter is provided in, for example, a so-called Bayer array, so that color image capturing is supported.

  The unit pixel 3 includes a vertical scanning unit 14 via a row control line 15 for row selection, a column processing unit 26 in which a column AD circuit 25 is provided for each vertical column via a vertical signal line 19, Each is connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The horizontal scanning circuit 12 has a function of a reading scanning unit that reads a count value from the column processing unit 26 to the horizontal signal line 18.

  Each element of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning circuit 14 is integrally formed with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. And configured as a solid-state imaging device which is an example of a semiconductor system.

  Each of these functional units is a so-called one-chip unit (provided on the same semiconductor substrate) integrally formed in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. As a CMOS image sensor which is an example of a semiconductor system, the solid-state imaging device 1 of the present embodiment is configured to be a part.

  Note that the solid-state imaging device 1 may be configured as one chip in which each unit is integrally formed in the semiconductor region as described above. Although not illustrated, the pixel array unit 10 and the drive control unit are omitted. 7. In addition to various signal processing units such as the column processing unit 26, an imaging function in which these are collectively packaged in a state including an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter It is good also as a modular form which has.

  The horizontal scanning unit 12 and the vertical scanning unit 14 include, for example, a decoder, and start a shift operation (scanning) in response to control signals CN1 and CN2 supplied from the communication / timing control unit 20. . For this reason, for example, the row control line 15 includes various pulse signals for driving the unit pixel 3 (for example, a pixel reset pulse RST that defines an initialization control potential, a transfer pulse TRG that defines a transfer control potential, a vertical selection) Pulse VSEL, etc.).

  Although not shown, the communication / timing control unit 20 is externally connected via a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal required for the operation of each unit and a pulse signal of a predetermined timing, and a terminal 5a. Receives the master clock CLK0 supplied from the main control unit, receives data instructing the operation mode supplied from the external main control unit via the terminal 5b, and further includes data including information of the solid-state imaging device 1. And a functional block of a communication interface that outputs to an external main control unit.

  The communication / timing controller 20 outputs, for example, a horizontal address signal to the horizontal decoder 12a and a vertical address signal to the vertical decoder 14a, and each decoder 12a, 14a receives it and selects a corresponding row or column. .

  At this time, since the unit pixel group 2 (in effect, the unit pixel 3) is arranged in a two-dimensional matrix, an analog signal generated by the pixel signal generation unit 5 and output in the column direction via the vertical signal line 19 is used. The pixel signal is accessed in row units (in column parallel) and read (vertical) scan reading is performed, and then the pixel signal (in this example, digitized pixel data) is accessed in the row direction, which is the arrangement direction of the vertical columns. It is preferable to speed up reading of pixel signals and pixel data by performing (horizontal) scan reading for reading out to the output side. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  In the communication / timing control unit 20, the clock CLK1 having the same frequency as the input clock (master clock) CLK0 input via the terminal 5a, a clock obtained by dividing the clock CLK1, or a low-speed clock obtained by further dividing the device are used as devices. For example, a horizontal scanning unit 12, a vertical scanning unit 14, a column processing unit 26, and the like. Hereinafter, the clocks divided by two and the clocks with lower frequencies are collectively referred to as a low-speed clock CLK2.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. For example, a vertical decoder 14a that defines a readout row in the vertical direction (selects a row of the pixel array unit 10), and a row control line 15 for the unit pixel 3 on the readout address (in the row direction) defined by the vertical decoder 14a. And a vertical drive unit 14b for driving by supplying pulses. Note that the vertical decoder 14a selects a row for electronic shutter, in addition to a row from which a signal is read.

  Here, like the CMOS type solid-state imaging device 1 of the present embodiment, the XY address type imaging device adopts an accumulation sequential readout method in which reading is performed every accumulation frame time of each surface element, and here it is driven in units of rows. Since the pulse is supplied, the light incident on the photoelectric conversion element during the same period is accumulated as signal charge, and read simultaneously from all the pixels to the vertical CCD, thereby satisfying the simultaneous accumulation. The exposure type is very different from the CCD type, which is line exposure (also called rolling shutter or focal plane accumulation).

  As this rolling shutter type electronic shutter operation, a certain readout row is set as a shutter operation row (shutter operation row) and a reset process is performed on the photoelectric conversion element (detecting unit) constituting the unit pixel 3. The exposure time is the time from when the readout row is set to the readout operation row (readout operation row) until the signal charge is actually read out to the vertical signal line 19 side.

  The horizontal scanning unit 12 sequentially selects the column AD circuit 25 of the column processing unit 26 in synchronization with the low-speed clock CLK2, and guides the signal to a horizontal signal line (horizontal output line) 18. For example, a horizontal decoder 12a that defines a horizontal readout column (selects each column AD circuit 25 in the column processor 26), and each of the column processors 26 according to a read address defined by the horizontal decoder 12a. A horizontal drive unit 12b for guiding a signal to the horizontal signal line 18. For example, if the number of horizontal signal lines 18 is n (n is a positive integer) handled by the column AD circuit 25, for example, 10 (= n) bits, 10 horizontal signal lines 18 are arranged corresponding to the number of bits. .

  In the solid-state imaging device 1 having such a configuration, the pixel signal output from the unit pixel 3 is supplied to the column AD circuit 25 of the column processing unit 26 via the vertical signal line 19 for each vertical column.

  Each column AD circuit 25 of the column processing unit 26 receives the analog signal So of the unit pixel 3 in the corresponding column and processes the analog signal So. For example, each column AD circuit 25 has an ADC (Analog Digital Converter) circuit that converts an analog signal So into, for example, a 10-bit digital signal using a low-speed clock CLK2.

  As the AD conversion processing in the column processing unit 26, a method is adopted in which analog signals So held in parallel in units of rows are AD converted in parallel for each row using the column AD circuit 25 provided for each column. . At this time, a single slope integration type (or ramp signal comparison type) AD conversion technique is used. Since this method can realize an AD converter with a simple configuration, it has a feature that the circuit scale does not increase even if it is provided in parallel.

  In the single slope integration type AD conversion, the analog processing target signal is converted into a digital signal based on the time from the start of conversion until the reference signal Vslop matches the processing target signal voltage. As a mechanism for this, in principle, a ramp-like reference signal Vslop is supplied to a comparator (voltage comparator), and counting (counting) with a clock signal is started and input via a vertical signal line 19. AD conversion is performed by counting the number of clocks until a pulse signal indicating the comparison result is obtained by comparing the analog pixel signal thus obtained with the reference signal Vslop.

  At this time, by devising the circuit configuration, the signal level immediately after the pixel reset (referred to as noise level or reset level) is applied to the voltage mode pixel signal input through the vertical signal line 19 together with AD conversion. ) And a true signal level Vsig (according to the amount of received light) (equivalent to a so-called CDS process) can be performed. As a result, noise signal components called fixed pattern noise (FPN) and reset noise can be removed.

<Details of reference signal generator and column AD circuit>
The reference signal generation unit 27 includes a DA converter circuit (DAC: Digital Analog Converter) 27a, and is synchronized with the count clock CKdac from the initial value indicated by the control data CN4 from the communication / timing control unit 20. Then, a stepped sawtooth wave (ramp waveform; hereinafter also referred to as a reference signal Vslop) is generated, and the generated stepped sawtooth wave reference signal Vslop is sent to each column AD circuit 25 of the column processing unit 26. Is supplied as a reference voltage (ADC standard signal) for AD conversion. Although illustration is omitted, a filter for preventing noise may be provided.

  The reference signal Vslop is faster than the reference signal Vslop generated based on the master clock CLK0 input via the terminal 5a, for example, based on a high-speed clock generated based on the multiplied clock generated by the multiplier circuit. Can be changed.

  The control data CN4 supplied from the communication / timing control unit 20 to the DA conversion circuit 27a of the reference signal generation unit 27 is time-dependent so that the reference signal Vslop for each comparison process basically has the same slope (change rate). It also includes information that makes the rate of change of digital data the same. Specifically, in synchronization with the count clock CKdac, the count value is changed by one per unit time, and the count value is converted into a voltage signal by a current addition type DA converter circuit.

  The column AD circuit 25 includes a reference signal Vslop generated by the DA conversion circuit 27a of the reference signal generation unit 27 and a row control line 15 (V1, V2, V3,..., Vv for the unit pixel group 2; A voltage comparison unit (comparator) 252 for comparing analog pixel signals obtained from the unit pixel 3 via the vertical signal lines 19 (H1, H2,..., Hh) for each pixel 3 row control line), and a voltage comparison unit 252 is configured to include a counter unit 254 that counts the time until the comparison processing is completed and holds the result, and has an n-bit AD conversion function.

  Here, in the present embodiment, the reference signal Vslop is commonly supplied from the DA conversion circuit 27a to the voltage comparison units 252 arranged for each column, and the pixel signal voltage Vx for which each voltage comparison unit 252 takes charge of processing is shared. The comparison processing is performed using the reference signal Vslop.

  The communication / timing control unit 20 functions as a control unit that switches the count processing mode in the counter unit 254 according to which of the reset level Vrst and the signal component Vsig of the pixel signal the voltage comparison unit 252 is performing comparison processing. have. Control for instructing the counter unit 254 of each column AD circuit 25 from the communication / timing control unit 20 whether the counter unit 254 operates in the down-count mode or the up-count mode, and other control information. The signal CN5 is input.

  One input terminal RAMP of the voltage comparison unit 252 receives the step-like reference signal Vslop generated by the reference signal generation unit 27 in common with the input terminal RAMP of the other voltage comparison unit 252, and inputs to the other input terminal. Are connected to the vertical signal lines 19 in the corresponding vertical columns, and the pixel signal voltages from the pixel array unit 10 are individually input thereto. The output signal of the voltage comparison unit 252 is supplied to the counter unit 254.

  The count clock CK0 from the communication / timing control unit 20 is input to the clock terminal CK of the counter unit 254 in common with the clock terminals CK of the other counter units 254.

  The counter unit 254 is omitted from the illustration of the configuration, but can be realized by changing the wiring form of the data storage unit constituted by the latch to the synchronous counter form, and can be realized by inputting one count clock CK0. Counting is to be performed. Similarly to the reference signal Vslop, the count clock CK0 can use a multiplied clock (high-speed clock) generated by a multiplier circuit. In this case, the count clock CK0 can be used more than using the master clock CLK0 input via the terminal 5a. High resolution can be achieved.

  Regardless of the count mode, the counter unit 254 uses a common up / down counter (U / D CNT) to perform a count process by switching between a down count operation and an up count operation (specifically, alternately). It is characterized in that it can be configured.

  Further, as the counter unit 254 of the present embodiment, it is preferable to use an asynchronous counter whose count output value is output without being synchronized with the count clock CK0. Basically, a synchronous counter can be used, but in the case of a synchronous counter, the operations of all flip-flops (counter basic elements) are limited by the count clock CK0. Therefore, when higher frequency operation is required, the counter unit 254 uses an asynchronous counter suitable for high speed operation because its operation limit frequency is determined only by the limit frequency of the first flip-flop (counter basic element). Is more preferable.

  A control pulse is input to the counter unit 254 from the horizontal scanning circuit 12 through the control line 12c. The counter unit 254 has a latch function for holding the count result, and holds the counter output value until an instruction by a control pulse through the control line 12c is given.

  On the output side of each column AD circuit 25, for example, the output of the counter unit 254 can be connected to the horizontal signal line 18. Alternatively, as shown in the figure, a data storage unit 256 as an n-bit memory device that holds the count result held by the counter unit 254, and the counter unit 254 and the data storage unit 256 are arranged at the subsequent stage of the counter unit 254. It is also possible to adopt a configuration comprising a switch 258 arranged in

  When the configuration including the data storage unit 256 is adopted, the switch 258 receives a memory transfer instruction pulse CN8 as a control pulse from the communication / timing control unit 20 at a predetermined timing in common with the switches 258 in the other vertical columns. Supplied. When the memory transfer instruction pulse CN8 is supplied, the switch 258 transfers the count value of the corresponding counter unit 254 to the data storage unit 256. The data storage unit 256 holds and stores the transferred count value.

  Note that the mechanism for holding the count value of the counter unit 254 in the data storage unit 256 at a predetermined timing is not limited to the configuration in which the switch 258 is disposed between them, and for example, the counter unit 254 and the data storage unit 256 are directly connected. While being connected, the output enable of the counter unit 254 can be realized by controlling the memory transfer instruction pulse CN8, or the memory transfer instruction pulse CN8 is used as a latch clock for determining the data take-in timing of the data storage unit 256. But it can be realized.

  A control pulse is input to the data storage unit 256 from the horizontal scanning circuit 12 through the control line 12c. The data storage unit 256 holds the count value fetched from the counter unit 254 until there is an instruction by a control pulse through the control line 12c.

  The horizontal scanning circuit 12 reads the count value held by each data storage unit 256 in parallel with the voltage comparison unit 252 and the counter unit 254 of the column processing unit 26 performing the processing that they are responsible for. It has the function of a readout scanning unit.

  The output of the data storage unit 256 is connected to the horizontal signal line 18. The horizontal signal line 18 has a signal line of an n-bit width which is the bit width of the column AD circuit 25, and is connected to the output circuit 28 via n sense circuits corresponding to the respective output lines (not shown). The

  In particular, if the configuration includes the data storage unit 256, the count result held by the counter unit 254 can be transferred to the data storage unit 256. Therefore, the count operation of the counter unit 254, that is, AD conversion processing, and the count result The reading operation to the horizontal signal line 18 can be controlled independently, and a pipeline operation in which AD conversion processing and signal reading operation to the outside are performed in parallel can be realized.

  In such a configuration, the column AD circuit 25 performs a count operation in the pixel signal readout period corresponding to the horizontal blanking period, and outputs a count result at a predetermined timing. That is, first, the voltage comparison unit 252 compares the ramp waveform voltage from the reference signal generation unit 27 with the pixel signal voltage input via the vertical signal line 19, and if both voltages are the same, the voltage comparison The comparator output of the unit 252 is inverted. For example, the voltage comparison unit 252 sets the H level such as the power supply potential to the inactive state, and transitions to the L level (active state) when the pixel signal voltage Vx matches the reference signal Vslop.

  The counter unit 254 starts the count operation in the down-count mode or the up-count mode in synchronization with the ramp waveform voltage generated from the reference signal generation unit 27, and the counter unit 254 is notified of the inverted information of the comparator output. Then, the count operation is stopped, and the AD conversion is completed by latching (holding / storing) the count value at that time as pixel data.

  Thereafter, the counter unit 254 sequentially stores the stored and held pixel data based on the shift operation by the horizontal selection signal CH (i) input from the horizontal scanning circuit 12 via the control line 12c at a predetermined timing. The data is output from the output terminal 5 c to the outside of the column processing unit 26 or the outside of the chip having the pixel array unit 10.

  Although not specifically illustrated because it is not directly related to the description of the present embodiment, other various signal processing circuits may be included in the components of the solid-state imaging device 1.

<Circuit configuration example of unit pixel group>
2 and 2A are diagrams illustrating a configuration example of the unit pixel group 2 used in the solid-state imaging device 1 illustrated in FIG. FIG. 2 is a diagram illustrating an arrangement layout example of each constituent element constituting the unit pixel group 2. FIG. 2A is a diagram illustrating a circuit configuration example of the unit pixel group 2 and a connection mode of a drive unit, a drive control line, and a pixel transistor. The configuration of the unit pixel group 2 in the pixel array unit 10 is characterized in that it has a pixel sharing structure having a configuration in which some elements in the unit pixel 3 are shared by the plurality of unit pixels 3.

  Here, as an example of the pixel sharing structure, a case where the unit pixel group 2 is configured by combining four unit pixels 3 is shown. In addition, the structure of the unit pixel 3 and the unit pixel group 2 which combined it is an example, and is not limited to what is shown here. For example, in the configuration illustrated in FIG. 2A, one unit pixel group 2 is configured by four unit pixels 3. However, the present invention is not limited to this. For example, one unit pixel group 2 is configured by two or eight unit pixels 3. It may be configured.

  Note that the configuration of the unit pixel (pixel cell) 3 constituting the unit pixel group 2 in the pixel array unit 10 is the same as that of a normal CMOS image sensor. In this embodiment, the CMOS sensor has a general-purpose 4TR configuration. Or a 3TR structure including three transistors can be used. Of course, these pixel configurations are merely examples, and any CMOS image sensor array configuration can be used.

  Further, as the intra-pixel amplifier, for example, a floating diffusion amplifier configuration is used. As an example, with respect to the charge generation unit, a read selection transistor that is an example of a charge readout unit (transfer gate unit / read gate unit), a reset transistor that is an example of a reset gate unit, a vertical selection transistor, and a floating diffusion As a CMOS sensor having a source follower configuration amplifying transistor, which is an example of a sensing element for detecting a change in potential, a sensor composed of four general-purpose transistors (hereinafter also referred to as a 4TR configuration) can be used.

  In terms of layout, when a unit pixel 3 having a 4TR configuration is basically used, as shown in FIG. 2, the photoelectric conversion function for receiving light and converting it into a charge is combined with each function of a charge storage function for storing the charge. The charge generation unit 32, a voltage conversion unit that converts a signal charge generated by photoelectric conversion in the charge generation unit 32 into a voltage signal, and a charge readout that controls reading of charges from the charge generation unit 32 to the voltage conversion unit There is a group of circuits for processing a read selection transistor (transfer transistor) 34 which is an example of a unit (transfer gate unit / read gate unit) and a charge signal transferred to the voltage conversion unit and a voltage signal converted by the voltage conversion unit. Wiring is provided for electrically connecting the transistor region to be arranged, and the voltage converter and a circuit group in the transistor region.

  As shown in FIG. 2A, the voltage converter includes, for example, a floating diffusion 38 that is a diffusion layer having a parasitic capacitance, and an amplification transistor 42 having a source follower configuration that is an example of a detection element that detects a potential change of the floating diffusion 38. It has as a main part. It is generally known that the smaller the parasitic capacitance of the floating diffusion 38, the higher the conversion efficiency.

  Such a unit pixel group 2 has a great feature in the layout of each component. Specifically, as shown in FIG. 2A, the charge generators 32 arranged in a two-dimensional array composed of a plurality of columns and a plurality of rows are diagonally adjacent to each other in the two-dimensional array. One voltage conversion unit is arranged between two charge generation units 32, and two charge generation units 32 are connected to one voltage conversion unit or transistor region via a read selection transistor 34 attached to each charge generation unit 32. It is configured to be shared.

  For example, as shown in FIG. 2B, sharing is performed in a two-dimensional array consisting of i, i + 1, i + 2,... And columns, j, j + 1, j + 2,. 32a and the (i, j + 1) coordinate charge generation unit 32b share a voltage conversion unit composed of one floating diffusion 38 and an amplification transistor 42, respectively, and the (i + 1, j + 2) coordinate charge generation unit 32c The charge generation unit 32d having the (i, j + 3) coordinate shares a voltage conversion unit formed of another floating diffusion 38 and an amplifying transistor 42, respectively.

  In addition, as shown in FIG. 2, a transistor region is provided between the charge generation units 32 where no voltage conversion unit is arranged. The circuit group in the transistor region is connected via the circuit group and the wiring. Thus, the two charge generation units 32 that are electrically connected to each other are shared. At this time, as shown in FIG. 2A, the shared circuit group includes a reset transistor 36, which is an example of a reset gate unit, a vertical selection transistor 40, and the like. Each of these circuit elements includes a plurality of transistor regions. It is assumed that they are arranged in a distributed manner.

  That is, in the solid-state imaging device 1 of this embodiment, as shown in FIG. 2, a set of circuit groups distributed in two transistor regions arranged along the column direction of the two-dimensional array is arranged along the column direction. The two voltage converters arranged side by side are shared, and each of the voltage converters is shared by two charge generation units 32 that are obliquely adjacent in the two-dimensional array, and these one circuit group, two voltage converters, and a total The four charge generation units 32 constitute a unit pixel group 2 that is one shared unit (unit block).

  In terms of circuit configuration, as shown in FIG. 2A, the unit pixel group 2 includes four charge generation units 32a, 32b, 32c, and 32d, and one pixel signal including a floating diffusion 38 and an amplification transistor 42. The generation unit 5 is shared. It is assumed that the pixels to be shared are adjacent to each other, and the adjacent direction is the vertical direction or the horizontal direction of the screen, or both (ie, diagonal) when the unit pixels 3 are arranged in a square lattice pattern. Either may be sufficient. In the present embodiment, it is assumed that one unit pixel group 2 is configured by sharing four unit pixels 3 in the row direction (vertical direction).

  Since one unit pixel group 2 is constituted by four unit pixels 3 so that the charge-voltage conversion unit (specifically, the pixel signal generation unit 5) of the FDA configuration is shared among the four pixels, readout selection is performed. The read transistor 34 and the transfer drive buffer BF1 are provided so that the transistor 34 functions as a means for transferring the signal charges accumulated in a plurality of (four in this example) charge generators 32 to the common pixel signal generator 5. Also, read selection transistors 34a, 34b, 34c, 34d and transfer drive buffers BF1a, BF1b, BF1c, BF1d are provided independently, and signal charges Qa, Qb are respectively supplied from the charge generation units 32a, 32b, 34c, 34d. , Qc, Qd are transferred (transferred) to the floating diffusion 38 independently.

  The charge generation unit 32a, the read selection transistor 34a, and the pixel signal generation unit 5 form a first unit pixel 3a, and the charge generation unit 32b, the read selection transistor 34b, and the pixel signal generation unit 5 form a second unit. The pixel 3b is configured, and the charge generation unit 32c, the readout selection transistor 34c, and the pixel signal generation unit 5 configure a third unit pixel 3c. The charge generation unit 32d, the readout selection transistor 34d, and the pixel signal generation unit 5 It can be seen that the fourth unit pixel 3d is configured.

  That is, in such a configuration, the unit pixel group 2 is composed of seven transistors as a whole, but when viewed from the respective charge generation units 32a, 32b, 34c, and 34d, four transistors are used. This is a 4TR configuration in which the unit pixel 3 is configured.

  In the case of color imaging, the unit pixel 3 to be shared is configured to share the charge-voltage conversion unit (pixel signal generation unit 5) having an FDA configuration not only with the same color pixel but also with a plurality of colors. Alternatively, the charge-voltage conversion unit (pixel signal generation unit 5) having the FDA configuration may be shared only by pixels of the same color.

<Circuit configuration example of unit pixel>
The read selection transistor 34 constituting the transfer section is driven via a transfer wiring (read selection line TX) 55 by a transfer drive buffer BF1 to which a transfer signal φTRG is supplied. The reset transistor 36 constituting the initialization unit is driven through a reset wiring (RST) 56 by a reset driving buffer BF2 to which a reset signal φRST is supplied. The vertical selection transistor 40 is driven via a vertical selection line (SEL) 52 by a selection drive buffer BF3 to which a vertical selection signal φVSEL is supplied. Each drive buffer can be driven by the vertical drive unit 14 b of the vertical scanning unit 14.

  The charge generation unit 32, which is an example of a detection unit including a light receiving element DET such as a photodiode PD, has a reference potential Vss (negative potential: about −1V, for example) at which one end (anode side) of the light receiving element DET is a low potential side. The other end (cathode side) is connected to the input end (typically the source) of the read selection transistor 34. The reference potential Vss may be the ground potential GND.

  The read selection transistor 34 has an output terminal (typically a drain) connected to a connection node to which a reset transistor 36, a floating diffusion 38 and an amplification transistor 42 are connected, and a control input terminal (gate) having a transfer drive. A transfer pulse TRG is supplied from the buffer BF1.

  The reset transistor 36 in the pixel signal generator 5 has a source connected to the floating diffusion 38, a drain connected to the power supply Vrd (usually common to the power supply Vdd), and a gate (reset gate RG) receiving a pixel reset pulse RST. Input from reset drive buffer.

  Although details will be described later, in the present embodiment, it is preferable to use a depletion structure as the reset transistor 36. This is because when the reset transistor 36 is turned on, the reset voltage Vrd serving as the power source of the unit pixel 3 and the potential of the floating diffusion 38 are made to coincide with each other without any variation, and the afterimage is eliminated by surely resetting. If the reset power supply Vrd and the power supply Vdd for the amplifying transistor 42 are made common, the potential of the floating diffusion 38 when the reset transistor 36 is on generally matches the potential level of each power supply line (in consideration of the threshold voltage). .

  If a depletion type transistor is used as the reset transistor 36, a leak current can flow even when the reset transistor 36 is in an off state (when not selected). Although details will be described later, in the present embodiment, this characteristic is used as a technique for countermeasures against blooming in the thinning readout mode.

  For example, in the vertical selection transistor 40, the drain is connected to the source of the amplification transistor 42, the source is connected to the pixel line 51, and the gate (in particular, the vertical selection gate SELV) is connected to the vertical selection line 52. In addition, the arrangement of the vertical selection transistor 40 and the amplification transistor 42 is not limited to this, and the vertical selection transistor 40 has a drain connected to the power supply Vdd and a source connected to the drain of the amplification transistor 42. The source of the amplifying transistor 42 may be connected to the pixel line 51. A vertical selection signal SEL is applied to the vertical selection line 52.

  The amplification transistor 42 has a gate connected to the floating diffusion 38, a drain connected to the power supply Vdd, a source connected to the pixel line 51 via the vertical selection transistor 40, and further connected to the vertical signal line 53 (19). It is like that.

  The transfer pulse TRG, the pixel reset pulse RST, and the vertical selection pulse VSEL are generally binary pulses of active H (high; power supply voltage level) and inactive L (low: reference level). . The power supply voltage level is about 3V, for example. The reference level is, for example, 0.4 to 0.7 V or the ground level of 0 V. However, in some cases, a negative potential of about −1 V may be set for some pulses.

  In this embodiment, the transfer pulse TRG supplied to the gate of the read selection transistor 34 is not only a binary drive using two kinds of potentials of a power supply voltage level and a reference level, but also a high level and a low level. A drive using at least three kinds of potentials (also referred to as ternary drive) that also uses any voltage between them (referred to as intermediate voltage: not including high level and low level) is also applicable. .

  In the normal all-pixel readout mode, binary driving is performed using binary values at both ends of the three values. In the thinning readout mode, the binary values and the three values at both ends of the ternary values are read out and thinned out. By using properly, measures against blooming in the thinning readout mode are taken. In order to cope with this, the transfer drive buffer BF1 is supplied with control information (ternary control signal G) for dealing with ternary driving. The use of binary and ternary values and the ternary control signal G will be described in detail later.

  Further, one end of the vertical signal line 53 extends to the column processing unit 26 side, and the read current source unit 24 is connected along the path, and a substantially constant operating current (read) is performed between the vertical signal line 53 and the amplifying transistor 42. A source follower configuration in which (current) is supplied is adopted.

  Specifically, the read current source unit 24 includes an NMOS type transistor (in particular, a load MOS transistor) 242 provided in each vertical column, a current generation unit 245 shared by all the vertical columns, and a gate and a drain. And a reference current source unit 244 having an NMOS type transistor 246 whose source is connected to the source line 248.

  Each load MOS transistor 242 has a drain connected to the vertical signal line 53 of the corresponding column and a source connected in common to a source line 248 that is a ground line. As a result, the load MOS transistors 242 in each vertical column are connected to each other so as to function as a current source with respect to the vertical signal line 19 by connecting the gates to the transistor 246 of the reference current source unit 244 to form a current mirror circuit. Has been.

  The source line 248 is connected to the ground (GND) as the substrate bias at the horizontal end (left and right vertical columns in FIG. 1), and the operating current (read current) with respect to the ground of the load MOS transistor 242 is changed to the left and right of the chip. It is configured to be supplied from both ends.

  A load control signal SFLACT for outputting a predetermined current only when necessary is supplied to the current generation unit 245 from a load control unit (not shown). When the signal is read, the current generation unit 245 receives an active state of the load control signal SFLACT so that the load MOS transistor 242 connected to each amplification transistor 42 continues to flow a predetermined constant current. It has become. In other words, the load MOS transistor 242 makes a signal output to the vertical signal line 53 by assembling the amplifying transistor 42 and the source follower in the selected row and supplying the read current to the amplifying transistor 42.

  In such a 4TR configuration, since the floating diffusion 38 is connected to the gate of the amplifying transistor 42, the amplifying transistor 42 outputs a signal corresponding to the potential of the floating diffusion 38 (hereinafter referred to as “FD potential”) in the voltage mode. The signal is output to the vertical signal line 19 (53) via the line 51.

  The reset transistor 36 resets the floating diffusion 38. The read selection transistor (transfer transistor) 34 transfers the signal charge generated by the charge generator 32 to the floating diffusion 38. A large number of pixels are connected to the vertical signal line 19. To select a pixel, the vertical selection transistor 40 is turned on only for the selected pixel. Then, only the selected pixel is connected to the vertical signal line 19, and the signal of the selected pixel is output to the vertical signal line 19.

  Even when the unit pixel group 2 having a structure in which a part of the plurality of unit pixels 3 is shared is used, a normal operation of individually reading information on all the pixels can be performed. Of course, thinning-out reading, which is another example of the high-speed method for shortening the pixel signal reading processing time, is also possible. Although details will be described later, at the time of thinning-out reading in the present embodiment, driving suitable for measures against blooming due to charges overflowing from the unit pixels 3 in the thinning-out row is performed, and in that case, the pixel sharing structure is also included. Drive in consideration.

  In order to control these various readout operations, by changing the timing of the pulse signal applied to each unit pixel 3 from the communication / timing generation unit 20, an all-pixel readout mode and a high-speed drive mode which are examples of the normal imaging mode The thinning readout mode, which is an example, is switched. The control of the unit pixel 3 in each mode and the operation of the column AD circuit 25 will be described later.

<Pixel structure>
FIG. 3 shows density distributions (profiles) in the BB ′ cross-sectional line and the CC ′ cross-sectional line of the unit pixels 3 constituting the unit pixel group 2 shown in FIG. 2 focusing on the charge generation unit 32 and the floating diffusion 38. FIG. 3 is a schematic diagram of a cross-sectional structure. 3A is an example of a potential sectional view taken along the line AA ′ in FIG. 3 and the line BB ′ in FIG. 2.

  As an example, a p-type impurity (P well) as a second conductivity type semiconductor layer is formed on an n-type silicon substrate (first conductivity type semiconductor substrate NSUB), and the second conductivity type semiconductor layer is formed on the second conductivity type semiconductor layer. A photodiode PD having a charge storage layer (first sensor region) formed by ion-implanting impurities of the first conductivity type is formed as a sensor unit (light receiving unit). That is, an n-type semiconductor substrate NSUB is used, and an n-type photodiode PD is formed in the P-well as the charge generation unit 32. Signal charges obtained by receiving light and performing photoelectric conversion are accumulated in the charge accumulation layer.

  More preferably, in such a sensor portion (photodiode PD), a hole accumulation layer (P + type impurity region) (P + type impurity region) is further formed on the charge accumulation layer on the surface side of the NP diode (N + type impurity region). A so-called HAD (Hole Accumulated Diode) structure in which the second sensor region is also stacked.

  In this case, the p-type concentration under the readout gate portion TRG is made higher than the p-type concentration of the well under the photodiode PD, and the potential barrier between the photodiode PD under the readout gate portion TRG and the floating diffusion FD is It is formed to be higher than the potential barrier between wells.

  When the amount of exposure to the photodiode PD increases and charges (for example, electrons) are generated excessively, the charges overflowing in the photodiode PD are discharged in the direction of lower potential barrier, and therefore from the well under the photodiode PD. By adopting a so-called vertical overflow drain structure that discharges charges in the direction of the semiconductor substrate NSUB, blooming in the horizontal direction is suppressed.

  However, even if such a vertical overflow drain structure is adopted, there is a considerable amount of charge movement through the well. If the amount of charge overflowing from the charge generation unit 32 is small, the advantage of blooming suppression by the vertical overflow drain structure is not a problem, but if the amount of overflowing overflow is too large, the charge transfer through this well is large. Therefore, there are some problems of blooming to adjacent pixels. The case will be described later.

<Operation of solid-state imaging device; basic operation>
FIG. 4 is a timing chart for explaining signal acquisition difference processing in the all-pixel readout mode, which is an example of the normal imaging mode, which is a basic operation in the column AD circuit 25 of the solid-state imaging device 1 shown in FIG. .

  In the all-pixel readout mode, each unit pixel 3 of the unit pixel group 2 is driven in the same manner as in the past, and individually from the charge generation units 32a, 32b, 32c, and 32d provided in each unit pixel 3. Read.

  Here, as a mechanism for converting an analog pixel signal sensed by each unit pixel 3 of the pixel array unit 10 into a digital signal, for example, a ramp wave that descends with a predetermined inclination (may be stepwise) A point where the reference signal Vslop having the shape matches the voltage of the reference component and the signal component in the pixel signal from the unit pixel 3 is searched, and the reference signal Vslop used in this comparison process is generated in the pixel signal from the generation (change start) point The count value of the pixel signal level corresponding to each size of the reference component and the signal component is obtained by counting (counting) with the count clock until the electrical signal corresponding to the reference component or the signal component matches the reference signal. Take the technique to get.

  That is, the analog pixel signal voltage Vx read out to the vertical signal line 19 is compared with the reference signal Vslop by the voltage comparison unit 252 of the column AD circuit 25 arranged for each column. At this time, like the voltage comparison unit 252, the counter unit 254 arranged for each column is operated, and the potential of the reference signal Vslop and the counter unit 254 are changed while taking a one-to-one correspondence. The pixel signal voltage Vx of the vertical signal line 19 is converted into digital data. Here, a change in the reference signal Vslop is to convert a change in voltage into a change in time, and the time is quantized with a certain period (clock) and counted by the counter unit 254 to be converted into digital data. Assuming that the reference signal Vslop changes by ΔV during a certain time Δt, when the counter unit 254 is operated at a period of Δt, the counter value when the reference signal Vslop changes by N × ΔV becomes N.

  Here, in the pixel signal So (pixel signal voltage Vx) output from the vertical signal line 19, the signal level Ssig appears after the reset level Srst including the noise of the pixel signal as a reference level as a time series. When the P-phase processing is performed for the reference level (reset level Srst, which is substantially equivalent to the reset level Vrst), the D-phase processing is processing for the signal level Ssig obtained by adding the signal component Vsig to the reset level Srst.

  Hereinafter, the reset control signal CLR, the count mode control signal UDC, and the data retention control pulse HLDC will be specifically described as being supplied from the communication / timing control unit 20 to the counter unit 254 as the control information CN5.

  First, when acquiring a signal of a precharge phase (may be abbreviated as P phase) that is an AD conversion period for the reset level Srst, the communication / timing control unit 20 sets the reset control signal CLR to active H, The count value output from the non-inverting output terminal Q of each flip-flop 510 of the counter unit 254 is reset to the initial value “0”, and the counter unit 254 is set to the down-count mode (t1). At this time, the communication / timing controller 20 sets the data holding control pulse HLDC to active H and sets the count mode control signal UDC to low level (that is, down count mode).

  At this time, in the unit pixel 3, the vertical selection signal φVSEL of the read target row Vn is set to active H to permit the output of the pixel signal So to the vertical signal line 19, and the reset signal φRST is set to active H almost at the same time. 38 is set to the reset potential (t1 to t2). This reset potential is output to the vertical signal line 19 as the pixel signal So. As a result, the reset level Srst appears on the vertical signal line 19 as the pixel signal voltage Vx.

  When the reset level Srst on the vertical signal lines 19 (H1, H2,...) Converges and becomes stable, the communication / timing control unit 20 seems to start changing the reference signal Vslop simultaneously with the start of the counting operation in the counter unit 254. Therefore, the data holding control pulse HLDC is used as the control data CN4, and this data holding control pulse HLDC is set to inactive L (t10).

  In response to this, the reference signal generation unit 27 as a reference signal Vslop, which is a comparison voltage to one input terminal RAMP of the voltage comparison unit 252, has an overall sawtooth shape (RAMP shape) starting from the initial voltage SLP_ini. Input a stepped or linear voltage waveform over time. The voltage comparison unit 252 compares the reference signal Vslop with the pixel signal voltage Vx of the vertical signal line 19 supplied from the pixel array unit 10.

  At the same time as the input of the reference signal Vslop to the input terminal RAMP of the voltage comparison unit 252, the comparison time in the voltage comparison unit 252 is synchronized with the reference signal Vslop issued from the reference signal generation unit 27, and the counter arranged for each row The unit 254 measures. Actually, the data holding control pulse HLDC is set to inactive L to generate the reference signal Vslop, and the holding operation of the data holding unit 512 is thereby released, so that the counter unit 254 counts the P phase. As an operation, the down-counting is started from the initial value “0”. That is, the count process is started in the negative direction.

  The voltage comparison unit 252 compares the ramp-shaped reference signal Vslop from the reference signal generation unit 27 with the pixel signal voltage Vx input through the vertical signal line 19 and when both voltages become the same, The comparator output is inverted from H level to L level. That is, the voltage signal (reset level Srst) corresponding to the reset level Vrst and the reference signal Vslop are compared, and the active low (L) having a magnitude in the time axis direction corresponding to the magnitude of the reset level Vrst. A pulse signal is generated and supplied to the counter unit 254.

  In response to this result, the counter unit 254 stops the counting operation almost simultaneously with the inversion of the comparator output, and latches (holds) the count value at that time (“−Drst” taking the sign into account) as pixel data. (Storing) to complete AD conversion. That is, the width of the active-low (L) pulse signal having a magnitude in the time axis direction obtained by the comparison process in the voltage comparison unit 252 is counted (counted) by the count clock CK0, thereby increasing the reset level Vrst. A count value indicating a digital value Drst corresponding to the value (indicating -Drst if a sign is added) is obtained.

  When the predetermined down-count period has elapsed, the communication / timing control unit 20 sets the data holding control pulse HLDC to active H (t14). As a result, the reference signal generator 27 stops generating the ramp-like reference signal Vslop (t14) and returns to the initial voltage SLP_ini.

  At the time of P-phase processing, the reset level Vrst in the pixel signal voltage Vx is detected by the voltage comparison unit 252 and the counter unit 254 performs the count operation. Therefore, the reset level Vrst of the unit pixel 3 is read and the reset level Vrst AD conversion will be performed.

  At the time of signal acquisition of the data phase (may be abbreviated as D phase) that is the AD conversion period for the subsequent signal level Ssig, in addition to the reset level Vrst, a signal corresponding to the amount of incident light for each unit pixel 3 The component Vsig is read, and the same operation as the P-phase reading is performed. That is, first, the communication / timing control unit 20 sets the count mode control signal UDC to the high level and sets the counter unit 254 to the up-count mode (t16).

  At this time, the unit pixel 3 reads the signal level Ssig to the vertical signal line 19 by setting the transfer signal φTRG to active H while keeping the vertical selection signal φVSEL of the read target row Vn active H (t18 to t19).

  When the signal level Ssig on the vertical signal lines 19 (H1, H2,...) Converges and becomes stable, the communication / timing control unit 20 starts changing the reference signal Vslop simultaneously with the start of the counting operation in the counter unit 254. Therefore, the data holding control pulse HLDC is used as the control data CN4, and this data holding control pulse HLDC is set to inactive L (t20).

  In response to this, the reference signal generation unit 27 as a reference signal Vslop, which is a comparison voltage to one input terminal RAMP of the voltage comparison unit 252, has a sawtooth as a whole having the initial voltage SLP_ini as the starting point and the same slope as the P phase. A stepped or linear voltage waveform that is time-varying in the shape (RAMP) is input. The voltage comparison unit 252 compares the reference signal Vslop with the pixel signal voltage Vx of the vertical signal line 19 supplied from the pixel array unit 10.

  At the same time as the input of the reference signal Vslop to the input terminal RAMP of the voltage comparison unit 252, the comparison time in the voltage comparison unit 252 is synchronized with the reference signal Vslop issued from the reference signal generation unit 27, and the counter arranged for each row The unit 254 measures. In this case as well, in practice, the data holding control pulse HLDC is set to inactive L to generate the reference signal Vslop, and thereby the holding operation of the data holding unit 512 is released. As the phase counting operation, the digital signal Drst (in this case, a negative value) of the reset level Srst of the pixel signal voltage Vx acquired at the time of P-phase reading and AD conversion is used, and the up-counting is performed contrary to the P-phase. To start. That is, the count process starts in the positive direction.

  The voltage comparison unit 252 compares the ramp-shaped reference signal Vslop from the reference signal generation unit 27 with the pixel signal voltage Vx input through the vertical signal line 19 and when both voltages become the same, The comparator output is inverted from H level to L level (t22). That is, a voltage signal corresponding to the signal component Vsig (the signal level Ssig of the pixel signal voltage Vx) is compared with the reference signal Vslop, and the active has a magnitude in the time axis direction corresponding to the magnitude of the signal component Vsig. A low (L) pulse signal is generated and supplied to the counter unit 254.

  In response to this result, the counter unit 254 stops the count operation almost simultaneously with the inversion of the comparator output, and latches (holds / stores) the count value at that time as pixel data, thereby completing the AD conversion (t22). ). That is, the width of the active low (L) pulse signal having a magnitude in the time axis direction obtained by the comparison processing in the voltage comparison unit 252 is counted (counted) by the count clock CK0, so that the pixel signal voltage Vx A count value corresponding to the signal level Ssig is obtained.

  When a predetermined up-count period elapses, in the unit pixel 3, the vertical selection signal φVSEL of the readout target row Vn is set to inactive L, and the output of the pixel signal So to the vertical signal line 19 is prohibited, and the next readout target row Vn + 1. , The vertical selection signal φVSEL is set to active H (t26). At this time, the communication / timing control unit 20 prepares for processing for the next read target row Vn + 1. For example, the count mode control signal UDC is set to a low level to set the counter unit 254 to the up / down count mode.

  At the time of this D-phase processing, the signal level Ssig at the pixel signal voltage Vx is detected by the voltage comparison unit 252, and the counting operation is performed. Therefore, the signal component Vsig of the unit pixel 3 is read and AD conversion of the signal level Ssig is performed. Will be implemented.

  Here, since the signal level Ssig is a level obtained by adding the signal component Vsig to the reset level Srst, the count value of the AD conversion result of the signal level Ssig is basically “Drst + Dsig”. Since the starting point is “−Drst”, which is the AD conversion result of the reset level Srst, the count value actually held is “−Drst + (Dsig + Drst) = Dsig”.

  That is, in the present embodiment, the counting operation in the counter unit 254 is down-counting during the P-phase processing and up-counting during the D-phase processing, so that the AD conversion of the reset level Srst is automatically performed within the counter unit 254. Difference processing (subtraction processing) is automatically performed between the count value “−Drst” as a result and the count value “Drst + Dsig” as an AD conversion result of the signal level Ssig, and according to the difference processing result. The count value Dsig is held in the counter unit 254. The count value Dsig held in the counter unit 254 corresponding to the difference processing result corresponds to the signal component Vsig.

  As described above, the variation for each unit pixel 3 is caused by the difference processing in the counter unit 254 by the two readings and the counting process, such as the down-counting in the P-phase process and the up-counting in the D-phase process. The included reset level Vrst can be removed, and an AD conversion result of only the signal component Vsig corresponding to the amount of incident light for each unit pixel 3 can be obtained with a simple configuration.

  Therefore, the column AD circuit 25 of the present embodiment operates not only as a digital conversion unit that converts an analog pixel signal into digital pixel data but also as a CDS (Correlated Double Sampling) processing function unit. It will be.

  Further, the column AD circuit 25 of the present embodiment includes a data storage unit 256 subsequent to the counter unit 254, and based on the memory transfer instruction pulse CN8 from the communication / timing control unit 20 before the operation of the counter unit 254. The count result of the preceding row Hx-1 can be transferred to the data storage unit 256.

  That is, after the AD conversion period ends, the data in the counter unit 254 is saved to the data storage unit 256, and the column AD circuit 25 starts AD conversion of the next row Vx + 1. The data in the data storage unit 256 is sequentially selected by the horizontal scanning circuit 12 behind it and can be read out using the output circuit 28.

  Here, the P-phase signal potential is obtained by automatically taking the difference between the digital data of the P-phase (reset level Srst) and the digital data of the D-phase (signal level Ssig) in the course of the AD conversion process twice. The AD conversion result of the signal component Vsig represented by the difference between the (reset level potential) and the D-phase signal potential (signal level potential) is obtained. In order for the AD conversion result to be accurate, P It is important to process the pixel signal voltage Vx (= Ssig) representing only the signal charge amount read from the charge generation unit 32 of the readout row to the floating diffusion 38 in the process phase of the D phase after the phase processing.

  Therefore, if unnecessary charges generated by the part other than the charge generation unit 32 in the read row flow into the floating diffusion 38 in the process of the D phase, the signal level Sn at that time becomes an unnecessary charge for the original signal level Ssig. Based on this, a count value obtained as an AD conversion result does not become Dsig even if the above-described CDS processing is performed (Sn = Ssig + Vnoise).

  That is, if the count value for the unnecessary signal component Vnoise is Dnoise, the count value “−Drst” that is the AD conversion result of the reset level Srst and the count value “−Drst” that is the AD conversion result of the “signal level Ssig + unnecessary signal component Vnoise”. The difference processing (subtraction processing) between “Drst + Dsig + Dnoise” is automatically performed, and the count value “Dsig + Dnoise” corresponding to the difference processing result is held in the counter unit 254. Obviously, the count value “Dsig + Dnoise” held in the counter unit 254 according to the difference processing result is not the digital data Dsig corresponding to the signal component Vsig, but is obtained by adding the unnecessary signal component Vnoise to the signal component Vsig. Represents.

  In particular, in the single slope integration type AD conversion as in the present embodiment, the acquisition time of the P phase and the processing time of the D phase are different, and the reference signal Vslop and the pixel signal level coincide with each other as the pixel signal level increases. The comparison processing time becomes longer, and the potential of the floating diffusion 38 continues to decrease during that time. As a result, the unnecessary signal component Vnoise that cannot be canceled by the CDS process increases as the pixel signal level increases. Cases where this problem occurs and countermeasures will be described later.

<< Thinning readout mode >>
Here, the solid-state imaging device 1 shown in FIG. 1 is a CMOS sensor of a type that reads pixel signals from the pixel array unit 10 at a time in units of rows, and performs two readouts of an all-pixel readout mode and a thinning readout mode. Has a mode.

  In the all-pixel reading mode in which the pixel signal voltage Vx is read out from all the unit pixels 3 constituting the pixel array unit 10, processing for the shutter row and processing for the reading row are sequentially selected from the first row to the last row. Thus, processing is performed at the timing as shown in FIG.

  Further, for example, when it is desired to operate at a high frame rate or to reduce the amount of information per frame, the thinning-out reading mode is applied, and not all rows are sequentially read out. A 1 / m thinning operation may be performed in which one row is selected for each row and used as a read row. That is, only pixel signals corresponding to 1 / m of the total number of rows of the pixel array unit 10 are read out by an operation sequence of reading out pixel signals for one row → m-1 skipping → reading one row →. This operation mode is referred to as a 1 / m-th thinning-out reading mode, a thinned-out line that occupies “m−1” lines in m lines is referred to as a thinned-out line (or a non-selected line), and a non-thinned-out line is read out ( Alternatively, it is called a selected row or a signal output row).

  If the 1 / m row thinning readout mode is provided in addition to the all-pixel readout mode, the amount of information per frame can be reduced to 1 / m and the imaging speed can be increased m times in the 1 / m row thinning readout mode. It can meet the conflicting needs of pixels and high-speed reading. For switching to the thinning operation, a signal for switching the operation mode to the 1 / m thinning mode is input from the outside, and a drive signal sent from the communication / timing control unit 20 to the horizontal scanning circuit 12 or the vertical scanning circuit 14 is 1. / M is performed by switching to thinning-out.

  For example, in a digital still camera, before taking a still image, usually, an operation of projecting a moving image (subject image) on, for example, a liquid crystal monitor on a small screen and confirming (monitoring) the subject is performed. At the stage where the subject is confirmed (monitoring mode), the image displayed on the LCD monitor does not need to have a high resolution, and may be a rough image (low resolution image) according to the number of pixels on the LCD monitor. Information thinning processing is performed. Further, in image transmission in a portable device such as a digital still camera, the transmission data rate is limited. Therefore, pixel information is thinned out to transmit high-definition images for still images, and pixel information is thinned out to transmit moving images with a reduced amount of information. It is.

  In the thinning process of pixel information in the vertical direction, a process of thinning out rows that are actually used is performed. In this case, after reading out pixel information from the image sensor for all pixels (for all rows), a method of thinning out pixel information in units of rows by an external signal processing system, and readout of pixel signals from unit pixels in units of rows Any of the thinning methods can be considered.

  In the thinning-out reading mode of this embodiment, a method of thinning out pixel signals from unit pixels per row is applied as in the latter case. Such a thinning-out operation can respond to an operation with low power consumption and is advantageous in that high-speed reading is possible because there are few rows to be read.

<1/3 line thinning readout mode>
5 and 6 are diagrams showing a first comparative example for the pixel driving method in the thinning readout mode of the present embodiment. In the first comparative example, as an example of the thinning-out reading mode, an operation in the 1 / 3-row thinning-out reading mode in which one row of signals is output every three rows is schematically shown.

  FIG. 5 schematically shows the arrangement of the unit pixels 3 arranged in a matrix in the pixel array unit 10 of the CMOS type solid-state imaging device 1, and each cell in the pixel array unit 10 of the outer frame. Indicates the unit pixel 3.

  As described above, in the all-pixel reading mode which is the normal reading mode, the pixels in all rows are selected in order (from the lower side of the figure) by the operation of the vertical scanning circuit 14, but the 1 / 3-row thinning-out reading mode is selected. In the pixel array unit 10, only one row indicated by hatching except for the thinned-out row that occupies the “3-1 = 2” rows in the continuous three rows is sequentially selected as a read row and read out. The operation is such that two lines per three lines indicated by the remaining white frames are not selected as thinning lines.

  FIG. 6 shows a timing chart for explaining the operation of the unit pixel 3 corresponding to FIG. Here, FIG. 6A shows the overall outline of the operation, and FIG. 6B shows over a plurality of horizontal periods by paying attention to the transfer pulse TRG.

  As can be seen from FIG. 6, only the read operation row or the shutter operation row is the high voltage or low voltage for the read selection transistor 34, the reset transistor 36, and the vertical selection transistor 40. A voltage is supplied to operate, and a low voltage is always supplied to the read selection transistor 34, the reset transistor 36, and the vertical selection transistor 40 for thinning-out.

  At a point in time when the readout row has a horizontal period corresponding to the row where the shutter operation is performed (shutter operation row), the transfer pulse TRG is set to active H to turn on the readout selection transistor 34, and the charge generation unit 32 accumulates before that. Charges that are unnecessary for reading are transferred to the floating diffusion 38, and the reset transistor 36 is turned on when the pixel reset pulse RST is set to active H almost simultaneously or thereafter, and the unnecessary charges transferred to the floating diffusion 38 are reset. Sweep to power supply Vrd. This operation is referred to as a shutter operation.

  Here, the activation timings of the transfer pulse TRG and the pixel reset pulse RST in the shutter operation row should not adversely affect the operation in the readout operation row that is processed in parallel with the shutter operation and the output image. Should be considered. For this purpose, it is important to match the timing of the transfer pulse TRG and the pixel reset pulse RST in the shutter operation row with the timing of other pulses in the readout operation row (in this example, the pixel reset pulse RST and the transfer pulse TRG).

  In this case, if the pixel reset pulse RST is generated after the transfer pulse TRG in the shutter operation row, the timing of the transfer pulse TRG in the shutter operation row and the pixel reset pulse RST in the readout operation row are necessarily matched. The timings of the pixel reset pulse RST in the shutter operation row and the transfer pulse TRG in the readout operation row are matched. In the shutter operation row, if the timings of the transfer pulse TRG and the pixel reset pulse RST are matched, the timings are matched with the timing of the pixel reset pulse RST or the transfer pulse TRG in the read operation row.

  In this embodiment, the timings of the transfer pulse TRG and the pixel reset pulse RST are matched in the shutter operation row, and those timings are matched with the timing of the pixel reset pulse RST in the readout operation row. In order to ensure the reset operation when the pixel reset pulse RST in the shutter operation row and the transfer pulse TRG in the readout operation row are matched, strictly speaking, the off timing is as shown by the dotted line in the figure. It is preferable to set the pixel reset pulse RST to inactive L after the transfer pulse TRG is set to inactive L.

  At a point in time when the row in which the shutter operation has been performed (shutter operation row) corresponds to the row from which the pixel signal is to be read (read operation row), the vertical selection pulse VSEL is set to active H and the vertical selection transistor 40 is turned on. First, the reset transistor 36 is turned on by setting the pixel reset pulse RST to active H, and unnecessary charges accumulated in the floating diffusion 38 are swept away to the reset power source Vrd.

  Thereafter, the transfer pulse TRG is set to active H to turn on the read selection transistor 34, and the charge (particularly referred to as signal charge) accumulated in the charge generation unit 32 after the shutter operation to this point is transferred to the floating diffusion 38. To do. As a result, the voltage of the floating diffusion 38 changes in accordance with the amount of signal charge, so that the amplification transistor 42 converts the change into a pixel signal voltage and the column processing unit via the vertical signal line 53 (vertical signal line 19). 26. As can be seen from this figure, the shutter operation row and the readout operation row are paired in a state shifted by a row defining the shutter period, and incremented every horizontal period.

<Problems caused by decimation readout>
However, when the unit pixel 3 is driven by such a method, various driving conditions (transistor driving frequency) for the unit pixel 3 are different between the thinning-out row and the readout row that is not thinned out. Problems arise.

  For example, in the unit pixel group 2 (unit pixel 3) shown in FIGS. 2 and 2A, after a long period of use, transistors and pixel wirings that constitute the unit pixel 3 in a thinning row and a reading row that is not thinned out Differences occur in the degree of deterioration of the driver transistors constituting each of the drive buffers BF1 to BF3 that drive the (vertical selection line 52, transfer wiring 55, and reset wiring 56). Degradation of visible image characteristics occurs.

  In order to cope with this, for example, when driving in the thinning readout mode, a driving signal is input to the thinned pixel rows to operate each pixel, and the driving frequency between the thinned pixels and the pixels that are not thinned out. It is conceivable to take a mechanism for preventing the occurrence of streak noise of the image in the all-pixel reading mode by eliminating the difference and aligning the degree of deterioration of the transistors constituting the pixels.

<Blooming>
Another problem is that the blooming phenomenon tends to occur in the thinning readout mode. That is, the charge generation unit 32 generates and accumulates signal charges (for example, electrons) by performing photoelectric conversion according to the total amount of incident light, but there is a limit to the capacity that can be accumulated. When the voltage is strong or the charge accumulation time is long, the signal charge photoelectrically converted exceeding the limit value overflows from the accumulation region. As described with reference to FIG. 3, the vertical overflow drain structure is adopted, and the device is designed so that most of the overflowing signal charge flows to the substrate side. As a result, the distance between the pixels to be processed becomes close, and as a result, the ratio of the overflowing signal charge that jumps into adjacent pixels increases.

  For example, in the case of a color imaging system, each unit pixel 3 of the pixel array unit 10 is provided with color filters for color separation, for example, R (red), G (green), and B (blue) in a predetermined arrangement order. . It is assumed that a large amount of light of the G color component is incident and there is less light of the R color component. In this case, when the amount of incident light is increased by opening the diaphragm of the camera system or the like, first, the charge generation unit 32 of the green pixel is filled with the signal charge and becomes saturated. The red charge generation unit 32 also jumps.

  On the other hand, in the unit pixel 3 that is actually read, the signal level of the unit pixel 3 depends on how much light is converted into the signal charge after the signal charge is read from the charge generation unit 32 and before the next signal charge is read. (Luminance) is determined. As described above, during the electronic shutter operation in the CMOS sensor, there is a problem from the charge sweeping reset process to the charge generation unit 32 until the signal charge is actually read out to the vertical signal line 53 (vertical signal line 19) side. It becomes. Therefore, in order to suppress the blooming phenomenon, it is important how much the signal charge jumping from the adjacent pixel can be reduced between the reset time and the readout in the shutter operation.

  In the 1 / m line thinning-out reading mode, one line becomes a reading line, and the subsequent m-1 lines become thinning lines, and this is repeated, so if simple thinning reading is performed, Since the read selection transistor 34 (read gate) is always turned off, electrons are accumulated in the charge generation unit 32 even in the case of still image capturing for capturing only one frame, particularly during long-time storage. As a result, it causes blooming to adjacent pixels. In addition, in the case of moving image capturing, there is continuous accumulation of signal charges over a plurality of frames, but reading is not performed. Therefore, if it is left as it is, excessive charges overflow in adjacent reading rows, and the problem of blooming almost certainly occurs. .

  That is, in the thinning-out reading mode, since the charge generation unit 32 of each unit pixel 3 is exposed to light in both the thinning-out and reading rows, the charge is adjacent to the thinning-out charge generation unit 32 unless the shutter operation is performed. It is feared that overflowing the readout row (pixels) to be read affects the pixel signal of the readout row (blooming phenomenon).

  In view of this point, a preliminary pixel reset (shutter operation) is performed in advance on the unit pixel 3 that is likely to overflow adjacent to the unit pixel 3 to be read, and attention is paid to it. It is considered preferable to minimize the influence of excess charges overflowing from other unit pixels 3 adjacent to a certain unit pixel 3. In the thinning-out reading mode, the pixel signal reading operation is not performed for the thinning-out row, but it is considered effective to perform only the shutter operation.

  FIG. 7 is a diagram showing a second comparative example with respect to the pixel driving method in the thinning readout mode according to the present embodiment. In the case of the 1/3 row thinning readout mode, FIG. 7 corresponds to FIG. 5 for the state of row scanning of the pixel array unit 10, and FIG. 8 corresponds to FIG. 6 for the timing chart for explaining the operation. As shown.

  The second comparative example illustrates one method for eliminating the above-mentioned blooming phenomenon. In this method, the pixel signal readout operation is not performed for the thinned rows, but only the shutter operation is performed. That is, before reading the signal charge from the unit pixel 3 in the readout row, the unit pixel 3 in the shutter row corresponding to the thinning row adjacent (sufficient on either side in the scanning direction) is preliminarily used by using the electronic shutter function. Pixel reset operation (shutter for preventing blooming) is performed. Regarding the shutter row corresponding to the thinning-out row on the other side in the scanning direction, the generation of excess charge can be suppressed by the shutter for preventing blooming in the next readout row.

  In the 1 / 3-row thinning-out reading mode, as shown in FIG. 7, one row indicated by diagonal lines excluding the thinning-out row that occupies “3-1 = 2” in 3 consecutive rows in the pixel array section 10. Only the read lines are sequentially selected and read, and the remaining two lines are not selected as thinned lines.

  At this time, the shutter is also applied to the thinning-out rows before and after the shutter row, so that the charge generated by the charge generation unit 32 is discharged to the reset power supply Vrd side, and the charge is not saturated in the charge generation unit 32. In this way, blooming to adjacent pixels is controlled. The shutter for preventing blooming for the thinning-out row is particularly called an auxiliary shutter, and the shutter for the reading row is called a normal shutter for distinguishing from the auxiliary shutter.

  After the auxiliary shutter operation, as in the normal shutter operation, charges corresponding to the subsequent exposure are accumulated in the charge generation unit 32. However, the vertical selection pulse VSEL is always inactive L and is selected as a read operation row. Therefore, the pixel signal corresponding to the electric charge accumulated after the auxiliary shutter operation is not output to the vertical signal line 53 (vertical signal line 19). In the case of moving image capturing, the charge accumulated in the charge generation unit 32 until then (in effect, one frame scanning period) is swept away to the reset power supply Vrd side by the auxiliary shutter operation at the next frame scanning.

  However, in such a system, a new vertical scanning circuit (row selection circuit) needs to be added for the auxiliary shutter operation for thinning-out rows (non-selected rows), which is disadvantageous in terms of chip size.

  In consideration of the point that the shutter operation is also performed for the thinned rows, a drive signal is input to the thinned pixel rows when driving in the thinning readout mode as disclosed in Patent Document 1 described above. Therefore, it is considered that operating each pixel is also effective as a technique for eliminating the blooming phenomenon.

  Further, as another method for eliminating the blooming phenomenon, the thinning-out is continuously shuttered, that is, the transfer selection pulse 34 and the reset transistor 36 are always turned on by always setting the transfer pulse TRG and the pixel reset pulse RST to active H. It is also conceivable to transfer the charges generated by the thinning-out charge generation unit 32 to the floating diffusion 38 and continue to discard them as they are to the reset power supply Vrd.

  However, this technique has a disadvantage in terms of chip size because it is necessary to newly add a single vertical scanning circuit (row selection circuit) for the continuous shutter operation of thinning rows. Also, the transistors 34, 36, and 40 constituting the unit pixel 3 are turned on / off only in the readout operation row and the readout operation row, and the readout selection transistor 34 and the reset transistor are used for the thinning-out row. 36 is always on, and the vertical selection transistor 40 is always off. Therefore, after a long period of use, the pixel driving frequency differs between the thinning-out row and the readout row that is not thinned out, resulting in deterioration of image characteristics. The same problem as described above occurs, and there is a disadvantage in image quality. In addition, when the transistor is always turned on, the absolute use time of the transistor is drastically increased, which is disadvantageous in terms of reliability as compared with the case where the transistor is always turned off.

  Regarding reliability, it is also related to element isolation formation. As a method for forming element isolation within a pixel, a method of forming an insulating oxide film in Si, such as STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon), or a method of forming element isolation by implantation is known. STI is a manufacturing method in which Si is etched to fill an insulating oxide film. However, dark current increases due to plasma damage during etching. LOCOS is a method in which only the Si portion is selectively oxidized by an oxidation furnace. However, an oxide film enters the gate end (gate bird's beak), resulting in parasitic capacitance. Further, this technique is not suitable for forming narrow element isolation, and in recent years, LOCOS has been replaced by STI.

  Since the pixel array unit 10 includes a photoelectric conversion portion (in this example, the charge generation unit 32), it is most preferable to form element isolation by implantation as a countermeasure against dark current. However, when element isolation is formed by implantation, an insulating oxide film is required on the element isolation in order to insulate the substrate and the gate electrode. The thickness of the insulating oxide film for element isolation is determined by the range of the source / drain diffusion implant, and does not penetrate the insulating oxide film when ion implantation is performed through the insulating oxide film, that is, does not affect the inside of the Si. It needs to be thick.

  However, when the element isolation is formed by high concentration implantation, if the reset transistor 36 is always turned on, the gate is turned on through the insulating oxide film on the element isolation when the insulating oxide film on the element isolation is not sufficiently insulated. This is not preferable because a dark current may be generated from the element isolation portion and reliability may be lowered. Note that the element isolation formation by STI has less reliability problems than the diffusion element isolation formation, and the thinning-out reset transistor 36 may be always turned on.

<< Thinning readout mode of this embodiment >>
<Measures against blooming>
FIG. 9 is a diagram illustrating a third comparative example for the pixel driving method in the thinning readout mode according to the present embodiment. In the 1/3 row thinning readout mode as an example, FIG. 9 shows the row scanning state of the pixel array unit 10 corresponding to FIG. 5, and FIG. 10 is a timing chart explaining the operation focusing on the transfer pulse TRG. Thus, it corresponds to FIG.

  As can be seen from the comparison between FIG. 9 and FIG. 5, in the thinning readout mode of the third comparative example, as in the first comparative example, the thinning row is used in the second comparative example. Do not put the auxiliary shutter.

  Instead, in the countermeasure against blooming of the third comparative example, the potential for transferring the overflow of charge in the thinning-out row to the own floating diffusion 38 side to the reading selection transistor 34 in the thinning-out row (hereinafter referred to as a countermeasure against blooming). The transfer pulse TRG is always supplied.

  In the third comparative example, an intermediate level potential (intermediate potential M) between the L level and the H level is used as the blooming countermeasure potential, or a floating state where no voltage is substantially applied is used. When floating, there is an advantage that a circuit for generating the intermediate potential M becomes unnecessary.

  In the thinning-out reading mode, with respect to the reading selection transistor 34 (also referred to as a transfer gate or a reading gate), the voltage applied to the gate terminal of the reading selection transistor 34 in the thinning-out mode is H The read selection transistor 34 is operated in an appropriate state by fixing it to an intermediate potential M (Middle) between a high potential H defining the level and a low potential L defining the L level, or for reading selection A floating state in which no transfer pulse TRG is supplied to the gate terminal of the transistor 34 is set.

  The intermediate potential M is preferably set to a potential that satisfies the range in which the overflow barrier is not in the semiconductor substrate (downward) direction but in the floating diffusion (lateral) direction, and the upper limit is the potential at which no dark current is generated. . By doing so, it is possible to suppress the blooming phenomenon during thinning-out reading while suppressing the influence of dark current due to the countermeasure against the blooming phenomenon.

  In the readout row, the readout selection transistor 34 is driven to be turned on / off with binary values of L level and H level, and the readout selection transistor 34 is turned on when corresponding to the shutter operation row and the readout operation row.

  In the thinning-out reading mode, all the row addresses of thinning-out rows that are not selected are selected, and the transfer pulse TRG supplied to the reading gate (reading selection transistor 34) of this thinning-out row is taken as an example of an anti-blooming potential. The overflow barrier (potential barrier) of the thinning-out charge generation unit 32 (photodiode, etc.) is lowered as compared with the case where a normal inactive potential (L level potential) is applied. Can do.

  Thereby, in the thinning-out reading mode, unnecessary charge that has accumulated in the charge generation unit 32 of the thinning-out row and overflowed to the adjacent row (vertical adjacent pixel) can be easily discharged to the floating diffusion 38 side. Blooming to the unit pixel 3 of the readout row to be reduced is reduced.

  If the pixel sharing method is not employed, when the transfer pulse TRG is set to the intermediate potential M, the dark current is slightly increased. However, in the thinning readout mode, the thinning row is not selected as the readout row. This is not a problem because it is not output as a signal to the vertical signal line 53 (vertical signal line 19). Therefore, it is possible to achieve a simple operation mode in which an auxiliary shutter is not required while suppressing a blooming phenomenon to adjacent pixels in the vertical direction due to unnecessary electrons moving through the well.

<Problems with pixel sharing method>
FIG. 11 is a schematic diagram for explaining a problem that occurs in a pixel signal when the third comparative example shown in FIGS. 9 and 10 is applied when the pixel array unit 10 is a pixel sharing method. Here, driving timings and states of pixel signals, reference signals, and the like are shown corresponding to FIG.

  As shown in FIG. 2A, when the pixel array unit 10 is a pixel sharing system configured by a unit pixel group 2 in which a plurality of unit pixels 3 share some elements of the unit pixel 3, a plurality of floating diffusions FD are provided. In the thinning readout mode, when the pixel signal of the readout row is read out to the vertical signal line 53 (vertical signal line 19), as shown in FIG. 32 (for example, a photodiode PD having a HAD structure) continues to be discharged to the floating diffusion FD, and the signal level Ssig of the D phase changes particularly between the acquisition of the P phase and the D phase of the readout row. .

  Charges generated by the charge generation unit 32 in another shared row (hereinafter simply referred to as a shared row) other than the charge generation unit 32 of the readout row can easily flow into the floating diffusion 38, for example, black without exposure. The level Ssig_BK and the level of the white level Ssig_WH that has been sufficiently exposed are signal components (unnecessary signal component Vnoise) based on unnecessary charges generated by the charge generation unit 32 of the shared row in the original signal levels Ssig_BK and Ssig_WH, respectively. The added values (Sn_BK = Ssig_BK + Vnoise, Sn_WH = Ssig_WH + Vnoise), and even if the CDS processing accompanying AD conversion is performed, the count values obtained as the AD conversion results are not Dsig_BK, Dsig_WH.

  As can be inferred from the figure, the potential of the floating diffusion 38 continues to decrease during the comparison process until the reference signal Vslop and the pixel signal level coincide with each other, so that both the black level and the white level are maintained. Although the signal level changes, since the comparison processing time becomes longer as the white level of the pixel signal is higher, the unnecessary signal component Vnoise that cannot be canceled by the CDS process accompanying AD conversion is the white level. Becomes larger.

<Anti-blooming technique for pixel sharing method>
12 to 14 are diagrams for explaining a pixel driving method in the thinning readout mode according to the present embodiment corresponding to the pixel sharing method. As shown in FIG. 2A, when the unit pixel group 2 shares four vertical pixels, FIG. 12 shows the state of row scanning of the pixel array unit 10 in FIG. 5 and FIG. FIG. 13 shows a timing chart for explaining the operation, focusing on the transfer pulse TRG, so as to correspond to FIG. 6 and FIG.

  FIG. 14 is a schematic diagram for explaining the effect when the driving method of the present embodiment shown in FIGS. 12 and 13 is applied when the pixel array unit 10 is a pixel sharing method. In FIG. 14, the driving timing and the state of the pixel signal and the reference signal are shown so as to correspond to FIG.

  As can be seen from the comparison between FIG. 12 and FIG. 9, in the thinning-out reading mode of the present embodiment, as in the first comparative example and the third comparative example, the thinning-out is adopted in the second comparative example. Do not put the auxiliary shutter that is.

  Instead, in the blooming countermeasure of the present embodiment, the transfer pulse TRG is set to an intermediate level potential or less than the intermediate level depending on whether or not the thinning row is shared with the read operation row. Further, it is characterized in that the potential on the inactive side is switched. That is, depending on whether or not a read operation row is included in the pixel sharing row, when the read row corresponds to the read operation row, an intermediate level transfer pulse TRG is supplied to the read selection transistor 34 in the thinning row, or The transfer pulse TRG is switched to a potential on the inactive side further than the intermediate level.

  Here, the potential on the inactive side further than the intermediate level is higher than the intermediate level in the range excluding the H level (active side) and L level (inactive side) in normal binary driving. Any potential may be used, and as an example, it may be the same as the potential defining the L level. A fourth potential between the intermediate level and the L level (inactive side) may be used, but in that case, it is necessary to deal with a circuit that generates the fourth potential separately. There is an advantage that the circuit configuration can be made compact by using the potential itself. In the following description, it is assumed that an L level potential is set as a potential on the inactive side further than the intermediate level.

  Specifically, in the thinning-out read mode, with respect to the read selection transistor 34 (also referred to as a transfer gate or a read gate), in the read row, the read selection transistor 34 is turned on / off in binary of L level and H level. The readout selection transistor 34 is turned on when it is driven off and corresponds to the shutter operation row and the readout operation row.

  In the thinning-out row, first, when not sharing with the read operation row, the voltage (transfer pulse TRG) applied to the gate end of the read selection transistor 34 is set to the high potential H that defines the H level in binary driving. The read selection transistor 34 is operated in an appropriate state by setting it to an intermediate potential M (Middle) between the low potential L that defines the L level. On the other hand, when the read operation row is shared, the voltage (transfer pulse TRG) applied to the gate terminal of the read selection transistor 34 is set to a low potential L that defines the L level, thereby completely turning off the read selection transistor 34. Keep it.

  Note that the timing at which the voltage applied to the read selection transistor 34 in the thinning-out row is dropped from the intermediate potential M to the low potential L that defines the L level is, for example, the first row (= first of the rows sharing the pixels). It is preferable that the pixel reset pulse RST of the row to be read) is set to the active level, that is, before the potential of the floating diffusion 38 is emptied.

  As an example, a period from the timing when the vertical selection pulse VSEL for the first read row (the ninth row in this example) becomes active H to the time when the pixel reset pulse RST in that row becomes active H may be used. On the other hand, the timing at which the L level is increased from the low potential L to the intermediate potential M is determined after the D-phase processing in the fourth row (= the last row to be read) of the pixels sharing, that is, the signal level Ssig AD It is preferable after the conversion data is determined. As an example, the vertical selection pulse VSEL for the row to be read after the AD conversion processing for the last row to be read (the 12th row in this example) is almost the same as the reference signal Vslop and the pixel signal level in this example. What is necessary is just to be a period until the timing which becomes inactive L.

  For example, in FIG. 12, in the case of 1/4 thinning readout in the case of 4 vertical pixel sharing, the pixel signals of the first row and the fourth row of the vertical 4 rows are sent to the vertical signal line 53 (vertical signal line 19). In the case of reading, in particular, the case where the ninth row is the read operation row is illustrated. In FIG. 13, attention is paid to the vicinity of the 9th and 12th read operation rows under the same thinning conditions as in FIG.

  In this case, as shown in FIG. 13, the 10th, 11th, and 12th rows are shared pixels in the 9th row read operation, and the 9th, 10th, and 11th rows are shared pixels in the 12th row read operation. It becomes. Therefore, for the 10th and 11th rows that are thinned out, the transfer pulse TRG is switched from the intermediate potential M to the low potential L before the pixel reset pulse RST is lowered in the 9th row to be shared first (Ts Thereafter, the transfer pulse TRG is held at the low potential L until the reading of the 12th row is completed, and after the AD conversion data is determined by the D-phase processing of the last 12th row, the transfer pulse TRG is changed. Switching from the low potential L to the intermediate potential M (Te).

  As described above, when a read operation row is included in the pixel sharing row, the transfer pulse TRG supplied to the read selection transistor 34 (transfer gate) in the thinning row is lowered from the blooming countermeasure potential (the intermediate potential M or the floating state). By switching to the potential L and cutting the signal from the thinning-out row to the floating diffusion 38, the above-described problem when the thinning-out reading mode is set at the time of pixel sharing can be avoided.

  As shown in FIG. 14, a third comparative example in which the thinning-out transfer pulse TRG is always set to a blooming countermeasure potential with respect to the unit pixel group 2 having a pixel sharing structure in which a plurality of unit pixels 3 share some elements. A signal level fluctuation caused by leakage of a signal from the charge generation unit 32 of the thinning row to the floating diffusion 38 of the reading operation row, which becomes a problem when applied, is a countermeasure against blooming when the thinning row is shared with the reading operation row. This can be resolved by setting the potential on the inactive side rather than the potential.

  Note that if the transfer pulse TRG for thinning-out is set to a blooming countermeasure potential (intermediate potential or floating state) and the shutter is not applied, that is, if the pixel reset pulse RST is always set to L level, the floating diffusion will be included in it. There is a concern that 38 may be filled with unnecessary charges, and an overflow phenomenon may occur in the floating diffusion 38. In particular, at the time of moving image capturing, since the image capturing operation is performed over a plurality of frames, this phenomenon is likely to occur.

  As a countermeasure, for example, at an appropriate timing (for example, in a V ranking period every several frames), the pixel reset pulse RST is made active H, and unnecessary charges accumulated in the floating diffusion 38 are swept away to the reset power supply Vrd side. It is possible. In the auxiliary shutter of the second comparative example, a separate vertical scanning circuit is required for setting the address of the thinning row. In this example, the interlocking process with the read operation row is performed like the shutter operation in the normal read operation. Is not necessary and may be performed at an appropriate timing that does not affect the control of the shutter operation row and the readout operation row. Since the vertical scanning circuit 14 can be used in the idle time, it is not necessary to prepare a special vertical scanning circuit. For example, the pixel reset pulse RST may be turned on for all thinning rows at an appropriate timing such as a V ranking period every several frames.

  Alternatively, as described above, if a depletion structure is used as the reset transistor 36, a leakage current can flow even when the reset transistor 36 is in an off state (when not selected). Naturally, the unnecessary charge accumulated in the floating diffusion 38 can be swept away to the reset power supply Vrd before the overflow of 38 occurs.

  When unnecessary charges are discharged to the reset power supply Vrd side using the characteristics of the reset transistor 36 having a depletion structure, if the intermediate potential is close to the potential that defines the H level, the amount of unnecessary charges increases rapidly. Since there is a concern that the discharge function of the unnecessary charge is not in time and the floating diffusion 38 is overflowed, in order to reliably discharge the unnecessary charge to the reset power supply Vrd without overflowing the floating diffusion 38, the intermediate potential is It is desirable that it is somewhat lower than the potential that defines the H level. A method for defining the intermediate potential in consideration of this point will be described in detail later.

<Configuration example of ternary drive circuit>
FIG. 15 is a diagram showing a configuration example of the transfer drive buffer BF1 for enabling ternary driving of the thinning-out transfer pulse TRG in the thinning-out reading mode. For reference, a reset driving buffer BF2 for pixel reset pulse RST and a selective driving buffer BF3 for vertical selection pulse VSEL corresponding to normal binary driving are also shown. FIG. 16 shows a truth table for explaining the operation of the transfer drive buffer BF1 shown in FIG.

  Although not shown, each of the drive buffers BF1, BF2, and BF3 is provided outside the solid-state imaging device 1 and has a first potential Vcc_H on the positive voltage side and an intermediate potential from a power supply circuit having a sufficiently small output impedance. The third potential Vcc_M and the third potential Vcc_L on the negative voltage side and the reference ground potential GND are supplied. Usually, the first potential Vcc_H is equal to the power supply potentials Vrd and Vdd (for example, about 3V) on the unit pixel 3 side, and the third potential Vcc_L is equal to the reference potential Vss (for example, about −1V).

  In relation to the binary output, the first potential Vcc_H corresponds to the H level, and the ground potential GND corresponds to the L level. In relation to the ternary output, the first potential Vcc_H corresponds to the H level, the second potential Vcc_M corresponds to the intermediate level, and the third potential Vcc_L corresponds to the L level.

  First, the reset drive buffer BF2 and the selection drive buffer BF3 will be described.

  As shown in FIG. 15, the reset drive buffer BF2 has an inverter 330 and an output buffer 348 that logically inverts the reset signal φRST generated by the vertical decoder 14a.

  The output buffer 348 is supplied with a first potential Vcc_H that defines the H level and a ground potential GND that defines the L level. For example, the output buffer 348 includes a p-channel transistor (p-type transistor) 348H and an n-channel transistor (n-type transistor) 348L arranged in series between the first potential Vcc_H and the ground potential GND. It has become the composition.

  The source of the p-type transistor 348H is connected to the first potential Vcc_H, and the source of the n-type transistor 348L is connected to the ground potential GND. The drains of the p-type transistor 348H and the n-type transistor 348L are connected in common, and the connection point is connected to the output terminal for the pixel reset pulse RST. The gates of the p-type transistor 348H and the n-type transistor 348L are connected in common, and the output of the inverter 330 (reset signal φNRST) is supplied to the connection point. As a whole, the p-type transistor 348H and the n-type transistor 348L are pixels for binary driving between the first potential Vcc_H and the ground potential GND based on the binary reset signal φRST supplied from the vertical decoder 14a. The CMOS inverter buffer is configured to output a reset pulse RST.

  For example, when the reset signal φRST supplied from the vertical decoder 14a is inactive L, the n-type transistor 348L is turned on (ON) and the p-type transistor 348H is turned off (OFF). L level corresponding to GND. Further, when the reset signal φRST supplied from the vertical decoder 14a is active H, the p-type transistor 348H is turned on (ON) and the n-type transistor 348L is turned off (OFF), so that the pixel reset pulse RST has the first potential. It becomes H level corresponding to Vcc_H.

  Similar to the reset drive buffer BF2, the selection drive buffer BF3 includes an inverter 350 and an output buffer 368 that logically inverts the vertical selection signal φVSEL generated by the vertical decoder 14a.

  The output buffer 368 is supplied with a first potential Vcc_H that defines the H level and a ground potential GND that defines the L level. For example, the output buffer 368 includes a p-channel transistor (p-type transistor) 368H and an n-channel transistor (n-type transistor) 368L arranged in series between the first potential Vcc_H and the ground potential GND. It has become the composition.

  The source of the p-type transistor 368H is connected to the first potential Vcc_H, and the source of the n-type transistor 368L is connected to the ground potential GND. The drains of the p-type transistor 368H and the n-type transistor 368L are connected in common, and the connection point is connected to the output terminal for the vertical selection pulse VSEL. The gates of the p-type transistor 368H and the n-type transistor 368L are connected in common, and the output of the inverter 350 (vertical selection signal φNVSEL) is supplied to the connection point. As a whole, the p-type transistor 368H and the n-type transistor 368L are for binary driving between the first potential Vcc_H and the ground potential GND based on the binary vertical selection signal φVSEL supplied from the vertical decoder 14a. The CMOS inverter buffer is configured to output a vertical selection pulse VSEL.

  For example, when the vertical selection signal φVSEL supplied from the vertical decoder 14a is inactive L, the n-type transistor 368L is turned on (ON) and the p-type transistor 368H is turned off (OFF), so that the vertical selection pulse VSEL is grounded. L level corresponding to the potential GND. When the vertical selection signal φVSEL supplied from the vertical decoder 14a is active H, the p-type transistor 368H is turned on (ON) and the n-type transistor 368L is turned off (OFF). It becomes an H level corresponding to the potential Vcc_H.

  On the other hand, the transfer drive buffer BF1 is configured to be able to generate a transfer pulse TRG for ternary driving based on the binary transfer signal φTRG and the intermediate potential setting signal G1 supplied from the vertical decoder 14a.

  That is, in the thinning readout mode, in order to always set the transfer pulse TRG for the thinning row to the intermediate potential, the vertical drive unit 14b of the vertical scanning circuit 14 in the configuration of the solid-state imaging device 1 shown in FIG. In the state where three types of voltages are supplied, the vertical decoder 14a determines the address of the thinning row based on an instruction from the communication / timing control unit 20, and the intermediate potential is always applied to the read selection transistor 34 of this thinning row. What is necessary is just to apply. On the other hand, a binary (H level and L level) transfer pulse TRG is supplied to the readout selection transistor 34 in the readout row, and one horizontal period (1H) at the time corresponding to the shutter operation row and the readout operation row. The read selection transistor 34 may be turned on at a predetermined timing.

  As shown in FIG. 15, the transfer drive buffer BF1 of this embodiment includes an inverter 310 that logically inverts the transfer signal φTRG generated by the vertical decoder 14a, and an inverter 312 that logically inverts the output of the inverter 310 (transfer signal φNTRG). And two-input type AND gates 316 and 318.

  Each of the AND gates 316 is an example of a ternary control signal G, and a control signal (indicated by “G2 with sharing” in the figure) indicating that the intermediate potential setting signal G1 and the thinning-out row share a read operation row. The logical product of Each of the AND gates 318 is an example of a ternary control signal G, and a control signal (indicated by “no sharing G3” in the figure) indicating that the intermediate potential setting signal G1 and the thinning-out row are not in a shared relationship with the read operation row. The logical product of The intermediate potential setting signal G1 is logic information that becomes active H only when the intermediate potential is set.

  The transfer drive buffer BF1 includes two-input type AND gates 320 and 322 and two-input type OR gates 324 and 326. In the AND gate 320, the output of the inverter 312 (transfer signal φTRG) is input to the first input terminal, and the intermediate potential setting signal G1 which is an example of the ternary control signal G is input to the second input terminal. The AND gate 322 takes the logical product of the logical product output of the AND gate 320 and the logical product output of the AND gate 318 and sets it as a transfer signal φMTRG. The OR gate 324 takes the logical sum of the output of the inverter 310 (transfer signal φNTRG) and the logical product output of the AND gate 316 to obtain a transfer signal φTRG. The OR gate 326 takes the logical sum of the output of the inverter 310 (transfer signal φNTRG) and the logical product output of the AND gate 320 as a transfer signal φNTRG.

  Note that the AND gate 318 is provided for symmetry with the AND gate 316, but in reality, the AND gate 320 functions with respect to the intermediate potential setting signal G1, so that the AND gate 318 is removed, and “unshared G3” is set. It may be supplied directly to the wiring Y1 of the AND gate 322. In addition, it can be considered that “G3 without sharing” is effectively a logical inversion of “G2 with sharing”. Instead of the AND gate 318, an inverter that logically inverts the output of “G2 with sharing” or the AND gate 316 is provided. You may make it substitute the output.

  The transfer drive buffer BF1 further includes an output buffer 328 similar to the inverter configuration so as to correspond to ternary output. The output buffer 328 is supplied with three types of voltages: a first potential Vcc_H on the positive voltage side, a second potential Vcc_M as an intermediate potential, and a third potential Vcc_L on the negative voltage side.

  As an example, the output buffer 328 has a configuration in which a p-channel transistor (p-type transistor) 328H and two n-channel transistors (n-type transistors) 328M and 328L arranged in parallel are arranged in series. It has become.

  The source of the p-type transistor 328H is connected to the first potential Vcc_H, the source of the n-type transistor 328M is connected to the second potential Vcc_M (for example, the ground potential GND), and the source of the n-type transistor 328L is connected to the third potential Vcc_L. ing. The drains of the p-type transistor 328H, the n-type transistor 328M, and the n-type transistor 328L are connected in common, and the connection point is connected to the output terminal for the transfer pulse TRG.

  The transfer signal φNTRG from the OR gate 326 is input to the gate of the p-type transistor 328H, the transfer signal φMTRG from the AND gate 322 is input to the gate of the n-type transistor 328M, and the OR gate is input to the gate of the n-type transistor 328L. The transfer signal φTRG from 324 is input.

  As a whole, the p-type transistor 328H and the n-type transistor 328L are for binary driving between the first potential Vcc_H and the third potential Vcc_L based on the binary transfer signal φTRG supplied from the vertical decoder 14a. The CMOS inverter buffer is configured to output the transfer pulse TRG. On the other hand, the n-type transistor 328M can set the intermediate potential to the transfer pulse TRG under certain conditions.

  For example, as in the truth table shown in FIG. 16, when the transfer signal φTRG supplied from the vertical decoder 14a is inactive L, the n-type transistor 328L is turned on (ON) regardless of the intermediate potential setting signal G1. Since the p-type transistor 328H and the n-type transistor 328M are turned off, the transfer pulse TRG becomes the L level corresponding to the third potential Vcc_L.

  Further, when the intermediate potential setting signal G1 supplied from the vertical decoder 14a is active H and the transfer signal φTRG is active H, when the shared G2 is active H, that is, the thinning row is shared with the readout row, When the intermediate potential setting signal G1 input at the time of thinning is active H, the n-type transistor 328L is turned on (ON) and the p-type transistor 328H and the n-type transistor 328M are turned off (OFF). It becomes L level corresponding to the potential Vcc_L.

  Further, when the intermediate potential setting signal G1 supplied from the vertical decoder 14a is active H and the transfer signal φTRG is active H, when no sharing G3 is active H, that is, the thinning-out row is not shared with the readout row. When the intermediate potential setting signal G1 input at the time of thinning is active H, the n-type transistor 328M is turned on (ON) and the p-type transistor 328H and the n-type transistor 328L are turned off (OFF). The M (intermediate) level corresponding to the two potentials Vcc_M.

  When the intermediate potential setting signal G1 supplied from the vertical decoder 14a is inactive L and the transfer signal φTRG is active H, the p-type transistor 328H is turned on, and the n-type transistor 328M and the n-type transistor 328L are turned on. Since it is turned off (OFF), the transfer pulse TRG becomes the H level corresponding to the first potential Vcc_H.

  As can be seen from FIG. 15, when the intermediate potential setting signal G1 is active H, the input to each gate terminal of the n-type transistor 328M and the n-type transistor 328L is shared G2 is active H or not shared G3 Depending on whether the active H is active, a circuit to gate is necessary, so the horizontal wiring Y1 and Y2 for two lines are increased, so that it is difficult to fit in the vertical pitch, which makes layout difficult. Accompany.

  The configuration example corresponding to the ternary drive of the transfer drive buffer BF1 shown here is merely an example, and various modifications can be adopted. For example, in principle, the truth table shown in FIG. 16 may be faithfully reflected. However, in practice, the p-type transistor 328H, the n-type transistor 328M, and the n-type are considered in terms of gate delay. A mechanism for slightly shifting the transition timing so as not to cause a period in which each of the transistors 328L, 328M, and 328H is turned on, in order to prevent occurrence of a through current due to any two or three of the transistors 328L being turned on simultaneously. It is possible to take.

  Here, the intermediate level or the intermediate potential M, which is an example of the blooming countermeasure potential, may be in a range excluding the H level and the L level in normal binary driving, and the H level is defined as the second potential Vcc_M. Any value may be used as long as it is a voltage level excluding the first potential Vcc_H and the third potential Vcc_L that define the L level.

  Since the potential at which charge overflow in thinning-out can be transferred to the floating diffusion 38 is the anti-blooming potential, originally, the active level (H level) is lower than the low potential that defines the inactive level (L level). Level) side potential and may be a potential that defines the H level. However, as will be described later, it is not a good idea to set the potential to the H level. , The potential that defines the H level is not used.

  That is, first, when it is excessively close to the third potential Vcc_L that defines the L level, the effect of preventing blooming is diminished, and when it is excessively close to the first potential Vcc_H that defines the H level, the read selection transistor 34 (transfer gate) is turned off. There is also a concern that even if a depletion structure is used as the reset transistor 36, the function of discharging unnecessary charges becomes insufficient and the floating diffusion 38 overflows even if the reset transistor 36 is used.

  For example, in order to increase the conversion efficiency when converting a signal charge into a voltage signal, it is necessary to reduce the capacitance (including parasitic capacitance) of the floating diffusion 38, and the floating diffusion 38 is likely to overflow. At this time, if there is an insufficient discharge capacity to the reset power supply Vrd via the depletion-type reset transistor 36, overflow is likely to occur.

  Considering that the use of the second potential Vcc_M is a countermeasure against blooming in the thinning-out reading mode, the optimum range of the second potential Vcc_M is that the unnecessary charge component overflowing from the thinning-out line easily flows to the floating diffusion 38 side. However, even if the exposure amount is large, it is sufficient that the unnecessary charge component overflowing from the thinning-out does not overflow the floating diffusion 38. Considering the above-described problems of reliability and dark current when the reset transistor 36 is always turned on, a voltage much lower than the first potential Vcc_H (for example, | first potential Vcc_H−third potential Vcc_L | 50% or less of the first potential Vcc_L) and a potential slightly higher than the third potential Vcc_L (for example, 10% or more with respect to | first potential Vcc_H−third potential Vcc_L |).

  As an example, if the first potential Vcc_H is about 3.0 to 3.3 V of the logic power supply voltage and the third potential Vcc_L is about −1 V, it is considered that −0.5 to 1.0 V or less is preferable. For example, the second potential Vcc_M can be fixed to 0 V, which is the ground potential GND.

  Note that there are pulses for driving the unit pixel 3 other than the transfer pulse TRG, and these pulses have a binary value (for example, 3.3V and −1V) for a certain purpose (the purpose is not specified here). In some cases, a ternary (or higher) driving scheme using an intermediate level (e.g., 0V) is used.

  Also, the transfer pulse TRG itself has an intermediate level (for example, 3.3 V and −1 V) at a certain timing (for example, 3.3 V and −1 V) at a certain timing for a certain purpose other than a countermeasure against blooming (the purpose is not specified here). In some cases, a ternary (or higher) driving method using 0V) is applied.

  In these cases, it is effective to make the circuit configuration compact by making the potential defining the intermediate level common to the second potential Vcc_M for preventing blooming in the present embodiment in the thinning-out reading mode. It is.

  That is, with respect to various pulses for driving the unit pixel 3, when a configuration in which three power sources are supplied to the vertical drive unit 14 b and the ternary pulse is used when the unit pixel 3 is driven has already been adopted, By using the intermediate potential that defines the intermediate level together with the second potential Vcc_M (intermediate potential) for the transfer pulse TRG for the thinning-out row used in this embodiment, it is not necessary to create a new voltage for the intermediate potential. There is an advantage that it is possible to cope with it only by changing the operation mode.

<Configuration example of switching drive circuit between ternary and floating>
FIG. 17 is a diagram showing a configuration example of the transfer driving buffer BF1 for switching the thinning-out transfer pulse TRG from the ternary driving state (which actually requires only the intermediate level) to the floating state in the thinning readout mode. Here, a modification to the configuration shown in FIG. 15 is shown.

  As can be seen from the comparison with FIG. 15, first, the n-type transistor 328M for setting the second potential Vcc_M (intermediate potential M defining the intermediate level) is removed. Further, a buffer 329 having an inhibit terminal INH is provided at the subsequent stage of the output buffer 328.

  In the buffer 329, the output of the output buffer 328 is input to the input terminal, the transfer signal φMTRG from the AND gate 320 is input to the inhibit terminal INH, and the transfer pulse TRG supplied to the read selection transistor 34 is output from the output terminal. Is done.

  The buffer 329 outputs the state of the input terminal (that is, the output logic of the output buffer 328) from the output terminal when the transfer signal φMTRG from the AND gate 322 input to the inhibit terminal INH is at the L level, and outputs when the transfer signal φMTRG is at the H level. Open the end.

  As a result, the transfer pulse TRG supplied to the read selection transistor 34 is generated between the first potential Vcc_H (for example, 3V) and the third potential Vcc_L (for example, −1V) when the transfer signal φMTRG from the AND gate 322 is at the L level. However, when the transfer signal φMTRG from the AND gate 322 is at the H level, the output terminal is opened to enter a floating state.

  The transfer signal φMTRG from the AND gate 322 becomes H level when the intermediate potential setting signal G1 supplied from the vertical decoder 14a is active H and the transfer signal φTRG is active H, as in FIG. And when there is no sharing. Therefore, in the thinning readout mode, the readout gate of the thinning out row (non-selected row) (the gate end of the readout selection transistor 34) is floated in consideration of whether or not the pixel is shared with the readout operation row. it can.

<Imaging device>
FIG. 18 is a diagram illustrating a schematic configuration of an imaging apparatus which is an example of a physical information acquisition apparatus using a mechanism similar to that of the solid-state imaging apparatus 1 of the present embodiment described above. The imaging device 8 is an imaging device that obtains a visible light color image.

  Control of imaging mode switching between the all-pixel readout mode and the thinning readout mode, or control such as correspondence of ternary driving and floating output in the transfer drive buffer BF1 at the time of thinning readout is performed by an external main control unit. A switching instruction or the like can be arbitrarily designated by data setting for the communication / timing control unit 20.

  The mechanism of the solid-state imaging device 1 described above can be applied not only to the solid-state imaging device but also to the imaging device. In this case, the imaging device also takes into account the pixel sharing structure (that is, thinning-out) so that the charges overflowing in the thinning-out charge generation unit 32 are easily transferred to the floating diffusion 38 side in the thinning-out reading mode. By executing control at a blooming countermeasure potential such that the transfer pulse TRG supplied to the read selection transistor 34 is an intermediate potential M or floating, depending on whether or not is shared with the read operation row) It will be possible to realize a mechanism to suppress this. Good image quality can be maintained in all imaging modes.

  In addition, if the decimation row is not in a shared relationship with the read operation row, the transfer pulse TRG of the decimation row is set to the blooming countermeasure potential. Therefore, it is possible to prevent the fluctuation of the signal level due to the leakage of the signal from the charge generation unit 32 in the thinning-out row to the pixel signal generation unit 5 (particularly, the floating diffusion 38) in the readout operation row.

  Specifically, the imaging device 8 includes a photographing lens 802 that guides light L carrying the image of the subject Z under the illumination device 801 such as a fluorescent lamp to the imaging device side, and an optical low-pass filter. 804, a color filter group 812 in which, for example, R, G, and B color filters are arranged in a Bayer array, a pixel array unit 10, a drive control unit 7 that drives the pixel array unit 10, and an output from the pixel array unit 10 A column processing unit 26 that performs CDS processing, AD conversion processing, and the like on the processed pixel signal, a reference signal generation unit 27 that supplies a reference signal Vslop to the column processing unit 26, and an imaging signal output from the column processing unit 26 Is provided with a camera signal processing unit 810.

  The optical low-pass filter 804 is for blocking high frequency components higher than the Nyquist frequency in order to prevent aliasing distortion. Further, as indicated by a dotted line in the drawing, an infrared light cut filter 805 that reduces the infrared light component can be provided in combination with the optical low-pass filter 804. This is the same as a general imaging device.

  The camera signal processing unit 810 provided at the subsequent stage of the column processing unit 26 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8.

  The imaging signal processing unit 820 outputs digital imaging signals supplied from the AD conversion function unit of the column processing unit 26 when a color filter other than the primary color filter is used as R (red), G (green), B A signal separation unit 822 having a primary color separation function that separates into (blue) primary color signals, and a color signal that performs signal processing on the color signal C based on the primary color signals R, G, and B separated by the signal separation unit 822 And a processing unit 830.

  The imaging signal processing unit 820 also converts the luminance signal Y / color signal C into a luminance signal processing unit 840 that performs signal processing on the luminance signal Y based on the primary color signals R, G, and B separated by the signal separation unit 822. And an encoder unit 860 that generates a video signal VD based on the encoder 860.

  Although not shown, the color signal processing unit 830 includes, for example, a white balance amplifier, a gamma correction unit, a color difference matrix unit, and the like. The white balance amplifier adjusts the gain of the primary color signal supplied from the primary color separation function unit of the signal separation unit 822 (white balance adjustment) based on the gain signal supplied from a white balance controller (not shown), and the gamma correction unit and brightness The signal is supplied to the signal processing unit 840.

  The gamma correction unit performs gamma (γ) correction for faithful color reproduction based on the primary color signal whose white balance is adjusted, and outputs the output signals R, G, and B for each color subjected to gamma correction as a color difference matrix unit To enter. The color difference matrix unit inputs the color difference signals RY and BY obtained by performing the color difference matrix processing to the encoder unit 860.

  Although not shown, the luminance signal processing unit 840 generates, for example, a high frequency signal that generates a luminance signal YH including a component having a relatively high frequency based on the primary color signal supplied from the primary color separation function unit of the signal separation unit 822. A luminance signal generation unit; a low frequency luminance signal generation unit that generates a luminance signal YL including only a component having a relatively low frequency based on a primary color signal adjusted from white balance supplied from a white balance amplifier; A luminance signal generation unit that generates the luminance signal Y based on the luminance signals YH and YL and supplies the luminance signal Y to the encoder unit 860;

  The encoder unit 860 digitally modulates the color difference signals RY and BY with a digital signal corresponding to the color signal subcarrier, and then synthesizes the digital image with the luminance signal Y generated by the luminance signal processing unit 840. The signal is converted into a signal VD (= Y + S + C; S is a synchronization signal, and C is a chroma signal).

  The digital video signal VD output from the encoder unit 860 is further supplied to a camera signal output unit that is not shown in the subsequent stage, and is used for monitor output, data recording on a recording medium, and the like. At this time, the digital video signal VD is converted into the analog video signal V by DA conversion as necessary.

  The camera control unit 900 of the present embodiment is a microprocessor that forms the center of an electronic computer whose representative example is a CPU (Central Processing Unit) in which calculation and control functions performed by a computer are integrated into an ultra-small integrated circuit. 902, a ROM (Read Only Memory) 904 that is a read-only storage unit, a RAM (Random Access Memory) 906 that is an example of a volatile storage unit that can be written and read at any time, and others that are not illustrated The peripheral member is included. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  In the above description, the “volatile storage unit” means a storage unit in which the stored contents are lost when the power of the apparatus is turned off. On the other hand, the “nonvolatile storage unit” means a storage unit in a form that keeps stored contents even when the main power supply of the apparatus is turned off. Any memory device can be used as long as it can retain the stored contents. The semiconductor memory device itself is not limited to a nonvolatile memory device, and a backup power supply is provided to make a volatile memory device “nonvolatile”. You may comprise as follows.

  Further, the present invention is not limited to a semiconductor memory element, and may be configured using a medium such as a magnetic disk or an optical disk. For example, a hard disk device can be used as a nonvolatile storage unit. In addition, it is possible to use as a nonvolatile storage unit by adopting a configuration for reading information from a recording medium such as a CD-ROM.

  The camera control unit 900 controls the entire system. In particular, in relation to the above-described blooming countermeasure potential control of the transfer pulse TRG supplied to the readout selection transistor 34, the transfer pulse TRG is driven in three values or “2”. It has a function of adjusting the on / off timing of various control pulses for “value driving + floating”.

  The ROM 904 stores a control program for the camera control unit 900. In this example, in particular, the camera control unit 900 stores a program for setting on / off timings of various control pulses.

  The RAM 906 stores data for the camera control unit 900 to perform various processes.

  The camera control unit 900 is configured so that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, a convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). To register data such as various set values such as on / off timing of various control pulses for controlling the blooming potential to make the transfer pulse TRG ternary drive or “binary drive + floating” Used.

  The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In addition, although such an imaging device 8 shows the drive control unit 7 and the column processing unit 26 in a module form separately from the pixel array unit 10, as described for the solid-state imaging device 1, Needless to say, the one-chip solid-state imaging device 1 integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used.

  In addition, in the figure, in addition to the pixel array unit 10, the drive control unit 7, the column processing unit 26, the reference signal generation unit 27, and the camera signal processing unit 810, a photographing lens 802, an optical low-pass filter 804, or an infrared light cut filter The image pickup apparatus 8 is shown in a state including an optical system such as 805, and this aspect is suitable for a module-like form having an image pickup function packaged together.

  Here, in relation to the modules in the solid-state imaging device 1 described above, as shown in the figure, the pixel array unit 10 (imaging unit), the column processing unit 26 having an AD conversion function and a difference (CDS) processing function, and the like A solid-state imaging device in the form of a module having an imaging function in a state where signal processing units closely related to the pixel array unit 10 side (excluding the camera signal processing unit following the column processing unit 26) are packaged together 1 is provided, and a camera signal processing unit 810, which is the remaining signal processing unit, is provided in the subsequent stage of the solid-state imaging device 1 provided in the module form so that the entire imaging device 8 is configured. Also good.

  Alternatively, although not shown, the solid-state imaging device 1 is provided in a modular form having an imaging function in a state where the pixel array unit 10 and the optical system such as the photographing lens 802 are packaged together. In addition to the solid-state imaging device 1 provided in the form of a module, a camera signal processing unit 810 may be provided in the module to constitute the entire imaging device 8.

  Further, as a module form in the solid-state imaging device 1, a camera signal processing unit 810 corresponding to the camera signal processing unit 200 may be included. In this case, the solid-state imaging device 1 and the imaging device 8 are practically the same. It can also be regarded as a thing.

  Such an imaging device 8 is provided as a portable device having an imaging function, for example, for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  The imaging device 8 having such a configuration is configured to include all the functions of the solid-state imaging device 1 described above, and can be the same as the basic configuration and operation of the solid-state imaging device 1 described above. Considering whether or not the thinning-out row is in a shared relationship with the read-out operation row so that the blooming phenomenon caused by the leakage of the charge overflowing from the charge generation unit 32 of the thinning-out row into the adjacent readout operation row is suppressed. As a result, it is possible to realize a mechanism for controlling the blooming potential such that the transfer pulse TRG to the thinning-out row is ternary driving or “binary driving + floating”.

  For example, a program that causes a computer to execute the above-described processing is distributed through a recording medium 924 such as a non-volatile semiconductor memory card such as a flash memory, an IC card, or a miniature card. Furthermore, the program may be downloaded and acquired from a server or the like via a communication network such as the Internet, or may be updated.

  In a semiconductor memory such as an IC card or a miniature card as an example of the recording medium 924, a part or all of the processing in the solid-state imaging device 1 described in the embodiment (particularly in the thinning readout mode, the pixel sharing structure is considered. It is possible to store a function of a part relating to blooming countermeasure potential control in which the transfer pulse TRG is ternary driving or “binary driving + floating”. Therefore, a program and a storage medium storing the program can be provided.

  For example, an anti-blooming potential control process program for performing ternary drive control of the transfer pulse TRG, that is, an anti-blooming potential control process software installed in the RAM 906 or the like is the anti-blooming potential control described for the solid-state imaging device 1. Similar to the processing, the control pulse setting function for realizing the blooming countermeasure potential control processing for suppressing the blooming phenomenon at the time of thinning-out reading is provided as software.

  The software is executed by the microprocessor 902 after being read into the RAM 906. For example, the microprocessor 902 executes a control pulse setting process based on a program stored in the ROM 904 and the RAM 906, which are examples of recording media, so that the transfer supplied to the read selection transistor 34 in the thinning row is performed in the thinning readout mode. By using the pulse TRG as a countermeasure against blooming at all times (for example, the intermediate potential M or floating), the function of suppressing the blooming phenomenon that the charge generated in the charge generation unit 32 of the thinning-out row overflows and leaks into the adjacent read operation row is software-like Can be realized.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Moreover, the said embodiment does not limit the invention concerning a claim (claim), and all the combinations of the characteristics demonstrated in embodiment are not necessarily essential for the solution means of invention. . The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, in the above-described embodiment, the blooming phenomenon to the pixels adjacent in the vertical direction in the row thinning driving and the countermeasures thereof have been described. However, the technical idea of the above embodiment can be similarly applied to the thinning in the column direction. Further, the pixel sharing relationship is not limited to a sharing relationship in a plurality of rows, but may be a sharing relationship in a plurality of columns. Furthermore, the driving of row thinning and the sharing relationship in a plurality of columns are not limited to the case where the direction of the thinning and the direction of the sharing relationship coincide with each other, such as the row thinning driving and the sharing relationship in a plurality of rows. It may be the case where the direction of thinning and the direction of the sharing relationship do not match, such as driving column thinning and a shared relationship in a plurality of rows.

  For example, with regard to row thinning, thinning readout is performed under the control of the vertical scanning circuit 14 as described above, and the pixel signals of each column thus read are controlled by the horizontal scanning circuit 12 in the horizontal direction. The decimation transfer may be performed under the above. Alternatively, thinning readout may be performed in the row direction and the column direction by setting a readout address for the pixel array unit 10 in a mechanism that can be freely set by the XY address method. Further, during thinning processing in the row direction (horizontal direction), for a column that is not read, the load current (read current) supplied to the vertical signal line 19 by the read current source unit 24 is stopped to reduce power consumption. It is good to do so.

It is a schematic block diagram of the CMOS solid-state imaging device which is one Embodiment of the solid-state imaging device concerning this invention. It is a figure which shows the example of arrangement | positioning layout of each component which comprises the unit pixel group used for the solid-state imaging device shown in FIG. FIG. 2 is a diagram illustrating a configuration example of a unit pixel group used in the solid-state imaging device illustrated in FIG. 1 and a connection mode of a drive unit, a drive control line, and a pixel transistor. FIG. 3 is a schematic diagram of a concentration distribution cross-sectional structure in a B-B ′ cross-sectional line and a C-C ′ cross-sectional line focusing on a charge generation unit and a floating diffusion of unit pixels constituting the unit pixel group illustrated in FIG. 2. FIG. 4 is an example of a potential cross-sectional view taken along a line A-A ′ in FIG. 3 and a line B-B ′ in FIG. 2. 3 is a timing chart for explaining signal acquisition difference processing, which is a basic operation in the column AD circuit of the solid-state imaging device shown in FIG. 1. It is a figure which paid its attention to the pixel array part explaining the 1st comparative example with respect to the pixel drive system at the time of thinning-out reading mode of this embodiment. 6 is a timing chart for explaining a first comparative example for a pixel driving method in a thinning readout mode according to the present embodiment. It is a figure which paid its attention to the pixel array part explaining the 2nd comparative example with respect to the pixel drive system at the thinning-out reading mode of this embodiment. 10 is a timing chart for explaining a second comparative example for the pixel driving method in the thinning readout mode according to the present embodiment. It is a figure which paid its attention to the pixel array part explaining the 3rd comparative example with respect to the pixel drive system at the time of thinning readout mode of this embodiment. 12 is a timing chart for explaining a third comparative example with respect to the pixel driving method in the thinning readout mode according to the present embodiment. FIG. 11 is a schematic diagram for explaining a problem that occurs in a pixel signal when the third comparative example shown in FIGS. 9 and 10 is applied when the pixel array unit is a pixel sharing method. It is a figure which paid its attention to the pixel array part explaining the pixel drive system at the time of thinning-out reading mode of this embodiment. 6 is a timing chart illustrating a pixel driving method in a thinning readout mode according to the present embodiment. FIG. 14 is a schematic diagram for explaining an effect when the driving method of the present embodiment shown in FIGS. 12 and 13 is applied when the pixel array unit is a pixel sharing method. It is a figure which shows the structural example of the transfer drive buffer for enabling ternary drive of the transfer pulse of a thinning line at the thinning-out reading mode. 16 is a truth table for explaining the operation of the transfer drive buffer shown in FIG. It is a figure which shows the structural example of the transfer drive buffer for switching the transfer pulse of a thinning line from a binary drive state to a floating state at the thinning-out reading mode. It is a figure which shows schematic structure of the imaging device which is an example of the physical information acquisition apparatus using the structure similar to the solid-state imaging device of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Unit pixel group, 3 ... Unit pixel, 10 ... Pixel array part, 12 ... Horizontal scanning circuit, 12a ... Horizontal decoder, 12b ... Horizontal drive part, 14 ... Vertical scanning circuit, 14a ... Vertical decoder , 14b ... vertical drive unit, 15 ... row control line, 18 ... horizontal signal line, 19 ... vertical signal line, 20 ... communication / timing control unit, 24 ... read current source unit, 25 ... column AD circuit, 252 ... voltage comparison Unit, 254 ... counter unit, 256 ... data storage unit, 258 ... switch, 26 ... column processing unit, 27 ... reference signal generation unit, 27a ... DA conversion circuit, 28 ... output circuit, 32 ... charge generation unit, 34 ... reading Selection transistor, 36 ... reset transistor, 38 ... floating diffusion, 40 ... vertical selection transistor, 42 ... amplification transistor, 5 ... pixel signal generator, 2 ... vertical selection line, 53 ... vertical signal line, 55 ... transfer wiring, 56 ... reset wiring, 7 ... drive control unit, 8 ... imaging device, 900 ... camera control unit, BF1 ... transfer drive buffer, BF2 ... reset drive buffer , BF3: Selection drive buffer

Claims (14)

A detection unit that detects a change in physical quantity by electric charge, a pixel signal generation unit that converts the electric charge detected by the detection unit into a pixel signal, and an electric charge detected by the detection unit based on an input transfer control potential A plurality of unit pixels include some of the unit pixels having a transfer unit that transfers to the signal generation unit and an initialization unit that initializes the potential of the pixel signal generation unit based on the input initialization control potential A pixel array unit in which unit pixel groups having a configuration shared in a matrix are arranged, and
A drive control unit for controlling the unit pixel in a thinning readout mode for reading out pixel signals of some unit pixels of the pixel array unit;
In the thinning readout mode, the drive control unit generates the pixel signal of the unit pixel in which the charges overflowing in the detection unit are thinned out for the unit pixel that is thinned out that is not shared with the unit pixel to be read out The control unit controls the blooming countermeasure potential, which is the transfer control potential supplied to the transfer unit of the thinned unit pixel so that the unit pixel is easily transferred to the unit side, and is in a shared relationship with the read unit pixel. A solid-state imaging device, wherein the transfer unit of the unit pixels to be thinned is controlled to supply a potential on the inactive side with respect to the blooming countermeasure potential as the transfer control potential. The solid-state imaging device according to claim 1, wherein the drive control unit sets the thinned unit pixels in units of rows or columns. The drive control unit supplies the transfer control potential supplied to the transfer unit of the unit pixels to be thinned out according to a point in time when the unit pixel to be read is actually a readout operation target pixel. The solid-state imaging device according to claim 1, wherein switching is performed between a potential on the inactive side with respect to the blooming countermeasure potential. The drive control unit performs binary driving with respect to the transfer unit of the unit pixel to be read with a potential that defines an inactive level and the transfer control potential that defines an active level, and the unit pixel to be thinned out. 2. The solid-state imaging device according to claim 1, wherein a potential on the active level side of a potential defining the inactive level is supplied to the transfer unit as the blooming countermeasure potential. The drive control unit performs binary driving with the transfer control potential including a potential that defines an inactive level and a potential that defines an active level for the transfer unit of the unit pixel to be read, and the thinning-out. 5. The intermediate potential between a potential defining the inactive level and a potential defining the active level is supplied to the transfer unit of the unit pixel as the blooming countermeasure potential. The solid-state imaging device described in 1. The drive control unit includes a potential defining an inactive level, a potential defining an active level, and at least one intermediate potential between a potential defining the inactive level and a potential defining the active level 5. The solid-state imaging device according to claim 4, wherein an element constituting the unit pixel is driven with a potential of three or more and the intermediate potential of the three values is used as the blooming countermeasure potential. . The drive control unit has a potential that defines an inactive level, a potential that defines an active level, and a potential that defines the inactive level and a potential that defines the active level, other than the purpose of the anti-blooming potential. The transfer control potential including at least one intermediate potential is driven with three or more values, and the intermediate potential of the three values is used as the blooming countermeasure potential. 6. The solid-state imaging device according to 6. The drive control unit includes a potential defining an inactive level, a potential defining an active level, and at least one intermediate potential between a potential defining the inactive level and a potential defining the active level The solid-state imaging device according to claim 6, wherein the initialization unit is driven with three or more initialization control potentials, and the intermediate potential of the three values is used as the blooming countermeasure potential. . The drive control unit performs binary driving with the transfer control potential including a potential that defines an inactive level and a potential that defines an active level for the transfer unit of the unit pixel to be read, and the thinning-out. The solid-state imaging device according to claim 1, wherein a floating state having no potential is supplied as the blooming countermeasure potential to the transfer unit of the unit pixel. The drive control unit performs binary driving with respect to the transfer unit of the unit pixel to be read with a potential that defines an inactive level and the transfer control potential that defines an active level, and the unit pixel to be thinned out. The solid-state imaging device according to claim 1, wherein a potential defining the inactivity level is supplied to the transfer unit as a potential on the inactive side with respect to the blooming countermeasure potential. The solid-state imaging device according to claim 1, wherein the initialization unit includes a transistor having a depletion structure. The drive control unit controls the initialization unit of the thinned unit pixel to discharge the charge transferred to the pixel signal generation unit by supplying the anti-blooming potential to the transfer unit. The solid-state imaging device according to claim 1. A detection unit that detects a change in physical quantity by electric charge, a pixel signal generation unit that converts the electric charge detected by the detection unit into a pixel signal, and an electric charge detected by the detection unit based on an input transfer control potential A plurality of unit pixels include some of the unit pixels having a transfer unit that transfers to the signal generation unit and an initialization unit that initializes the potential of the pixel signal generation unit based on the input initialization control potential A pixel array unit in which unit pixel groups having a configuration shared in a matrix are arranged, and
A drive control unit for controlling the unit pixels in a thinning-out reading mode for reading out pixel signals of some unit pixels of the pixel array unit;
A main control unit that instructs the drive control unit to generate the control potential for controlling the unit pixel;
In the thinning readout mode, the drive control unit generates the pixel signal of the unit pixel in which the charges overflowing in the detection unit are thinned out for the unit pixel that is thinned out that is not shared with the unit pixel to be read out The control unit controls the blooming countermeasure potential, which is the transfer control potential supplied to the transfer unit of the thinned unit pixel so that the unit pixel is easily transferred to the unit side, and is in a shared relationship with the read unit pixel. An image pickup apparatus, wherein the transfer unit of the unit pixel to be thinned is controlled so as to supply a potential on an inactive side with respect to the blooming countermeasure potential as the transfer control potential. The main control unit controls the drive control unit to read out pixel signals from all unit pixels in the pixel array unit, and reads out pixel signals from some unit pixels in the pixel array unit. The imaging apparatus according to claim 13, wherein the thinning readout mode is switched.

Images