JP2012244055A - Manufacturing method of semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor element capable of simplifying a manufacturing step of the semiconductor element.SOLUTION: A manufacturing method of a semiconductor light-emitting element 100 comprises the steps of forming a current constriction layer 10 above an n-type substrate 20, and forming a current constriction part 14 composed of the current constriction layer 10 by etching the current constriction layer 10, and then forming an alignment mark 12 composed of the current constriction layer 10 on a region different from the current constriction part 14. This allows a manufacturing step of the semiconductor element to be simplified using the alignment mark.

Description

  The present invention relates to a method for manufacturing a semiconductor element.

  In manufacturing a semiconductor element, for example, an alignment mark for use in a photolithography process may be formed. By performing alignment using this alignment mark, it becomes easy to realize accurate photolithography. Examples of the technique related to the alignment mark include those described in Patent Documents 1 to 3.

  The technique described in Patent Document 1 relates to an epitaxial wafer for light-emitting diodes, and creates irregularities between the current blocking unit and the substrate, thereby forming irregularities on the surface of the epitaxial layer grown on the current blocking unit. That's it. The technique described in Patent Document 2 uses the etching rate difference between the InP buried region and the InP clad layer and the active layer to leave the portion below the active layer in the mark mesa. The technique described in Patent Document 3 is to suppress the disappearance of the insulating film by providing a cap layer on the insulating film covering the alignment mark.

JP 2003-133586 A JP 2009-111088 A JP 2007-165538 A

  In the case of forming the alignment mark, another process for forming the alignment mark is required in addition to the process for manufacturing the semiconductor element. In this case, the manufacture of the semiconductor element becomes complicated. Therefore, it is required to simplify the manufacturing process of the semiconductor element.

The outline of typical inventions among the inventions disclosed in the present invention will be briefly described as follows.
According to a method for manufacturing a semiconductor device according to an embodiment of the present invention, a step of forming a first semiconductor layer on a substrate;
Etching the first semiconductor layer to form a current confinement portion made of the first semiconductor layer and forming an alignment mark made of the first semiconductor layer in a region different from the current confinement portion;
Is provided.

  According to one embodiment of the present invention, the semiconductor layer is etched to form the current constriction and the alignment mark. For this reason, another process for forming the alignment mark is not required. Therefore, the manufacturing process of the semiconductor element using the alignment mark can be simplified.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, the manufacturing process of the semiconductor element can be simplified.

It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 1st Embodiment. 1 is a cross-sectional view showing a semiconductor element according to a first embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor element which concerns on 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

1 to 4 are cross-sectional views illustrating a method for manufacturing the semiconductor light emitting device 100 according to the first embodiment. FIG. 5 is a cross-sectional view showing the semiconductor light emitting device 100 according to the first embodiment. In the method of manufacturing the semiconductor light emitting device 100 according to the present embodiment, the step of forming the current confinement layer 10 on the n-type substrate 20 and the current confinement portion 14 made of the current confinement layer 10 by etching the current confinement layer 10. And forming an alignment mark 12 made of the current confinement layer 10 in a region different from the current confinement portion 14.
The semiconductor light emitting device 100 in the present embodiment is a nitride semiconductor light emitting device.

In the present embodiment, alignment is performed by an LSA (Laser Step Alignment) method. In alignment by the LSA method, alignment is performed by irradiating an alignment beam toward the alignment mark and detecting light diffracted or scattered by the alignment mark. For example, the alignment marks are arranged in a dot shape on the substrate.
As the alignment beam, for example, a HeNe (helium neon) laser is used. The HeNe laser has a wavelength of about 633 nm.
The alignment may be performed by, for example, an FIA (Field Image Alignment) method, an LIA (Laser Interferometric Alignment) method, or the like.

  Next, the configuration of the semiconductor light emitting element 100 will be described. As shown in FIG. 5, the semiconductor light emitting device 100 includes an n-type buffer layer 22, an n-type cladding layer 24, an n-side optical confinement layer 26, an active layer 28, a cap layer 30, p, The side optical confinement layer 32, the current confinement layer 10, the p-type cladding layer 34, and the p-type contact layer 36 are laminated in this order. An n-side electrode 50 is provided on the other surface of the n-type substrate 20 opposite to the one surface. A p-side electrode 52 is provided on the p-type contact layer 36.

  The n-type substrate 20 is made of, for example, a GaN substrate. The n-type buffer layer 22 is made of, for example, GaN. The film thickness of the n-type buffer layer 22 is, for example, 1 μm. The n-type cladding layer 24 is made of, for example, AlGaN. Further, the film thickness of the n-type cladding layer 24 is, for example, 2 μm. The n-side optical confinement layer 26 is made of, for example, GaN. The film thickness of the n-side optical confinement layer 26 is, for example, 0.1 μm.

  The active layer 28 has a multiple quantum well structure including, for example, an InGaN well layer and an InGaN barrier layer. The cap layer 30 is made of, for example, AlGaN. The film thickness of the cap layer 30 is, for example, 10 nm. The p-side optical confinement layer 32 is made of, for example, GaN. The film thickness of the p-side light confinement layer 32 is, for example, 0.1 μm.

  The current confinement layer 10 has a current confinement portion 14. The current confinement portion 14 has openings provided in a stripe shape in plan view, for example, and forms a current path in the semiconductor light emitting device 100. The current confinement layer 10 is made of, for example, AlN. The current confinement layer 10 may be made of AlGaN having an Al composition higher than the average Al composition of the p-type cladding layer 34. The film thickness of the current confinement layer 10 is, for example, 0.1 μm. Moreover, the opening part which the current confinement part 14 has has a width | variety of 1-2 micrometers, for example.

The p-type cladding layer 34 is provided on the current confinement layer 10 and on the opening provided in the current confinement layer 10. The p-type cladding layer 34 and the p-type contact layer 36 are provided, for example, so that the surfaces are flat.
The p-type cladding layer 34 and the p-type contact layer 36 are made of a material that is transparent to the alignment beam used in the alignment. Thereby, the alignment mark 12 covered with the p-type cladding layer 34 and the p-type contact layer 36 can be detected in the alignment step described later. The p-type cladding layer 34 has a 130-period superlattice structure made of, for example, GaN and AlGaN. In this case, for example, a layer made of GaN in the p-type cladding layer 34 has a thickness of 2.5 nm, and a layer made of AlGaN in the p-type cladding layer 34 has a thickness of 2.5 nm. The p-type contact layer 36 is made of, for example, GaN. The film thickness of the p-type contact layer 36 is, for example, 0.1 μm.

The refractive index of the layer formed of the p-type cladding layer 34 and the p-type contact layer 36 is, for example, 2.5 to 2.54. Moreover, the refractive index of the current confinement layer 10 is, for example, 2.1 to 2.3. Since the refractive index of the layer composed of the p-type cladding layer 34 and the p-type contact layer 36 and the refractive index of the current confinement layer 10 are different, there is a difference in the reflectance of the alignment beam. Thereby, the alignment beam 12 is diffracted or scattered, and the alignment mark 12 can be detected.
Further, since the refractive index of the current confinement layer 10 is lower than the refractive index of the p-type cladding layer 34, the average refractive index of the region having the opening provided in the current confinement layer 10 is the average of other regions. Higher than the refractive index. Thereby, the light is distributed so as to gather in the region having the opening. Thus, the current confinement layer 10 has a function of controlling the light distribution in the plane direction horizontal to the substrate surface.

  An n-type impurity used in the semiconductor light emitting device 100 is, for example, Si. The p-type impurity is, for example, Mg.

Next, a method for manufacturing the semiconductor light emitting device 100 according to this embodiment will be described.
First, as shown in FIG. 1A, an n-type buffer layer 22, an n-type cladding layer 24, an n-side optical confinement layer 26, an active layer 28, a cap layer 30, and a p-side optical confinement are formed on an n-type substrate 20. The layer 32 and the current confinement layer 10 are stacked in this order. The n-type buffer layer 22, the n-type cladding layer 24, the n-side optical confinement layer 26, the active layer 28, the cap layer 30, the p-side optical confinement layer 32 and the current confinement layer 10 are formed on the n-type substrate 20. This is done by epitaxial growth in order.

First, after putting the n-type substrate 20 into the MOVPE apparatus, the temperature of the n-type substrate 20 is raised while supplying ammonia. Next, when the growth temperature is reached, epitaxial growth is started. Then, after the epitaxial growth is completed, the n-type substrate 20 on which the stacked structure shown in FIG. 1A is formed is taken out from the MOVPE apparatus.
The growth temperature is 200 to 800 ° C. for the current confinement layer 10, 800 ° C. for the active layer 28, and 1100 ° C. for the other layers. Since the current confinement layer 10 is grown at a low temperature, it is amorphous in the state shown in FIG.

  In the epitaxial growth step, a 300 hPa reduced pressure MOVPE apparatus is used. As the carrier gas, a mixed gas of hydrogen and nitrogen is used. As sources of Ga, Al, and In, for example, trimethylgallium, trimethylaluminum, and trimethylindium are used, respectively. For example, silane is used as the n-type impurity. As the p-type impurity, for example, biscyclopentadienyl magnesium is used.

Next, an insulating film 70 is deposited on the current confinement layer 10. The insulating film 70 is made of, for example, SiO ₂ . Next, a resist 60 is applied on the insulating film 70. Then, as shown in FIG. 1B, the resist 60 is selectively removed by photolithography to form a resist mark 62. At this time, an opening 64 described later is not formed. For example, the resist mark 62 is constituted by a portion remaining after the resist 60 is removed.
The registration mark 62 functions as an alignment mark in the step of forming an opening 64 described later. Therefore, a plurality of registration marks 62 are formed so as to be arranged in a dot shape, for example. Further, the resist mark 62 is provided, for example, in an alignment mark formation region where the semiconductor light emitting element 100 is not formed.

  In photolithography for forming the resist mark 62, for example, contact exposure or stepper exposure can be used. About these exposure methods, it can select suitably according to the objective.

Next, as shown in FIG. 2A, an opening 64 is formed in the resist 60. The opening 64 is formed by selectively removing the resist 60 by photolithography. In the photolithography, the reticle is first aligned with reference to the resist mark 62 as an alignment mark. Then, after exposure using a reticle, development is performed to selectively remove the resist 60.
In the photolithography, for example, contact exposure or stepper exposure can be used, and can be appropriately selected according to the purpose. For example, when stepper exposure is used, the opening 64 having a fine opening width of about 1 to 2 μm can be formed with high dimensional accuracy. The opening 64 is provided for each of the plurality of semiconductor light emitting elements 100 formed in the manufacturing method according to this embodiment.
Next, the insulating film 70 is selectively removed by etching using the resist 60 as a mask.

  In the present embodiment, the resist 60 used for photolithography for forming the resist mark 62 can be used for photolithography for forming a mask used for etching the insulating film 70. That is, the same resist 60 can be used in these different photolithography. For this reason, it is not necessary to reapply a resist in photolithography for forming a mask used for etching the insulating film 70. Thereby, manufacture of a semiconductor element becomes easy.

  Next, the current confinement layer 10 is selectively removed by etching using the resist 60 and the insulating film 70 as a mask. Next, the resist 60 and the insulating film 70 are removed to obtain the structure shown in FIG. As a result, as shown in FIG. 2B, the current confinement portion 14 having an opening formed corresponding to the opening 64 is formed. In addition, the alignment mark 12 formed corresponding to the resist mark 62 is formed. Thus, the alignment mark 12 is constituted by a portion of the current confinement layer 10 remaining after etching. The alignment mark 12 is formed so as to be located in a region different from the current confinement portion 14.

  The current confinement portion 14 includes a current confinement layer 10 and an opening formed in the current confinement layer 10. In addition, the current confinement part 14 is provided for each of the plurality of semiconductor light emitting elements 100 formed by the manufacturing method according to the present embodiment. The plurality of current confinement portions 14 are provided continuously with each other, for example.

  The alignment marks 12 correspond to the registration marks 62, and a plurality of alignment marks 12 are provided so as to be arranged in a dot shape, for example. Moreover, the alignment mark 12 is arrange | positioned at the alignment formation area | region in which the semiconductor light emitting element 100 is not formed, for example. Further, as shown in FIG. 2B, the alignment mark 12 is constituted by a portion of the current confinement layer 10 remaining after etching.

  According to the present embodiment, the alignment mark 12 can be formed using the resist mark 62 formed as an alignment mark used in photolithography for forming the opening 64. For this reason, it is not necessary to newly provide a resist pattern for forming the alignment mark 12. Therefore, the manufacturing process of the semiconductor element can be simplified and the manufacturing cost can be reduced.

In the etching of the current confinement layer 10, for example, a mixture of phosphoric acid and sulfuric acid maintained at 50 to 200 ° C. can be used as an etching solution.
In the step of etching the current confinement layer 10, the current confinement layer 10 has an amorphous shape that can be easily etched. Further, when the p-side light confinement layer 32 is made of single-crystal GaN, it is difficult to etch the p-side light confinement layer 32 located below the current confinement layer 10. That is, the etching rate for the current confinement layer 10 is larger than the etching rate for the p-side optical confinement layer 32. For this reason, it becomes possible to perform etching with good controllability.

  The alignment mark 12 may be provided corresponding to a resist pattern other than the resist mark 62, for example. In this case, the resist pattern can be formed simultaneously with the opening 64 by, for example, photolithography referring to the resist mark 62 as an alignment mark. A plurality of resist patterns are provided so as to be arranged in a dot shape, for example. Further, the resist pattern is provided, for example, in an alignment mark formation region where the semiconductor light emitting element 100 is not formed.

  Next, as shown in FIG. 3A, a p-type cladding layer 34 and a p-type contact layer 36 are sequentially formed on the current confinement layer 10 and the p-side optical confinement layer 32. As a result, the alignment mark 12 and the current confinement portion 14 are buried by the p-type cladding layer 34. The p-type cladding layer 34 and the p-type contact layer 36 are formed by epitaxially growing each layer on the current confinement layer 10 and the p-side optical confinement layer 32 in order.

First, the n-type substrate 20 on which the laminated structure shown in FIG. 2B is formed is put into the MOVPE apparatus, and then the laminated structure is heated while supplying ammonia. Through this temperature raising process, single crystallization of the current confinement layer 10 proceeds. Next, when the growth temperature is reached, epitaxial growth is started. Then, after the epitaxial growth is completed, the n-type substrate 20 on which the stacked structure shown in FIG. 3A is formed is taken out from the MOVPE apparatus.
The epitaxial growth step is for forming the n-type buffer layer 22, the n-type cladding layer 24, the n-side optical confinement layer 26, the active layer 28, the cap layer 30, the p-side optical confinement layer 32, and the current confinement layer 10. It can be performed under the same conditions as in the epitaxial growth step.

  Next, as shown in FIG. 4, a groove 80 for separating the semiconductor light emitting element 100 from the wafer state is formed. The groove 80 penetrates, for example, the p-type contact layer 36, the p-type cladding layer 34, the current confinement layer 10, the p-side optical confinement layer 32, the cap layer 30, the active layer 28, and the n-side optical confinement layer 26. It is formed so as to reach the layer 24.

The groove 80 is formed as follows, for example. First, as shown in FIG. 3B, an insulating film 72 and a resist 66 are sequentially formed on the p-type contact layer 36. The insulating film 72 is made of, for example, SiO ₂ . Next, the resist 66 is selectively removed by photolithography. In the photolithography, first, alignment of the reticle is performed with reference to the alignment mark 12. Then, after exposure using a reticle, development is performed to selectively remove the resist 66. Thereby, a resist pattern having an opening 68 for forming the groove 80 is formed. Next, the insulating film 72 is selectively removed by etching using the resist 66 as a mask. Next, a groove 80 is formed by etching using the insulating film 72 as a mask. The groove 80 is provided so as to partition the current confinement portion 14, for example. Thereby, the structure shown in FIG. 4 is obtained.
In photolithography for removing the resist 66, for example, contact exposure or stepper exposure can be used, and can be appropriately selected according to the purpose.
Thereafter, the insulating film 72 and the resist 66 are removed.

Next, the p-side electrode 52 is formed on the p-type contact layer 36, and the n-side electrode 50 is formed on the other surface of the n-type substrate 20.
The p-side electrode 52 is formed as follows, for example. First, a metal film is formed on the p-type contact layer 36. Next, a resist is formed on the metal film formed on the p-type contact layer 36. Next, the resist is selectively removed by photolithography. In the photolithography, first, alignment of the reticle is performed with reference to the alignment mark 12. Then, after exposure using a reticle, development is performed to selectively remove the resist. Next, the metal film is patterned by etching using a resist as a mask.
The alignment mark 12 is not limited to photolithography in the step of forming the groove 80 and the step of forming the p-side electrode 52, and can be similarly referred to in other photolithography.
Thereafter, the plurality of semiconductor light emitting devices 100 are separated into pieces along the grooves 80 from the wafer state. As a result, the semiconductor light emitting device 100 shown in FIG. 5 is obtained.

  Next, the operation and effect of this embodiment will be described. According to the method for manufacturing the semiconductor light emitting device 100 according to this embodiment, the current confinement layer 10 is etched to form the current confinement portion 14 and the alignment mark 12. For this reason, another process for forming the alignment mark 12 is not required. Therefore, the manufacturing process of the semiconductor light emitting element using the alignment mark can be simplified and the manufacturing cost can be reduced.

Further, when the alignment mark is buried by a semiconductor layer grown on the alignment mark, a step of exposing the alignment mark is required as described in Patent Document 2. However, for example, in a semiconductor element made of a nitride semiconductor, there is no appropriate selective etching means, and it is difficult to expose the alignment mark.
On the other hand, according to the method for manufacturing the semiconductor light emitting device 100 according to the present embodiment, the p-type cladding layer 34 and the p-type contact layer 36 covering the alignment mark 12 are transparent to the alignment beam used in the alignment. Consists of. For this reason, it is not necessary to expose the alignment mark 12 embedded by the p-type cladding layer 34. Therefore, the manufacturing process of the semiconductor element can be simplified and the manufacturing cost can be reduced.

  The alignment mark 12 is covered with a p-type cladding layer 34 and a p-type contact layer 36. That is, the alignment mark 12 is protected by the p-type cladding layer 34 and the p-type contact layer 36. For this reason, it can suppress that the alignment mark 12 lose | disappears or is damaged.

FIG. 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor light emitting device 100 according to the second embodiment, and corresponds to FIG. 3A in the first embodiment.
In the method for manufacturing the semiconductor light emitting device 100 according to this embodiment, the resist mark 62 is configured by an opening provided by selectively removing the resist 60 (not shown). Therefore, as shown in FIG. 6, the alignment mark 12 formed corresponding to the resist mark 62 is constituted by the opening 16 provided by removing the current confinement layer 10. Except for this point, the manufacturing method of the semiconductor light emitting device 100 according to this embodiment has the same configuration as the manufacturing method of the semiconductor light emitting device 100 according to the first embodiment.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

FIG. 7 is a cross-sectional view illustrating the method for manufacturing the semiconductor light emitting device 100 according to the third embodiment, and corresponds to FIG. 3A in the first embodiment.
In the method for manufacturing the semiconductor light emitting device 100 according to this embodiment, the current confinement portion 14 constituting one semiconductor light emitting device 100 and the current confinement portion 14 constituting another semiconductor light emitting device 100 are separated from each other. Except for this point, the manufacturing method of the semiconductor light emitting device 100 according to this embodiment has the same configuration as the manufacturing method of the semiconductor light emitting device 100 according to the first embodiment.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

Further, when the area of the current confinement layer 10 is large, the flatness of the p-type cladding layer 34 and the p-type contact layer 36 provided on the current confinement layer 10 is deteriorated. This is due to the fact that the epitaxial growth on the current confinement layer 10 is suppressed compared to the portion where the current confinement layer 10 is not provided.
According to the present embodiment, the current confinement part 14 constituting one semiconductor light emitting element 100 and the current confinement part 14 constituting another semiconductor light emitting element 100 are separated from each other. That is, the p-side optical confinement layer 32 is provided to be exposed between the adjacent current confinement portions 14. For this reason, the area of the current confinement layer 10 can be reduced. Therefore, the flatness of the p-type cladding layer 34 and the p-type contact layer 36 can be improved. Thereby, the characteristic variation between the semiconductor light emitting elements 100 can be suppressed.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

10 current confinement layer 12 alignment mark 14 current confinement portion 16 opening 20 n-type substrate 22 n-type buffer layer 24 n-type cladding layer 26 n-side optical confinement layer 28 active layer 30 cap layer 32 p-side optical confinement layer 34 p-type cladding Layer 36 p-type contact layer 50 n-side electrode 52 p-side electrode 60 resist 62 resist mark 64 opening 66 resist 68 opening 70 insulating film 72 insulating film 80 groove 100 semiconductor light emitting device

Claims (14)

Forming a first semiconductor layer on a substrate;
Etching the first semiconductor layer to form a current confinement portion made of the first semiconductor layer and forming an alignment mark made of the first semiconductor layer in a region different from the current confinement portion;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, further comprising a step of forming a second semiconductor layer on the current confinement portion and the alignment mark after the step of forming the current confinement portion and the alignment mark. In the manufacturing method of the semiconductor device according to claim 2,
The method of manufacturing a semiconductor element, wherein the second semiconductor layer is made of a material that transmits an alignment beam irradiated to the alignment mark. In the manufacturing method of the semiconductor element according to claim 2 or 3,
The second semiconductor layer is a method of manufacturing a semiconductor device having a flat surface. In the manufacturing method of the semiconductor element according to any one of claims 2 to 4,
The method for manufacturing a semiconductor device, wherein the first semiconductor layer has a refractive index different from that of the second semiconductor layer. In the manufacturing method of the semiconductor element according to any one of claims 2 to 5,
After the step of forming the second semiconductor layer,
Applying a first resist on the second semiconductor layer;
Using the alignment mark to align the first reticle;
Selectively removing the first resist by performing exposure using the first reticle and developing thereafter;
Forming a groove for partitioning the current confinement portion by etching using the first resist as a mask;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor element according to any one of claims 2 to 6,
After the step of forming the second semiconductor layer,
Forming a metal film on the second semiconductor layer;
Applying a second resist on the metal film;
Using the alignment mark to align the second reticle;
Selectively removing the second resist by performing exposure using the second reticle, followed by development;
Patterning the metal film by etching using the second resist as a mask to form an electrode;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor element of any one of Claim 1 thru | or 7,
The method for manufacturing a semiconductor device, wherein the first semiconductor layer is made of AlN or AlGaN. In the manufacturing method of the semiconductor device according to any one of claims 1 to 8,
After the step of forming the first semiconductor layer and before the step of forming the current confinement portion and the alignment mark,
Applying a third resist on the first semiconductor layer;
Selectively removing the third resist and forming a pattern corresponding to the alignment mark in the third resist without forming a pattern corresponding to the current confinement portion;
A step of aligning a third reticle using a pattern corresponding to the alignment mark of the third resist as an alignment mark;
Performing the exposure using the third reticle and then developing to selectively remove the third resist and form a pattern corresponding to the current confinement portion in the third resist;
With
The step of forming the current confinement portion and the alignment mark is performed by etching the first semiconductor layer using the third resist as a mask. In the manufacturing method of the semiconductor device according to any one of claims 1 to 8,
After the step of forming the first semiconductor layer and before the step of forming the current confinement portion and the alignment mark,
Forming an insulating film on the first semiconductor layer;
Applying a third resist on the insulating film;
Selectively removing the third resist and forming a pattern corresponding to the alignment mark in the third resist without forming a pattern corresponding to the current confinement portion;
A step of aligning a third reticle using a pattern corresponding to the alignment mark of the third resist as an alignment mark;
Performing the exposure using the third reticle and then developing to selectively remove the third resist and form a pattern corresponding to the current confinement portion in the third resist;
Selectively removing the insulating film by etching using the third resist as a mask;
With
The step of forming the current confinement portion and the alignment mark is performed by etching the first semiconductor layer using the insulating film as a mask. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the alignment mark is constituted by a portion of the first semiconductor layer remaining after etching. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the alignment mark is constituted by a portion from which the first semiconductor layer is removed. In the manufacturing method of the semiconductor element according to any one of claims 1 to 12,
A method of manufacturing a semiconductor device, wherein in the step of forming the current confinement portion and the alignment mark, a plurality of the current confinement portions separated from each other are formed. In the manufacturing method of the semiconductor device according to any one of claims 1 to 13,
The method of manufacturing a semiconductor device, wherein the semiconductor device is a nitride semiconductor light emitting device.

Images