JP2005353804A - Semiconductor element and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element which prevents the occurrence of cracks, which forms a nitride semiconductor growth layer having proper surface planarization properties, and which does not have current leakage paths or damages, and to provide a method of manufacturing the same. <P>SOLUTION: The nitride semiconductor growth layer, having proper surface property, can be formed and the semiconductor element having proper yield can be manufactured, by forming SiO<SB>2</SB>walls on both ends of a hill in a processing substrate having a digging-down region made of a recess, and suppressing to form a nitride semiconductor thin film by moving atoms, molecules that serve as the raw material of the nitride semiconductor thin film into the digging region by a migration from the upper surface grown part of the surface of the hill. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a nitride semiconductor laser device and a manufacturing method thereof.

  Nitride semiconductors such as GaN, AlGaN, GaInN, AlGaInN, and mixed crystals thereof are characterized by having a large band gap Eg and a direct transition semiconductor material compared to AlGaInAs semiconductors and AlGaInP semiconductors. ing. Therefore, these nitride semiconductors are used as materials for semiconductor light-emitting elements such as semiconductor lasers capable of emitting short-wavelength light from ultraviolet to green and light-emitting diodes capable of covering a wide emission wavelength range from ultraviolet to red. It is attracting attention and is widely considered for high-density optical discs, full-color displays, and environmental and medical fields.

In addition, this nitride semiconductor has higher thermal conductivity than GaAs-based semiconductors and the like, and is expected to be applied to devices that operate at high temperature and high output. Furthermore, since a material corresponding to arsenic (As) in an AlGaAs-based semiconductor, cadmium (Cd) in a ZnCdSSe-based semiconductor, and its raw material (arsine (AsH ₃ )) are not used, the compound semiconductor material has a low environmental load. Be expected.

  However, conventionally, in the manufacture of a nitride semiconductor laser element which is one of the nitride semiconductor elements, the ratio of the number of non-defective elements obtained to the number of nitride semiconductor laser elements manufactured on one wafer is There is a problem that the yield value shown is very low.

  The cause of such a decrease in yield is the occurrence of cracks. This crack may occur due to a nitride semiconductor growth layer stacked on the substrate. That is, when a nitride semiconductor laser device is manufactured, a nitride semiconductor growth layer is stacked on a substrate, and the nitride semiconductor growth layer is composed of different types of films such as GaN, AlGaN, and InGaN. At this time, the films constituting the nitride semiconductor growth layer have different lattice constants and cause lattice mismatch, and thus cracks are generated. Therefore, a method of reducing cracks by forming a recess without using a processed substrate to grow a nitride semiconductor growth layer and then flattening the surface of the nitride semiconductor growth layer has been proposed (patented). Reference 1). For example, by using the method described in Patent Document 1, it is possible to suppress cracks that are generated due to lattice mismatch of each film constituting the nitride semiconductor growth layer formed on the substrate.

  When a nitride semiconductor laser device is manufactured using the technique described in Patent Document 1 described above, for example, the nitride semiconductor growth layer is configured as shown in FIG.

That is, the nitride semiconductor growth layer 11 formed on the surface of the processed substrate 10 (see FIG. 9) made of etched n-type GaN or the like has, for example, an n-thickness of 1.0 μm on the surface of the processed substrate 10. N-type Al _0.062 Ga _0.938 N first cladding layer 101 having a layer thickness of 1.5 μm, n-type Al _0.1 Ga _0.9 N second cladding layer 102 having a layer thickness of 0.2 μm, and a layer thickness of _0.1 μm. An n-type Al _0.062 Ga _0.938 N third cladding layer 103 having a thickness of 1 μm, an n-type GaN guide layer 104 having a thickness of 0.1 μm, three InGaN well layers having a thickness of 4 nm, and four GaN barrier layers having a thickness of 8 nm. A multi-quantum well active layer 105 composed of layers, a p-type Al _0.3 Ga _0.7 N evaporation preventing layer 106 with a layer thickness of 20 nm, a p-type GaN guide layer 107 with a layer thickness of 0.05 μm, and a p-type with a layer thickness of 0.5 μm Al _0.062 Ga _0.938 N clad layer 10 8 and a p-type GaN contact layer 109 having a layer thickness of 0.1 μm are sequentially stacked. The multiple quantum well active layer 105 is formed in the order of barrier layer / well layer / barrier layer / well layer / barrier layer / well layer / barrier layer.

  In addition, when the index indicating the crystal plane or orientation is negative, it is a rule of crystallography to indicate the absolute value with a horizontal line, but in the following, since such notation is not possible, the absolute value A negative sign “−” is added in front of to indicate a negative index.

  Further, the “heterogeneous substrate” described in the present specification means a substrate other than a nitride semiconductor. As a specific heterogeneous substrate, a sapphire substrate, a SiC substrate, a GaAs substrate, or the like is used.

The “processed substrate” is a nitride semiconductor substrate, or a substrate in which a dug region and a hill are formed on the surface of a nitride semiconductor substrate or a nitride semiconductor thin film laminated on the surface of a different type of substrate. . Further, a p-type Al _0.3 Ga _0.7 N evaporation preventing layer 106 doped with Mg, a p-type GaN guide layer 107, a p-type Al _0.062 Ga _0.938 N clad layer 108, and a p-type GaN contact layer 109 are obtained. Hereinafter, the nitride semiconductor layer is referred to as a “p layer”.

  By depositing the nitride semiconductor growth layer 11 on the processed substrate 10 surface using the MOCVD (Metal Organic Chemical Vapor Deposition) method, there is a depression on the surface of the nitride semiconductor growth layer 11 as shown in FIG. A nitride semiconductor wafer is formed. In FIG. 9, the plane orientation is also displayed.

The n-type GaN substrate used as the processed substrate 10 shown in FIG. 9 is dug in stripes using a dry etching technique such as RIE (Reactive Ion Etching) in the [1-100] direction. Region 16 and hill 19 are formed. The width of the dug area is 5 μm, the depth is 3 μm, and the period between adjacent dug areas is 15 μm. A nitride semiconductor growth layer 11 having a laminated structure as shown in FIG. 10 is formed on the processed substrate 10 subjected to such etching by a growth method such as MOCVD.
JP 2002-246698 A

  However, with the technique according to Patent Document 1 described above, an n-type GaN substrate is used as the processed substrate 10, and a nitride semiconductor growth layer 11 is epitaxially grown on the n-type GaN substrate using the MOCVD method or the like, thereby producing a nitride semiconductor laser. Fabrication of the element was effective in reducing cracks, but the yield was not significantly improved. That is, using the technique of Patent Document 1, a plurality of nitride semiconductor laser elements were fabricated, and 100 nitride semiconductor laser elements were randomly picked out from the nitride semiconductor laser elements, and the half widths of the FFP in the horizontal direction and the vertical direction were measured. . At this time, when the nitride semiconductor laser element within ± 1 degree with respect to the design value of the half width of the FFP is regarded as a non-defective product, there are 30 nitride semiconductor lasers whose half width of the FFP satisfies the standard, The result was very low yield.

  This is because if the recess is left on the nitride semiconductor growth layer 11, the remaining recess causes the film flatness to deteriorate. If the flatness deteriorates, the thickness of each layer varies within the nitride semiconductor growth layer 11, the characteristics of each nitride semiconductor laser element differ, and the number of elements that satisfy the characteristics within the standard range decreases. Therefore, in order to improve the yield, it is necessary not only to reduce the generation of cracks but also to improve the flatness of the film.

  Further, when the surface flatness in the nitride semiconductor wafer surface formed as shown in FIGS. 9 and 10 is measured, the measurement result of the surface flatness measured in the [1-100] direction is as shown in FIG. The measurement was performed under the measurement conditions of a measurement length of 600 μm, a measurement time of 3 s, a stylus pressure of 30 mg, and a horizontal resolution of 1 μm / sample. At this time, in the measured region of 600 μm width, the level difference between the highest part and the lowest part of the surface was 200 nm from the graph of FIG.

The difference in flatness is as shown in FIG. 9B because the thickness of each layer of the nitride semiconductor growth layer 11 stacked on the surface of the processed substrate 10 varies depending on the position of the wafer. It is. Therefore, the characteristics of the nitride semiconductor laser element vary greatly depending on the in-plane position of the wafer on which the element is manufactured, and the thickness of the p layer doped with Mg that greatly affects the characteristics of the nitride semiconductor laser element (FIG. 10). (Which corresponds to the sum of the layer thicknesses of the p layers stacked from the p-type Al _0.3 Ga _0.7 N evaporation prevention layer 106 to the p-type GaN contact layer 109) shown in FIG.

  Also, when a ridge structure that is a current confinement structure is formed, the ridge portion is left in a stripe shape having a width of 2 μm, and the other portions are etched using a dry etching technique using an ICP (Inductively Coupled Plasma) apparatus or the like. . Therefore, if the p-layer thickness before etching varies depending on the in-plane position of the wafer, the remaining thickness of the p-layer after etching that most affects the characteristics of the nitride semiconductor laser device also varies greatly depending on the in-plane position of the wafer. It becomes. For these reasons, the nitride semiconductor laser elements have different layer thicknesses, and even within a single nitride semiconductor laser element, the p-layer has almost no remaining film thickness and remains significantly. Will be mixed. Thus, if the remaining film thickness of the p layer varies, the lifetime of the nitride semiconductor laser element and characteristics such as the half width of FFP (Far Field Pattern) are affected as described above.

  Thus, a large layer thickness distribution exists in the wafer surface because the growth rate of the film epitaxially grown on the hill portion of the processed substrate including the nitride semiconductor substrate changes due to the influence of the digging region. This is probably because the uniformity in the surface deteriorated.

  That is, when the epitaxial growth is started on the processed substrate 10 in which the digging region 16 is formed as shown in FIG. 12, the digging region 16 is shown in FIG. The digging region in-growth portion 122 made of a nitride semiconductor thin film grown on the bottom surface portion 124 and the side surface portion 126 of the burying portion fills only a part of the digging region 16. At this time, the growth of the upper surface growth portion 121 made of the nitride semiconductor thin film growing on the surface of the upper surface portion 123 of the hill 19 proceeds with the surface of the nitride semiconductor thin film being flat.

  When the epitaxial growth of the nitride semiconductor thin film progresses from the state of FIG. 12A described above, the nitride grown on the bottom surface portion 124 and the side surface portion 126 of the digging region 16 as shown in FIG. 12B. The grooving region growth portion 122 made of a thin semiconductor thin film almost fills the digging region 16, and the upper surface growth portion 121 and the growth portion 125 made of a nitride semiconductor thin film grown on the surface of the upper surface portion 123 of the hill 19. It becomes a connected state. In such a state, the atoms / molecules (Ga atoms, etc.) that are the raw materials attached to the surface of the nitride semiconductor thin film grown on the upper surface portion 123 of the hill 19 migrate due to thermal energy, and the growth portion 125 or It moves to the in-digging region growth part 122. The movement of atoms / molecules due to this migration occurs very unevenly in the wafer plane, and the movement distance also takes a different value in the wafer plane. As a result, as shown in FIG. 12B, the flatness of the surface of the upper surface growth portion 121 is deteriorated.

  The flatness of such a nitride semiconductor thin film is due to the non-uniformity of the nitride semiconductor substrate itself such as the off-angle wafer in-plane distribution and the substrate curvature in-wafer distribution, or the epitaxial growth rate in-plane non-uniformity. Also, the non-uniformity in the substrate surface of the digging process affects the [1-100] direction. That is, the time until the digging region 16 is filled differs depending on the [1-100] direction, and the portion that has been buried quickly is an atom that becomes a raw material of the nitride semiconductor thin film by migration or the like from the upper surface growth portion 121 of the hill 19. A molecule moves to the growth part 125 or the growth part 122 in the digging region. As a result, the time for forming the nitride semiconductor thin film becomes longer when moved, and as a result, the thickness of the nitride semiconductor thin film formed in the digging region 16 increases. On the other hand, in the portion where the digging region 16 is not completely filled, the atoms / molecules which are the raw materials of the nitride semiconductor thin film do not move from the upper surface growth portion 121 of the hill 19 into the digging region 16, or even if they move, the nitride The time for forming the semiconductor thin film is short. Therefore, the film thickness of the nitride semiconductor thin film formed in the digging region 16 is thinner than the portion where the digging region 16 is buried early.

  Also, when the growth rate of the nitride semiconductor thin film is controlled by the flux of atoms / molecules supplied to the wafer surface, the so-called supply-controlled state, the atoms / molecules that are the raw material of the nitride semiconductor thin film migrate When flowing into the digging region 16 by, for example, the upper surface growth in which the nitride semiconductor thin film grows on the upper surface portion 123 of the hill 19 because the flux of atoms and molecules as the raw material supplied to the entire wafer surface is constant. The film thickness of the portion 121 is reduced. In the reverse case, that is, when the atoms / molecules that are the raw material of the nitride semiconductor thin film do not flow into the digging region 16 due to migration or the like, the upper surface growth portion 121 portion where the nitride semiconductor thin film grows on the upper surface portion 123 of the hill 19 The film thickness becomes thicker.

  Due to this, the layer thickness of the upper surface growth portion 121 on the upper surface portion 123 of the hill 19 differs within the wafer surface, and as a result, the flatness of the surface of the nitride semiconductor thin film deteriorates. In other words, in order to improve the flatness, atoms / molecules which are the raw material of the nitride semiconductor thin film move from the upper surface growth portion 121 of the hill 19 to the growth portion 125 or the in-digging region growth portion 122 by migration or the like. It is necessary to suppress the formation of a physical semiconductor thin film.

Further, when a nitride semiconductor laser device is manufactured by the technique according to Patent Document 1 described above, if an electrode is formed in a recessed portion on the surface of the nitride semiconductor growth layer 11, a current leakage path is generated in the recessed portion, and normal. As a result, it was found that the IV characteristics could not be obtained. Usually, an insulating film such as SiO ₂ is formed on the depression and an electrode is formed thereon. However, since the depression exists, the insulating film is not uniformly formed on the surface. There are many small cracks, very thin areas, and small holes (pits). For this reason, current leakage occurs through the uneven insulating film portion.

  In view of such a problem, the present invention provides a semiconductor device such as a nitride semiconductor laser device by stacking a nitride semiconductor growth layer on a substrate having a nitride semiconductor layer on at least a part of its surface. Prevent the generation of cracks, and at the same time, the migration of the top surface of the hill surface causes migration of atoms / molecules as the raw material of the nitride semiconductor thin film to the digging region to form the nitride semiconductor thin film. An object of the present invention is to provide a nitride semiconductor growth layer with good surface flatness by suppressing the semiconductor element, and to provide a semiconductor element free from a current leak path and damage and a manufacturing method thereof.

  In order to achieve the above object, the present invention forms a digging region consisting of at least one concave portion and a hill portion which is a non-digging region on a substrate having a nitride semiconductor layer on at least a part of its surface. In the method of manufacturing a semiconductor device including the first step of manufacturing the processed substrate, the second step of forming the inflow prevention walls made of convex portions on both ends of the hill portion included in the processed substrate, and the second step And forming a nitride semiconductor laminated portion made of at least one nitride semiconductor thin film on both the digging region of the processed substrate and the hill surface where the inflow prevention wall is formed. The nitride semiconductor laminated portion is laminated on the inflow prevention wall formed in the portion, and a step is provided between the flat surface of the nitride semiconductor laminated portion laminated on the hill surface. Characterized in that it comprises a third step of forming a convex inflow prevention portion that, the.

  In such a method, the concave portion constituting the digging region may be formed in a stripe shape or a grid shape.

  Further, in such a method of manufacturing a semiconductor device, when the nitride semiconductor multilayer portion is formed in the third step, the concave portion of the digging region may not be completely buried.

In such a method of manufacturing a semiconductor device, in the second step, the inflow prevention wall may be composed of any one of SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZrO, and W. Absent.

When a film of GaN or AlGaN is formed on the surface of these materials described above, there is selectivity such that the growth rate of GaN or AlGaN is slow or GaN or AlGaN does not grow. A material other than SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZrO, and W may be used as long as it has such selectivity.

  Further, in such a method of manufacturing a semiconductor element, when forming the inflow prevention wall in the second step, the thickness in the normal direction that is a direction perpendicular to the surface of the hill portion in the inflow prevention wall, It may be 50 nm or more and 3 μm or less.

  In the method of manufacturing a semiconductor device, when the inflow prevention wall is formed in the second step, the width in the direction perpendicular to the longitudinal direction of the inflow prevention wall may be 1 μm or more and 25 μm or less. I do not care.

Further, in such a method of manufacturing a semiconductor device, a wire for electrical connection to the outside is formed on the nitride semiconductor laminated portion laminated on the processed substrate surface provided with the flow-in prevention wall in the third step. In the fourth step, an electrode pad for performing bonding is formed to form a plurality of semiconductor elements on the substrate.
The electrode pad is not formed on the digging region.

  Further, in such a method of manufacturing a semiconductor device, a digging region composed of at least one recess and a hill portion that is not digging are formed on a substrate having a nitride semiconductor layer on at least a part of its surface. A first step of fabricating a processed substrate, and a second step of stacking a nitride semiconductor stacked portion made of at least one type of nitride semiconductor thin film on both the digging region and the hill surface of the processed substrate. In the method for manufacturing a semiconductor device, the second step, from the surface of the hill portion of the nitride semiconductor stacked portion that is stacked on both ends of the hill portion in the vicinity of the digging region. The nitride semiconductor multilayer portion from the hill surface of the nitride semiconductor multilayer portion, wherein the film thickness to the nitride semiconductor multilayer portion surface is laminated in a region other than both ends of the hill portion. By laminating thicker than the film thickness up to the surface, the nitride semiconductor laminated portion laminated on the surface of the region other than the both end portions of the hill portion on both ends of the hill portion in the vicinity of the digging region The inflow prevention portion having a convex shape is formed on the surface of the flat portion.

  Further, in such a method for manufacturing a semiconductor device, the recess of the digging region is not completely buried when the nitride semiconductor stacked portion is formed in the second step.

  Further, in such a method of manufacturing a semiconductor element, in the second step, the gap is formed between the flat surface of the nitride semiconductor stacked portion stacked on the hill surface and the convex inflow preventing portion. It is assumed that the step difference is 150 nm or more.

  In such a method, by setting the above-described step to 150 nm or more, a semiconductor element can be manufactured with high yield.

  In such a semiconductor device manufacturing method, in the second step, the nitride semiconductor thin film in contact with the processed substrate surface is made GaN having a thickness of 0.5 μm or less.

  According to such a method, even after growing GaN that is easy to migrate to the surface of the processed substrate, the nitride layered on the hill surface is continuously laminated by laminating a nitride semiconductor thin film such as AlGaN. The step formed between the flat portion surface of the semiconductor stacked portion and the convex flow-in prevention portion can be 150 nm or more.

  In such a method of manufacturing a semiconductor device, in the second step, the nitride semiconductor thin film in contact with the processed substrate surface may be AlGaN.

  In such a method of manufacturing a semiconductor device, in the second step, the nitride semiconductor thin film in contact with the processed substrate surface is GaN, and the substrate surface temperature when forming the GaN on the processed substrate surface is set to It may be 1025 ° C.

  According to such a method, even when the nitride semiconductor thin film in contact with the processed substrate is GaN, the flat portion surface of the nitride semiconductor laminated portion laminated on the hill surface and the convex inflow prevention The step formed between the portions can be 150 nm or more, and a semiconductor element can be manufactured with high yield.

  Further, in such a method of manufacturing a semiconductor element, in the second step, the nitride semiconductor thin film in contact with the processed substrate surface is GaN, and when the GaN is formed, a raw material containing a group III gallium atom The ratio of the number of moles of the flow rate supplied per unit time of the raw material containing a nitrogen atom that is a group V to the number of moles of the flow rate supplied per unit time may be 2000 or more.

  According to such a method, even when the nitride semiconductor thin film in contact with the processed substrate is GaN, the flat portion surface of the nitride semiconductor laminated portion laminated on the hill surface and the convex inflow prevention The step formed between the portions can be 150 nm or more, and a semiconductor element can be manufactured with high yield.

  Further, in such a method of manufacturing a semiconductor device, in the second step, the nitride semiconductor thin film constituting the nitride semiconductor multilayer portion includes an AlGaN layer having an Al composition ratio of 0.02 or more. It does not matter.

  Further, in such a method for manufacturing a semiconductor device, an electrode for performing wire bonding for electrical connection to the outside on the nitride semiconductor laminated portion laminated on the processed substrate surface in the second step. A fourth step of forming a plurality of semiconductor elements on the substrate by forming a pad is provided, and in the fourth step, the electrode pad is not formed above the digging region.

  Further, in such a method for manufacturing a semiconductor element, in the fourth step, the electrode pad may be formed at a distance of 30 μm or more from the end of the digging region.

  Further, in such a semiconductor element manufacturing method, one semiconductor element may be formed on the hill portion sandwiched between two adjacent digging regions, or a plurality of the semiconductor elements may be formed. It does n’t matter what you do.

  Further, in such a method of manufacturing a semiconductor element, the surface of the nitride semiconductor laminated portion laminated in the digging region or the back side of the processed substrate which is a portion immediately below the digging region is scribed, thereby dividing the chip. It does not matter even if it implements.

  In such a method of manufacturing a semiconductor element, the depth of the concave portion may be 1 μm or more and 20 μm or less when the digging region including the concave portion is formed in the first step.

  In such a method of manufacturing a semiconductor element, when the digging region including the recess is formed in the first step, the opening width of the recess is 1 μm or more.

  According to such a method, the digging region is filled with the nitride semiconductor thin film, and the nitride semiconductor thin film associates above the digging region to form a cavity in the digging region. Is prevented.

  In such a method of manufacturing a semiconductor element, when forming the digging region including the concave portion in the first step, a width of the hill portion sandwiched between adjacent digging regions is 140 μm or more and 4 mm. The following may be used.

  Furthermore, the semiconductor element of the present invention is manufactured by any one of the above-described methods for manufacturing a semiconductor element.

According to the present invention, a flow prevention wall made of a convex portion made of SiO ₂ or the like is formed on both end portions of a hill portion of a processed substrate having a digging region, and a nitride semiconductor thin film is grown on the processed substrate surface to flow in. Thick convex inflow prevention portions are formed at both end portions of the hill portion where the prevention walls are formed. When the nitride semiconductor thin film is further grown on the substrate surface by this inflow prevention part, the atoms / molecules that are the raw material of the nitride semiconductor thin film move from the upper surface growth part of the hill surface into the digging region by migration or the like. The formation of the nitride semiconductor thin film in the recessed region is suppressed. As a result, a nitride semiconductor thin film with good surface flatness can be formed in the upper surface growth portion of the hill surface, and as a result, the thickness of each nitride semiconductor thin film can be made uniform.

In addition, according to the present invention, when the thickness of the inflow prevention wall made of SiO ₂ or the like is 50 nm or more, the inflow prevention wall having a uniform thickness can be formed in the wafer surface. Further, when the thickness of the inflow prevention wall is 3 μm or less, or the width in the direction perpendicular to the longitudinal direction of the inflow prevention wall is 25 μm or less, stress is applied from the inflow prevention wall to the nitride semiconductor thin film. Can be suppressed. In addition, when the width in the direction perpendicular to the longitudinal direction of the inflow prevention wall is 1 μm or more, the inflow prevention wall can be easily formed.

  In addition, according to the present invention, by setting the depth or opening width of the recesses constituting the digging region to be 1 μm or more, the digging region is prevented from being filled with the nitride semiconductor thin film, and the nitride semiconductor The strain contained in the laminated portion can be released and the generation of cracks can be suppressed. Further, by setting the depth of the digging region to 20 μm or less, it is possible to prevent the wafer from cracking in the subsequent chip dividing step.

  In addition, according to the present invention, by making the width of a hill sandwiched between adjacent digging regions 140 μm or more, a semiconductor element is produced on a flat portion of the hill, and wire bonding is performed for electrical connection with the outside. Easy to implement. In addition, by setting the width of the hill sandwiched between adjacent digging regions to 4 mm or less, the occurrence of cracks in the nitride semiconductor laminated portion in which the nitride semiconductor thin films are laminated is suppressed.

  In addition, according to the present invention, the electrode pad is not formed on the upper part of the digging region, and the distance from the end of the digging region to the electrode pad is set to 30 μm or more so that the insulating film and nitride in the digging region Not affected by defects, dislocations, cracks, etc. in semiconductor thin films. As a result, a semiconductor element free from current leakage and damage can be manufactured.

  In addition, according to the present invention, the surface of the nitride semiconductor laminated portion laminated in the digging region or the back side of the processed substrate that is directly below the digging region is scribed to divide the chip. For this reason, the groove in the digging region can be used as a guide for chip division, and chipping and division in an unintended direction can be prevented.

  Further, according to the present invention, the digging region having the concave portion is formed on the substrate, and the layer thickness can be increased at both end portions of the hill portion near the digging region, thereby forming the convex inflow prevention portion. When the nitride semiconductor thin film is further grown by this inflow prevention part, the atoms / molecules that are the raw material of the nitride semiconductor thin film move from the upper surface growth part of the hill surface into the digging region by migration or the like, and digging. Formation of the nitride semiconductor thin film in the region is suppressed. As a result, a nitride semiconductor thin film with good surface flatness can be formed in the upper surface growth portion of the hill surface, and as a result, the thickness of each nitride semiconductor thin film can be made uniform.

  First, in this specification, the meaning of some terms will be clarified in advance. First, the “digging region” means, for example, a recess processed into a stripe shape on the surface of a nitride semiconductor substrate or a different substrate as shown in FIG. FIG. 2 is a schematic cross-sectional view of the substrate in which the digging process is performed and the digging region 16 and the hill 19 are formed. The cross-sectional shape of the digging region 16 is not necessarily rectangular, and may be a Δ shape or a trapezoidal shape as shown in FIG. Further, the digging region 16 does not necessarily have to be a single concave portion, and may include a plurality of concave portions and a narrow flat portion sandwiched between the concave portions.

  The “hill” is a convex portion that is similarly processed into a stripe shape. The digging region 16 and the hill 19 shown in FIG. 2 are stripe arrangements processed along one direction, but may be a grid arrangement in which the digging region 16 or the hill 19 intersect each other. Further, digging regions 16 having different shapes, digging regions having different digging depths, and widths may exist on one substrate. Further, the period in which the digging region 16 is formed on one substrate may be different.

“Nitride semiconductor substrate” means a substrate made of Al _x Ga _y In _z N (0 ≦ x ≦ 1; 0 ≦ y ≦ 1; 0 ≦ z ≦ 1; x + y + z = 1). However, about 10% or less of the nitrogen element of the nitride semiconductor substrate may be substituted with an element of As, P, or Sb (however, the hexagonal system of the substrate is maintained). The nitride semiconductor substrate may be doped with Si, O, Cl, S, C, Ge, Zn, Cd, Mg, or Be. Furthermore, as these n-type nitride semiconductors, Si, O, and Cl are particularly preferable among these doping materials. The principal plane orientation of the nitride semiconductor substrate is preferably a C plane {0001}, A plane {11-20}, R plane {1-102}, M plane {1-100}, or {1-101} plane. Can be used. Further, if the substrate main surface has an off angle within 2 ° from these crystal plane orientations, the surface morphology can be good.

<First Embodiment>
Next, a first embodiment of the present invention will be described with reference to the drawings. In each of the following embodiments, a nitride semiconductor laser will be described as an example of a semiconductor element, but the present invention can also be applied to other semiconductor elements. FIG. 1A is a schematic cross-sectional view of the nitride semiconductor laser device according to this embodiment, and FIG. 1B is a top view of FIG. FIG. 3B is a schematic cross-sectional view of the processed substrate 10 before growing the nitride semiconductor thin film according to the embodiment of the present invention, and FIG. 3A is a top view of FIG. 1 and 3, the plane orientation is also displayed.

In the nitride semiconductor laser device of the present embodiment, the processed substrate 10 made of a nitride semiconductor substrate provided with the digging region 16 serving as a recess is further formed on both ends of the hill 19 which is a non-digging region [ A stripe-shaped SiO ₂ wall extending in the 1-100] direction is formed, and the nitride semiconductor growth layer 11 is grown on the processed substrate 10. In such a nitride semiconductor laser device, first, a method for manufacturing the processed substrate 10 will be described with reference to the drawings. In this embodiment, an n-type GaN substrate is used as the processed substrate 10.

First, sputter deposited SiO ₂ or the like having a thickness of 1μm on the entire surface of the n-type GaN substrate to form a SiO ₂ film, subsequently, in a general photolithography process, a photoresist pattern of stripes, the resist opening portion It is formed in the [1-100] direction so that the width (hereinafter referred to as the period) in the direction parallel to the [11-20] direction between the stripe central part and the adjacent stripe central part is 250 μm in width. Next, a dry etching technique such as RIE (Reactive Ion Etching) technique is used to etch the SiO ₂ film and the n-type GaN substrate so that the digging depth Y is 5 μm and the opening width X is 5 μm. 16 is formed. Thereafter, SiO ₂ is removed using HF (hydrofluoric acid) or the like as an etchant, thereby manufacturing the processed substrate 10 including the dug region 16 and the hill 19.

In this embodiment, SiO ₂ is deposited to form the SiO ₂ film on the surface of the n-type GaN substrate. However, the present invention is not limited to this, and other dielectric films are formed on the surface of the n-type GaN substrate. It does not matter as what is formed. Further, the above-described method for forming the SiO ₂ film is not limited to sputtering deposition, and methods such as electron beam deposition and plasma CVD may be used. Also, the period of the resist pattern is not limited to the above 250 μm, and may be changed depending on the width of the nitride semiconductor laser element to be manufactured. Furthermore, in this embodiment, the dry etching technique is used to form the digging region 16, but the present invention is not limited to this method, and a wet etching technique or the like may be used.

  The processed substrate 10 formed in this manner may be formed by digging the digging region 16 directly on the surface of the n-type GaN substrate as described above, or other than the n-type GaN substrate or the n-type GaN substrate. Alternatively, a nitride semiconductor thin film such as GaN, InGaN, AlGaN, or InAlGaN may be grown on the surface of the nitride semiconductor substrate or the surface of a different substrate, and then formed by digging.

In this way, after forming the processed substrate 10 provided with a recessed region 16, further SiO ₂ is deposited on the hill 19 is an area that is not recessed, to form a SiO ₂ film. Subsequently, at both ends of the hill 19, a stripe-shaped resist pattern having a width D is formed in the [1-100] direction using a general photolithography technique. At this time, the resist pattern is formed so that the line extending from the side surface portion of the digging region 16 coincides with the side wall surface of the resist pattern. Then, the SiO ₂ film is etched until the n-type GaN substrate surface is exposed using a dry etching technique or a wet etching technique using HF (hydrofluoric acid) or the like. As a result, as shown in FIG. 3, the digging region 16 and the hill 19, and stripes extending in the [1-100] direction where the width is D and the thickness is T at both ends of the hill 19. The processed substrate 10 having the SiO ₂ wall 17 formed thereon is obtained.

In this embodiment, the SiO ₂ wall 17 is formed using SiO ₂ as a material. However, the material of the wall is not limited to SiO ₂ , and Al ₂ O ₃ , TiO ₂ , ZrO, W, Etc. may be used. These materials such as Al ₂ O ₃ , TiO ₂ , ZrO, W, etc., when GaN or AlGaN is formed on the surface of the material, the growth rate of GaN or AlGaN is slow, or GaN or AlGaN does not grow, etc. Selectivity. When walls are formed at both ends of the hill 19 using such a material having selectivity, the flow of atoms / molecules as a raw material of GaN or AlGaN into the digging region 16 is suppressed. Therefore, a material having selectivity such as SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZrO, and W is preferable as the wall material.

When the SiO ₂ wall 17 is formed by the above-described method, if the thickness T of the SiO ₂ film formed on the hill 19 is smaller than 50 nm, an SiO ₂ film having a uniform thickness on the wafer surface is formed. It is not easy to form. Conversely, when the SiO ₂ wall 17 is formed by the above-described method, if the value T of the SiO ₂ film formed on the hill 19 is greater than 3 μm, stress is applied from the SiO ₂ film to the nitride semiconductor thin film. Is not desirable. Therefore, when the SiO ₂ wall 17 is formed, the thickness T of the SiO ₂ film formed on the hill 19 is preferably 50 nm or more and 3 μm or less.

Further, if the width D in the direction parallel to the [11-20] direction of the SiO ₂ wall 17 is less than 1 μm, the difficulty in carrying out the process increases and the formation of the SiO ₂ wall 17 becomes difficult, which is not preferable. . On the other hand, if the width D is larger than 25 μm, stress is applied from the SiO ₂ film to the nitride semiconductor thin film, which is not preferable. Therefore, it is preferable that the width D in the direction parallel to the [11-20] direction of the SiO ₂ wall 17 is 1 μm or more and 25 μm or less.

  Further, when the depth Y of the digging region 16 formed as described above is less than 1 μm, the digging region 16 is filled with the nitride semiconductor growth layer 11 and is included in the nitride semiconductor growth layer 11. Strain is not released, and as a result, cracks occur. Further, when the depth Y is set to 20 μm or more, the wafer may be cracked at this time in order to polish the wafer until the thickness of the wafer reaches about 100 μm in the subsequent chip dividing step. Therefore, the depth Y of the dug region 16 is preferably 1 μm or more and 20 μm or less.

  For example, a nitride semiconductor growth layer 11 made of a plurality of nitride semiconductor thin films as shown in FIG. 10 is formed on the processed substrate 10 obtained as described above by appropriately using a known technique such as MOCVD. The nitride semiconductor laser element shown in FIG. 1 is produced by epitaxial growth.

A nitride semiconductor thin film is grown in order to stack the nitride semiconductor growth layer 11 on the processed substrate 10 having the digging region 16 and the hill 19 and having the SiO ₂ walls 17 formed at both ends of the hill 19. FIG. 4 shows a schematic cross-sectional view of the wafer in the case of being made. As shown in FIG. 4, the nitride semiconductor thin film, the center portion of the upper surface portion 41 of the hills 19 as the upper surface growth portions 45 (corresponding to the SiO ₂ wall 17 in FIG. 1) SiO ₂ walls 17a, 17b are formed The both sides of the upper surface portion 41 of the hill 19 grow as flow-in prevention portions 44, and the side surface portion 42 and the bottom surface portion 43 in the digging region 16 grow as digging region growth portions 47, respectively. Further, the inflow prevention portion 44 and the in-digging region growth portion 47 are coupled via the growth portion 46.

As shown in FIG. 4, when the processed substrate 10 includes the SiO ₂ walls 17 a and 17 b, the inflow prevention portion 44 has a raised shape. This is because the SiO ₂ walls 17a and 17b suppress the migration and migration of atoms / molecules, which are the raw material of the nitride semiconductor thin film, from the upper surface portion 41 of the hill 19 into the digging region 16. is there. By forming the inflow prevention portion 44 in a convex shape in this way, the atoms / molecules that are the raw material of the nitride semiconductor thin film migrate and move from the upper surface portion 41 of the hill 19 into the digging region 16. Furthermore, it is strongly suppressed.

  That is, even if atoms / molecules that are the raw material of the nitride semiconductor thin film adhere to the surface of the upper surface growth portion 45 grown on the upper surface portion 41 of the hill 19, the growth portion 45 and the dug region 16 are caused by the inflow prevention portion 44. The migration and movement to the inner side surface portion 42 and the bottom surface portion 43 are suppressed. Therefore, atoms / molecules attached to the surface of the upper surface portion 45 migrate only on the surface of the upper surface portion 45. As a result, the flatness of the surface of the upper surface portion 45 is improved, and the nitride semiconductor has a uniform film thickness. A thin film is formed. The width of the inflow prevention portion 44 in the direction parallel to the [11-20] direction is about 10 μm to 30 μm.

In this specification, “flatness” refers to the flatness on the surface of the upper surface growth portions 45 and 75 (described later: see FIG. 7) and on the surface of the nitride semiconductor thin film laminated on the upper surface growth portions 45 and 75. Point to. Further, as shown in FIG. 4, the cross-sectional shape when cut along a plane perpendicular to the extending direction of the SiO ₂ walls 17a, 17b may be rectangular like the SiO ₂ wall 17a, or the SiO ₂ wall A shape other than a rectangle, such as 17b, may be used.

  When the nitride semiconductor growth layer 11 is stacked in this way, if the opening width X of the digging region 16 is less than 1 μm, the digging region 16 becomes a growth portion in the digging region as shown in FIG. 47 completely fills up and cracks occur. Alternatively, as shown in FIG. 5B, the upper surface growing portion 45 that grows on the surface of the hill 19 also grows in the lateral direction, and as a result, the upper surface growing portion 45 associates above the digging region 16 to form the cavity 51. Is done. In such a case, the flatness of the surface of the upper surface growth portion 45 is deteriorated and the effect of reducing cracks is remarkably reduced. Therefore, the opening width X of the digging region 16 needs to be 1 μm or more.

  In this way, the flow preventing portion 44 can provide good surface flatness in the upper surface growing portion 45 formed on the upper surface portion 41 of the hill 19. A plurality of nitride semiconductor thin films are sequentially stacked on the top surface growth portion 45 with good flatness to form, for example, a nitride semiconductor growth layer 11 having a configuration as shown in FIG. A nitride semiconductor laser device is manufactured. The nitride semiconductor growth layer 11 is formed by appropriately using a well-known technique such as MOCVD method, and a detailed description thereof will be omitted.

The nitride semiconductor growth layer 11 formed on the processed substrate 10 is provided with a laser stripe 12 as a laser optical waveguide and a laser stripe 12 sandwiched between the surfaces of the nitride semiconductor growth layer 11 and is intended for current confinement. An SiO ₂ film 13 is formed. A p-side electrode 14 is formed on the surface of each of the laser stripe 12 and the SiO ₂ film 13, and an n-side electrode 15 is formed on the back surface of the processed substrate 10. At this time, the protrusion on the surface of the p-side electrode 14 immediately above the laser stripe 12 is defined as a stripe 18. The distance between the center of the laser stripe 12 and the end of the SiO ₂ wall 17 on the laser stripe 12 side is defined as d. In this embodiment, the distance d is 40 μm.

Further, in such a nitride semiconductor laser device, the p-side electrode 14 is formed from Mo / Au, Mo / Pt / Au, or only an Au single layer from the side close to the nitride semiconductor growth layer 11. Is done. In this embodiment, the SiO ₂ film 13 is used as an insulating film for current confinement, but ZrO, TiO ₂ or the like may be used as an insulating film material. Further, FIG. 1 shows a nitride semiconductor laser device obtained by performing chip division at a place different from the digging region 16 which is a position where the chip is actually divided, which will be described later, in order to make the sectional structure easy to understand. It is the figure which shows a cross section.

Such a nitride semiconductor laser element having a ridge structure is manufactured by appropriately using a well-known technique after the nitride semiconductor growth layer 11 is laminated on the processed substrate 10, and its detailed manufacturing method and the like. Description of is omitted. Then, by stacking the nitride semiconductor growth layer 11, a plurality of nitride semiconductor laser elements formed on the processed substrate 10 (wafer) are divided into individual elements. At this time, first, a part of the processed substrate 10 is removed, and the thickness of the wafer is reduced to about 100 μm. Thereafter, the n-side electrode 15 is formed on the back side of the processed substrate 10. Subsequently, the wafer was cleaved along a direction parallel to the [11-20] direction (see FIG. 1) to form a resonator end face, and as shown in FIG. 6, a plurality of nitride semiconductor laser elements were provided. Make it a bar. At this time, in this embodiment, the resonator length, which is the length in the resonator direction ([1-100] direction), is 600 μm, but is not limited to this value, and preferably the resonator length is 300 μm. To 1200 μm. Then, a dielectric film made of SiO ₂ and TiO ₂ is alternately deposited on the cavity end face by using an electron beam deposition method or the like to form a dielectric multilayer reflective film. The dielectric material for forming the dielectric multilayer reflective film is not limited to SiO ₂ / TiO ₂ , and for example, SiO ₂ / Al ₂ O ₃ may be used.

  By doing so, a bar having a plurality of nitride semiconductor laser elements as shown in FIG. 6 is obtained. FIG. 6B is a part of a schematic cross-sectional view of a bar shape formed by cleaving the wafer in a direction parallel to the [11-20] direction (see FIG. 1) to form a resonator end face. FIG. 6A is a top view thereof.

In the bar having the configuration as shown in FIG. 6, a nitride semiconductor growth layer 11 is laminated on a processing substrate 10 in which SiO ₂ walls 17 are formed at both ends of a dug region 16 and a hill 19, and the surface A p-side electrode pad 60 made of an insulating film such as the SiO ₂ film 13 and the p-side electrode 14 (see FIG. 1) is formed. Since the p-side electrode pad 60 is subjected to wire bonding on the surface thereof, the thickness is usually set to about 100 nm to 1 μm. At this time, in the “embedded current confinement laser” that has a current confinement layer in the nitride semiconductor growth layer 11 and performs current confinement in this layer, only the p-side electrode 14 becomes the p-side electrode pad 60. In addition, a convex stripe 18 is provided on the surface of the p-side electrode pad 60 thus configured, and an n-side electrode 15 is formed on the back surface of the processed substrate 10. Furthermore, at this time, as shown in FIG. 6, the distances from both ends of the p-side electrode pad 60 to the end portions of the digging region 16 adjacent to both ends are M and N, respectively.

The p-side electrode pad 60 formed in this way is not formed on the digging region 16 as shown in FIG. This is because, since the surface of the nitride semiconductor growth layer 11 is not flat on the digging region 16, when an insulating film such as SiO ₂ is formed on the surface, there are cracks, threading dislocations, holes, and a partial thickness. This is because there are thin portions and the like, and the insulating property is low as compared with other regions other than the digging region 16, and a leak current flows.

In the state where the digging region 16 is buried, the digging region 16 is buried by stacking the nitride semiconductor thin film even if the groove or the depression is not visually confirmed. Defects, dislocations, cracks and the like are generated in the nitride semiconductor thin film in the digging region 16. For this reason, when SiO ₂ or the like is formed on the surface of the nitride semiconductor growth layer 11 in the digging region 16, the insulating property is lowered. Therefore, when the p-side electrode pad 60 is formed on the digging region 16 or the depression, spontaneous emission light may be confirmed in that region. The spontaneous emission light is generated when a leak current flows in the nitride semiconductor laser element. Furthermore, since the inflow prevention portions 44 having a width in the direction parallel to the [11-20] direction of about 10 μm to 30 μm are formed at both ends of the hill 19, the p electrode pad 60 is formed in that region. It is not preferable.

  From the above, when the p-side electrode pad 60 is formed at a distance of 30 μm or more from the end of the digging region 16, light emission from the region other than the region of the laser stripe 12 (see FIG. 1) is not observed for the spontaneous emission light described above. It was. Therefore, the distances M, N from the end of the dug region 16 to both ends of the p-side electrode pad 60 are preferably 30 μm or more.

Further, in the present embodiment, the ridge stripe type laser that performs current confinement using an insulating film such as SiO ₂ on the nitride semiconductor growth layer 11 has been described. However, the present invention is not limited to this. A VSIS (V-channeled Substrate Inner Stripe) type laser having a current confinement layer inside the growth layer 11 may be used. Such a laser does not have an insulating film for current confinement on the surface of the nitride semiconductor growth layer 11, and the p-side electrode pad 60 comprises only the p-side electrode 14. In this specification, an electrode pad refers to an electrode pad on an insulating film or the electrode itself. Even in such a laser, when the p-side electrode pad 60 is formed in the digging region 16, a large leak current is generated as in the ridge stripe type laser, the characteristics of the nitride semiconductor laser device are deteriorated, and laser oscillation occurs. I couldn't. This is presumably because the crystallinity of the current confinement layer above the digging region 16 has deteriorated. Therefore, even in a laser such as a VSIS type laser, the distances M and N from the end of the digging region 16 to both ends of the p-side electrode pad 60 are preferably 30 μm or more.

  In this embodiment, n-type GaN is used as the processed substrate 10 and the electrode pad formed on the surface of the nitride semiconductor growth layer 11 is the p-side electrode pad. However, the present invention is not limited to this, and the processed substrate 10 Also, a nitride semiconductor laser device having a structure in which a p-type semiconductor material is used, the surface of the nitride semiconductor growth layer 11 is composed of an n-type nitride semiconductor thin film, and an electrode pad formed on the surface is an n-side electrode pad. I do not care.

  Also, depending on the structure of the nitride semiconductor laser element, when wire bonding is performed, the diameter of the ball portion at the tip of the wire is approximately 80 μm, so the width of the p-side electrode pad 60 is approximately 80 μm or more. is there. Therefore, the interval T between adjacent digging regions 16 is T ≧ {width of the p-side electrode pad 60 (80 μm or more) +60 μm (the sum of the distances M and N between both ends of the p electrode pad 70 and the end of the digging region 16) Minimum value)}. That is, if the interval T between the adjacent dug regions 16 is smaller than 140 μm, it becomes difficult to manufacture the nitride semiconductor laser element. For this reason, it is preferable that the space | interval T of the adjacent digging area | region 16 is 140 micrometers or more. Further, if the value of T is larger than 4 mm, cracks are likely to occur in the laminated nitride semiconductor thin film. As a result, the value of the interval T between the adjacent dug regions 16 is preferably 140 μm or more and 4 mm or less. .

  Further, individual nitride semiconductor laser elements can be obtained by dividing the bar shown in FIG. 6 described above into chips. Hereinafter, chip division will be described with reference to the drawings.

  When performing such chip division, first, one of the chip division portions 61 or 62 shown in FIG. 6 is scribed. The chip division location 62 becomes the surface of the nitride semiconductor growth layer 11 stacked on the digging region 16 included in the processing substrate 10, and the chip division location 61 becomes the back surface of the processing substrate 10 that is a portion immediately below the digging region 16. Become the side. This scribing is performed with a diamond pen or the like. A blade having a sharp tip shape is applied to this scribed line (hereinafter referred to as a scribe line), and pressure is applied using a braking device to break it. The position of the scribe line is preferably at the center of the digging region 16. However, in the present embodiment, as described above, the digging region 16 is not completely filled with the nitride semiconductor growth layer 11, and a groove is formed, so that the groove serves as a guide when the chip is divided. For this reason, even if the position of the scribe line is deviated from the center of the digging region 16, it is possible to prevent the occurrence of chipping or unintended division in the digging region 16.

  Further, even when the position of the scribe line is deviated from the digging area 16, when the chip is divided, the breaking direction may be separated from the scribe line, and the crack may proceed in an unintended direction. However, even if this unintentional crack occurs, when the crack reaches the adjacent digging region 16, the crack advances along the groove in the digging region 16, and therefore the adjacent nitride semiconductor laser element is also reached. There is no destruction. The reason why the divided portion does not spread out from the digging region 16 as described above is that the crystallinity and the plane orientation of the nitride semiconductor thin film stacked in the digging region 16 are in a flat portion on the hill 19. This is considered to be because it is different from the grown nitride semiconductor thin film.

  In the present embodiment, as shown in FIG. 6, one nitride semiconductor laser element is fabricated on a hill 19 that is an unexcavated region sandwiched between adjacent excavated regions 16. However, the present invention is not limited to this, and a plurality of nitride semiconductor laser elements may be manufactured. In the present embodiment, the digging region 16 is composed of one concave portion, but is not limited to this, and may be composed of a plurality of concave portions and a narrow flat portion sandwiched between the concave portions. Absent.

In the method according to this embodiment described above, a nitride semiconductor laser element is formed using a processed substrate on which a SiO ₂ wall 17 having a thickness T of 500 nm and a width D in the direction parallel to the [11-20] direction of 3 μm is formed. Several were produced. Then, 100 nitride semiconductor laser elements were randomly taken out from them, and the half-value widths of the FFP in the horizontal direction and the vertical direction were measured. At this time, when the nitride semiconductor laser element within ± 1 degree with respect to the design value of the half-width of the FFP was determined to be a non-defective product, there were 92 nitride semiconductor lasers whose half-width of the FFP satisfied the standard. . In contrast, in the case of the nitride semiconductor laser device manufactured using the above-described conventional technique, there are 30 non-defective products, and it can be seen that the yield is greatly improved as compared with that.

  This is because, in the region where the nitride semiconductor laser device is manufactured, the convex flow-in prevention portions 44 are formed on both ends of the hill 19 so that the inside of the digging region 16 of atoms / molecules as the raw material of the nitride semiconductor thin film is formed. This is because the migration to the server could be suppressed. That is, the surface flatness of the region in which the nitride semiconductor laser device is manufactured is improved, and as a result, the thicknesses of the nitride semiconductor thin films constituting the nitride semiconductor growth layer 11 become uniform.

  Further, by using the processed substrate 10 provided with the digging region 16, the strain included in the nitride semiconductor growth layer 11 becomes non-uniform in the wafer surface, and the strain is applied in various directions. The strain included in the layer 11 can be released. Furthermore, the release of the strain was promoted by making the digging region not completely buried by the nitride semiconductor growth layer 11. Therefore, no crack was generated.

<Second Embodiment>
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 7 is a schematic cross-sectional view of a part of a wafer in which a nitride semiconductor thin film is grown on the processed substrate 10 in the present embodiment. Unlike the first embodiment, SiO ₂ walls are not formed at both ends of the hill 19 which is a region where the processed substrate 10 is not dug.

  FIG. 7 shows a schematic cross-sectional view of the wafer when a nitride semiconductor thin film is grown on the processed substrate 10 having such a dug region 16. As shown in FIG. 7, the nitride semiconductor thin film is prevented from flowing into the vicinity of the digging region 16 at both ends of the upper surface portion 71 of the hill 19 as an upper surface growth portion 75 in the central portion of the upper surface portion 71 of the hill 19. As the portion 74, the side surface portion 72 and the bottom surface portion 73 in the digging region 16 grow as digging region growing portions 77, respectively. Further, the inflow prevention portion 74 and the in-digging region growth portion 77 are connected via the growth portion 76.

As shown in FIG. 7, in the present embodiment, even if the SiO ₂ wall is not formed, the inflow prevention portion 74 that rises in a convex shape is formed, and the inflow prevention portion 74 is more than the upper surface growth portion 75. The nitride semiconductor thin film grows thick and a step is formed. Hereinafter, the value of the step is assumed to be H. The difference in thickness of the nitride semiconductor growth layer 11 between the inflow prevention portion 74 and the upper surface growth portion 75 is that the nitride semiconductor in the inflow prevention portion 74 at both ends of the upper surface portion 71 of the hill 19 in the vicinity of the digging region 16. This is because the growth rate of the thin film is higher than the growth rate of the nitride semiconductor thin film in the upper surface growth portion 75 that is a region other than both ends of the upper surface portion 71 of the hill 19. As described above, the growth rate of the nitride semiconductor thin film is greatly different between the inflow prevention portion 74 and the upper surface growth portion 75 because the atoms and the raw material of the nitride semiconductor thin film adsorbed on the growth surface of the nitride semiconductor thin film once. This is because the re-evaporation probability, which indicates the probability that the molecule evaporates again from the growth surface without forming a nitride semiconductor thin film, is different.

  That is, the atoms / molecules that are the raw materials attached to the surface of the nitride semiconductor thin film grown on the upper surface portion 71 of the hill 19 between the dug regions 16 migrate on the growth surface and are stable in terms of energy. After moving to the region, it combines with the surface atoms and molecules to form a nitride semiconductor thin film. However, if it cannot move to a region that is stable in energy within a certain time, it re-evaporates from the growth surface. Further, when the digging region 16 is formed on the substrate surface like the processed substrate 10, the most stable portion in terms of energy in the upper surface portion 71 of the hill 19 between the digging regions 16 is in the vicinity of the digging region 16. It is known that both ends. Therefore, the re-evaporation probability at both ends near the dug area 16 is low. As a result, the growth rate of the nitride semiconductor thin film at both ends of the upper surface portion 71 of the hill 19 in the vicinity of the digging region 16 is higher than the other portions of the upper surface portion 71 of the hill 19, and as a result, the upper surface growth portion 75. As a result, the inflow prevention part 74 is formed in which the nitride semiconductor thin film is grown thicker.

  Such an inflow prevention part 74 is formed by growing a GaN layer or an AlGaN layer on the processed substrate 10. Further, when GaN and AlGaN are compared, the tendency of migration of atoms and molecules as raw materials for GaN is more pronounced when GaN is formed. For this reason, atoms / molecules that are GaN raw materials attached to the upper surface portion 71 of the hill 19 usually move by migrating into the digging region 16, and digging regions are formed on the surfaces of the side surface portion 72 and the bottom surface portion 73. As the inner growth portion 77 grows thick GaN, the inflow prevention portion 74 is formed only with the inflow prevention portion 74 having a step H of only about 10 nm from the surface of the upper surface growth portion 75. On the other hand, when an AlGaN film is formed, the tendency of migration of atoms / molecules (particularly Al) as a raw material for AlGaN is weak. For this reason, the atoms / molecules that are the raw material of AlGaN adhering to the upper surface portion 71 of the hill 19 do not move into the digging region 16 but remain on the upper surface portion 71 of the hill 19. The atoms and molecules as the raw material of AlGaN remaining on the upper surface portion 71 of the hill 19 migrate on the upper surface portion 71 of the hill 19. At this time, as described above, since both ends of the upper surface portion 71 of the hill 19 are energetically stable regions, re-evaporation of atoms / molecules serving as a raw material for AlGaN in the region is suppressed, and a film is formed. As a result, an AlGaN layer that is thicker than the upper surface growth portion 75 grows to form the inflow prevention portion 74. The inflow prevention portion 74 formed by the AlGaN layer has a thick layer thickness when the Al composition ratio of AlGaN is 2% or more. Thus, by forming the flow-in prevention part 74, atoms / molecules serving as a raw material for AlGaN adhering to the surface of the upper surface growth part 75 migrate only on the surface of the upper surface growth part 75. Therefore, the upper surface growth portion 75 with good surface flatness is formed. Further, the width Z in the direction parallel to the [11-20] direction of the inflow prevention portion 74 formed in this way (see FIG. 7) is a value of about 10 to 30 μm.

  As described above, the nitride semiconductor growth layer 11 made of a plurality of nitride semiconductor thin films is stacked on the processed substrate 10 having the digging region 16 and the hills 19, and the surface of the upper surface growth portion 75 and the flow-in prevention are prevented as described above. A plurality of nitride semiconductor laser elements each having a step H between the tip portion of the portion 74 were fabricated. Then, 100 nitride semiconductor laser elements were randomly taken out from them, and the half-value widths of the FFP in the horizontal direction and the vertical direction were measured. At this time, a nitride semiconductor laser element within ± 1 degree with respect to the design value of the half width of the FFP was regarded as a good product. FIG. 8 shows a correlation diagram of the number of nitride semiconductor laser elements that are stepped and non-defective. As shown in FIG. 8, when the step H is 150 nm or more, the number of non-defective nitride semiconductor laser elements is 85 or more, and a high yield result is obtained. On the other hand, when the step H is smaller than 150 nm, the number of non-defective nitride semiconductor laser elements is 40 or less, and the yield is drastically reduced. This is because, in a nitride semiconductor laser element having a step H of less than 150 nm, the thickness of each nitride semiconductor thin film stacked on the upper surface 71 of the hill 19 is not only in the wafer plane but also one nitride semiconductor laser. This is because there is variation in the elements. Therefore, in order to manufacture a nitride semiconductor laser device with a high yield, it is necessary that the step H between the surface of the upper surface growth portion 75 and the tip portion of the inflow prevention portion 74 is 150 nm or more. That is, by setting the step H to 150 nm or more, each nitride layered on the upper surface portion 71 of the hill 19 is formed when the nitride semiconductor growth layer 11 composed of a plurality of nitride semiconductor thin films is formed on the processed substrate 10. By obtaining sufficiently good surface flatness on the surface of the semiconductor thin film, variations in the layer thickness of each nitride semiconductor thin film can be suppressed.

  Further, as described above, when the inflow prevention portion 74 is manufactured using AlGaN, even if GaN having a strong tendency to migrate is grown thereafter, the GaN raw material is introduced into the digging region 16 by the inflow prevention portion 74. Movement due to migration of atoms and molecules is suppressed. That is, when AlGaN having a low migration tendency is first formed on the processed substrate 10, the inflow prevention portion 74 having a large step H with respect to the surface of the upper surface growth portion 75 is formed. Thereafter, even if a GaN film having a strong tendency to migrate is formed, the growth of the GaN as the digging region growth portion 77 on the side surface portion 72 and the bottom surface portion 73 in the digging region 16 is suppressed.

Further, even when GaN is first formed on the processed substrate 10, if the GaN layer thickness is 0.5 μm or less, then, for example, n-type Al _0.062 Ga _0.938 N shown in FIG. By sequentially laminating the nitride semiconductor thin films from the first cladding layer 101 to the p-type GaN contact layer 109, the inflow prevention portion 74 having a step value H of 150 nm or more can be formed. On the other hand, when the layer thickness of GaN is thicker than 0.5 μm, atoms / molecules as GaN raw material migrate and flow into the digging region 16, and grow in the digging region on the side surface portion 72 and the bottom surface portion 73. As shown in FIG. 12B, most of the digging region 16 is buried with GaN. As a result, migration to the digging region 16 is further promoted, the GaN layer thickness becomes non-uniform, and the surface flatness of the upper surface growth portion 75 deteriorates. Accordingly, when the nitride semiconductor growth layer 11 having the structure as shown in FIG. 10 is stacked, the thickness of the n-type GaN layer 100 in contact with the surface of the processed substrate 10 is set to 0.5 μm or less, whereby the n-type GaN is formed. Inflow of atoms / molecules as a raw material of the layer 100 is suppressed. Even if the n-type GaN layer 100 is not stacked on the surface of the processed substrate 10 and the nitride semiconductor growth layer 11 is formed starting from the n-type Al _0.062 Ga _0.938 N first clad layer 101, the surface flatness is _maintained . A good nitride semiconductor growth layer 11 can be produced.

In this way, the AlGaN is grown on the processed substrate 10 having the digging region 16 to form the inflow prevention portion 74. Even in the case of growing GaN, the susceptor temperature, the molar ratio of raw materials V / III (controlling the ratio of the number of moles of flow rate supplied per unit time of NH ₃ as a raw material of group V to the number of moles of flow rate per unit time of TMGa as a raw material of group III Ga) As a result, it was found that the inflow prevention wall 74 having a step difference H with respect to the upper surface growth portion 75 of 150 nm or more can be produced by suppressing the migration of atoms / molecules as the raw material of GaN. Hereinafter, the growth conditions for forming the inflow prevention portion 74 where the step H with respect to the surface of the upper surface growth portion 75 is 150 nm or more by growing GaN on the processed substrate 10 provided with the digging region 16 will be described. Note that the susceptor temperature is substantially equal to the surface temperature of the processed substrate.

  Normally, when the n-type GaN layer 100 (see FIG. 10) is grown on the processed substrate 10, the susceptor temperature on which the processed substrate 10 (wafer) is placed is 1075 ° C. In this case, atoms / Molecules migrate to cause a large inflow into the digging region 16 and the inflow prevention portion 74 having a sufficiently large step H is not formed. Therefore, when the susceptor temperature is set to 1025 ° C., which is 50 ° C. lower than the normal susceptor temperature, and n-type Ga is grown at that temperature, the step H with respect to the surface of the upper surface growth portion 75 is 300 nm. 74 was formed. This is presumably because by lowering the susceptor temperature, the temperature of the surface of the processed substrate 10 is lowered, and as a result, migration of atoms and molecules (Ga atoms, N atoms, etc.) that are raw materials of n-type GaN is suppressed.

In addition, regarding the molar ratio V / III of the raw material, the n-type GaN layer 100 is usually grown under film forming conditions in which the molar ratio V / III of the raw material is 1033. The n-type GaN layer 100 was grown under film forming conditions in which the value of / III was doubled to 2066. At this time, under normal film forming conditions, the step H between the upper surface growth portion 75 and the inflow prevention portion 74 is approximately 10 nm, whereas the value of the molar ratio V / III of the raw materials is 2066 and 2000 or more. In the case of the value, the step H is about 320 nm, and the inflow prevention portion 74 having a sufficiently large step H is formed. This is because when the GaN raw material atoms and molecules adhere to the growth film surface and migrate the growth film surface by thermal energy, if the raw material molar ratio V / III is large, the supply amount of NH ₃ is very high. This is because N atoms in NH ₃ and Ga in TMGa react quickly and become GaN and are taken into the film. That is, when the molar ratio V / III of the raw material is large, the migration of atoms / molecules (Ga atom, N atom, etc.) serving as the GaN raw material on the growth film surface is suppressed, and as a result, AlGaN is formed. As in the case, the inflow prevention portion 74 having a large step H is formed. On the contrary, when the molar ratio V / III of the raw material is small, the supply amount of NH ₃ is small, so that the Ga atoms attached to the growth film surface cannot react with N atoms promptly to become GaN. Therefore, the distance moved by migration on the surface of the growth film of atoms / molecules which are raw materials of GaN such as Ga atoms is increased, and the flow into the digging region 16 is promoted. That is, by increasing the value of the raw material molar ratio V / III to 2000 or more, the migration of atoms / molecules as the GaN raw material on the growth film surface is suppressed, and sufficient between the surface of the upper surface growth portion 75. An inflow prevention portion 74 having a large step H is formed.

As described above, when the nitride semiconductor growth layer 11 composed of a plurality of nitride semiconductor thin films is stacked on the processed substrate 10, the n-type GaN layer 100 is formed, so that 150 nm is formed between the upper surface growth portion 75. In order to form the inflow preventing portion 74 having the above step H, first, only the n-type GaN layer 100 is formed at a susceptor temperature of 1025 ° C., and then the susceptor temperature is increased to 1075 ° C. The n-type Al _0.062 Ga _0.938 N first clad layer 101 to p-type GaN contact layer 109 except for 105 are formed. The multi-quantum well active layer 105 is formed at 700 ° C. to 800 ° C. because the vapor pressure of In increases at 1075 ° C. and In is not taken into the film.

Further, only the n-type GaN layer 100 is formed under a film forming condition in which the raw material molar ratio V / III is 2000 or more, and then at least the n-type Al _0.062 Ga _0.938 N first cladding layer 101 to n-type Al. _{The 0.062} Ga _0.938 N third cladding layer 103 is formed with a raw material molar ratio V / III value of 2000 or less. At this time, for the n-type GaN guide layer 104 to the p-type GaN contact layer 109 to be subsequently formed, the value of the raw material molar ratio V / III may be 2000 or more and 2000 or less.

  By forming the n-type GaN layer 100 using each of these conditions and laminating the nitride semiconductor growth layer 11 on the processed substrate 10, the flow difference H between the upper surface growth portion 75 becomes 150 nm or more. The prevention part 74 is formed. Therefore, as a result, the nitride semiconductor growth layer 11 can be a laminate of nitride semiconductor thin films having good surface flatness. When the n-type GaN layer 100 is formed, the above two conditions are combined, that is, the susceptor temperature is 1025 ° C., and the raw material molar ratio V / III is 2000 or more. It doesn't matter.

  In addition, when forming the inflow prevention portion 74 when laminating the nitride semiconductor growth layer 11 in this way, the narrower one with respect to the width Z of the inflow prevention portion 74 in the direction parallel to the [11-20] direction, The flat portion of the hill 19 is widened, which is preferable for producing a nitride semiconductor laser device on the surface. Furthermore, the width Z can be made narrower as the atoms / molecules that are the raw materials of GaN migrate more strongly, but if the tendency to migrate becomes too strong, the flow into the digging region 16 is not preferable. From the above, it is preferable to control the width Z of the inflow prevention portion 74 to be 10 to 30 μm.

1 is a schematic diagram of a nitride semiconductor laser device according to a first embodiment of the present invention. It is a schematic sectional drawing of the process board | substrate with which the digging area | region of various shapes was formed. It is the schematic of the process board | substrate in the 1st Embodiment of this invention. In the 1st Embodiment of this invention, it is a schematic sectional drawing of a part of wafer at the time of growing a nitride semiconductor thin film on a process board | substrate. It is explanatory drawing of the embedding condition of a digging area. It is the schematic of the nitride semiconductor substrate divided | segmented into the bar shape in the 1st Embodiment of this invention. In the 2nd Embodiment of this invention, it is a schematic sectional drawing of a part of wafer at the time of growing a nitride semiconductor thin film on a process board | substrate. In the 2nd Embodiment of this invention, it is a correlation diagram of the level | step difference H and the number of good products. It is the schematic of the wafer which laminated | stacked the nitride semiconductor growth layer on the conventional process board | substrate. It is a schematic sectional drawing of a nitride semiconductor growth layer. It is a surface level | step difference plot figure of the wafer which laminated | stacked the nitride semiconductor growth layer on the conventional process board | substrate. It is explanatory drawing explaining the model of flatness deterioration.

Explanation of symbols

10 processed substrate 11 nitride semiconductor growth layer 12 the laser stripe 13 SiO ₂ film 14 p-side electrode 15 n-side electrode 16 recessed region 17 SiO ₂ wall 17a SiO ₂ wall 17b SiO ₂ wall 18 stripe 19 hills 41 top portion 42 side portion 43 bottom surface portion 44 inflow prevention portion 45 upper surface growth portion 46 growth portion 47 growth portion in digging region 60 p-side electrode pad 61 chip division location 62 chip division location 71 upper surface portion 72 side surface portion 73 bottom surface portion 74 inflow prevention portion 75 upper surface growth Part 76 growth part 77 growth part in the digging region 100 n-type GaN layer 101 n-type Al _0.062 Ga _0.938 N first cladding layer 102 n-type Al _0.1 Ga _0.9 N second cladding layer 103 n-type Al _0.062 Ga _0.938 N third Clad layer 104 n-type GaN guide layer 105 Multiple quantum well active layer 106 p Al _0.3 Ga _0.7 N evaporation preventing layer 107 p-type GaN guide layer 108 p-type Al _0.062 Ga _0.938 N cladding layer 109 p-type GaN contact layer 121 top growth portions 122 engraved area growth portions 123 top portion 124 bottom portion 125 growth portions 126 Side

Claims (23)

A first step of producing a processed substrate by forming a digging region composed of at least one concave portion and a hill portion which is a non-digging region on a substrate having a nitride semiconductor layer on at least a part of the surface; In a method for manufacturing a semiconductor device,
A second step of forming a flow-in prevention wall consisting of convex portions on both ends of the hill portion provided in the processed substrate;
By forming a nitride semiconductor stacked portion composed of at least one type of nitride semiconductor thin film on both the digging region of the processed substrate and the hill surface where the flow-in prevention wall is formed in the second step, The nitride semiconductor multilayer portion is stacked on the inflow prevention wall formed at both ends of the hill, and a step is provided between the flat surface of the nitride semiconductor multilayer portion stacked on the hill surface. A third step of forming the convex inflow prevention portion formed,
The manufacturing method of the semiconductor element characterized by the above-mentioned. When forming the nitride semiconductor multilayer portion in the third step,
The method for manufacturing a semiconductor device according to claim 1, wherein the concave portion of the digging region is not completely buried. In the second step,
_{3. The} method of manufacturing a semiconductor device according to claim 1, wherein the inflow prevention wall is made of any one of SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZrO, and W. 4. In forming the flow-in prevention wall in the second step,
The thickness of the normal direction which is a direction perpendicular | vertical to the said hill surface in the said inflow prevention wall is 50 nm or more and 3 micrometers or less, The semiconductor element in any one of Claims 1-3 characterized by the above-mentioned. Production method. In forming the flow-in prevention wall in the second step,
5. The method of manufacturing a semiconductor element according to claim 1, wherein a width of the flow preventing wall in a direction perpendicular to a longitudinal direction is 1 μm or more and 25 μm or less. Forming an electrode pad for performing wire bonding for electrical connection with the outside on the nitride semiconductor laminated portion laminated on the processed substrate surface having the flow-in prevention wall in the third step; A fourth step of forming a plurality of semiconductor elements on the substrate;
In the fourth step,
6. The method of manufacturing a semiconductor element according to claim 1, wherein the electrode pad is not formed on an upper portion of the digging region. A first step of forming a processed substrate by forming a digging region composed of at least one recess and a hill portion which is a non-digging region on a substrate having a nitride semiconductor layer on at least a part of the surface; In a method for manufacturing a semiconductor device, comprising: a second step of laminating a nitride semiconductor multilayer portion composed of at least one kind of nitride semiconductor thin film on both the dug region provided on the processed substrate and the hill surface.
In the second step,
The film thickness from the hill surface to the nitride semiconductor multilayer surface of the nitride semiconductor multilayer portion laminated on both ends of the hill portion in the vicinity of the digging region is determined at both ends of the hill portion. The both ends of the hill part which becomes the vicinity of the digging area | region by laminating | stacking thicker than the film thickness from the hill part surface of the nitride semiconductor lamination | stacking part laminated | stacked to area | regions other than a part to the nitride semiconductor lamination part surface Forming a flow-in prevention part having a convex shape with respect to a flat part surface of the nitride semiconductor laminated part laminated on a surface of a region other than both ends of the hill part on both sides Device manufacturing method. When forming the nitride semiconductor multilayer portion in the second step,
The method of manufacturing a semiconductor device according to claim 7, wherein the concave portion of the digging region is not completely buried. In the second step,
The step formed between the flat part surface of the nitride semiconductor laminated part laminated on the hill surface and the convex inflow prevention part is 150 nm or more, or 9. A method for producing a semiconductor device according to 8. In the second step,
The method for manufacturing a semiconductor device according to claim 7, wherein the nitride semiconductor thin film in contact with the processed substrate surface is made of GaN having a thickness of 0.5 μm or less. In the second step,
The method for manufacturing a semiconductor device according to claim 7, wherein the nitride semiconductor thin film in contact with the surface of the processed substrate is AlGaN. In the second step,
The nitride semiconductor thin film in contact with the processed substrate surface is GaN,
10. The method of manufacturing a semiconductor element according to claim 7, wherein the substrate surface temperature when forming the GaN film on the processed substrate surface is set to 1025 ° C. 10. In the second step,
The nitride semiconductor thin film in contact with the processed substrate surface is GaN,
When forming the GaN film, the number of moles of the flow rate supplied per unit time of the raw material containing group V nitrogen atoms relative to the number of moles of the flow rate supplied per unit time of the raw material containing group III gallium atoms The method of manufacturing a semiconductor element according to claim 7, wherein the ratio of the above is 2000 or more. In the second step,
The semiconductor according to any one of claims 7 to 13, wherein the nitride semiconductor thin film constituting the nitride semiconductor multilayer portion includes an AlGaN layer having an Al composition ratio of 0.02 or more. Device manufacturing method. A plurality of semiconductors are formed on the substrate by forming electrode pads for performing wire bonding for electrical connection with the outside on the nitride semiconductor laminated portion laminated on the processed substrate surface in the second step. Comprising a fourth step of forming the element;
In the fourth step,
The method of manufacturing a semiconductor element according to claim 7, wherein the electrode pad is not formed on an upper portion of the digging region. In the fourth step,
The method of manufacturing a semiconductor device according to claim 6, wherein the electrode pad is formed at a distance of 30 μm or more from an end of the digging region.   The method for manufacturing a semiconductor device according to claim 1, wherein one semiconductor device is formed in the hill portion sandwiched between two adjacent digging regions.   The method of manufacturing a semiconductor element according to claim 1, wherein a plurality of the semiconductor elements are formed in the hill portion sandwiched between two adjacent digging regions.   The chip division is performed by scribing the surface of the nitride semiconductor laminated portion laminated in the digging region or the back side of the processed substrate which is a portion immediately below the digging region. The method for manufacturing a semiconductor device according to claim 17. In the first step, when forming the digging region consisting of the recess,
The depth of the said recessed part is 1 micrometer or more and 20 micrometers or less, The manufacturing method of the semiconductor element in any one of Claims 1-19 characterized by the above-mentioned. In the first step, when forming the digging region consisting of the recess,
21. The method of manufacturing a semiconductor element according to claim 1, wherein an opening width of the concave portion is 1 [mu] m or more. In the first step, when forming the digging region consisting of the recess,
The method of manufacturing a semiconductor element according to any one of claims 1 to 21, wherein a width of the hill portion sandwiched between adjacent digging regions is 140 µm or more and 4 mm or less.   A semiconductor element manufactured by the method for manufacturing a semiconductor element according to claim 1.

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