JP2012239010A - Solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state image pickup device that enables a higher frame rate than a conventional device.SOLUTION: In a solid image pickup device, plural drive circuits 61 are provided corresponding to plural horizontal signal lines LT1, and output drive signals TX1 for driving respective pixel parts 10 connected to the corresponding horizontal signal lines via the corresponding horizontal signal lines, respectively. A control circuit 80 outputs row selection signals AB_B-AD_B indicating whether a corresponding row of the rows of the plural pixel parts is a selection row or not to the plural drive circuits, respectively. Each of the drive circuits includes a first latch circuit 61A that is brought into a setting condition according to the row selection signals, and a second latch circuit 62B that is brought into a setting condition according to the condition of the first latch circuit. The drive signals TX1 are output according to the condition of the second latch circuit 61B.

Description

  The present invention relates to a solid-state imaging device.

  Until now, film-type cameras have been the mainstream, but recently, digital cameras have been replaced by digital cameras. The improvement in image quality of digital cameras is remarkable, and the latest digital cameras have surpassed the performance of film cameras. The digital camera is equipped with a CCD (Charge Coupled Device) type or CMOS (Complementary Metal-Oxide Semiconductor) type image sensor.

  In a CMOS image sensor, a photodiode, a floating diffusion, an amplification transistor, and the like are provided for each pixel. The electric charge generated in the photodiode is accumulated in the floating diffusion, and a voltage signal corresponding to the accumulated electric charge is output from the amplification transistor.

  In the CMOS method, since a fixed amplification transistor is assigned to each pixel, fixed pattern noise is generated for each amplification transistor, and the image quality is inferior to that of the CCD method. However, in recent years, an image quality higher than that of a CCD has been obtained due to the progress of correction techniques such as CDS (Correlated Double Sampling). As a result, it is increasingly used in digital single-lens reflex cameras because it can be designed in a large size, which is an advantage of the CMOS method, and can reduce costs.

  Recently, digital cameras and camcorders have captured each other's functions. That is, it corresponds to the moving picture of the digital camera and the still picture of the video camera. In digital single-lens reflex cameras, it is becoming an essential function to support high-quality full-high definition (Full-HD) moving images by taking advantage of the features.

  Japanese Patent Laying-Open No. 2009-33316 (Patent Document 1) discloses pixel mixing in which charges accumulated in a plurality of pixels are mixed and read for each predetermined number of pixels. Pixel mixing is an indispensable technique when shooting a moving image using a high-resolution digital camera having a larger number of pixels than a video camera.

  Japanese Patent Laying-Open No. 2003-274291 (Patent Document 2) discloses a solid-state imaging device using a shift register in a scanning circuit for selecting pixels. This shift register is composed of a plurality of transfer registers capable of normal scanning and reverse scanning, and each transfer register is composed of a master circuit and a slave circuit.

JP 2009-33316 A JP 2003-274291 A

  In capturing a moving image using a CMOS image sensor, a rolling electronic shutter system is generally used in which shutters are sequentially released for each scanning line (that is, a shutter operation and a signal reading operation are performed for each row). In the rolling electronic shutter system, it is necessary to select a pixel reset row for resetting the accumulated charge of the photodiode in the pixel and a readout row for reading the accumulated charge (different from the pixel reset row) within one vertical scanning period. In particular, when pixel mixing is performed, it is necessary to select a plurality of pixel reset rows and a plurality of readout rows within the same one vertical scanning period. Even when the pixel reset is performed a plurality of times in order to sufficiently discharge charges, it is necessary to select a plurality of pixel reset rows within the same vertical scanning period. As described above, in moving image shooting, since it is necessary to select many pixel reset rows and readout rows within one vertical scanning period, it is difficult to perform shooting at a high frame rate corresponding to FULL-HD. .

  Accordingly, an object of the present invention is to provide a solid-state imaging device capable of achieving a higher frame rate than before.

  A solid-state imaging device according to an embodiment of the present invention includes a plurality of pixel units, a plurality of horizontal signal lines, a plurality of drive circuits, and a control circuit. The plurality of pixel portions are arranged in a matrix, and each includes a photoelectric conversion element. The plurality of horizontal signal lines are provided corresponding to the rows of the plurality of pixel portions, respectively, and each is connected to each pixel portion included in the corresponding row. The plurality of driving circuits are provided corresponding to the plurality of horizontal signal lines, respectively, and drive signals for driving the respective pixel units connected to the corresponding horizontal signal lines via the corresponding horizontal signal lines. Output. The control circuit outputs a row selection signal indicating whether or not a corresponding row among the rows of the plurality of pixel portions is a selected row to each of the plurality of drive circuits. Each of the plurality of drive circuits includes a first latch circuit that is set based on a row selection signal and a second latch circuit that is set based on the state of the first latch circuit. The drive signal is output based on the state of the second latch circuit.

  According to the above-described embodiment, a high frame rate solid-state imaging device can be realized by driving each pixel unit provided in a corresponding row using the first and second latch circuits.

It is a block diagram which shows the structure of the image sensor (solid-state imaging device) by Embodiment 1 of this invention. 2 is a block diagram showing a configuration of a pixel array 1. FIG. FIG. 2 is a circuit diagram illustrating an example of a configuration of each pixel unit 10 provided in the pixel array 1 of FIG. 1. It is a figure for demonstrating vertical 3 pixel mixing. It is a timing diagram at the time of vertical 3 pixel mixing. It is a figure for demonstrating operation | movement of the vertical scanning part 2 when image | photographing a moving image with a rolling electronic shutter. FIG. 5 is a timing chart schematically showing a pixel reset operation and a read operation by a rolling electronic shutter method. It is a block diagram which shows the structure of the vertical scanning part 2 of FIG. 3 is a circuit diagram showing a configuration of a TX1 decoding unit 61. FIG. It is a timing diagram which shows typically operation of a vertical scanning part by a comparative example. It is a timing diagram which shows the row selection operation | movement by the vertical scanning part of a comparative example. FIG. 6 is a timing chart schematically showing the operation of the vertical scanning unit according to the present embodiment. It is a block diagram which shows the structure of 2 A of vertical scanning parts used with the image sensor by Embodiment 2 of this invention. 3 is a circuit diagram showing a configuration of a TX1 decoding unit 31. FIG. 3 is a circuit block diagram showing a part related to generation of a transfer signal TX in the control circuit 20. FIG. FIG. 16 is a block diagram showing components of the signal clock generation circuit 23 of FIG. 15. FIG. 17 is a timing diagram of each signal in the circuit of FIG. 16. FIG. 15 is a timing chart showing an operation of the vertical scanning unit 2A of FIG. 14 during reading. It is a block diagram which shows the structure of the vertical scanning part 2B used with the image sensor by Embodiment 3 of this invention. 3 is a circuit block diagram showing a part related to generation of a transfer signal TX in a control circuit 81. FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Basic configuration of image sensor]
FIG. 1 is a block diagram showing a configuration of an image sensor (solid-state imaging device) according to Embodiment 1 of the present invention. Referring to FIG. 1, the image sensor includes a pixel array 1, a vertical scanning unit 2, a horizontal scanning unit 3, a timing generator 4, an output circuit 5, a plurality of horizontal signal lines LR, LT1, LT0, LS, LF, and a plurality. Vertical signal lines LV.

(Configuration of pixel array)
FIG. 2 is a block diagram showing the configuration of the pixel array 1. The pixel array 1 includes a plurality of pixel portions 10 arranged in a plurality of rows and a plurality of columns. The horizontal signal lines LR, LT1, LT0, LS, and LF are provided corresponding to the rows of the plurality of pixel units 10 constituting the pixel array 1, and are respectively provided in the columns of the plurality of pixel units 10 constituting the pixel array 1. Correspondingly, a vertical signal line LV is provided.

  FIG. 3 is a circuit diagram showing an example of the configuration of each pixel unit 10 provided in the pixel array 1 of FIG. Referring to FIG. 3, each pixel unit 10 includes two photodiodes (photoelectric conversion elements) 11A and 11B, two transfer transistors 12A and 12B, a reset transistor 13, an amplification transistor 14, and a selection transistor 15. , FD connection transistor 16.

  The photodiodes 11A and 11B store an amount of negative charge corresponding to the intensity of incident light. The anodes of the photodiodes 11A and 11B are connected to the ground node GND, and the cathodes thereof are connected to the floating diffusion FD via the transfer transistors 12A and 12B. The floating diffusion FD is a part that converts the negative charge read from the pixel into a voltage. The gates of transfer transistors 12A and 12B are connected to corresponding horizontal signal lines LT0 and LT1, and receive transfer signals TX0 and TX1, respectively. The transfer transistors 12A and 12B are selectively turned on by the transfer signals TX0 and TX1.

  The amplification transistor 14 and the selection transistor 15 are connected in series between the power supply node VCC and the corresponding vertical signal line LV (note that the same reference sign VCC is given to the power supply node and the power supply voltage). The gate of the amplification transistor 14 is connected to the floating diffusion FD. The gate of the selection transistor 15 is connected to the corresponding horizontal signal line LS and receives the selection signal SEL.

  The reset transistor 13 is connected between the power supply node VCC and the gate of the amplification transistor 14. The gate of the reset transistor 13 is connected to the corresponding horizontal signal line LR and receives the reset signal RST.

  The FD connection transistor 16 is connected between the floating diffusions FD of pixels adjacent in the vertical direction. The gate of the FD connection transistor 16 is connected to the corresponding horizontal signal line LF and receives the FD connection signal FDSW. The reason why the FD connection transistor 16 is provided is to realize vertical pixel mixing. By connecting a predetermined number of floating diffusions FD in the vertical direction, negative charges read from a plurality of photodiodes are mixed in the connected FD. This is equivalent to an increase in area per pixel due to pixel mixing, and image quality is improved.

  In the structure of the pixel unit 10, the other four transistors (reset transistor 13, amplification transistor 14, selection transistor 15, and FD connection transistor 16) except for the transfer transistors 12A and 12B are shared by the two photodiodes 11A and 11B. 3Tr type. The coefficient “3” of “3Tr type” means the number of transistors per one photodiode.

  Next, the operation of the pixel unit 10 will be briefly described. In the following description, the case where the negative charge generated in the photodiode 11A is read by setting the transfer signal TX0 to the “H” (high) level to turn on the transfer transistor 12A will be described. The same applies to the case where the negative charge generated in the photodiode 11B is read by setting the transfer signal TX1 to the “H” level to turn on the transfer transistor 12B.

  During the pixel reset operation, the transfer signal TX0 and the reset signal RST are set to the “H” level to turn on the transistors 12A and 13 to reset the negative charge stored in the photodiode 11A. When the transistors 12A and 13 are turned off by setting the transfer signal TX0 and the reset signal RST to the “L” (low) level, an amount of negative charge corresponding to the intensity of incident light is stored in the photodiode 11A.

  During the read operation, the selection signal SEL is set to “H” level to turn on the selection transistor 15. Next, the reset signal RST is set to “H” level for a predetermined time to turn on the reset transistor 13 and reset the floating diffusion FD to a voltage lower than the power supply voltage VCC by the threshold voltage of the reset transistor 13. At this time, a dark signal (reference signal) is generated on the vertical signal line LV via the transistors 14 and 15.

  Next, the transfer signal TX is set to “H” level for a predetermined time to turn on the transfer transistor 12A, and the cathode of the photodiode 11A is connected to the floating diffusion FD. At this time, an optical signal is generated on the vertical signal line LV via the transistors 14 and 15. The dark signal is used to correct the optical signal.

(Other peripheral circuit configurations)
Referring again to FIG. 1, timing generator 4 provides a clock, a row selection address, and a control signal to vertical scanning unit 2, and a column selection address and a control signal to horizontal scanning unit 3.

  The vertical scanning unit 2 has functions of a vertical scanning circuit and a voltage level shift circuit. The vertical scanning unit 2 sequentially selects a plurality of rows of the pixel array 1 in accordance with a row selection address and a control signal, and each pixel in the row via the horizontal signal lines LR, LT1, LT0, LS, LF of the selected row. A reset signal RST, transfer signals TX1, TX0, a selection signal SEL, and an FD connection signal FDSW (hereinafter, these signals are collectively referred to as “pixel drive signal”) are given to the unit 10 at a predetermined timing.

  As will be described later with reference to FIGS. 6 to 9, the vertical scanning unit 2 is provided with a latch circuit (master latch circuit and slave latch circuit) corresponding to each pixel drive signal for each row of the pixel array 1. It is done. When supplying a pixel drive signal to a certain row, the latch circuit corresponding to that row is set.

  The horizontal scanning unit 3 has functions of a horizontal scanning circuit and a column circuit. The horizontal scanning unit 3 receives a plurality of dark signals and optical signals output to each vertical signal line LV from each of the plurality of pixel units 10 included in the row selected by the vertical scanning unit 2. The column circuit corrects the optical signal received for each vertical signal line LV with a dark signal.

The output circuit 5 outputs a plurality of corrected optical signals generated by the horizontal scanning unit 3 to the outside.
The power supply voltage is different between the pixel array 1 and peripheral circuits such as the timing generator 4. The pixel array 1 requires a high power supply voltage in order to secure a saturation electron amount related to performance, and a peripheral circuit can use a fine process by reducing the power supply voltage. As a result, power consumption and circuit area can be reduced. For this reason, the vertical scanning unit 2 is provided with a voltage level shift circuit.

[Pixel mixture]
FIG. 4 is a diagram for explaining vertical three-pixel mixing.

  Referring to FIG. 4A, the pixel array of a general CMOS image sensor is a Bayer array. In the Bayer array, each pixel is assigned one color among red (R), green (G), and blue (B). The green (G) pixels are arranged in a checkered pattern, and the red (R) pixel and the blue (B) pixel are arranged between the green pixels. In FIG. 4, a green pixel adjacent to the red (R) pixel in the horizontal direction is described as Gr, and a green pixel adjacent to the blue (B) pixel in the horizontal direction is described as Gb. Note that two pixels adjacent in the vertical direction are included in one pixel unit 10 shown in FIG. That is, in FIG. 2, each row of the pixel portion 10 corresponds to two pixel rows.

  In order to realize the mixing of three pixels by the Bayer array, it is necessary to select three pixels every other pixel. Since the pixel unit 10 of the present embodiment has a structure in which two floating pixels in the vertical direction share one floating diffusion FD, vertical pixel mixing is achieved by connecting a plurality of vertical floating diffusions FD in succession. Can be realized.

  Specifically, in the case of FIG. 4, the three floating diffusions FD are connected in the vertical direction by turning on the two FD connection transistors 16 provided between the three floating diffusions FD. Then, the pixels of the same color in the three rows are activated by the pixel drive signal output from the vertical scanning unit 2. As a result, as shown in FIG. 4B, for each of R and Gr, the charges accumulated in the three vertical pixels can be mixed by the three connected floating diffusions FD.

  FIG. 5 is a timing chart when three vertical pixels are mixed. FIG. 5A shows a timing chart during the pixel reset operation, and FIG. 5B shows a timing chart during the reading operation. In FIGS. 5A and 5B, a period from time t1 to time t8 is referred to as one vertical scanning period (referred to as “1H”). One vertical scanning period is a unit for performing pixel reset operation and readout operation.

  Referring to FIG. 5A, during the pixel reset operation, the selection signal SEL is always at the “L” level, so that the selection transistor 15 in FIG. 3 is always in an off state. First, the reset signal RST becomes “H” level between time t3 and time t4, so that the reset transistor 13 in FIG. 3 is turned on. Next, between time t5 and time t6, for example, the transfer signals TX0 corresponding to the first, third, and fifth pixel rows are simultaneously turned on, so that these pixel rows The transfer transistor 12A provided in the pixel portion corresponding to is turned on. Usually, the pixel reset operation is repeated a plurality of times (for example, five times) in order to sufficiently discharge charges (electrons) accumulated in the cathode and floating diffusion of the photodiode.

  Referring to FIG. 5B, during the read operation, selection signal SEL is set to “H” level, whereby selection transistor 15 in FIG. 3 is maintained in the on state from time t2 to time t7. . First, between time t3 and time t4, the reset signal RST corresponding to the first, third, and fifth pixel rows is set to the “H” level, so that the reset transistor of FIG. 13 is turned on. Next, between time t5 and time t6, for example, the transfer signals TX0 corresponding to the first, third, and fifth pixel rows are simultaneously turned on, so that these pixel rows The transfer transistor 12A provided in the pixel portion corresponding to is turned on.

[Rolling electronic shutter]
FIG. 6 is a diagram for explaining the operation of the vertical scanning unit 2 when shooting a moving image with the rolling electronic shutter. In FIG. 6, the vertical axis indicates the row of the pixel array, and the horizontal axis indicates the time expressed in units of the vertical scanning period. In the figure, the pixel reset operation is indicated by “RS”, and the read operation is indicated by “RD”.

  In the CMOS image sensor, the pixel signal can be read only for each row. For this reason, in capturing moving images with a CMOS image sensor, a rolling electronic shutter system is generally used in which the shutter is sequentially released for each scanning line (that is, the shutter operation and the signal reading operation are performed for each row). It is also necessary to perform a pixel reset operation performed before each read operation for each row.

  Furthermore, pixel mixing or pixel thinning is necessary to capture a moving image with a digital camera having a high pixel count. For example, in order to output Full-HD (1920 (H) × 1080 (V)) moving image data with a digital camera having 10 million (10M) pixels (3600 (H) × 2800 (V)), the amount of data is reduced. It is necessary to reduce by 1/2 or more. Pixel mixing is equivalent to an increase in the area of the light-receiving surface, which is advantageous for high-sensitivity imaging in a dark place, but has the disadvantage of reducing spatial resolution. If the shooting location is bright and low-sensitivity shooting is sufficient, pixel thinning is performed when high spatial resolution is required. It is desirable to use pixel mixing and pixel thinning properly depending on the shooting conditions. FIG. 6 shows a case where a reading operation is performed by mixing three vertical pixels.

  Referring to FIG. 6, in the pixel portions corresponding to the first row, the third row, and the fifth row, the pixel reset operation is continued five times during the vertical scanning period T1 to T5. It is done. The reading operation is performed during the vertical scanning period T11 in which the exposure time between the vertical scanning periods T6 and T10 has elapsed. The reason for performing the pixel reset operation a plurality of times is to sufficiently discharge the charge accumulated in the pixel. Similarly, for the pixel portions corresponding to the pixel rows of the fourth row, the sixth row, and the eighth row, the pixel reset operation is continuously performed five times during the vertical scanning period T2 to T6. It is. The readout operation is performed during the vertical scanning period T12 in which the exposure time between the vertical scanning periods T7 and T11 has elapsed.

  In a conventional solid-state imaging device, it is necessary to select a row for performing a pixel reset operation (pixel reset row) and a row for performing a read operation (readout row) for each vertical scanning period. Therefore, in the above case, it is necessary to select a total of six rows in the vertical scanning periods T1 to T5 and T11 only in the first row, the third row, and the fifth row. There was a lot of waste in terms of current.

  In the solid-state imaging device according to the present embodiment, as will be described later with reference to FIGS. 8 and 9, the vertical scanning unit 2 is provided with a latch circuit (master latch circuit, slave latch circuit). For this reason, the reset row is selected by setting the latch circuit at the start of the pixel reset operation (in FIG. 6, the start of row selection is indicated by enclosing “RS” in a bold frame). At the end of the pixel reset operation, the selection of the reset row is canceled by bringing the latch circuit into a reset state (in FIG. 6, the row selection cancellation is represented by “UL”). The same applies to the read operation “RD”.

  More precisely, as will be described later with reference to FIG. 12, row selection is started and canceled by a pipeline operation using a master latch circuit and a slave latch circuit. For example, the master latch circuit is set in the vertical scanning periods T0 and T10 for the pixel portions corresponding to the first, third and fifth pixel rows, and the vertical scanning periods T1 and T11 are set. The slave latch circuit enters the set state.

  FIG. 7 is a timing chart schematically showing a pixel reset operation and a read operation by the rolling electronic shutter method. The vertical axis in FIG. 7 indicates the row number of the pixel array, and the horizontal axis indicates time. The maximum line number is Nmax, and the minimum is 1. FIG. 7 shows a case where neither pixel mixing nor pixel thinning is performed.

  Referring to FIG. 7, in a certain vertical scanning period Th, a pixel reset operation is performed on the pixel rows from Na to Nb, and a read operation is performed on the pixel rows of Nc. In this case, the address selection of the pixel row of the Nath row is performed to start the pixel reset operation, and the address selection of the pixel row of the (Nb-1) th row is performed to end the pixel reset operation. Further, the address selection of the pixel row of the Nc-th row is performed for the reading operation, and the address selection of the pixel row of the Nc-th row is performed for canceling the reading operation. Since the timing generator 4 in FIG. 1 sequentially outputs row selection addresses, these address selections are performed serially. Therefore, four row address selections are required for each vertical scanning period. When performing vertical three-pixel mixing, twelve row address selections are required for each vertical scanning period.

[Schematic configuration of vertical scanning unit]
FIG. 8 is a block diagram showing a configuration of the vertical scanning unit 2 of FIG. Referring to FIG. 8, vertical scanning unit 2 includes a control circuit 80 and a signal generation circuit 60.

  Control circuit 80 receives clock signal CLK, row selection addresses A12 to A0 (13 bits) and a control signal from timing generator 4 in FIG. The control signals include master latch set signals TX_SET, RST_SET, SEL_SET, FDSW_SET, master latch reset signals TX_RST, RST_RST, SEL_RST, FDSW_RST, slave latch set signals TX_TR_SET, RST_TR_SET, SELSW_TR_ST, FDSW_TR, FDSW_TR , FDSW_TR_RST, and shaping signals TX_DRV, RST_DRV, SEL_DRV, and FDSW_DRV.

  The control circuit 80 predecodes the 13-bit row selection addresses A12 to A0, and generates AG <3: 0> to AB <3: 0> and AA <1: 0> as predecoded address signals. . For example, AG <3: 0> is obtained by converting the upper 2 bits A12 and A11 of the row selection address into four 1-bit signals AG <3>, AG <2>, AG <1>, and AG <0>. is there. Therefore, one of the 1-bit signals AG <3>, AG <2>, AG <1>, AG <0> is “1” and the rest is “0” according to the values of A12 and A11. It becomes. Similarly for the other signals, AF <3: 0> to AB <3: 0> set the row selection address by 2 bits (that is, “A10, A9”, “A8, A7”, “A6, A5”). , “A4, A3”, “A2, A1”) are predecoded. Address signals AA <1: 0> (AA <1>, AA <0>) are obtained by predecoding the least significant bit A1 of the row selection address. Address signals AG <3: 0> to AB <3: 0> after predecoding are shaped by a buffer circuit provided in control circuit 80 (in FIG. 8, “_B” is added to the end of the signal. Represented by In this specification, the address signal after predecoding is also referred to as a row selection signal.

  The upper 6 bits A12 to A7 of the row selection address are used for block selection every 128 rows. The address signal after predecoding corresponds to AG_B <3: 0> to AE_B <3: 0>.

  The middle 6 bits A6 to A1 of the row selection address are used for selection within the block every 128 rows. The address signal after predecoding corresponds to AD_B <3: 0> to AB_B <3: 0>.

  The predecoded address signal AA <1: 0> (corresponding to the row selection address A0) is used to select the two transfer transistors 12A and 12B in FIG. The TX1 and TX0 signal generation circuit provided in the control circuit 80 includes a master latch set signal TX_SET and a master latch reset signal TX_RST, and pre-decoded address signals AA <1> and AA <0>. The logical product of As a result, master latch set signals TX0_SET and TX1_SET and master latch reset signals TX1_RST and TX0_RST are generated as signals for TX1 and TX0. The slave latch set signal TX_TR_SET, the slave latch reset signal TX_TR_RST, and the shaping signal TX_DRV do not perform a logical product with the address signal AA <1: 0>, and output the same signal waveforms as they are as signals for TX1 and TX0. These control signals are shaped by a buffer circuit provided in the control circuit 80 (represented by adding “_B” to the end of the signal in FIG. 8).

  Other control signals, that is, master latch set signals RST_SET, SEL_SET, FDSW_SET, master latch reset signals RST_RST, SEL_RST, FDSW_RST, slave latch set signals RST_TR_SET, SEL_TR_SET, FDSW_TR_SET, slave latch reset signals RST_TR_RST_TR_ST, RST_TR_RST RST_DRV, SEL_DRV, and FDSW_DRV are also shaped by a buffer circuit provided in the control circuit 80 (represented by adding “_B” to the end of the signal in FIG. 8).

  Further, the control circuit 80 converts voltages for some signals and supplies them to the decoding units 61 to 65. Specifically, the shaping signal TX_DRV for TX1 and TX0 converts the “H” level from the power supply voltage VDD to the power supply voltage VTXH, and the “L” level from the ground voltage GND to the negative voltage VTXL lower than the ground voltage GND. To do. The shaping signals RST_DRV, SEL_DRV, and FDSW_DRV convert the “H” level from the power supply voltage VDD to a power supply voltage higher than the power supply voltage VDD.

  The signal generation circuit 60 includes a TX1 decoding unit 61, a TX0 decoding unit 62, an RST decoding unit 63, a SEL decoding unit 64, an FDSW decoding unit 65, and a block selection AND gate 36. Each of these elements is provided corresponding to each row of the plurality of pixel portions 10 constituting the pixel array 1 of FIG. Each of the decoding units 61 to 65 functions as a drive circuit that supplies a pixel drive signal to the horizontal signal line in the corresponding row.

  The block selection AND gate 36 inputs one signal from each of the pre-decoded addresses AG_B <3: 0> to AE_B <3: 0> used for block selection, and selects the logical product of the input signals as a block. Generated as signal BS. When all are at the “H” level, the block selection signal BS is at the “H” level which means the selection level.

  The TX1 decode unit 61 includes a block selection signal BS, predecoded address signals AD_B <3: 0>, AC_B <3: 0>, AB_B <3: 0>, a master latch set signal TX1_SET_B, and a master latch reset signal TX1_RST_B. The slave latch set signal TX_TR_SET_B, the slave latch reset signal TX_TR_RST_B, and the shaping signal TX_DRV_B are received. Based on these signals, the TX1 decoding unit 61 generates a transfer signal TX1 to be output to the horizontal signal line LT1 of the corresponding row. Details of the TX1 decoding unit 61 will be described later with reference to FIG.

  The TX0 decoding unit 62 includes a block selection signal BS, pre-decoded address signals AD_B <3: 0>, AC_B <3: 0>, AB_B <3: 0>, a master latch set signal TX0_SET_B, a master latch reset signal TX0_RST_B. The slave latch set signal TX_TR_SET_B, the slave latch reset signal TX_TR_RST_B, and the shaping signal TX_DRV_B are received. Based on these signals, the TX0 decoding unit 62 generates a transfer signal TX0 to be output to the horizontal signal line LT0 of the corresponding row.

  The RST decoding unit 63 includes a block selection signal BS, pre-decoded address signals AD_B <3: 0>, AC_B <3: 0>, AB_B <3: 0>, a master latch set signal RST_SET_B, a master latch reset signal RST_RST_B. The slave latch set signal RST_TR_SET_B, the slave latch reset signal RST_TR_RST_B, and the shaping signal RST_DRV_B are received. Based on these signals, the RST decoding unit 63 generates a reset signal RST to be output to the horizontal signal line LR of the corresponding row.

  The SEL decoding unit 64 includes a block selection signal BS, pre-decoded address signals AD_B <3: 0>, AC_B <3: 0>, AB_B <3: 0>, a master latch set signal SEL_SET_B, and a master latch reset signal SEL_RST_B. The slave latch set signal SEL_TR_SET_B, the slave latch reset signal SEL_TR_RST_B, and the shaping signal SEL_DRV_B are received. Based on these signals, the SEL decoding unit 64 generates a selection signal SEL to be output to the horizontal signal line LS of the corresponding row.

  The FDSW decoding unit 65 includes a block selection signal BS, pre-decoded address signals AD_B <3: 0>, AC_B <3: 0>, AB_B <3: 0>, a master latch set signal FDSW_SET_B, a master latch reset signal FDSW_RST_B. The slave latch set signal FDSW_TR_SET_B, the slave latch reset signal FDSW_TR_RST_B, and the shaping signal FDSW_DRV_B are received. Based on these signals, the FDSW decoding unit 65 generates an FD connection signal FDSW to be output to the horizontal signal line LF of the corresponding row.

[Detailed Configuration of TX1 Decoding Unit]
FIG. 9 is a circuit diagram showing a configuration of the TX1 decoding unit 61. The other decoding units 62 to 65 have the same configuration.

  The TX1 decoding unit 61 includes a row selection decoding circuit 71, a voltage level shift circuit 52, a shaping circuit 53, and an output buffer. Row selection decode circuit 71 includes a master latch circuit 61A and a slave latch circuit 61B.

  The master latch circuit 61A includes AND circuits AND1 to AND3, NMOS (Negative-channel Metal Oxide Semiconductor) transistors Q0 to Q3, and inverters INV1 to INV4.

  The AND circuit AND1 outputs a logical product signal of one signal of the predecoded address signal AB_B <3: 0> and the master latch set signal TX1_SET_B. The AND circuit AND2 outputs a logical product signal of the block selection signal BS, one signal of the predecoded address signal AC_B <3: 0>, and one signal of the predecoded address AD_B <3: 0>. . The AND circuit AND3 outputs a logical product signal of one signal of the predecoded address signal AB_B <3: 0> and the master latch reset signal TX1_RST_B. Which one of the four address signals is ANDed by each of the AND circuits AND1, AND2 and AND3 depends on the row address.

  NMOS transistors Q0 and Q1 are connected in series between node N1 and ground node GND, and their gates receive the output signals of AND circuits AND1 and AND2, respectively. NMOS transistors Q2 and Q3 are connected in series between node N2 and ground node GND, and their gates receive output signals of AND circuits AND3 and AND2, respectively.

  Inverter INV2 is connected between nodes N1 and N2, and outputs a signal obtained by inverting the logic level of the signal appearing at node N1 to node N2. Inverter INV1 is connected between nodes N2 and N1, and outputs a signal obtained by inverting the logic level of a signal appearing at node N2 to node N1. Each of inverters INV1 and INV2 is driven by power supply voltage VDD and ground voltage GND. The ground voltage and the ground node are represented by the same reference symbol GND.

  NMOS transistors Q0 to Q3 and inverters INV0 and INV1 constitute a latch circuit that can be set to a set state and a reset state. When the output signals of the AND circuits AND1 and AND2 are both set to “H” level, the NMOS transistors Q0 and Q1 are turned on, and the node N1 is set to “L” level (ground voltage GND). As a result, the master latch circuit 61A is set, and the node N2 becomes the “H” level (power supply voltage VDD).

  If at least one of the NMOS transistors Q0 and Q1 is non-conductive and the output signals of the AND circuits AND2 and AND3 are both set to "H" level, the NMOS transistors Q2 and Q3 are conductive and the node N1 becomes It is set to “H” level. As a result, master latch circuit 61A is reset, and node N2 attains the “L” level (ground voltage GND).

  The input nodes of inverters INV3 and INV4 are connected to nodes N1 and N2, respectively. Inverters INV3 and INV4 drive the gates of NMOS transistors Q5 and Q7 provided in slave latch circuit 61B, respectively. If an output buffer is provided in place of inverters INV3 and INV4, node N1 is connected to the gate of NMOS transistor Q7 via the output buffer, and node N2 is connected to the gate of NMOS transistor Q5 via the output buffer. Connected.

  Slave latch circuit 61B includes NMOS transistors Q4-Q7 and inverters INV5, INV6.

  Inverter INV6 is connected between nodes N3 and N4, and outputs a signal obtained by inverting the logic level of the signal appearing at node N3 to node N4. Inverter INV5 is connected between nodes N4 and N3, and outputs a signal obtained by inverting the logic level of the signal appearing at node N4 to node N3. Each of inverters INV5 and INV6 is driven by power supply voltage VTXH and ground voltage GND. Therefore, slave latch circuit 61B also serves as a voltage level shift circuit that converts the “H” level of the input signal from power supply voltage VDD to power supply voltage VTXH.

  NMOS transistors Q4 and Q5 are connected in series between node N3 and ground node GND. NMOS transistors Q6 and Q7 are connected in series between node N4 and ground node GND. The gates of the NMOS transistors Q4 and Q6 receive the slave latch set signal TX_TR_SET_B and the slave latch reset signal TX_TR_RST_B output from the control circuit 80, respectively. The gates of NMOS transistors Q5 and Q7 receive the output signals of inverters INV3 and INV4, respectively.

  When the master latch circuit 61A is in the set state (that is, the voltage of the node N1 is “L” level) and the slave latch set signal TX_TR_SET_B is set to “H” level, the NMOS transistors Q4 and Q5 are turned on and the node N3 Becomes “H” level (power supply voltage VTXH). As a result, the slave latch circuit 61B is set, and the node N4 becomes the “H” level (power supply voltage VTXH).

  When at least one of the NMOS transistors Q4 and Q5 is non-conductive, the master latch circuit 61A is in a reset state (that is, the voltage at the node N2 is “L” level), and the slave latch reset signal TX_TR_RST_B is “H”. ", The NMOS transistors Q6 and Q7 are turned on, and the node N4 becomes" L "level (ground voltage GND). As a result, the slave latch circuit 61B is reset, and the voltage at the node N4 becomes L level (ground voltage GND).

  The slave latch set signal TX_TR_SET_B and the slave latch reset signal TX_TR_RST_B are data transfer enable signals from the master to the slave. When the signal is “H” level, the data of the master latch circuit 61A is transferred to the slave latch circuit 61B.

  The voltage level shift circuit 52 converts the “L” level of the node N4 from the ground voltage GND to a negative voltage VTXL lower than the ground voltage GND. The reason why the voltage level shift circuit 52 converts the voltage to the negative voltage VTXL lower than the ground voltage GND is to prevent the transfer transistor between the photodiode and the floating diffusion FD from leaking when the transfer signal TX is OFF. The same applies to the TX0 decoding unit 62. Since each of the reset signal RST, the selection signal SEL, and the FD connection signal FDSW does not need to be a negative voltage, the voltage level shift circuit 52 is included in the RST decoding unit 63, the SEL decoding unit 64, and the FDSW decoding unit 65. Is not provided.

  The forming circuit 53 includes an AND circuit AND4. The AND circuit AND4 is driven by the power supply voltage VTXH and the negative voltage VTXL. The AND circuit AND4 generates a logical product signal of the output signal of the voltage level shift circuit 52 (a signal appearing at the node N4) and the shaping signal TX_DRV_B. When the node N4 is at “H” level, the transfer signal TX1 that is an output signal can be controlled depending on whether the shaping signal TX_DRV_B is at “H” level or “L” level.

  The output buffer 54 includes a buffer BUF1. Buffer BUF1 is driven by power supply voltage VTXH and negative voltage VTXL. The output signal of the AND circuit AND4 is augmented by the buffer BUF1 to become the transfer signal TX1. Transfer signal TX1 is applied to corresponding horizontal signal line LT1.

  In the TX1 decoding unit 61 shown in FIG. 9, the driving voltage of each part is as follows. Master latch circuit 61A is driven by power supply voltage VDD and ground voltage GND. Slave latch circuit 61B is driven by power supply voltage VTXH and ground voltage GND. Voltage level shift circuit 52, shaping circuit 53, and output buffer 54 (reference numeral 61C) are driven by power supply voltage VTXH and negative voltage VTXL.

[effect]
FIG. 10 is a timing chart schematically showing the operation of the vertical scanning unit according to the comparative example. FIG. 10 shows an operation when it is assumed that the slave latch circuit 61B shown in FIG. 9 is not provided and is operated by one latch circuit (in other words, in FIG. The operation when the latch set signal TX_TR_SET_B and the slave latch reset signal TX_TR_RST_B are always at “H” level is shown).

  As described with reference to FIG. 7, when a moving image is shot by the rolling electronic shutter method, writing to the latch is performed prior to driving pulse output (from time t2 to time t3) for each vertical scanning period (1H). It is necessary to perform four times (from time t1 to time t2). In the case of mixing three pixels, the number of times of writing to the latch is twelve.

  By the way, in general, since an image sensor has a large imaging pixel, an address and a control signal in the vertical scanning unit are long-distance wirings of several mm or more. For this reason, skew between signals tends to lead to selection errors of row addresses. In particular, the size of an image sensor for a single-lens reflex camera with high image quality is a full size (36 mm × 24 mm) or an APS-C size (23.6 mm × 15.8 mm).

  In order to prevent a row selection error due to skew, three clock cycles are required for one row selection, as will be described later with reference to FIG. In the case of a mixture of three pixels, 36 clock cycles are required per vertical scanning period. If writing to the latch takes too much time, it becomes difficult to realize a high frame rate (60 fps) as in the FULL-HD standard.

  FIG. 11 is a timing chart showing a row selection operation by the vertical scanning unit of the comparative example. When a row is selected, an AND operation between the address signal and the set signal is performed. In order to prevent a row selection error due to skew, for example, as shown in FIG. 11, the cycle of the address signal needs to be 3 cycles (3 × Tc) of the clock signal.

FIG. 12 is a timing chart schematically showing the operation of the vertical scanning unit according to this embodiment.
In this embodiment, since the row selection decode circuit 71 includes two latch circuits as described in FIG. 9, writing to the master latch circuit 61A and writing to the slave latch circuit 61B can be realized by pipeline operation. . Therefore, it is possible to hide the time for writing to the master latch circuit 61A. Hereinafter, a case where three-pixel mixing is performed will be specifically described with reference to FIG.

  In the vertical scanning period immediately before the current vertical scanning period from time t3 to time t6, writing to the master latch circuit 61A is performed 12 times from time t1 to time t2. Accordingly, in the current vertical scanning period, only data transfer from the master latch circuit 61A to the slave latch circuit 61B needs to be performed between time t3 and time t4. Since a total of 12 row selections have been completed, the data transfer from the master to the slave takes only two clock cycles.

  In the current vertical scanning period, writing to the master latch circuit 61A for the next vertical scanning period (from time t6 to time t8) is also performed (time t4 to time t5). The written data is transferred to the slave latch circuit 61B between time t6 and time t7 in the next vertical scanning period.

  Thus, in the case of the present embodiment, the time other than the output of the drive pulse in each vertical scanning period is 2 clock cycles of data transfer from the master to the slave, and is reduced from the 36 clock cycles of FIG. can do. For this reason, a high frame rate (60 fps) like the FULL-HD standard can be easily realized.

<Embodiment 2>
In the image sensor according to the second embodiment, the writing time to the latch circuit is shortened by using a method different from the method of providing the master / slave two-stage latch circuit as in the first embodiment. This will be specifically described below.

[Schematic configuration of vertical scanning unit]
FIG. 13 is a block diagram showing the configuration of the vertical scanning unit 2A used in the image sensor according to the second embodiment of the present invention. Referring to FIG. 13, vertical scanning unit 2 </ b> A includes a control circuit 20 and a signal generation circuit 30.

  The control circuit 20 receives a clock signal CLK, row selection addresses A12 to A0 (13 bits) and a control signal from the timing generator 4 of FIG. The control signals include latch set signals TX_SET, RST_SET, SEL_SET, FDSW_SET, latch reset signals TX_RST, RST_RST, SEL_RST, FDSW_RST, and shaping signals TX_DRV, RST_DRV, SEL_DRV, FDSW_DRV. Unlike the case of FIG. 8 described in the first embodiment, the control signals received from the timing generator 4 include slave latch set signals TX_TR_SET, RST_TR_SET, SEL_TR_SET, FDSW_TR_SET, slave latch reset signals TX_TR_RST, RST_TR_RST, SEL_TR_RST, FDSW_TR_RST. Not.

  The control circuit 20 predecodes the 13-bit row selection addresses A12 to A0, and generates AG <3: 0> to AB <3: 0> and AA <1: 0> as predecoded address signals. . Address signal AA <1: 0> (corresponding to row selection address A0) is used to select two transfer transistors 12A and 12B in FIG. Each of the other address signals AG <3: 0> to AB <3: 0> has a pulse width changed so that the clock signal becomes a valid signal only during the “H” level period. In other words, each of the address signals AG <3: 0> to AB <3: 0> is modified so as to be synchronized with the clock signal and have a pulse width equal to or less than a half cycle of the clock signal. Hereinafter, this pulse deformation operation is referred to as “clocking” (represented by adding “C” to the end of the signal in FIG. 13). Further, the address signals AG <3: 0> to AB <3: 0> are shaped by a buffer circuit provided in the control circuit 20 (in FIG. 13, by adding “B” to the end of the signal) Represented).

  Control circuit 20 further calculates the logical product of each of latch set signal TX_SET and latch reset signal TX_RST and each of predecoded address signals AA <1> and AA <0>. As a result, latch set signals TX0_SET, TX1_SET and latch reset signals TX1_RST, TX0_RST are generated as signals for TX1 and TX0. The shaping signal TX_DRV is not logically ANDed with the address signal AA <1: 0>, and the same signal waveform is output as it is as a signal for TX1 and TX0.

  The control circuit 20 performs clocking and shaping by the buffer circuit for the latch set signals TX1_SET, TX0_SET, RST_SET, SEL_SET, FDSW_SET and the latch reset signals TX1_RST, TX0_RST, RST_RST, SEL_RST, FDSW_RST (in FIG. “_CB” is added to the end).

  The control circuit 20 shapes the shaping signals TX_DRV, RST_DRV, SEL_DRV, and FDSW_DRV by the buffer circuit but does not clock them (in FIG. 13, “_B” is added to the end of the signal).

  Further, the control circuit 80 converts voltages for some signals and supplies them to the decoding units 31 to 35. Specifically, the shaping signal TX_DRV for TX1 and TX0 converts the “H” level from the power supply voltage VDD to the power supply voltage VTXH, and the “L” level from the ground voltage GND to the negative voltage VTXL lower than the ground voltage GND. To do. The shaping signals RST_DRV, SEL_DRV, and FDSW_DRV convert the “H” level from the power supply voltage VDD to a power supply voltage higher than the power supply voltage VDD. A more detailed operation of the control circuit 20 will be described later with reference to FIGS.

  The signal generation circuit 30 includes a TX1 decoding unit 31, a TX0 decoding unit 32, an RST decoding unit 33, a SEL decoding unit 34, an FDSW decoding unit 35, and a block selection AND gate 36. Since the operation of clock selection gate 36 is the same as that of FIG. 8, description thereof will not be repeated.

  The TX1 decoding unit 31 includes a block selection signal BS, predecoded address signals AD_CB <3: 0>, AC_CB <3: 0>, AB_CB <3: 0>, a latch set signal TX1_SET_CB, a latch reset signal TX1_RST_CB, and A molding signal TX_DRV_B is received. Based on these signals, the TX1 decoding unit 31 generates the transfer signal TX1 to be output to the horizontal signal line LT1 of the corresponding row. Details of the TX1 decoding unit 31 will be described later with reference to FIG.

  The TX0 decoding unit 32 includes a block selection signal BS, predecoded address signals AD_CB <3: 0>, AC_CB <3: 0>, AB_CB <3: 0>, a latch set signal TX0_SET_CB, a latch reset signal TX0_RST_CB, and A molding signal TX_DRV_B is received. Based on these signals, the TX0 decoding unit 32 generates a transfer signal TX0 to be output to the horizontal signal line LT0 of the corresponding row.

  The RST decoding unit 33 includes a block selection signal BS, pre-decoded address signals AD_CB <3: 0>, AC_CB <3: 0>, AB_CB <3: 0>, a latch set signal RST_SET_CB, a latch reset signal RST_RST_CB, and A molding signal RST_DRV_B is received. Based on these signals, the RST decoding unit 33 generates a reset signal RST to be output to the horizontal signal line LR of the corresponding row.

  The SEL decoding unit 34 includes a block selection signal BS, pre-decoded address signals AD_CB <3: 0>, AC_CB <3: 0>, AB_CB <3: 0>, a latch set signal SEL_SET_CB, a latch reset signal SEL_RST_CB, and A molding signal SEL_DRV_B is received. Based on these signals, the SEL decoding unit 34 generates a selection signal SEL to be output to the horizontal signal line LS of the corresponding row.

  The FDSW decoding unit 35 includes a block selection signal BS, pre-decoded address signals AD_CB <3: 0>, AC_CB <3: 0>, AB_CB <3: 0>, a latch set signal FDSW_SET_CB, a latch reset signal FDSW_RST_CB, and A molding signal FDSW_DRV_B is received. Based on these signals, the FDSW decoding unit 35 generates an FD connection signal FDSW to be output to the horizontal signal line LF of the corresponding row.

[Detailed Configuration of TX1 Decoding Unit]
FIG. 14 is a circuit diagram showing a configuration of the TX1 decoding unit 31. The other decoding units 32 to 35 have the same configuration.

  The TX1 decoding unit 31 includes a row selection decoding circuit 51, a voltage level shift circuit 52, a shaping circuit 53, and an output buffer.

  Row selection decode circuit 51 includes AND circuits AND1-AND3, NMOS transistors Q0-Q3, and inverters INV1, INV2.

  The AND circuit AND1 outputs a logical product signal of one signal of the predecoded address signal AB_CB <3: 0> and the latch set signal TX1_SET_CB. The AND circuit AND2 outputs a logical product signal of the block selection signal BS, one signal of the predecoded address signal AC_CB <3: 0>, and one signal of the predecoded address AD_CB <3: 0>. . The AND circuit AND3 outputs a logical product signal of one signal of the predecoded address signal AB_CB <3: 0> and the latch reset signal TX1_RST_CB. Which one of the four address signals is ANDed by each of the AND circuits AND1, AND2 and AND3 depends on the row address. The AND circuits AND1 to AND3 are driven by the power supply voltage VDD and the ground voltage GND.

  NMOS transistors Q0 and Q1 are connected in series between node N1 and ground node GND, and their gates receive the output signals of AND circuits AND1 and AND2, respectively. NMOS transistors Q2 and Q3 are connected in series between node N2 and ground node GND, and their gates receive output signals of AND circuits AND3 and AND2, respectively.

  Inverter INV2 is connected between nodes N1 and N2, and outputs a signal obtained by inverting the logic level of the signal appearing at node N1 to node N2. Inverter INV1 is connected between nodes N2 and N1, and outputs a signal obtained by inverting the logic level of a signal appearing at node N2 to node N1. Each of inverters INV1 and INV2 is driven by power supply voltage VTXH and ground voltage GND.

  NMOS transistors Q0 to Q3 and inverters INV0 and INV1 form a latch circuit 31B that can be set to a set state and a reset state. When the output signals of the AND circuits AND1 and AND2 are both set to the “H” level, the NMOS transistors Q0 and Q1 are turned on and the node N1 is set to the “L” level (ground voltage GND). As a result, the latch circuit 31B is set, and the node N2 becomes the “H” level (power supply voltage VTXH).

  If at least one of the NMOS transistors Q0 and Q1 is non-conductive and the output signals of the AND circuits AND2 and AND3 are both set to "H" level, the NMOS transistors Q2 and Q3 are conductive and the node N1 becomes Becomes “H” level. As a result, the latch circuit 31B is reset, and the node N2 is set to the “L” level (ground voltage GND). As described above, the latch circuit 31B also serves as a voltage level shift circuit that converts the “H” level of the signal from the power supply voltage VDD to the power supply voltage VTXH.

  Voltage level shift circuit 52 converts the “L” level of node N2 from ground voltage GND to negative voltage VTXL lower than ground voltage GND. The same applies to the TX0 decoding unit 32. Since each of the reset signal RST, the selection signal SEL, and the FD connection signal FDSW does not need to be a negative voltage, the voltage level shift circuit 52 is included in the RST decoding unit 33, the SEL decoding unit 34, and the FDSW decoding unit 35. Is not provided.

  The forming circuit 53 includes an AND circuit AND4. The AND circuit AND4 is driven by the power supply voltage VTXH and the negative voltage VTXL. The AND circuit AND4 generates a logical product signal of the output signal of the voltage level shift circuit 52 (a signal appearing at the node N2) and the shaping signal TX_DRV_B. When the node N2 is at the “H” level, the transfer signal TX1 that is an output signal can be controlled depending on whether the shaping signal TX_DRV_B is at the “H” level or the “L” level.

  The output buffer 54 includes a buffer BUF1. Buffer BUF1 is driven by power supply voltage VTXH and negative voltage VTXL. The output signal of the AND circuit AND4 is augmented by the buffer BUF1 to become the transfer signal TX1. Transfer signal TX1 is applied to corresponding horizontal signal line LT1.

  In the TX1 decoding unit 31 shown in FIG. 13, the driving voltage of each part is as follows. The AND circuits AND1 to AND3 (reference numeral 31A) are driven by the power supply voltage VDD and the ground voltage GND. Latch circuit 31B is driven by power supply voltage VTXH and ground voltage GND. Voltage level shift circuit 52, shaping circuit 53, and output buffer 54 (reference numeral 31C) are driven by power supply voltage VTXH and negative voltage VTXL.

[Detailed configuration of control circuit]
FIG. 15 is a circuit block diagram showing a part related to generation of the transfer signal TX in the control circuit 20. Hereinafter, only the part related to the TX signal in the control circuit 20 will be described, but the same applies to other signals (RST, SEL, FDSW).

  Referring to FIG. 15, control circuit 20 includes a predecoder 21, a voltage level shift circuit 22, a signal clocking circuit 23, a buffer 24, and a signal generation circuit 25 for TX1 and TX0. Each output signal of the control circuit 20 is supplied to the TX decoding units 31 and 32 via the buffer 24.

  The predecoder 21 predecodes the row selection addresses A12 to A0 to generate address signals AG <3: 0> to AB <3: 0>, AA <1: 0>. The predecoded address signal AA <1: 0> is two signals because one bit of the row selection address A0 is predecoded. Address signal AA <1: 0> is used to select two transfer transistors 12A and 12B. The other address signals AB <3: 0> to AG <3: 0> are each four signals because the row selection address is predecoded two bits at a time.

  The signal generation circuit 25 for TX1 and TX0 includes AND circuits 25A and 25B. The AND circuit 25A performs an AND operation between the latch set signal TX_SET and each of the addresses AA <1: 0> after predecoding. The AND circuit 25A outputs the operation result as the latch set signals TX1_SET and TX0_SET. Similarly, AND circuit 25B performs an AND operation on latch reset signal TX_RST and each of pre-decoded addresses AA <1: 0>. The AND circuit 25B outputs the operation result as latch reset signals TX1_RST and TX0_RST.

  The voltage level shift circuit 22 converts the “H” level of the shaping signal TX_DRV from the power supply voltage VDD to the power supply voltage VTXH, and the “L” level from the ground voltage GND to the negative voltage VTXL lower than the ground voltage GND.

  The signal clock circuit 23 is a circuit that outputs an input signal as a signal that is valid only during the High period of the clock signal CLK. The signal clock circuit 23 clocks the pre-decoded addresses AG <3: 0> to AB <3: 0>, the latch set signals TX1_SET, TX0_SET, and the latch reset signals TX1_RST, TX0_RST.

  FIG. 16 is a block diagram showing components of the signal clock circuit 23 of FIG. The signal clocking circuit 23 of FIG. 15 is provided with a circuit having the configuration of FIG. 16 for each input signal.

  Referring to FIG. 16, signal clocking circuit 23 includes a flip-flop (FF) 41, a latch circuit (LAT) 42, and an AND gate 43. The flip-flop 41 holds the logic level of the input signal IN at the positive edge of the clock signal CLK. The latch circuit 42 allows the output signal S1 of the flip-flop 41 to pass while the clock signal CLK is at “L” level. The latch circuit 42 holds the logic level of the signal S1 immediately before the clock signal CLK is switched to the “H” level while the clock signal CLK is at the “H” level. The AND gate 43 outputs a logical product of the output signal S2 of the latch circuit 42 and the clock signal CLK as the output signal OUT.

  FIG. 17 is a timing chart of each signal in the circuit of FIG. FIG. 17 shows, in order from the top, voltage waveforms of the clock signal CLK, the input signal IN, the output signal S1 of the flip-flop 41, the output signal S2 of the latch circuit, and the output signal OUT.

  Referring to FIG. 17, when there is no skew between clock signal CLK and input signal IN, a signal obtained by clocking input signal IN is obtained by obtaining a logical product of clock signal CLK and input signal IN. Can do. Actually, the rising and falling of the input signal IN are delayed from the timings t1 and t2 at which the clock signal CLK rises, respectively. Therefore, by performing a logical operation using the circuit shown in FIG. 16, it is possible to generate a signal having a pulse width of a half cycle of the clock between time t4 and time t5.

  FIG. 18 is a timing chart showing the operation of the vertical scanning unit 2A of FIG. 14 during reading. The read operation includes a first step for setting the latch circuit 31B in FIG. 14, a second step for shaping the transfer signal TX1, and a third step for resetting the latch circuit 31B. FIG. 18 shows operations of the first and second steps. However, for the sake of simplicity, the shaping signal TX_DRV is always at the “H” level.

  Referring to FIG. 18, pre-decoded address signals AB <3: 0> to AG <3: 0> and latch set signal TX1_SET are input to signal clock circuit 23 shown in FIG. Assume that the address signal and the latch set signal are switched in one clock cycle. Specifically, a signal corresponding to the n-th row of the pixel unit 10 configuring the pixel array is input from time t1 to time t2, and the (n + 1) -th pixel of the pixel unit 10 configuring the pixel array from time t2 to time t3. A signal corresponding to the row is input.

  At time t3, the signal clocking circuit 23 corresponding to the nth row of the pixel unit 10 constituting the pixel array is clocked with the clocked address signals AB_C <3: 0> to AG_C <3: 0>. The latch set signal TX1_SET_C <n> is output. At time t4, the signal clocking circuit 23 corresponding to the (n + 1) th row of the pixel unit 10 receives the clocked address signals AB_C <3: 0> to AG_C <3: 0> and the clocked latch set signal TX1_SET_C. <N + 1> is output.

  In response to the output from the control circuit 20, in the latch circuit 31B corresponding to the nth row of the pixel portion 10, the voltage at the node N2 is switched to the “H” level at time t3. In the latch circuit 31B corresponding to the (n + 1) th row of the pixel unit 10, the voltage at the node N2 is switched to the “H” level at time t4. As a result, the transfer signal TX1 <n> supplied to the nth horizontal signal line LT <n> at time t3 is switched to the “H” level, and at time t4, the (n + 1) th horizontal signal line LT <n + 1>. The transfer signal TX1 <n + 1> supplied to is switched to the “H” level.

[effect]
As described above, in the vertical scanning unit 2A, the address signals AB_C <3: 0> to AG_C <3: 0>, the latch set signal, and the latch reset signal are clocked. In these clocked signals, there is always a period of “L” level before and after “H” level. For this reason, a row selection error due to a signal skew (a mistake of performing a set operation for a latch circuit in an unselected row) does not occur.

  Further, by setting the address signals AB_C <3: 0> to AG_C <3: 0>, the latch set signal, and the latch reset signal as clocks, the set operation and reset operation of the latch circuit can be performed in one clock cycle. . Therefore, referring to the timing chart shown in FIG. 10, the time required for row selection (writing time to the latch) for each vertical scanning period is 12 clock cycles even in the case of mixing three pixels. When clocking is not performed, 36 clock cycles are required, so that the write time to the latch can be reduced to about 1/3.

  Although there is a method for preventing a row selection error by adjusting the timing of each address signal and latch set signal by using an RC delay element, the method according to the second embodiment (signal clocking) is more advantageous in the following points. is there.

  First, if the method of Embodiment 2 is taken, there will be no area increase by providing RC delay element. Considering the skew in the long distance wiring in the image sensor, the RC delay element requires a considerably large area.

  Further, in the second embodiment, since signal processing is synchronized with the clock, it is easy to adjust timing. The RC delay element requires time for timing adjustment.

<Embodiment 3>
The method of providing the master latch circuit and the slave latch circuit described in Embodiment 1 may be combined with the signal clocking described in Embodiment 2. This will be specifically described below.

  FIG. 19 is a block diagram showing the configuration of the vertical scanning unit 2B used in the image sensor according to Embodiment 3 of the present invention. Referring to FIG. 19, vertical scanning unit 2 </ b> B includes a control circuit 81 and a signal generation circuit 60.

  Since signal generation circuit 60 in FIG. 19 is the same as signal generation circuit 60 in FIG. 8, description thereof will not be repeated. The control circuit 81 is obtained by adding the signal clocking circuit 23 described with reference to FIGS. 15 and 16 to the control circuit 80 of FIG.

  FIG. 20 is a circuit block diagram showing a part related to generation of the transfer signal TX in the control circuit 81. Hereinafter, only the part related to the TX signal in the control circuit 81 will be described, but the same applies to other signals (RST, SEL, FDSW).

  Referring to FIG. 20, control circuit 81 includes a predecoder 21, a voltage level shift circuit 22, a signal clocking circuit 23, a buffer 24, and a signal generation circuit 72 for TX1 and TX0. Each output signal of the control circuit 81 is supplied to the TX decoding units 61 and 62 via the buffer 24.

  The predecoder 21 predecodes the row selection addresses A12 to A0 to generate address signals AG <3: 0> to AB <3: 0>, AA <1: 0>. The predecoded address signal AA <1: 0> is two signals because one bit of the row selection address A0 is predecoded. Address signal AA <1: 0> is used to select two transfer transistors 12A and 12B. The other address signals AB <3: 0> to AG <3: 0> are each four signals because the row selection address is predecoded two bits at a time.

  The signal generation circuit 72 for TX1 and TX0 includes AND circuits 72A and 72B. The AND circuit 72A performs an AND operation between the master latch set signal TX_SET and each of the addresses AA <1: 0> after predecoding. The AND circuit 72A outputs the operation result as master latch set signals TX1_SET, TX0_SET. Similarly, the AND circuit 72B performs an AND operation on the master latch reset signal TX_RST and each of the pre-decoded addresses AA <1: 0>, and outputs the operation results as master latch reset signals TX1_RST and TX0_RST. .

  The voltage level shift circuit 22 converts the “H” level of the shaping signal TX_DRV from the power supply voltage VDD to the power supply voltage VTXH, and the “L” level from the ground voltage GND to the negative voltage VTXL lower than the ground voltage GND.

  The signal clock circuit 23 is a circuit that outputs an input signal as a signal that is valid only during the High period of the clock signal CLK. The signal clock circuit 23 clocks pre-decoded addresses AG <3: 0> to AB <3: 0>, master latch set signals TX0_SET and TX1_SET, and master latch reset signals TX1_RST and TX0_RST.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 pixel array, 2, 2A, 2B vertical scanning unit, 3 horizontal scanning unit, 4 timing generator, 10 pixel unit, 11A, 11B photodiode, 12A, 12B transfer transistor, 13 reset transistor, 14 amplification transistor, 15 selection transistor, 16 connected transistors, 20, 80, 81 control circuit, 23 signal clock generation circuit, 31-35, 61-65 decoding unit (drive circuit), 31B latch circuit, 61A master latch circuit, 61B slave latch circuit, A12-A0 row selection Address, AA to AG address signal, BS block selection signal, FD floating diffusion, LF, LR, LT1, LT0, LS horizontal signal line, LV vertical signal line, N1 to N4 nodes, TX_SET (master) latch set Signal, TX_RST (master) latch reset signal, TX_TR_SET slave latch set signal, TX_TR_RST slave latch reset signal, TX_DRV molding signal, FDSW connection signal, RST reset signal, SEL selection signal, TX1, TX0 transfer signal.

Claims (11)

A plurality of pixel portions arranged in a matrix and each including a photoelectric conversion element;
A plurality of horizontal signal lines provided corresponding to the rows of the plurality of pixel portions, each connected to each pixel portion included in the corresponding row;
A plurality of drives provided corresponding to the plurality of horizontal signal lines, each of which outputs a drive signal for driving each pixel unit connected to the corresponding horizontal signal line via the corresponding horizontal signal line Circuit,
A control circuit that outputs to each of the plurality of drive circuits a row selection signal indicating whether or not a corresponding row of the plurality of pixel portions is a selected row;
Each of the plurality of drive circuits includes:
A first latch circuit that is set based on the row selection signal;
A second latch circuit that is set based on the state of the first latch circuit,
The solid-state imaging device, wherein the driving signal is output based on a state of the second latch circuit. The control circuit further outputs a first set signal and a second set signal as signals common to the plurality of drive circuits,
The first latch circuit is set when the row selection signal is active and the first set signal is active,
2. The solid-state imaging device according to claim 1, wherein the second latch circuit is set when the first latch circuit is in a set state and the second set signal is in an active state. The solid-state imaging device has, as an operation mode, a pixel mixture mode in which the plurality of pixel units are simultaneously driven in a plurality of rows,
In the pixel mixture mode, the control circuit sequentially activates a plurality of the row selection signals to be output to a drive circuit for a plurality of selected rows to be driven,
The control circuit activates the second set signal after the plurality of first latch circuits corresponding to a plurality of selected rows are all set in the pixel mixture mode. The solid-state imaging device described.   The control circuit is included in the first selected row when each pixel unit included in the first selected row is driven and then each pixel unit included in the second selected row is driven. The solid-state imaging device according to claim 2, wherein the row selection signal output to the driving circuit for the second selected row is activated during driving of each pixel unit. The control circuit further outputs a first reset signal and a second reset signal as signals common to the plurality of drive circuits,
The first latch circuit is in a reset state when the row selection signal is in an active state and the first reset signal is in an active state,
The solid-state imaging device according to claim 2, wherein the second latch circuit is in a reset state when the first latch circuit is in a reset state and the second reset signal is in an active state. The first latch circuit includes:
A first node;
A second node;
A first inverter that outputs a signal obtained by inverting the logic level of the first node to the second node;
A second inverter that outputs a signal obtained by inverting the logic level of the second node to the first node;
A first switch connected between the first node and a reference node for applying a reference voltage, and is turned on when the row selection signal is in an active state and the first set signal is in an active state; ,
A second switch unit connected between the second node and the reference node, wherein the second switch unit is conductive when the row selection signal is in an active state and the first reset signal is in an active state;
The second latch circuit includes:
A third node;
A fourth node;
A third inverter that outputs a signal obtained by inverting the logic level of the third node to the fourth node;
A fourth inverter that outputs a signal obtained by inverting the logic level of the fourth node to the third node;
A third switch connected between the third node and the reference node and conducting when the voltage of the first node is equal to the reference voltage and the second set signal is in an active state; ,
A fourth switch connected between the fourth node and the reference node and conducting when the voltage of the second node is equal to the reference voltage and the second reset signal is in an active state; Including
The solid-state imaging device according to claim 5, wherein the drive signal is output based on a logic level of the third or fourth node.   The row selection signal, the first set signal, and the first reset signal are signals that are synchronized with a clock signal and have a pulse width of a half cycle of the clock signal. Solid-state imaging device. Each of the plurality of pixel portions further includes
A transfer electrode connected to a corresponding horizontal signal line and transferring charges generated in the photoelectric conversion element; and
A charge storage unit connected to the photoelectric conversion element via the transfer transistor and storing charges generated by the photoelectric conversion element;
4. The solid-state imaging device according to claim 3, further comprising: a coupling transistor that is provided between a charge storage unit of another pixel unit arranged in the column direction and is in a conductive state in the pixel mixed mode. A plurality of pixel portions arranged in a matrix and each including a photoelectric conversion element;
A plurality of horizontal signal lines provided corresponding to the rows of the plurality of pixel portions, each connected to each pixel portion included in the corresponding row;
A plurality of drives provided corresponding to the plurality of horizontal signal lines, each of which outputs a drive signal for driving each pixel unit connected to the corresponding horizontal signal line via the corresponding horizontal signal line Circuit,
A control circuit that outputs to each of the plurality of drive circuits a row selection signal indicating whether or not a corresponding row of the plurality of pixel portions is a selected row;
The control circuit further outputs a set signal common to the plurality of drive circuits,
Each of the row selection signal and the set signal is a signal that is synchronized with a clock signal and has a pulse width of a half cycle of the clock signal,
Each of the plurality of drive circuits includes a latch circuit that is in a set state when the row selection signal is in an active state and the set signal is in an active state,
The solid-state imaging device, wherein the drive signal is output based on a state of the latch circuit. The control circuit further outputs a reset signal that is a signal common to the plurality of drive circuits,
The reset signal is a signal that is synchronized with a clock signal and has a pulse width of a half cycle of the clock signal,
The solid-state imaging device according to claim 9, wherein the latch circuit is in a reset state when the row selection signal is in an active state and the reset signal is in an active state. The latch circuit is
A first node;
A second node;
A first inverter that outputs a signal obtained by inverting the logic level of the first node to the second node;
A second inverter that outputs a signal obtained by inverting the logic level of the second node to the first node;
A first switch connected between the first node and a reference node for applying a reference voltage, and is turned on when the row selection signal is active and the set signal is active;
A second switch unit connected between the second node and the reference node, the second switch unit being in a conductive state when the row selection signal is in an active state and the reset signal is in an active state;
The solid-state imaging device according to claim 10, wherein the drive signal is output based on a logic level of the first or second node.

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