JP2012238089A - Integrated circuit device, verification device and verification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily verify whether or not an integrated circuit device works according to specifications.SOLUTION: An integrated circuit device 10 includes: a master module 11; an interconnect 12 connected to the master module 11; and a slave module 13 set as the connection destination of the master module 11 by the interconnect 12. The integrated circuit device 10 further includes: a fixed value response circuit 14 for receiving a reading instruction signal to be transmitted from the interconnect 12 to the slave module 13. The fixed value response circuit 14 which has received the reading instruction signal from the interconnect 12 is configured to transmit a fixed value which is unique to the slave module 13 set as the connection destination of the master module 11 by the interconnect 12 to the interconnect 12. Thus, it is possible to verify whether or not the connection destination is set according to specifications on the basis of the fixed value.

Description

  The present invention relates to an integrated circuit device, a verification device and a verification method for verifying an integrated circuit device.

  With respect to an integrated circuit device such as a system LSI (Large Scale Integration), a technique for connecting a predetermined master module to a predetermined slave module via an interconnect (also called a bus switch, a bus matrix, etc.) is known. . In the interconnect, a slave module to be connected is determined based on an address signal or the like.

  Furthermore, a technique for providing a plurality of interconnects between a master module and a slave module and a technique for connecting a plurality of interconnects with a bus bridge are also known. There is also known a technique that enables transactions to be performed simultaneously on a plurality of different combinations of master modules and slave modules connected to an interconnect.

JP 2007-199859 A JP 2004-126646 A

  By the way, when the master module and the slave module are connected by the interconnect as described above, it may be verified whether the master module is connected to the slave module as specified by the interconnect. As a verification method, there is a method of visually verifying the circuit configuration and signal waveform of the interconnect. There is also a method of performing a logic simulation and verifying whether the slave module is connected to the specification based on a read value from a slave module connected to the master module in response to a predetermined read command.

  However, in the method of visual verification, proper verification may be difficult if the circuit configuration becomes relatively complicated, such as a plurality of interconnects provided between the master module and the slave module. In the method of verifying by logic simulation, an appropriate read value may be obtained from the slave module only after following a predetermined operation flow, and an appropriate read value may not be obtained from the slave module. In such a case, a visual verification operation is performed.

  As described above, in an integrated circuit device including a master module and a slave module and an interconnect, it is not always easy to verify whether or not the connection between the modules via the interconnect is in accordance with the specifications of the integrated circuit device. It was.

  According to one aspect of the present invention, a first module that issues a command by itself and a connection destination of the first module that is connected to the first module and that is designated based on the signal is connected to the first module. When the interconnect to be transferred, the second module specified as the connection destination of the first module by the interconnect, and the read command signal to the second module are transmitted from the interconnect, the read command signal is An integrated circuit device is provided that includes a fixed value response circuit that receives and transmits a fixed value specific to the second module to the interconnect.

  Further, according to one aspect of the present invention, a verification device and a verification method using such a hardware model of an integrated circuit device are provided.

  In the integrated circuit device or its hardware model, it is possible to easily verify whether or not the connection between the modules via the interconnect is in accordance with the specifications.

It is a figure which shows the structural example of an integrated circuit device. 1 is a diagram illustrating a configuration example of a system LSI according to a first embodiment. It is explanatory drawing of the principal part of the system LSI which concerns on 1st Embodiment. It is explanatory drawing of an example of a fixed value response circuit. It is a figure which shows an example of an address map. It is a figure which shows the structural example of a logic simulation apparatus. It is a figure which shows an example of the logic simulation apparatus which concerns on 1st Embodiment. It is a figure which shows an example of the logic simulation flow which concerns on 1st Embodiment. It is a figure which shows another example of a logic simulation apparatus. It is a figure which shows another example of a logic simulation flow. It is a figure explaining the example of application of a 1st bus protocol. It is a figure explaining the example of application of a 2nd bus protocol. It is explanatory drawing of the principal part of the system LSI which concerns on 2nd Embodiment. It is a figure which shows the structural example of the system LSI which concerns on 3rd Embodiment. It is explanatory drawing of the principal part of the system LSI which concerns on 3rd Embodiment. It is a figure which shows an example of the logic simulation apparatus which concerns on 3rd Embodiment. It is explanatory drawing of the master module at the time of the logic simulation which concerns on 3rd Embodiment. It is a figure which shows an example of the logic simulation flow which concerns on 3rd Embodiment. It is explanatory drawing of the principal part of the system LSI which concerns on 4th Embodiment. It is a figure which shows the structural example of the hardware of a logic simulation apparatus.

FIG. 1 is a diagram illustrating a configuration example of an integrated circuit device.
An integrated circuit device 10 shown in FIG. 1 includes a master module 11, an interconnect 12, a slave module 13, and a fixed value response circuit 14. The master module 11 is connected to the interconnect 12, and a slave module 13 and a fixed value response circuit 14 are connected to the interconnect 12. The interconnect 12 has a function of interconnecting, for example, the master module 11 and the slave module 13 serving as a connection destination (access destination).

  The master module 11 is a module typified by a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and a DMA (Direct Memory Access) controller, and is a module that issues instructions such as transactions to the bus.

  The slave module 13 is a module represented by a memory controller, an interrupt controller, and a timer. The slave module 13 receives a command such as a transaction from the master module through a bus and returns a response to the command.

The interconnect 12 is a module having a function of connecting the master module 11 and the slave module 13 to each other.
FIG. 1 illustrates a case where a master module 11 and a slave module 13 as a connection destination are connected to the interconnect 12 one by one. In addition, a plurality of master modules 11 may be connected to the interconnect 12, and a plurality of slave modules 13 may be connected. In this case, the interconnect 12 may have a function of mutually connecting a predetermined combination of the master module 11 and the slave module 13 based on a predetermined control signal. Further, the fixed value response circuit 14 can be provided corresponding to each of the plurality of slave modules 13 or corresponding to a part of the plurality of slave modules 13.

  The fixed value response circuit 14 receives a signal transmitted from the interconnect 12 to the slave module 13 to which the master module 11 is connected. In the integrated circuit device 10, the slave module 13 or the fixed value response circuit 14 receives such a signal to which the slave module 13 is connected, for example, using a selector (selection circuit). The fixed value response circuit 14 transmits a unique value (fixed value) set to the slave module 13 to the interconnect 12 when receiving a signal from the interconnect 12 to which the slave module 13 is connected (response) )

  According to the integrated circuit device 10 having such a configuration, it is possible to easily know whether or not the slave module 13 is appropriate as a connection destination of the master module 11. That is, the fixed value response circuit 14 of the integrated circuit device 10 receives a signal sent to the slave module 13 to which the master module 11 is connected by the interconnect 12 instead of the slave module 13. The fixed value response circuit 14 that has received the signal responds to the interconnect 12 with a fixed value unique to the slave module 13. The slave module 13 to which the master module 11 is connected by the interconnect 12 can be identified by the fixed value returned from the fixed value response circuit 14 without performing processing inside the slave module 13. . Thereby, it is possible to easily know whether or not the connection by the interconnect 12 between the master module 11 and the slave module 13 is appropriate, in other words, whether or not the connection is in accordance with the specifications of the integrated circuit device 10. .

  In the manufacture of such an integrated circuit device 10, when verification by logic simulation is performed, a hardware model described in a hardware description language having a circuit configuration as shown in FIG. 1 is used.

Hereinafter, the integrated circuit device and the verification thereof will be described in more detail using the system LSI and the verification thereof as an example.
First, the first embodiment will be described.

FIG. 2 is a diagram illustrating a configuration example of the system LSI according to the first embodiment, and FIG. 3 is an explanatory diagram of a main part of the system LSI according to the first embodiment.
A system LSI 10A illustrated in FIG. 2 includes a master module 100, a slave module 300, and an interconnect 200 that connects them. Here, as an example, a case where four master modules 100 (M0, M1, M2, M3) and four slave modules 300 (S0, S1, S2, S3) are connected by one interconnect 200 (IC) is illustrated. doing.

  In the master module 100, for example, the master modules M0 and M1 can be CPUs, the master module M2 can be a DMA controller, and the master module M3 can be a GPU. Further, the slave module 300 can use, for example, the slave module S0 as a memory controller, the slave module S1 as an interrupt controller, the slave module S2 as an internal memory, and the slave module S3 as a system control register.

  Each master module 100 has a bus interface (I / F) 110 (MB0, MB1, MB2, MB3) for exchanging signals with the interconnect 200. The master module 100 issues a control signal (for example, a read command signal such as a read transaction) including an address signal, a bus control signal, and the like. The signal issued by the master module 100 is transmitted to the interconnect 200 via the bus I / F 110.

  As shown in FIG. 2, the interconnect 200 includes bus I / Fs 210 and 240, a decoding unit 220 (D0, D1, D2, and D3), and an arbitration unit 230 (A0, A1, A2, and A3). .

  The bus I / F 210 is provided corresponding to each master module 100 (bus I / F 110). The interconnect 200 exchanges signals with each master module 100 via each bus I / F 210. The bus I / F 240 is provided corresponding to each slave module 300. The interconnect 200 exchanges signals with each slave module 300 via each bus I / F 240.

  The decoding unit 220 and the arbitrating unit 230 of the interconnect 200 are functional blocks provided corresponding to the master modules 100 and the slave modules 300, respectively.

  Each decoding unit 220 decodes a control signal including an address signal and the like transmitted from the corresponding master module 100. Each decoding unit 220 connects the access destination arbitration unit 230 with a bus according to the decoding result. That is, the decoding unit 220 performs a process of transferring a signal from the corresponding master module 100 to the access destination slave module 300 specified based on the signal.

  Each arbitration unit 230 arbitrates signals such as read transactions transferred from a plurality (four in this case) of decoding units 220. Each arbitration unit 230 transmits the transferred signal to the corresponding slave module 300 via the bus I / F 240 according to the arbitration result.

  Each slave module 300 has a bus I / F 310 (SB0, SB1, SB2, SB3, SB) for exchanging signals with the interconnect 200. Furthermore, each slave module 300 has a functional block (circuit block) 320 (SF0, SF1, SF2, SF3, SF) that is connected to the bus I / F 310 and implements the processing function of each slave module 300.

  Furthermore, as shown in FIGS. 2 and 3, each slave module 300 (S0 to S3, S) includes a fixed value response circuit 400 (SR0, SR1, SR2, SR3, SR) provided therein and a selection. The device 410 (SS0, SS1, SS2, SS3, SS) is included.

  When the fixed value response circuit 400 receives a predetermined input, the fixed value response circuit 400 outputs a signal including a unique value (fixed value) to the slave module 300 in which the fixed value response circuit 400 is provided. The fixed value is set for each slave module 300 in advance.

  The selector 410 transmits a signal sent from the interconnect 200 to the functional block 320 via the bus I / F 310 or to the fixed value response circuit 400 based on a test signal (TEST) that is a selection signal. Select (switch). When the signal from the interconnect 200 is transmitted to the functional block 320, the slave module 300 executes the processing of the functional block 320 and returns the processing result to the interconnect 200 via the bus I / F 310 and the selector 410. To do. On the other hand, when the signal from the interconnect 200 is transmitted to the fixed value response circuit 400, the slave module 300 transmits the fixed value set in the slave module 300 from the fixed value response circuit 400 via the selector 410 to the interconnect 200. Respond to.

FIG. 4 is an explanatory diagram of an example of a fixed value response circuit.
A fixed value response circuit 400 shown in FIG. 4 includes a valid transfer determination circuit 401 and a response signal generation circuit 402.

  The valid transfer determination circuit 401 transfers a valid signal that can be processed by the slave module 300 including the valid transfer determination circuit 401 based on a signal input from the interconnect 200 via the selector 410. It is determined whether or not. For example, whether the transferred signal is a valid signal that has been transferred to the slave module 300 from the address signal included in the signal from the interconnect 200 and the bus control signal indicating continuation or termination of the transfer. Determined.

  When the valid transfer determination circuit 401 determines that a valid signal has been transferred, the response signal generation circuit 402 generates a signal including a fixed value of the slave module 300 in which the response signal generation circuit 402 is included. Further, the response signal generation circuit 402 generates a bus control signal indicating that the generated signal including the fixed value is an effective signal that can be processed in the transfer destination module. A signal (response signal) generated by the response signal generation circuit 402 including a fixed value and a bus control signal is transmitted (response) to the interconnect 200 via the selector 410.

  The signal transmitted from the fixed value response circuit 400 to the interconnect 200 is transmitted to the master module 100 that has issued a read command signal to the slave module 300 including the fixed value response circuit 400 via the arbitration unit 230 and the decoding unit 220. I will reply.

  In the system LSI 10A having the above configuration, in order to realize the processing operation according to the specifications, in addition to the processing operation of each master module 100 and each slave module 300, the processing operation of the interconnect 200 connecting them is verified.

The processing operation of each master module 100 itself and the processing operation of each slave module 300 itself are verified by function simulation or the like.
Here, for the interconnect 200, it is verified by logic simulation using the hardware model of the system LSI 10A, for example, whether the decoding processing operation of the decoding unit 220 is the same as the address map specification of the system LSI 10A.

First, an example of an address map is shown in FIG.
FIG. 5 shows an example of the relationship between the address signal (ADR) 0xN (N = 0.0000000 to FFFFFFFF) and the slave module 300 (S0 to S3) as seen from each master module 100 (M0 to M3). Such a relationship is set based on the specifications (specifications) of the system LSI 10A.

  In the address map of FIG. 5, an example of fixed values set for the slave modules S0 to S3 is also shown for convenience. That is, in this example, fixed values of 0x1900BA5E are set in the slave module S0, 0x1901BA5E is set in the slave module S1, 0x1902BA5E is set in the slave module S2, and 0x1903BA5E is set in the slave module S3. Such fixed values are output from the fixed value response circuit 400 provided in each of the slave modules 300 (S0 to S3).

  The fixed values of the slave modules S0 to S3 exemplified in the address map of FIG. 5 are values (expected values) expected as output values of the logic simulation performed based on the address signal ADR as described later. I can say that.

  The interconnect 200 originally transfers signals using the slave modules S0 to S3 defined by the address map as shown in FIG. 5 as the access destination based on the address signal ADR included in the signal transmitted to the decoding unit 220. . In the first embodiment, the decoding unit 220 of the interconnect 200 performs a processing operation (decoding and transfer based on the address map specification) as shown in FIG. 5 or is output from the fixed value response circuit 400 by logic simulation. Verify based on a fixed value.

First, a verification device (logic simulation device) used for verification by logic simulation will be described.
FIG. 6 is a diagram illustrating a configuration example of the logic simulation apparatus.

  A logic simulation apparatus 500 illustrated in FIG. 6 includes a hardware model 510, a test bench 550, a simulation unit 520, a collation unit 530, and a storage unit 540.

  The hardware model 510 is a model in which a system LSI to be verified is described in a hardware description language. The hardware model 510 is created based on the specifications of the system LSI to be verified, and is mounted on the logic simulation apparatus 500. In addition, a test bench 550 for verifying the operation of the created hardware model 510 is created, and is mounted on the logic simulation apparatus 500 together with the hardware model 510.

  The simulation unit 520 executes a logic simulation of the hardware model 510 using the test bench 550 and various data and programs required for the logic simulation (simulation information 560). The simulation information 560 may be implemented in the logic simulation apparatus 500 together with the hardware model 510 and the test bench 550. The simulation unit 520 executes a logic simulation and acquires the output value of the hardware model 510. The simulation unit 520 stores the acquired output value in the storage unit 540.

  The collation unit 530 compares the output value acquired by the simulation unit 520 with a preset expected value, and determines whether the output value matches the expected value. The collation unit 530 stores information indicating the determination result in the storage unit 540.

  The storage unit 540 stores information such as an output value acquired by the simulation unit 520, an expected value for collation with the output value, and a determination result by the collation unit 530, for example, as a database (DB).

A case where the processing operation of the system LSI 10A is verified using such a logic simulation apparatus 500 will be described in more detail.
FIG. 7 is a diagram illustrating an example of a logic simulation apparatus according to the first embodiment. FIG. 8 is a diagram illustrating an example of a logic simulation flow according to the first embodiment.

  In the verification of the system LSI 10A by the logic simulation, as shown in FIG. 7, the hardware model 510A of the system LSI 10A is mounted on the logic simulation apparatus 500 together with the test bench 550A. The logic simulation apparatus 500 executes a simulation by the simulation unit 520 based on the test bench 550A and the like.

  At that time, the logic simulation apparatus 500 first sets the test signal TEST input to the selector 410 provided in the slave module 300 to valid (“1”) (step S1). Whether or not to enable the test signal TEST can be set for the logic simulation apparatus 500 by the operator when the logic simulation is executed.

  Next, the logic simulation device 500 activates the master module 100 (step S2). Further, the logic simulation device 500 executes a command for reading one address signal ADR0xN, and issues a read command signal including the read address signal ADR and a bus control signal from the master module 100 (step S3). For example, the logic simulation apparatus 500 causes the master module 100 to issue a read command signal such as a read transaction based on the test bench 550A and the master module control program 560A that controls the master module 100.

  The read command signal output from the master module 100 is decoded by the decoding unit 220 of the interconnect 200 as described above, and transferred to the corresponding slave module 300 via the access arbitration unit 230 indicated by the decoding result. The In the slave module 300, the test signal TEST is set to be valid (“1”), so that the signal from the interconnect 200 is transmitted to the fixed value response circuit 400 by the selector 410. Then, the fixed value response circuit 400 responds with a signal including the fixed value (0x1900BA5E, 0x1901BA5E, 0x1902BA5E, 0x1903BA5E) of the slave module 300 in which the fixed value response circuit 400 is included. At that time, the fixed value response circuit 400 responds to the interconnect 200 through the selector 410 with a signal including the fixed value of the slave module 300 together with a signal indicating that it is valid.

  For example, when a signal arrives from the interconnect 200, the fixed value response circuit 400 responds to the interconnect 200 with a valid signal including the fixed value of the slave module 300 in which the fixed value response circuit 400 is included.

  When the fixed value response circuit 400 includes the valid transfer determination circuit 401 and the response signal generation circuit 402 as shown in FIG. 4, for example, the fixed value of the slave module 300 is included as follows. A valid signal is returned to interconnect 200. That is, first, the valid transfer determination circuit 401 determines whether a valid signal has arrived from the interconnect 200. When the valid transfer determination circuit 401 determines that a valid signal has arrived, the response signal generation circuit 402 responds to the interconnect 200 with a valid signal including the fixed value of the slave module 300.

From the fixed value response circuit 400, a valid signal including a fixed value of the slave module 300 is returned to the interconnect 200.
The signal including the fixed value of the slave module 300 that is responded to the interconnect 200 is returned to the master module 100 to which the issued read command signal is transferred to the slave module 300 (fixed value response circuit 400). The logic simulation device 500 acquires a fixed value included in the signal transmitted to the master module 100 as a read value (RD) (step S4). Then, the logic simulation apparatus 500 stores the read value RD together with the current address signal ADR in the storage unit 540 (read value DB 540a).

  After the simulation by the simulation unit 520, the logic simulation device 500 executes the matching process by the matching unit 530 for the read value RD acquired by the logic simulation.

  At that time, as shown in FIG. 8, the logic simulation apparatus 500 collates the acquired read value RD with an expected value (EXP) that is set in advance and stored in the storage unit 540 (expected value DB 540b) ( Step S5). The expected value EXP is a fixed value set in advance for each slave module 300 in the address map shown in FIG. 5 set based on the specification 570 of the system LSI 10A.

  For example, assume that the current address signal ADR is 0x00000000. In this case, the logic simulation apparatus 500 compares the read value RD transmitted to each of the master modules M0 to M3 with each expected value EXP, that is, 0x1900BA5E, 0x1902BA5E, 0x1902BA5E, 0x1903BA5E.

  The logic simulation apparatus 500 compares the read value RD obtained in this way with the current address signal ADR and the expected value EXP corresponding to the address signal ADR. If they match (step S6), PASS data indicating that they match is stored in the storage unit 540 (verification result DB 540c) (step S7). If they do not match (step S6), FAIL data indicating that they do not match is stored in the storage unit 540 (verification result DB 540c) (step S8). For example, if a monitor is connected to the logic simulation apparatus 500, the PASS data and the FAIL data can be displayed on the monitor.

  Thereafter, the logic simulation apparatus 500 determines whether or not the current address signal ADR is the maximum value (step S9). If the current address signal ADR is not the maximum value, the address signal ADR is changed (N = N + 1) (step S10). ), The process returns to step S3. The logic simulation apparatus 500 repeats the processes of steps S3 to S10 until the address signal ADR reaches the maximum value.

  In this way, the logic simulation device 500 changes the address signal ADR, issues a read command signal from the master module 100, and acquires the fixed value of the slave module 300 from the fixed value response circuit 400 of the slave module 300. Then, it is determined whether or not the acquired fixed value (read value RD) matches the expected value EXP corresponding to the address map.

  Thereby, it can be verified from the acquired fixed value whether or not the read command signal issued by the master module 100 is transferred to the slave module 300 according to the address map specification. In other words, the decoding unit 220 of the interconnect 200 verifies whether or not the read command signal issued by the master module 100 is transferred to the slave module 300 according to the address map specifications from the acquired fixed value. Can do.

  Here, a fixed value returned from the fixed value response circuit 400 of each slave module 300 is used for verifying whether the decoding unit 220 of the interconnect 200 is performing a processing operation according to the address map specification. Therefore, the processing operation can be easily verified as compared with the case where the processing operation of the decoding unit 220 is verified using the output value from the functional block 320 of each slave module 300.

Here, for comparison, a verification example of a system LSI that does not include the fixed value response circuit as described above will be described.
FIG. 9 is a diagram showing another example of the logic simulation apparatus, and FIG. 10 is a diagram showing another example of the logic simulation flow.

  The logic simulation apparatus 500a shown in FIG. 9 uses the system LSI hardware model 510a that does not include the fixed value response circuit 400 and the selector 410 as described above, and thus the logic simulation apparatus 500 shown in FIG. Is different. In the logic simulation apparatus 500a shown in FIG. 9, such a hardware model 510a and its test bench 550a are mounted, and a simulation is executed.

First, the logic simulation apparatus 500a initializes and starts each master module 100 and each slave module 300 (step S20).
Next, the logic simulation device 500a executes an instruction for reading one address signal ADR0xN. Then, the logic simulation device 500a issues a read command signal such as a read transaction from the master module 100 based on the test bench 550a and the master module control program 560a (step S21).

  The read command signal output from the master module 100 in this manner is decoded by the decoding unit 220 of the interconnect 200 and transferred to the corresponding slave module 300 via the access arbitration unit 230 indicated by the decoding result. . The signal transferred to the slave module 300 is transmitted to the functional block 320 via the bus I / F 310.

  The output value obtained as a result of executing the processing operation in the functional block 320 is returned to the interconnect 200 and returned to the master module 100 to which the read command signal issued to the functional block 320 is transferred. When a valid response is obtained from the functional block 320 in the master module 100, the logic simulation device 500a determines that reading (reading) is successful (step S22). Then, the logic simulation device 500a acquires the response signal from the functional block 320 as a read value (RDa), and stores it in the read value DB 540a together with the current address signal ADR (step S23).

  Next, the logic simulation device 500a collates the read value RDa (output value from the functional block 320 of the slave module 300) with the expected value (EXPa) stored in the expected value DB 540b (step S24). The expected value EXPa here is a value expected as an output value (read value RDa) from the functional block 320 of the slave module 300 for each address signal ADR in the address map based on the specification 570 of the system LSI. .

  When the read value RDa acquired by the current address signal ADR matches the expected value EXPa (step S25), the logic simulation device 500a stores the PASS data in the verification result DB 540c (step S26). If they do not match (step S25), the FAIL data is stored in the verification result DB 540c (step S27). The logic simulation device 500a similarly stores the FAIL data in the verification result DB 540c even when it is determined that the valid response is not returned to the master module 100 in step S22 and the read is unsuccessful (step S27). .

  Thereafter, the logic simulation device 500a determines whether or not the current address signal ADR is the maximum value (step S28). If the current address signal ADR is not the maximum value, the logic simulation device 500a changes the address signal ADR (step S29) and proceeds to step S21. Return. The logic simulation device 500a repeats the processes of steps S21 to S29 until the address signal ADR reaches the maximum value.

  As described above, in the verification using the logic simulation device 500a, the output value from the functional block 320 of each slave module 300 is set as the read value RDa and compared with the expected value EXPa to determine whether or not they match. .

  However, in this case, in order to acquire the read value RDa, it is necessary to actually operate (simulate) the functional block 320 of each slave module 300, and verification may not be performed efficiently.

  In addition, a valid response is not always acquired from the functional block 320 of each slave module 300 as the read value RDa. This is because each slave module 300 may have to follow a predetermined operation flow in order to output a valid response to a read command signal such as a read transaction.

  For example, when the slave module S0 is a memory controller, if the slave module S0 is not connected to an external main memory, nothing is read or a read error occurs even if a read command signal is received. I will do. Further, when the slave module S1 is an interrupt controller, a read error or the like occurs even if a read command signal is received if there is no predetermined external interrupt operation. Further, when the slave module S2 is an internal memory, a read error or the like occurs even if a read command signal is received unless the internal memory has been previously written. Further, when the slave module S3 is used as a system control register, as a result of receiving a read command signal, the hardware model 510a (system LSI) shifts to an unintended operation mode, and a target read value RDa is obtained. There can be nothing.

  Thus, each slave module 300 may not be able to output a valid response to a read command signal such as a read transaction unless it follows a predetermined operation flow. In this case, a valid response (read value RDa) cannot be obtained simply by issuing a read transaction while changing the address signal ADR.

  If a valid response is not obtained, the logic simulation device 500a determines that the read is unsuccessful in step S22. However, among those that are read unsuccessfully, the decoding unit 220 of the interconnect 200 transfers the read command signal from the master module 100 to the slave module 300 that is the access destination according to the address map specification. Can also be included. Therefore, in the case of unsuccessful read, whether or not the decoding unit 220 transfers the read command signal from the master module 100 to the slave module 300 according to the address map specification based on the signal waveform, the specification 570, and the like. Will be verified visually.

  Such visual verification requires time and labor. Here, although one interconnect 200 is taken as an example, a plurality of interconnects 200 connected in series may be provided between the master module 100 and the slave module 300 depending on the system LSI. In addition, the specifications may differ depending on the master module 100, such as the decoding mechanism of the corresponding decoding unit 220. As described above, when the circuit configuration between the master module 100 and the slave module 300 becomes relatively complicated, appropriate visual verification work may be difficult.

  On the other hand, in the verification of the processing operation of the decoding unit 220 of the system LSI 10A using the logic simulation apparatus 500, it is possible to perform the verification efficiently without performing such visual verification work. Become.

  That is, in the logic simulation apparatus 500, when the read command signal issued by the master module 100 is transferred from the interconnect 200 to the slave module 300, the fixed value response circuit 400 responds with the fixed value of the slave module 300. To do. Then, the decoding unit 220 of the interconnect 200 verifies whether the read command signal issued by the master module 100 is transferred to the slave module 300 according to the address map specification from the fixed value that is returned. Since the functional block 320 is not passed during the verification by the logic simulation, the occurrence of a read error or the like can be suppressed. Therefore, the processing operation of the decoding unit 220 can be efficiently verified without performing visual verification work. It becomes possible to do.

  The slave module 300 of the system LSI 10A is provided with a selector 410 that transmits a signal from the interconnect 200 to either the fixed value response circuit 400 side or the functional block 320 side. When the test signal TEST input to the selector 410 is set to invalid (“0”), the signal from the interconnect 200 is transmitted to the functional block 320 via the bus I / F 310. In this case, the signal output by the operation of the functional block 320 can be acquired in the hardware model 510A of the system LSI 10A. In the logic simulation using the hardware model 510A of the system LSI 10A, a signal output by the operation (simulation) of the functional block 320 can be acquired as the read value RDa and compared with the expected value EXPa. It is.

  Various bus protocols can be applied to the system LSI 10A including the fixed value response circuit 400 and the hardware model 510A thereof. Examples of application of two types of bus protocols are shown below.

FIG. 11 is a diagram for explaining an application example of the first bus protocol.
FIG. 11 shows an application example of the Advanced High-performance Bus (AHB) protocol of AMBA (Advanced Microcontroller Bus Architecture).

  A read command signal issued by the master module 100 is transferred to the slave module 300 via the interconnect 200. For example, the HADDR signal, the HTRANS signal, the HWRITE signal, the HSIZE signal, the HWDATA signal, the HSEL signal, and the HREADYin signal are transferred to the slave module 300.

  The HADDR signal is a signal indicating a system address bus of a predetermined bit. The HTRANS signal is a signal indicating a transfer type (NONSEQUENTIAL, SEQUENTIAL, IDLE, BUSY). The HWRITE signal is a signal indicating writing or reading, and is a signal indicating reading when High and reading when Low. The HSIZE signal is a signal indicating the transfer size (number of bytes). The HWDATA signal is a signal indicating a write data bus at the time of writing. The HSEL signal is a signal obtained by decoding a combination of address buses and indicates selection of the slave module 300 to which the signal is transferred. The HREADYin signal is a signal indicating the continuation or termination of the transfer at the time of input to the slave module 300, and indicates that the transfer has been completed in the case of High, and that the transfer has been continued in the case of Low. Signal.

For example, these signals are input from the interconnect 200 to the selector 410 of the slave module 300 (dotted line arrow in FIG. 11).
When the test signal TEST of the selector 410 is set to “1” (High) indicating that it is valid, the signal input to the selector 410 is input to the fixed value response circuit 400. The fixed value response circuit 400 receives the input and responds to the interconnect 200 via the selector 410 with a predetermined signal including the fixed value of the slave module 300 in which the fixed value response circuit 400 is provided. From the fixed value response circuit 400, for example, each signal of the HRDATA signal, the HREADYout signal, and the HRESP signal is returned to the interconnect 200.

  When the test signal TEST of the selector 410 is set to “0” (Low) indicating that it is invalid, the signal input from the interconnect 200 to the selector 410 is sent to the bus I / F 310. To the function block 320. The functional block 320 receives the input and a clock signal input to the slave module 300, executes predetermined processing, and selects a predetermined signal including the processing result (output value) and the bus I / F 310. Responds to interconnect 200 via device 410. During the processing in the functional block 320, the slave module 300 receives the HCLK signal and the HRESETn signal. From the functional block 320 side, for example, each signal of the HRDATA signal, the HREADYout signal, and the HRESP signal is returned to the interconnect 200.

  The HCLK signal input to the slave module 300 is a signal indicating a clock. The HRESETn signal is a signal for resetting the system and the bus, and is set to High during normal operation and set to Low at reset.

  The HRDATA signal output from the fixed value response circuit 400, the bus I / F 310, and the selector 410 is a signal indicating a read data bus at the time of reading, and is a fixed value set in the slave module 300 or a function block 320. Contains the output value of. The HREADYout signal is a signal indicating the continuation or termination of the transfer at the time of output from the slave module 300, and indicates that the transfer has been completed in the case of High, and that the transfer has been continued in the case of Low. Signal. The HREADYout signal is fixed to High when a fixed value is output from the fixed value response circuit 400. The HRESP signal is a signal indicating a transfer state (OKAY, ERROR, RETRY, SPLIT), and is fixed to Low when a fixed value is output from the fixed value response circuit 400.

The fixed value response circuit 400 in FIG. 11 shows an example of each signal of the HRDATA signal, the HREADYout signal, and the HRESP signal.
FIG. 12 is a diagram for explaining an application example of the second bus protocol.

FIG. 12 shows an application example of AMBA APB (Advanced Peripheral Bus) 3 protocol.
A read command signal issued by the master module 100 is transferred to the slave module 300 via the interconnect 200. For example, a PADDR signal, a PSEL signal, a PENABLE signal, a PWRITE signal, and a PWDATA signal are transferred to the slave module 300.

  The PADDR signal is a signal indicating an address bus. The PSEL signal is a signal indicating that the slave module 300 is selected and transfer is performed. The PENABLE signal is a signal indicating the timing of access to the slave module 300. The PWRITE signal is a signal indicating writing or reading, and is a signal indicating reading when High and reading when Low. The PWDATA signal is a signal indicating a write data bus at the time of writing.

For example, these signals are input from the interconnect 200 to the selector 410 of the slave module 300 (dotted line arrows in FIG. 12).
When the test signal TEST of the selector 410 is set to “1” (High) indicating that it is valid, the signal input to the selector 410 is input to the fixed value response circuit 400. The fixed value response circuit 400 receives the input and responds to the interconnect 200 via the selector 410 with a predetermined signal including the fixed value of the slave module 300 in which the fixed value response circuit 400 is provided. From the fixed value response circuit 400, for example, each of a PRDATA signal, a PREADY signal, and a PSLVERR signal is returned to the interconnect 200.

  When the test signal TEST of the selector 410 is set to “0” (Low) indicating that it is invalid, the signal input from the interconnect 200 to the selector 410 is sent to the bus I / F 310. To the function block 320. The functional block 320 receives the input and a clock signal input to the slave module 300, executes a predetermined process, and selects a predetermined signal including an output value corresponding to the process by the bus I / F 310. Responds to interconnect 200 via device 410. During the processing in the functional block 320, the PCLK signal and the PRESETn signal are input to the slave module 300. From the functional block 320 side, for example, the PRDATA signal, the PREADY signal, and the PSLVERR signal are returned to the interconnect 200.

  The PCLK signal input to the slave module 300 is a signal indicating a clock. The PRESETn signal is a signal for resetting the system and the bus, and is set to High during normal operation and set to Low at reset.

  The PRDATA signal output from the fixed value response circuit 400, the bus I / F 310, and the selector 410 is a signal indicating a read data bus at the time of reading, and is a fixed value set in the slave module 300 or a function block 320. Contains the output value of. The PREADY signal is a signal indicating the continuation or termination of the transfer at the time of output from the slave module 300, and indicates that the transfer has been completed in the case of High, and that the transfer has been continued in the case of Low. Signal. The PREADY signal is fixed to High when a fixed value is output from the fixed value response circuit 400. The PSLVERR signal is a signal indicating a transfer state, and is fixed to Low when a fixed value is output from the fixed value response circuit 400.

The fixed value response circuit 400 in FIG. 12 shows an example of each of the PRDATA signal, the PREADY signal, and the PSLVERR signal.
Here, the AHB protocol and the APB3 protocol are illustrated, but it is also possible to realize the system LSI 10A and its hardware model 510A by applying other bus protocols such as an AXI (Advanced eXtensible Interface) protocol.

  In the above description, the system LSI 10A in which the fixed value response circuit 400 and the selector 410 are provided in the slave module 300 and the hardware model 510A thereof are exemplified.

  The system LSI to be manufactured may include the fixed value response circuit 400 and the selector 410 as described above. In this case, the test signal TEST input to the selector 410 may be set to invalid (“0”) during the operation of such a system LSI. It is also possible to set the test signal TEST input to the selector 410 to be valid (“1”) and check the operation of the system LSI.

  The system LSI to be manufactured may be configured such that the fixed value response circuit 400 and the selector 410 are not provided. In this case, the hardware model 510A provided with the fixed value response circuit 400 and the selector 410 as described above may be used at the time of verification by logic simulation performed when manufacturing such a system LSI.

Next, a second embodiment will be described.
FIG. 13 is an explanatory diagram of a main part of the system LSI according to the second embodiment.
In the first embodiment, as illustrated in FIG. 3 and the like, the fixed value response circuit 400 and the selector 410 provided in the system LSI 10A are exemplified in the slave module 300. The system LSI 10B according to the second embodiment shown in FIG. 13 is different from the first embodiment in that the fixed value response circuit 400 and the selector 410 are provided outside the slave module 300. This is different from the system LSI 10A. In FIG. 13, a part of the interconnect 200 is shown, and the master module 100 is not shown.

In the system LSI 10B according to the second embodiment, the fixed value response circuit 400 and the selector 410 can be provided corresponding to each slave module 300, respectively.
A read command signal such as a read transaction issued by the master module 100 is transferred from the interconnect 200 to the access target slave module 300 according to the decoding result of the decoding unit 220. A signal transferred in the interconnect 200 to the slave module 300 to be accessed is first input to a selector 410 provided corresponding to the slave module 300.

  If the test signal TEST is set to be valid (“1”), the signal input to the selector 410 is input to the fixed value response circuit 400 provided corresponding to the slave module 300, similarly to the selector 410. Is done. The fixed value response circuit 400 outputs a signal including a fixed value set in the corresponding slave module 300, and the output signal is returned to the interconnect 200 via the selector 410 and returned to the master module 100. .

  If the test signal TEST is set to invalid (“0”), the signal input to the selector 410 is input to the function block 320 of the corresponding slave module 300 via the bus I / F 310. The functional block 320 executes the processing and responds to the interconnect 200 via the bus I / F 310 and the selector 410 with a signal including the processing result.

  At the time of verification by logic simulation, the hardware model of the system LSI 10B in which the fixed value response circuit 400 and the selector 410 are provided outside the corresponding slave module 300 is used.

  Note that the system LSI to be manufactured may include the fixed value response circuit 400 and the selector 410 as described above. In this case, the test signal TEST input to the selector 410 may be set to invalid (“0”) during the operation of such a system LSI. It is also possible to set the test signal TEST input to the selector 410 to be valid (“1”) and check the operation of the system LSI.

  The system LSI to be manufactured may be configured such that the fixed value response circuit 400 and the selector 410 are not provided. In this case, a hardware model provided with the fixed value response circuit 400 and the selector 410 as described above may be used at the time of verification by logic simulation performed when manufacturing such a system LSI.

  Even when the fixed value response circuit 400 and the selector 410 are provided outside the corresponding slave module 300 as in the second embodiment, the same effect as described in the first embodiment is obtained. Can be obtained.

Next, a third embodiment will be described.
FIG. 14 is a diagram illustrating a configuration example of a system LSI according to the third embodiment, and FIG. 15 is an explanatory diagram of a main part of the system LSI according to the third embodiment.

  A system LSI 10C according to the third embodiment shown in FIGS. 14 and 15 includes a master module 100 (M0 to M3, M), a read command issue circuit 600 (MR0 to MR3, MR), and a selector 610 (MS0). To MS3, MS). In this respect, the system LSI 10C according to the third embodiment is different from the system LSI 10A according to the first embodiment.

  The read command issue circuit 600 includes an address counter 601 that changes an address signal ADR0xN (N = 0.0000000 to FFFFFFFF). For each address signal ADR set by the address counter 601, the read command issue circuit 600 replaces the functional block 120 (MF0 to MF3, MF) of the master module 100 with a read command signal (control signal) such as a valid read transaction. ).

  Based on the test signal TEST, the selector 610 transmits a read command signal to be transmitted to the interconnect 200 via the bus I / F 110 (MB0 to MB3, MB) from the read command issue circuit 600 or from the functional block 120. Select whether to do.

  In the system LSI 10C, the response (read value RD) to the read command signal issued from the read command issue circuit 600 and the address signal ADR at the time of issuing the read command signal are extracted to the outside of the master module 100, for example. ing.

  Next, a case where the processing operation of the decoding unit 220 of the interconnect 200 is verified by logic simulation using such a hardware model of the system LSI 10C will be described.

  For the verification by the logic simulation of the system LSI 10C, for example, the logic simulation device 500 having the configuration as shown in FIG. 6 can be used. A case where the processing operation of the system LSI 10C is verified using such a logic simulation apparatus 500 will be described in more detail.

  FIG. 16 is a diagram illustrating an example of a logic simulation apparatus according to the third embodiment, FIG. 17 is an explanatory diagram of a master module at the time of logic simulation according to the third embodiment, and FIG. 18 is a third embodiment. It is a figure which shows an example of the logic simulation flow concerning.

  In verification by the logic simulation of the system LSI 10C, as shown in FIG. 16, the hardware model 510C (510) of the system LSI 10C is mounted on the logic simulation apparatus 500 together with the test bench 550C (550). The logic simulation device 500 executes a simulation by the simulation unit 520 based on the test bench 550C and the like.

  At that time, the logic simulation apparatus 500 first sets the test signal TEST input to the selector 610 provided in the master module 100 and the selector 410 provided in the slave module 300 to be valid (“1”) (step S30). ).

  Next, the logic simulation device 500 activates the read command issue circuit 600 (step S31). Further, the logic simulation apparatus 500 sets one address signal ADR0xN by the address counter 601 (FIG. 17) provided in the read command issue circuit 600. Then, the logic simulation apparatus 500 issues a read command signal such as a valid read transaction corresponding to the set address signal ADR by the read command issue circuit 600 (step S32).

  The signal output from the read command issuing circuit 600 of the master module 100 is decoded by the decoding unit 220 of the interconnect 200 and transferred to the slave module 300 that is the access destination indicated by the decoding result. In the slave module 300, the test signal TEST is set to valid (“1”), so that the signal from the interconnect 200 is transmitted to the fixed value response circuit 400 by the selector 410. From the fixed value response circuit 400, a valid signal including a fixed value of the slave module 300 including the fixed value response circuit 400 is returned to the interconnect 200.

  The signal responded to the interconnect 200 is returned to the master module 100 (selector 610). The logic simulation device 500 acquires a fixed value included in the signal transmitted to the selector 610 of the master module 100 as a read value RD (step S33). Then, the logic simulation apparatus 500 stores the read value RD together with the current address signal ADR in the read value DB 540a.

  After the simulation by the simulation unit 520, the logic simulation device 500 executes the matching process by the matching unit 530 for the read value RD acquired by the logic simulation.

  At that time, as shown in FIG. 18, the logic simulation apparatus 500 converts the read value RD into the expected value EXP stored in the expected value DB 540b (fixed value set in each slave module 300 based on the specification 570). (Step S34).

  When the read value RD acquired by the current address signal ADR matches the expected value EXP (step S35), the logic simulation device 500 stores the PASS data in the verification result DB 540c (step S36). If they do not match (step S35), the FAIL data is stored in the verification result DB 540c (step S37). For example, if a monitor is connected to the logic simulation apparatus 500, the PASS data and the FAIL data can be displayed on the monitor.

  Thereafter, the logic simulation device 500 determines whether or not the current address signal ADR is the maximum value (step S38). If the address signal ADR is not the maximum value, the process returns to step S32, the address signal ADR is changed by the address counter 601 (N = N + 1), and the processes after step S32 are executed. The logic simulation apparatus 500 repeats the processes of steps S32 to S38 until the address signal ADR reaches the maximum value.

  According to such a logic simulation, an effective read command signal is issued while sequentially changing the address signal ADR. Therefore, the control flow at the time of the logic simulation is unified for any master module 100. A master module control program for each master module 100 can be eliminated. Therefore, the processing operation of the decoding unit 220 of the interconnect 200 can be verified more efficiently than when the read command signal is output from the functional block 120 of the master module 100.

  The master module 100 is provided with a selector 610 that transmits a read command signal to the interconnect 200 from either the read command issue circuit 600 side or the functional block 120 side. If the test signal TEST input to the selector 410 is set to invalid (“0”), the read command signal issued by the functional block 120 can be transmitted to the interconnect 200 via the bus I / F 110.

In the third embodiment, the system LSI 10C provided with the read command issuing circuit 600 and the selector 610 and its hardware model 510C are exemplified.
The system LSI to be manufactured may include the read command issue circuit 600 and the selector 610 as described above, and the fixed value response circuit 400 and the selector 410. In this case, the test signal TEST input to the selectors 610 and 410 may be set to invalid (“0”) during the operation of such a system LSI. It is also possible to set the test signal TEST input to the selectors 610 and 410 to be valid (“1”) and check the operation of the system LSI.

  The system LSI to be manufactured may be configured not to include the read command issue circuit 600 and the selector 610, and the fixed value response circuit 400 and the selector 410. In this case, a hardware model 510C provided with the read command issue circuit 600, the fixed value response circuit 400, and the selectors 610 and 410 as described above at the time of verification by logic simulation performed when manufacturing such a system LSI. May be used.

  The read command issue circuit 600 and the selector 610 are the same as the master module 100 of the system LSI 10B according to the second embodiment in which the fixed value response circuit 400 and the selector 410 are provided outside the slave module 300. It is applicable to.

Next, a fourth embodiment will be described.
FIG. 19 is an explanatory diagram of a main part of a system LSI according to the fourth embodiment.
In the third embodiment, the case where the read command issue circuit 600 and the selector 610 are provided in the master module 100 is illustrated. The system LSI 10D according to the fourth embodiment shown in FIG. 19 is different from the third embodiment in that a read command issuing circuit 600 and a selector 610 are provided outside the master module 100. This is different from the system LSI 10C. In FIG. 19, a part of the interconnect 200 is shown, and the slave module 300 and the fixed value response circuit 400 and the selector 410 provided inside or outside thereof are not shown.

  In the system LSI 10D according to the fourth embodiment, the read command issuing circuit 600 and the selector 610 can be provided corresponding to each master module 100. At the time of verification by logic simulation, the hardware model of the system LSI 10D in which the read command issuing circuit 600 and the selector 610 are provided outside the corresponding master module 100 is used.

  As described in the third embodiment, the system LSI to be manufactured includes the read command issue circuit 600, the fixed value response circuit 400, and the selectors 610 and 410, and inputs to the selectors 610 and 410. The operation may be controlled by the test signal TEST.

  Further, the read command issue circuit 600, the fixed value response circuit 400, and the selectors 610 and 410 may be provided not in the system LSI to be manufactured but in a hardware model used for verification by logic simulation.

  As in the fourth embodiment, when the read command issuing circuit 600 and the selector 610 are provided outside the corresponding slave module 300, the same effect as described in the third embodiment is obtained. Can be obtained.

  In the above, the system LSI, its hardware model, and the logic simulation apparatus and logic simulation method using the hardware model have been described. A computer can be used as the logic simulation apparatus.

FIG. 20 is a diagram illustrating a hardware configuration example of the logic simulation apparatus.
The entire logic simulation apparatus 500 is controlled by a CPU (Central Processing Unit) 581. A RAM (Random Access Memory) 582 and a plurality of peripheral devices are connected to the CPU 581 via a bus 588.

  The RAM 582 is used as a main storage device of the logic simulation device 500. The RAM 582 temporarily stores at least part of an OS (Operating System) program and application programs to be executed by the CPU 581. The RAM 582 stores various data necessary for processing by the CPU 581.

  Peripheral devices connected to the bus 588 include a hard disk drive (HDD) 583, a graphic processing device 584, an input I / F 585, an optical drive device 586, and a communication I / F 587.

  The HDD 583 magnetically writes and reads data to and from the built-in disk. The HDD 583 is used as a secondary storage device of the logic simulation device 500. The HDD 583 stores an OS program, application programs, and various data. A semiconductor storage device such as a flash memory can also be used as the secondary storage device.

  A monitor 591 is connected to the graphic processing device 584. The graphic processing device 584 displays an image on the screen of the monitor 591 in accordance with a command from the CPU 581. Examples of the monitor 591 include a display device using a CRT (Cathode Ray Tube) and a liquid crystal display device.

  A keyboard 592 and a mouse 593 are connected to the input I / F 585. The input I / F 585 transmits a signal sent from the keyboard 592 or the mouse 593 to the CPU 581. Note that the mouse 593 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

  The optical drive device 586 reads data recorded on the optical disk 594 using a laser beam or the like. The optical disk 594 is a portable recording medium on which data is recorded so that it can be read by reflection of light. The optical disk 594 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (ReWritable), and the like.

  Communication I / F 587 is connected to network 700. The communication I / F 587 transmits and receives data to and from other computers or communication devices via the network 700.

With the hardware configuration as described above, the processing function of the logic simulation apparatus 500 can be realized.
The processing functions of the logic simulation apparatus 500 are realized by a computer, and in this case, a program describing the processing contents of the functions of the logic simulation apparatus 500 is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium. Examples of the computer-readable recording medium include a magnetic storage device, an optical disk, a magneto-optical recording medium, and a semiconductor memory. Magnetic storage devices include HDDs, flexible disks (FD), magnetic tapes, and the like. Optical discs include DVD, DVD-RAM, CD-ROM / RW, and the like. Magneto-optical recording media include MO (Magneto-Optical disk).

  When distributing the program, for example, a portable recording medium such as a DVD or a CD-ROM in which the program is recorded is sold. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. In addition, each time a program is transferred from a server computer connected via a network, the computer can sequentially execute processing according to the received program.

  Further, at least a part of the above processing functions can be realized by an electronic circuit such as a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or a PLD (Programmable Logic Device).

Regarding the embodiment described above, the following additional notes are further disclosed.
(Supplementary Note 1) A first module that issues an instruction by itself;
An interconnect connected to the first module and transferring a received signal to a connection destination of the first module specified based on the signal;
A second module designated as a connection destination of the first module by the interconnect;
A fixed value response circuit that receives the read command signal and transmits a fixed value specific to the second module to the interconnect when a read command signal is transmitted from the interconnect to the second module;
An integrated circuit device comprising:

  (Supplementary note 2) The integrated circuit device according to supplementary note 1, further comprising a selector that inputs the read command signal to either the second module or the fixed value response circuit based on a selection signal.

(Supplementary Note 3) The interconnect includes a decoding unit that decodes a control signal including an address signal transmitted to the interconnect, and the second module is changed to the first module based on a decoding result of the decoding unit. Specify the connection destination of
The integrated circuit device according to appendix 1 or 2, wherein the read command signal is a signal obtained by decoding the control signal by the decoding unit.

(Supplementary note 4) The integrated circuit device according to Supplementary note 3, wherein the first module generates the control signal and transmits the control signal to the interconnect.
(Supplementary note 5) The integrated circuit device according to supplementary note 3, further comprising a read command issue circuit that generates the control signal and transmits the generated control signal to the interconnect.

(Supplementary Note 6) The integrated circuit device according to any one of Supplementary Notes 1 to 5, wherein the fixed value response circuit is provided in the second module.
(Supplementary note 7) The integrated circuit device according to any one of Supplementary notes 1 to 6, wherein an AMBA AHB protocol or APB3 protocol is used for the fixed value response circuit.

(Supplementary Note 8) A first module that issues a command itself, an interconnect that is connected to the first module and that transfers a received signal to a connection destination of the first module that is designated based on the signal; When a read command signal for the second module designated by the interconnect as a connection destination of the first module and a read command signal for the second module are transmitted from the interconnect, the read command signal is received and the second module is received. A hardware model of an integrated circuit device including a fixed value response circuit that transmits a fixed value specific to two modules to the interconnect;
Using the hardware model, a simulation unit that acquires the fixed value by executing a simulation that causes the fixed value response circuit to receive the read command signal;
A collation unit for collating the fixed value acquired by the simulation unit with an expected value set based on a specification of the integrated circuit device;
The verification apparatus characterized by including.

(Supplementary Note 9) The hardware model includes a selector that transmits the read command signal to either the second module or the fixed value response circuit based on a selection signal.
In the simulation, the fixed value response circuit receives the read command signal by the selector.
The verification apparatus according to appendix 8, characterized by:

(Supplementary Note 10) The interconnect includes a decoding unit that decodes a control signal including an address signal transmitted to the interconnect, and the second module is changed to the first module based on a decoding result of the decoding unit. Specify the connection destination of
10. The verification apparatus according to appendix 8 or 9, wherein the read command signal is a signal obtained by decoding the control signal by the decoding unit.

  (Additional remark 11) The said simulation part produces | generates the said control signal by the said 1st module, and transmits to the said interconnect, The verification apparatus of Additional remark 10 characterized by the above-mentioned.

(Supplementary Note 12) The hardware model includes a read command issue circuit that generates the control signal and transmits the generated control signal to the interconnect.
11. The verification apparatus according to appendix 10, wherein the simulation unit generates the control signal by the read command issue circuit and transmits the control signal to the interconnect.

  (Additional remark 13) The said simulation part produces | generates the said control signal about the said each address signal, changing an address signal, The verification apparatus of Additional remark 11 or 12 characterized by the above-mentioned.

(Supplementary note 14)
A first module that issues a command by itself; an interconnect that is connected to the first module and that transfers a received signal to a connection destination of the first module that is designated based on the signal; and When the read command signal for the second module specified as the connection destination of the first module and the interconnect is transmitted from the interconnect to the second module, the read command signal is received and the second module specific Using a hardware model of an integrated circuit device including a fixed value response circuit that transmits a fixed value of the fixed value response circuit to the interconnect, and executing a simulation for causing the fixed value response circuit to receive the read command signal by a simulation unit. Get the value
The collation unit collates the fixed value acquired by the simulation unit and the expected value set based on the specifications of the integrated circuit device.
A verification method characterized by that.

(Supplementary note 15)
A first module that issues a command by itself; an interconnect that is connected to the first module and that transfers a received signal to a connection destination of the first module that is designated based on the signal; and When the read command signal for the second module specified as the connection destination of the first module and the interconnect is transmitted from the interconnect to the second module, the read command signal is received and the second module specific Using a hardware model of an integrated circuit device including a fixed value response circuit that transmits a fixed value of the fixed value response circuit to the interconnect, and executing a simulation for causing the fixed value response circuit to receive the read command signal by a simulation unit. Get the value
The collation unit collates the fixed value acquired by the simulation unit and the expected value set based on the specifications of the integrated circuit device.
A verification program characterized by causing processing to be executed.

10 Integrated Circuit Device 10A, 10B, 10C, 10D System LSI
11,100 Master module 12,200 Interconnect 13,300 Slave module 14,400 Fixed value response circuit 110, 210, 240, 310 Bus I / F
120, 320 Functional block 220 Decoding unit 230 Arbitration unit 401 Effective transfer determination circuit 402 Response signal generation circuit 410, 610 Selector 500, 500a Logic simulation device 510, 510a, 510A, 510C Hardware model 520 Simulation unit 530 Verification unit 540 Storage Section 540a Read value DB
540b Expected value DB
540c Verification result DB
550, 550a, 550A, 550C Test bench 560 Simulation information 560a, 560A Master module control program 570 Specification 581 CPU
582 RAM
583 HDD
584 Graphic processing unit 585 Input I / F
586 Optical drive device 587 Communication I / F
588 bus 591 monitor 592 keyboard 593 mouse 594 optical disk 600 read command issue circuit 601 address counter 700 network

Claims (8)

A first module that issues its own instructions;
An interconnect connected to the first module and transferring a received signal to a connection destination of the first module specified based on the signal;
A second module designated as a connection destination of the first module by the interconnect;
A fixed value response circuit that receives the read command signal and transmits a fixed value specific to the second module to the interconnect when a read command signal is transmitted from the interconnect to the second module;
An integrated circuit device comprising: The interconnect includes a decoding unit that decodes a control signal including an address signal transmitted to the interconnect, and based on a decoding result of the decoding unit, the second module is set as a connection destination of the first module. Specify
2. The integrated circuit device according to claim 1, wherein the read command signal is a signal obtained by decoding the control signal by the decoding unit.   The integrated circuit device according to claim 2, further comprising a read command issue circuit that generates the control signal and transmits the generated control signal to the interconnect. A first module that issues a command by itself; an interconnect that is connected to the first module and that transfers a received signal to a connection destination of the first module that is designated based on the signal; and When the read command signal for the second module specified as the connection destination of the first module and the interconnect is transmitted from the interconnect to the second module, the read command signal is received and the second module specific A hardware model of an integrated circuit device including a fixed value response circuit that transmits a fixed value of
Using the hardware model, a simulation unit that acquires the fixed value by executing a simulation that causes the fixed value response circuit to receive the read command signal;
A collation unit for collating the fixed value acquired by the simulation unit with an expected value set based on a specification of the integrated circuit device;
The verification apparatus characterized by including. The interconnect includes a decoding unit that decodes a control signal including an address signal transmitted to the interconnect, and based on a decoding result of the decoding unit, the second module is set as a connection destination of the first module. Specify
The verification apparatus according to claim 4, wherein the read command signal is a signal obtained by decoding the control signal by the decoding unit. The hardware model includes a read command issue circuit that generates the control signal and transmits the generated control signal to the interconnect,
The verification apparatus according to claim 5, wherein the simulation unit generates the control signal by the read command issue circuit and transmits the control signal to the interconnect.   The verification apparatus according to claim 6, wherein the simulation unit generates the control signal for each address signal while changing the address signal. Computer
A first module that issues a command by itself; an interconnect that is connected to the first module and that transfers a received signal to a connection destination of the first module that is designated based on the signal; and When the read command signal for the second module specified as the connection destination of the first module and the interconnect is transmitted from the interconnect to the second module, the read command signal is received and the second module specific Using a hardware model of an integrated circuit device including a fixed value response circuit that transmits a fixed value of the fixed value response circuit to the interconnect, and executing a simulation for causing the fixed value response circuit to receive the read command signal by a simulation unit. Get the value
The collation unit collates the fixed value acquired by the simulation unit and the expected value set based on the specifications of the integrated circuit device.
A verification method characterized by that.

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