JP2012233732A - Test system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a test time for the electrical measurement of a semiconductor device at low cost without impairing the effect of noise attenuation.SOLUTION: A power supply circuit 4 provided on a semiconductor tester 2 generates a power supply voltage VCC, which is supplied to a semiconductor device DUT as an operation power supply, and a power supply voltage VCC1 whose voltage level is approximately the same as that of the power supply voltage VCC. A test board 3 on which the semiconductor device DUT is mounted comprises capacitors 5 and 6 which eliminate the noise of the power supply voltage VCC. The capacitor 5 having a capacitance value on the order of 470 μF is connected between a power supply line 7 to which the power supply voltage VCC is connected and a power supply line 8 to which the power supply voltage VCC1 generated by the power supply circuit 4 is connected. By connecting the capacitor 5 through AC coupling, the noise applied to the power supply voltage VCC is eliminated with the time of charging/discharging the capacitor 5 cancelled.

Description

  The present invention relates to an electrical measurement technique for a semiconductor device, and more particularly to a technique effective for efficient removal of noise applied to a power supply voltage of a semiconductor device.

  In a semiconductor device, for example, a probe test or the like is applied to a bonding pad formed on a semiconductor wafer to test the electrical characteristics of a die, and a wafer test for selecting non-defective / defective products or a semiconductor device before shipment. A final test is performed to test the electrical characteristics and confirm that the mounted semiconductor chip functions correctly.

  For example, the final test is performed by mounting a plurality of semiconductor devices on a test board such as a burn-in board electrically connected to a tester for testing the semiconductor devices.

  A plurality of sockets for mounting semiconductor devices are mounted on this type of test board, and a semiconductor device serving as a device under test is mounted in the sockets. In addition, a noise removing capacitor, a so-called power bypass capacitor, is mounted on the test board.

  For example, a capacitor having a capacitance of about 0.1 μF is used as the power bypass capacitor. However, as the circuit scale of the semiconductor device increases and the operation content becomes complicated, noise countermeasures in various frequency bands Countermeasures for power supply fluctuations are necessary.

  Therefore, in order to stabilize the power supply voltage VCC, a capacitor having a large capacitance value of about 470 μF, for example, is used as a power supply bypass capacitor in addition to the above-described capacitor of about 0.1 μF.

  These power bypass capacitors are connected between the power supply voltage VCC, which is the operation power supply of the semiconductor device supplied from the power supply circuit of the tester, and the reference potential VSS, and are applied to the power supply voltage VCC as described above. It is used for noise removal.

  However, the present inventors have found that the noise removal technique in the electrical characteristic test of the semiconductor device as described above has the following problems.

  In other words, when measuring a weak current such as a standby current of a semiconductor device in a tester, the current of the semiconductor device is measured after the electric charge is accumulated in the capacitor in order to separate the current flowing in the capacitor from the measurement current. It must be started, and a waiting time until the capacitor accumulates charge is required.

  Further, the tester is provided with a detection resistor used when measuring the current of the semiconductor device, and the current consumption of the semiconductor device is derived from the voltage generated by supplying the power supply voltage VCC through the detection resistor. Is detected.

  For this reason, the time constant of the RC circuit formed by the detection resistor and the capacitor is required, which causes a problem that a long measurement waiting time is generated and a test time for electrical characteristics is lengthened.

  Further, as a technique for reducing the waiting time during which charge is accumulated in the capacitor, a relay is provided between the power supply voltage VCC and the capacitor, and the capacitor is disconnected from the power supply voltage VCC when measuring a weak current such as a standby current. Things are known.

  However, in this case, a relay must be mounted on the test board, which not only increases the number of parts and increases the cost, but also increases the size of the test board.

  Furthermore, a program for turning on / off the relay must be created separately, which complicates the test program and increases the man-hours.

  An object of the present invention is to provide a technique capable of reducing the test time for electrical measurement of a semiconductor device at a low cost without impairing the effect of noise attenuation.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention relates to a semiconductor test apparatus for testing electrical characteristics of a semiconductor device, and a device serving as an interface for transmitting a test signal input / output from the semiconductor test apparatus to a plurality of semiconductor devices serving as devices to be mounted. The semiconductor test apparatus includes a first power supply circuit that generates a first power supply voltage that is an operating voltage of the semiconductor device, and a first power supply circuit that generates the first power supply circuit. And a second power supply circuit for generating a second power supply voltage having a voltage level substantially the same as the power supply voltage of the device, and the device interface board is connected between the first power supply voltage and the reference potential, A first capacitance element that attenuates noise applied to the power supply voltage, and a capacitance value larger than the first capacitance element, and attenuates noise applied to the first power supply voltage That the second and a capacitive element, the second capacitive element is intended to be connected between a first power supply voltage and a second power supply voltage.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) The measurement waiting time when performing electrical measurement of a semiconductor device can be greatly shortened without impairing the effect of noise attenuation.

  (2) According to the above (1), the electrical measurement test of the semiconductor device can be efficiently performed, and the productivity of the semiconductor device can be improved.

  (3) Moreover, since components such as a relay mounted on the test board are not required, the cost and size of the test system can be reduced.

It is explanatory drawing which shows an example of the test system by one embodiment of this invention. It is explanatory drawing which shows an example of the power supply circuit provided in the test system of FIG. It is explanatory drawing which showed an example of the current waveform at the time of capacitor | condenser charge by the test system which this inventor examined. It is explanatory drawing which showed an example of the current waveform at the time of capacitor | condenser charge in the test system of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is an explanatory diagram showing an example of a test system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a power supply circuit provided in the test system of FIG. 1, and FIG. FIG. 4 is an explanatory diagram showing an example of a current waveform at the time of capacitor charging in the test system of FIG. 1.

<Summary of invention>
A first outline of the present invention is a semiconductor test apparatus (semiconductor tester 2) for testing electrical characteristics of a semiconductor device (semiconductor device DUT) and a test signal that is input / output from the semiconductor test apparatus. It comprises a test system (test system 1) comprising a device interface board (test board 3) serving as an interface for transmission to a plurality of semiconductor devices serving as measurement devices.

  The semiconductor test apparatus generates a first power supply circuit (D / A converter 9, operational amplifier 10) that generates a first power supply voltage that is an operating voltage of the semiconductor device, and the first power supply circuit. And a second power supply circuit (op-amp 11) that generates a second power supply voltage that is substantially the same voltage level as the first power supply voltage.

  Further, the device interface board is connected between the first power supply voltage and a reference potential, and a first capacitance element (capacitor 6) that attenuates noise applied to the first power supply voltage; A second capacitance element (capacitor 5) having a larger capacitance value than the first capacitance element and attenuating noise applied to the first power supply voltage; The second capacitance element is configured to be connected between the first power supply voltage and the second power supply voltage.

  Hereinafter, the embodiment will be described in detail based on the above-described outline.

  In the first embodiment, the test system 1 includes a semiconductor tester 2 and a test board 3 as shown in FIG. The test system 1 is a system that performs, for example, a final test for testing electrical characteristics of a semiconductor device DUT that is a device under test.

  The semiconductor tester 2 executes a final test of the semiconductor device DUT based on a test program output from an externally connected personal computer or the like. The semiconductor tester 2 includes a power supply circuit 4.

  The power supply circuit 4 is a circuit that generates power supply voltages VCC and VCC1, respectively. The power supply voltage VCC is output from the output unit OUT1, and the power supply voltage VCC is output from the output unit OUT2.

  The power supply voltage VCC output from the output unit OUT1 is a power supply supplied to the semiconductor device DUT as an operation power supply, and the power supply voltage VCC1 output from the output unit OUT2 is a power supply supplied to the capacitor 5 described later. Here, the power supply voltage VCC and the power supply voltage VCC1 are substantially the same voltage level.

  The test board 3 is connected to the semiconductor tester 2. A plurality of IC sockets (not shown) are mounted on the test board 3. Each of these IC sockets is equipped with a semiconductor device DUT.

  The test board 3 is an interface board that transmits a test signal input / output to / from the semiconductor tester 2 to the semiconductor device DUT. The test board 3 is equipped with capacitors 5 and 6 for removing noise of the power supply voltage VCC output from the semiconductor tester 2.

  The output part OUT1 of the power supply circuit 4 is connected to the power supply terminal of the semiconductor device DUT via the power supply line 7 which is a wiring pattern formed on the test board 3, and is output from the power supply circuit 4 as described above. A power supply voltage VCC is supplied as an operating power supply for the semiconductor device DUT.

  One connection portion of the capacitor 5 and one connection portion of the capacitor 6 are connected to the power line 7. A reference potential VSS is connected to the other connection portion of the capacitor 6.

  The output part OUT2 of the power supply circuit 4 is connected to the other connection part of the capacitor 5 through a power supply line 8 which is a wiring pattern formed on the test board 3. Therefore, the power supply voltage VCC1 generated by the power supply circuit 4 is supplied to the other connection portion of the capacitor 5.

  Capacitor 5 is made of an electrolytic capacitor or the like, and has a capacitance value of about 470 μF, for example, and removes noise in a low frequency band and stabilizes power supply voltage VCC.

  In FIG. 1, the capacitor 5 is an electrolytic capacitor. However, the capacitor 5 may be other than an electrolytic capacitor such as a film capacitor or a multilayer ceramic capacitor. The capacitor 6 has a capacitance value of about 0.1 μF, for example, and removes noise in a frequency band higher than that of the capacitor 5.

  FIG. 2 is an explanatory diagram illustrating an example of the power supply circuit 4.

  The power supply circuit 4 is composed of a D / A converter 9 and operational amplifiers 10 and 11 as shown in the figure.

  The D / A converter 9 converts a digital signal output from a personal computer connected to the semiconductor tester 2 into an analog signal. The digital signal input to the D / A converter 9 is a signal for setting the voltage level of the power supply voltage VCC supplied to the semiconductor device DUT.

  The D / A converter 9 is connected to the operational amplifiers 10 and 11. The positive (+) side input sections of the operational amplifiers 10 and 11 are connected so that analog signals (voltages) output from the D / A converter 9 are respectively input.

  Further, the negative (−) side input part of the operational amplifier 10 is connected to the output part of the operational amplifier 10, and the negative (−) side input part of the operational amplifier 11 is connected to the output part of the operational amplifier 11. Yes.

  These operational amplifiers 10 and 11 are used as buffer amplifiers (non-inverting amplifier circuits), and impedance-convert analog signals output from the D / A converter 9 and output them.

  Next, the operation of the power supply circuit 4 in the present embodiment will be described.

  First, when the electrical measurement of the semiconductor device DUT is started, a digital signal for setting the voltage level of the power supply voltage VCC is input to the power supply circuit 4. The D / A converter 9 converts the input digital signal into an analog signal and outputs the analog signal to the operational amplifiers 10 and 11, respectively.

  The operational amplifiers 10 and 11 impedance-convert input analog signals and output power supply voltages VCC and VCC1 at desired voltage levels, respectively. Since the same analog signal output from the D / A converter 9 is input to the operational amplifiers 10 and 11, respectively, the power supply voltages VCC and VCC1 having substantially the same voltage level are output at substantially the same timing.

  As described above, the voltage output from the output unit of the operational amplifier 10 is supplied to the semiconductor device DUT as the power supply voltage VCC and also supplied to one of the connection parts of the capacitors 5 and 6. The voltage output from the output section of the operational amplifier 11 is supplied to the other connection section of the capacitor 5 as the power supply voltage VCC1.

  Here, since the power supply voltages VCC and VCC1 of substantially the same voltage level are supplied to both connection portions of the capacitor 5 having a large capacitance value, the capacitor 5 has a so-called AC coupling configuration.

  Since the power supply voltages VCC and VCC1 are supplied to both connection portions of the capacitor 5 at substantially the same timing, the potential difference of the capacitor 5 becomes substantially zero and charging / discharging is eliminated. As a result, noise applied to the power supply voltage VCC can be removed while canceling the charging time in the capacitor 5.

  Further, in the test board 3, the power supply lines 7 and 8 are respectively formed in a solid wiring layer that is wired almost on the entire surface of the test board 3, and the impedance is lowered with respect to the ground (VSS to the reference output). AC coupling.

  FIG. 3 is an explanatory diagram showing an example of a current waveform at the time of capacitor charging by the test system examined by the present inventor, and FIG. 4 shows an example of a current waveform at the time of capacitor charging in the test system 1 of FIG. FIG.

  A general test system has a configuration in which a noise removing capacitor is connected between a power supply voltage VCC and a reference potential VSS.

  When the capacitor 5 of about 470 μF is connected between the power supply voltage VCC and the reference potential VSS without AC coupling, when the power supply voltage is supplied from the power supply circuit to the semiconductor device, the capacitor 5 is connected as shown in FIG. Charging time T1 is required.

  If the standby current of the semiconductor device or the like is measured during this time T1, it is not possible to know whether the measured value is a standby current measurement value or a current value obtained by charging a capacitor, and an accurate current value cannot be measured. .

  Therefore, the current consumption of the semiconductor device cannot be measured until the period of time T1 has passed, and the time T1 becomes a useless time as a measurement waiting time as it is.

  On the other hand, when the capacitor 5 shown in FIG. 1 has an AC coupling configuration, as shown in FIG. 4, it is only the time T2 for charging the capacitor 6 of about 0.1 μF, and the period of the time T1 shown in FIG. Compared to, measurement waiting time can be greatly reduced.

  As a result, according to the present embodiment, the time until the capacitor 5 accumulates electric charge (charging time) becomes unnecessary, so that the measurement waiting time can be shortened and the test efficiency of the semiconductor device DUT is greatly improved. Can be made.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, the power supply circuit 4 (FIG. 2) is configured such that the analog signal output from the D / A converter 9 is input to the operational amplifiers 10 and 11, respectively. The power supply voltage VCC may be input to the operational amplifier 11.

  In this case, the output section of the operational amplifier 10 is connected to the positive (+) side input section of the operational amplifier 11, and other connection configurations are the same as those in FIG.

  The present invention is suitable for a technique for shortening a measurement waiting time in an electrical characteristic test of a semiconductor device.

DESCRIPTION OF SYMBOLS 1 Test system 2 Semiconductor tester 3 Test board 4 Power supply circuit 5 Capacitor 6 Capacitor 7 Power supply line 8 Power supply line 9 D / A converter 10 Operational amplifier 11 Operational amplifier DUT Semiconductor device

Claims (1)

A semiconductor test apparatus for testing electrical characteristics of the semiconductor device; and a device interface board serving as an interface for transmitting a test signal input / output from the semiconductor test apparatus to the plurality of semiconductor devices serving as mounted devices to be measured; A test system comprising:
The semiconductor test apparatus includes:
A first power supply circuit that generates a first power supply voltage to be an operating voltage of the semiconductor device;
A second power supply circuit that generates a second power supply voltage that is substantially the same voltage level as the first power supply voltage generated by the first power supply circuit;
The device interface board is:
A first capacitance element that is connected between the first power supply voltage and a reference potential and attenuates noise applied to the first power supply voltage;
A second capacitance element having a larger capacitance value than the first capacitance element and attenuating noise applied to the first power supply voltage;
The second capacitance element is:
The test system is connected between the first power supply voltage and the second power supply voltage.

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