JP2012227642A - A/d converter and method of correcting the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter that outputs a high accuracy A/D conversion result excluding outliers such as noise.SOLUTION: The A/D converter includes a majority circuit M4 for correcting A/D conversion results by bit-specific majority in an odd number of sampling cycles. The majority circuit M4 includes first determination circuits M11, M13, first correction circuits M15, M17, second determination circuits M12, M14 and second correction circuits M16, M18. The first determination circuits determine that a carry is about to take place and there is a carry if the occurrence frequency of an A/D conversion result "1" in the bit-specific sampling matches a first criterion value. The first correction circuits correct A/D conversion results of the bits lower than the determined bit to "0". The second determination circuits determine that a carry is about to take place and there is no carry if the occurrence frequency of the A/D conversion result "1" in the bit-specific sampling matches a second criterion value. The second correction circuits correct A/D conversion results of the bits lower than the determined bit to "1".

Description

  The present invention relates to an A / D converter, and more particularly to an A / D converter having a circuit for correcting a conversion result and a correction method thereof.

  In recent years, with the expansion of the healthcare market and the security market, attention has been focused on sensing technology. The sensing performance depends on the function of recognizing the state and converting it into an electrical signal and the digital signal processing performance on the signal. Therefore, a technique for further increasing the resolution and accuracy of an A / D (Analog / Digital) converter, which is the basic component, is desired.

  On the other hand, it is known that the miniaturization of the manufacturing process increases the characteristic variation and noise sensitivity for an analog circuit and decreases the accuracy. On the other hand, a technique for realizing high accuracy using a correction technique such as statistical processing is required. As such a technique, Japanese Unexamined Patent Application Publication No. 2008-042380 (Patent Document 1) discloses an analog / digital converter technique.

  This analog / digital converter performs A / D conversion by dividing the upper bit and the lower bit, and corrects the A / D conversion result of the lower bit constituted by the parallel A / D converter. Thereby, even when noise occurs inside the A / D converter, A / D conversion can be performed without losing accuracy. In the correction of the A / D conversion result of the lower bits, the majority circuit reads the output of the parallel A / D converter a predetermined number of times, performs majority for each bit, and determines the bit output to be “0” or “1”. To the conversion result storage register.

FIG. 1 is a block diagram illustrating a configuration of an A / D converter disclosed in Patent Document 1. As illustrated in FIG.
The A / D converter 100 divides the analog input signal S001 into upper bits and lower bits and performs A / D conversion. The control circuit 101, the D / A converter 102, the switched comparator 103, the successive approximation register 104, and the D / A converter 105 constitute an upper bit A / D converter that outputs the upper bit portion of the analog input signal S001. . A parallel A / D converter 106 is provided for the lower bits of the analog input signal S001. The majority circuit 107 samples the output of the parallel A / D converter 106 (A / D conversion result) a plurality of times, and determines and outputs the value of each bit in the lower bits by majority.

FIG. 2 is a block diagram showing the configuration of the majority circuit of Patent Document 1. In FIG.
The majority circuit 103 includes three sets of single-bit majority circuits 1010-1 to 1010-3 when correcting up to 3 bits. The first bit from the lower order of the digital signal S011 is input to the single-bit majority circuit 1010-1, the second bit is input to the single-bit majority circuit 1010-2, and the third bit is input to the single-bit majority circuit 1010-3. Entered.

  The adder circuit 1011 adds the value (1 bit) of the digital signal S011 and the value stored in the 8-bit register 1012 at the rising change timing of the clock signal S012, and stores the result in the 8-bit register 1012. . The 8-bit register 1012 is an 8-bit register that operates in synchronization with the clock signal S012. The bit selection circuit 1013 stores the third bit data of the 8-bit register 1012 in the flip-flop 1014 at the rising change timing of the clock signal S005. The flip-flop 1014 holds the output of the bit selection circuit 1013 at the rising change timing of the clock signal S005. The ratio of the frequencies of the clock signals S012 and S005 is set so that the output of the flip-flop 1014 is held after the addition circuit 1011 has added seven times. That is, according to this frequency setting, each single-bit majority circuit 1010 outputs “1” when four or more of seven readings (sampling) are “1”.

  In each single-bit majority circuit 1010, the adder circuit 1011 and the flip-flop 1014 both receive the clock signal via the switch circuit 3200 controlled by the control signal S014. Therefore, when the control signal S014 is “00”, the clock signals S012 and S005 are supplied to the single-bit majority circuit 1010-1, and the single-bit majority circuits 1010-2 and 1010-3 operate. S005 is not supplied and does not operate. When the control signal S014 is “01”, the single-bit majority circuits 1010-1 and 1010-2 are supplied with the clock signals S012 and S005, but the single-bit majority circuit 1010-3 is operated with the clock signal S012. S005 is not supplied and does not operate. When the control signal S014 is “11”, the single-bit majority circuits 1010-1, 1010-2, and 1010-3 are supplied with clock signals S012 and S005 to operate. As described above, the bit length of the lower bits for majority decision can be changed to an arbitrary number of bits.

  As a related technique, Japanese Patent Laid-Open No. 03-016432 (Patent Document 2) discloses an analog-digital converter. This analog-to-digital converter is provided with a circuit for performing a majority operation on the outputs of the three adjacent comparators after the plurality of comparators having analog inputs connected in common.

JP 2008-042380 A Japanese Patent Laid-Open No. 03-016432

  The inventor's research has revealed for the first time that the technique of Patent Document 1 has the following problems. Consider a case where the sampled A / D conversion result is, for example, 3 bits. In this case, when an abnormal A / D conversion result due to noise or the like occurs for an analog input near a carry where “011” and “100” occur at the same frequency, it is normal by majority vote. The correction output result cannot be output.

  FIG. 3 is a table showing an example of the relationship between the A / D conversion result of Patent Document 1 and the output of the majority circuit. Specifically, this figure shows the respective A / D conversion results and the output values (correction) of the majority circuit when the lower three bits are read seven times (sampling; first to seventh times). Four examples (Examples 1 to 4) are shown in relation to the output results. Example 1 is an A / D conversion result in a state in which no carry has occurred in the lower 3 bits. Examples 2 to 3 are conversion results in a state where a carry has occurred in the most significant bit in the lower 3 bits. Example 4 shows a conversion result in a state where a carry is generated in the lower 2 bits in the lower 3 bits. At this time, the correction output result is majority voted for each bit, and “1” is output when “4” or more is “1”, and “0” is output when it is three or less. In each of the A / D conversion results of Examples 1 to 4, it is assumed that an abnormal value (a value surrounded by a round dotted line) occurs as an example.

  As in Example 1, even if an abnormal value “000” such as noise occurs in the fourth reading, if all the remaining conversion results are “011”, the result of the majority circuit becomes “011” and the abnormal value Can be removed. However, as in Example 2, when “011” and “100” are read three times before the sixth reading, the number of occurrences of “1” for each bit is three times, so that Regardless of the value, a majority decision is made at the seventh value, and the majority decision result is output. In other words, in the case of Example 2, an abnormal value of the seventh read value “000” is output as the majority result. Similarly, in Example 3, “011” and “100” are read three times at the first, second, and fourth to seventh times, and the third abnormal value “111” is output as the majority result. The state in which “011” and “100” occur at the same frequency as shown in Example 2 and Example 3 frequently occurs in the state in which the carry of the most significant bit of the lower 3 bits occurs.

  The same applies to the carry other than the most significant bit of the lower 3 bits for majority decision. As in Example 4, when “101” and “110” in which the carry is generated in the lower 2 bits each occur 3 times, the number of occurrences of “1” in the lower 2 bits and the least significant bit is 3 respectively. The remaining read value becomes the majority result. That is, since the lower 2 bits of the abnormal value “000” generated at the sixth time is “00”, “100” is output as the majority result.

  As described above, since the technique of Patent Document 1 has a circuit configuration in which a majority decision is made independently for each bit, “1” and “0” as in Examples 2 to 4 are comparable in sampling for majority decision. Abnormal values such as noise cannot be removed from analog inputs near carry that occur frequently.

  Hereinafter, means for solving the problem will be described using the numbers and symbols used in the embodiments for carrying out the invention. These numbers and symbols are added with parentheses in order to clarify the correspondence between the description of the claims and the mode for carrying out the invention. However, these numbers and symbols should not be used for interpreting the technical scope of the invention described in the claims.

  Therefore, the A / D converter of the present invention corrects the A / D conversion result based on the majority vote performed for each bit by sampling at least an odd number of 5 times or more. The A / D converter includes a majority circuit (M4) that determines a value for each bit based on a result of majority vote for each bit of the A / D conversion result. The majority circuit (M4) includes a first determination circuit (M11, M13), a first correction circuit (M15, M17), a second determination circuit (M12, M14), and a second correction circuit (M16, M18). And. In the first determination circuit (M11, M13), for every bit except the least significant bit, the number of occurrences of “1” of the A / D conversion result by sampling coincides with a predetermined first determination value set in advance. In this case, it is determined that it is near the carry and carry. The first correction circuit (M15, M17) corrects the A / D conversion result in the lower bits from the bits that are near the carry and determined to carry, to “0”. In the second determination circuit (M12, M14), for every bit except the least significant bit, the number of occurrences of “1” of the A / D conversion result by sampling coincides with a predetermined second determination value set in advance. In this case, it is determined that the carry is in the vicinity of the carry and is not carried. The second correction circuit (M16, M18) corrects the A / D conversion result in the lower bits than the bit determined to be near the carry and not carry to “1”.

  The semiconductor device of the present invention includes an analog signal supply circuit and an A / D converter. The analog signal supply circuit outputs an analog signal. The A / D converter is described in the above paragraph and converts the analog signal into a digital signal.

  According to the A / D conversion result correction method of the present invention, the A / D conversion result is corrected based on a majority vote performed for each bit by sampling an odd number of times of at least five times. In this A / D conversion result correction method, for every bit except the least significant bit, the number of occurrences of “1” of the A / D conversion result by sampling coincides with a predetermined first determination value set in advance. In this case, the step of determining that the carry is in the vicinity of the carry and the carry is performed, and the A / D conversion result in the lower bit than the bit in the vicinity of the carry and the carry is determined is corrected to “0”. If the number of occurrences of “1” in the A / D conversion result by sampling matches the predetermined second determination value set in advance for every bit except the least significant bit, it is near the carry. And a step of determining that no carry has been performed, and a step of correcting an A / D conversion result in a lower bit than a bit determined to be near and not carried as “1”. .

  According to the present invention, an abnormal value such as noise can be removed from an analog input near a carry in an A / D converter. Thereby, a highly accurate A / D conversion result can be output.

FIG. 1 is a block diagram illustrating a configuration of an A / D converter disclosed in Patent Document 1. As illustrated in FIG. FIG. 2 is a block diagram showing the configuration of the majority circuit of Patent Document 1. In FIG. FIG. 3 is a table showing an example of the relationship between the A / D conversion result of Patent Document 1 and the output of the majority circuit. FIG. 4 is a block diagram showing the configuration of the A / D converter according to the embodiment of the present invention. FIG. 5 is a block diagram showing a majority circuit of the A / D converter according to the embodiment of the present invention. FIG. 6 is a table showing an example of the relationship between the A / D conversion result and the output of the majority circuit according to the present embodiment. FIG. 7 is a flowchart showing an operation method of the A / D converter M0 according to the embodiment of the present invention.

  Hereinafter, an A / D converter and a correction method thereof according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  The A / D converter according to the embodiment of the present invention corrects the conversion result by performing a majority decision for each bit by sampling at least an odd number of times of 5 or more. This A / D converter includes a majority circuit. The majority circuit includes a first determination circuit, a “0” correction circuit, a second determination circuit, and a “1” correction circuit. The first determination circuit is in the vicinity of a carry because the number of occurrences of “1” in the A / D conversion result by sampling matches [(sampling number + 1) / 2] for every bit except the least significant bit. And it is determined that “carrying”. The “0” correction circuit corrects the result of the majority circuit to “0” when the bit is near the carry and is lower than the bit determined to be “carrying”. In the second determination circuit, the number of occurrences of “1” in the A / D conversion result by sampling for every bit except the least significant bit is close to the carry because of the coincidence with [(sampling number−1) / 2]. And it is determined that “no carry”. The “1” correction circuit corrects the result of the majority circuit to “1” when the bit is near the carry and is lower than the bit determined as “not carrying”. As a result, this A / D converter is capable of generating noise even for an analog input near a carry in which at least “1” and “0” are generated at the same frequency in an odd number of samplings of at least 5 times. Thus, it is possible to correct the conversion result by majority vote without being affected by the above, and to output a highly accurate A / D conversion result. This will be specifically described below.

  A configuration of an A / D converter according to an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 4 is a block diagram showing the configuration of the A / D converter according to the embodiment of the present invention. The A / D converter M0 includes an upper bit A / D converter (successive comparison type A / D converter) M1, a reference voltage supply unit (reference voltage Vref), and a lower bit A / D converter (parallel type). A / D converter) M2, an analog input voltage supply unit (analog input signal N1), a lower bit reference voltage generation circuit M3, a majority circuit M4, and a conversion result storage register M5.

  The analog input voltage receiving unit (analog input signal N1) is an analog signal supply unit outside the A / D converter M1 (example: sensor circuit, other circuit of the semiconductor device including the A / D converter M1; An analog input signal N1 is received from (not shown) and output to the successive approximation A / D converter M1 and the parallel A / D converter M2. The reference voltage receiving unit (reference voltage Vref) is a reference voltage supply unit outside the A / D converter M1 (example: power circuit, other circuit of the semiconductor device including the A / D converter M1; And the reference voltage Vref is output to the successive approximation A / D converter M1.

  The successive approximation A / D converter (upper bit A / D converter) M1 A / D converts the upper bits of the analog input signal N1 based on the reference voltage Vref, and converts the A / D conversion result N2 into the conversion result. The data is output to the storage register M5 and the lower bit reference voltage generation circuit M3 for determining the lower bit reference voltage. For this, a conventionally known successive approximation A / D converter can be used.

  The lower bit reference voltage generation circuit M3 generates an upper limit reference voltage N3 and a lower limit reference voltage N4 of the lower bits based on the A / D conversion result N2, and outputs them to the parallel A / D converter M2.

  A parallel A / D converter (A / D converter for lower bits) M2 performs A / D conversion on the lower bits of the analog input signal N1 based on the upper limit reference voltage N3 and the lower limit reference voltage N4 of the lower bits. The / D conversion result N5 is output to the majority circuit M4. For this, a conventionally known parallel A / D converter can be used.

  The majority circuit M4 samples the A / D conversion result N5 output from the parallel A / D converter M2 a plurality of times, and determines and outputs the value of each bit by majority.

  The conversion result storage register M5 stores an A / D conversion result N2 of the successive approximation A / D converter M1 and a result N6 of the A / D conversion result N5 of the parallel A / D converter M2 corrected by the majority circuit M4. .

  FIG. 5 is a block diagram showing details of the majority circuit of the A / D converter according to the embodiment of the present invention shown in FIG. The majority circuit M4 includes three sets of single-bit majority circuits M6-1 to M6-3, a “0” correction circuit M15, a “1” correction circuit M16, a “0” correction circuit M17, and a “1” correction circuit. M18.

  The three sets of single-bit majority circuits M6-1 to M6-3 perform a majority decision on the lower 3 bits of the A / D conversion result N5 for each bit based on the clock signal N7 and the clock signal N14. The first bit from the lower order of the A / D conversion result N5 is input to the single-bit majority circuit M6-1, the second bit is input to the single-bit majority circuit M6-2, and the third bit is the single-bit majority circuit M6-3. Is input. The single-bit majority circuits M6-1 to M6-3 output the majority results N8-1 to N8-3, respectively. Further, the single bit majority circuit M6-3 outputs digital signals N9 and N10. The single bit majority circuit M6-2 outputs digital signals N11 and N12.

  The “0” correction circuit M15 performs a predetermined logical operation based on the digital signal N10 output from the single-bit majority circuit M6-3 and the majority result N8-2 output from the single-bit majority circuit M6-2. The calculation result is output to the “1” correction circuit M16.

  The “1” correction circuit M16 performs a predetermined logical operation on the basis of the digital signal N9 output from the single-bit majority circuit M6-3 and the signal output from the “0” correction circuit M15, The corrected output result N13-2 is output.

  The “0” correction circuit M17 includes the digital signal N10 output from the single bit majority circuit M6-3, the digital signal N12 output from the single bit majority circuit M6-2, and the majority vote output from the single bit majority circuit M6-1. Based on the result N8-1, a predetermined logical operation is performed, and the operation result is output to the “1” correction circuit M18.

  The “1” correction circuit M18 includes a digital signal N9 output from the single-bit majority circuit M6-3, a digital signal N11 output from the single-bit majority circuit M6-2, and a signal output from the “0” correction circuit M17. Based on the above, a predetermined logical operation is performed, and a corrected output result N13-1 as an operation result is output.

  The majority circuit M4 includes a majority result N8-3 output from the single-bit majority circuit M6-3, a correction output result N13-2 output from the “1” correction circuit M16, and a correction output from the “1” correction circuit M18. The output result N13-1 is output as a correction result N6 which is 3-bit output data. However, the majority decision result N8-3 is the majority decision result of the third bit from the lower order of the A / D conversion result, the correction output result N13-2 is the correction output result of the second bit from the lower order, and the correction output result N13-1 is the lower order. To the first bit correction output result.

  The single-bit majority circuit M6-1 includes an adder circuit M7-1, an 8-bit register M8-1, a bit selection circuit M9-1, and a flip-flop M10-1. The adder circuit M7-1 adds the first bit from the lower order of the A / D conversion result N5 and the feedback value of the 8-bit register M8-1 based on the clock signal N7. The 8-bit register M8-1 stores and outputs the output of the adder circuit M7-1 based on the clock signal N7. The bit selection circuit M9-1 outputs the third bit data for the 8-bit register M8-1. The flip-flop M10-1 outputs the output of the bit selection circuit M9-1 as the majority result signal N8-1 of the lower first bit based on the clock signal N14.

  The single bit majority circuit M6-2 includes an addition circuit M7-2, an 8-bit register M8-2, a bit selection circuit M9-2, a flip-flop M10-2, a determination circuit M13, and a determination circuit M14. ing. The adder circuit M7-2 adds the second bit from the lower order of the A / D conversion result N5 and the feedback value of the 8-bit register M8-2 based on the clock signal N7. The 8-bit register M8-2 stores and outputs the output of the adder circuit M7-2 based on the clock signal N7. The bit selection circuit M9-2 outputs the third bit data with respect to the output of the 8-bit register M8-2. The flip-flop M10-2 outputs the output of the bit selection circuit M9-2 as the majority result signal N8-2 of the lower second bit based on the clock signal N14. The determination circuit M13 executes a predetermined determination process based on the output of the 8-bit register M8-2 and outputs a determination result signal N12. The determination circuit M14 executes a predetermined determination process based on the output of the 8-bit register M8-2 and outputs a determination result signal N11.

  The single-bit majority circuit M6-3 includes an addition circuit M7-3, an 8-bit register M8-3, a bit selection circuit M9-3, a flip-flop M10-3, a determination circuit M11, and a determination circuit M12. ing. Based on the clock signal N7, the adder circuit M7-3 adds the third bit from the lower order of the A / D conversion result N5 and the feedback value of the 8-bit register M8-3. The 8-bit register M8-3 stores and outputs the output of the adder circuit M7-3 based on the clock signal N7. The bit selection circuit M9-3 outputs the third bit data with respect to the output of the 8-bit register M8-3. Based on the clock signal N14, the flip-flop M10-3 outputs the output of the bit selection circuit M9-3 as the majority result signal N8-3 of the lower third bit. The determination circuit M11 executes a predetermined determination process based on the output of the 8-bit register M8-3, and outputs a determination result signal N10. The determination circuit M12 executes a predetermined determination process based on the output of the 8-bit register M8-3, and outputs a determination result signal N9.

The operation of each component shown in FIG. 5 will be described below.
First, the operation of the single bit majority circuit M6-1 will be described. The adder circuit M7-1 adds the value of the input digital signal N5 and the feedback value of the 8-bit register M8-1 for each bit at the rising change timing of the clock signal N7, and outputs the result to the 8-bit register M8-. 1 is stored. The 8-bit register M8-1 stores the output data of the adder circuit M7-1 in synchronization with the clock signal N7, and outputs the result to the bit selection circuit M9-1. The bit selection circuit M9-1 stores the third bit data of the output data of the 8-bit register M8-1 in the flip-flop M10-1 at the rising change timing of the clock signal N14. The flip-flop M10-1 holds the output of the bit selection circuit M9-1 at the rising change timing of the clock signal N14, and outputs the majority decision result signal N8-1 as the output of the single-bit majority decision circuit M6-1.

  Next, the operation of the single bit majority circuit M6-2 will be described. The adder circuit M7-2 adds the value of the input digital signal N5 and the feedback value of the 8-bit register M8-2 bit by bit at the rising change timing of the clock signal N7, and the result is the 8-bit register M8-. 2 is stored. The 8-bit register M8-2 stores the output data of the adder circuit M7-2 in synchronization with the clock signal N7, outputs the result to the bit selection circuit M9-2, and further outputs them to the determination circuits M13 and M14. The bit selection circuit M9-2 stores the third bit data of the output data of the 8-bit register M8-2 in the flip-flop M10-2 at the rising change timing of the clock signal N14. The flip-flop M10-2 holds the output of the bit selection circuit M9-2 at the rising change timing of the clock signal N14, and outputs the majority result signal N8-2 as the output of the single-bit majority circuit M6-2. The determination circuit M13 sets [(sampling count + 1) / 2] as a determination value in advance. If the output data of the 8-bit register M8-2 matches the determination value, “1” is output, and if they do not match, “0” is output. Similar to the determination circuit M12, the determination circuit M14 sets [(sampling count−1) / 2] as a determination value in advance. If the output data of the 8-bit register M8-2 matches the determination value, “1” is output, and if they do not match, “0” is output.

  Next, the operation of the single bit majority circuit M6-3 will be described. The adder M7-3 adds the value of the input digital signal N5 and the feedback value of the 8-bit register M8-3 for each bit at the rising change timing of the clock signal N7, and the result is the 8-bit register M8-. 3 is stored. The 8-bit register M8-3 stores the output data of the adder circuit M7-3 in synchronization with the clock signal N7, outputs the result to the bit selection circuit M9-3, and outputs the result to the determination circuits M11 and M12, respectively. . The bit selection circuit M9-3 stores the third bit data of the output data of the 8-bit register M8-3 in the flip-flop M10-3 at the rising change timing of the clock signal N14. The flip-flop M10-3 holds the output of the bit selection circuit M9-3 at the rising change timing of the clock signal N14, and outputs the majority result signal N8-3 as the output of the single bit majority circuit M6-3. The determination circuit M11 sets [(sampling count + 1) / 2] as a determination value in advance. If the output data of the 8-bit register M8-3 matches the determination value, “1” is output, and if they do not match, “0” is output. The determination circuit M12 sets [(sampling count−1) / 2] as a determination value in advance. If the output data of the 8-bit register M8-3 matches the determination value, “1” is output, and if they do not match, “0” is output.

  Note that the determination value [(sampling number + 1) / 2] is not limited to this example, and a predetermined width (number of times) from [(sampling number + 1) / 2] (times) to the upper bit side. It may be a value that it has. For example, [(sampling count + 1) / 2] (times) to [(sampling count + 1) / 2] +1 (times). This additional amount can be determined corresponding to the number of samplings. For example, the increase amount is increased as the number of samplings is increased. Similarly, the determination value [(sampling count-1) / 2] is not limited to this example, and a predetermined width ([sampling count-1) / 2] (times) from the ((sampling count-1) / 2) to the lower bit side. (Number of times). For example, [(sampling count-1) / 2] (times) to [(sampling count-1) / 2] -1 (times). This additional amount can be determined corresponding to the number of samplings. For example, the amount of decrease is increased as the number of samplings is increased.

  Next, the operation of the “0” correction circuit M15 will be described. The “0” correction circuit M15 is composed of, for example, a two-input AND circuit, and receives the inverted value of the determination result signal N10 output from the determination circuit M11 and the majority result N8-2 of the single-bit majority circuit M6-2. When the determination result signal N10 is “1”, “0” is output to the “1” correction circuit M16 regardless of the value of the majority result N8-2. On the other hand, when the determination result signal N10 is “0”, the value of the majority result N8-2 is output to the “1” correction circuit M16 as it is.

  Next, the operation of the “1” correction circuit M16 will be described. The “1” correction circuit M16 is composed of, for example, a two-input OR circuit, and receives the determination result signal N9 output from the determination circuit M12 and the output data of the “0” correction circuit M15. The determination result signal N9 is “1”. In the case of "," the correction result output N13-2 is corrected to "1" and output regardless of the output data of the "0" correction circuit M15. On the other hand, when the determination result signal N9 is “0”, the output data of the “0” correction circuit M15 is output as it is as the correction result output N13-2.

  Next, the operation of the “0” correction circuit M17 will be described. The “0” correction circuit M17 is formed of, for example, a three-input AND circuit, and an inverted value of the determination result signal N10 output from the determination circuit M11, an inverted value of the determination result signal N12 output from the determination circuit M13, and a single value. When the majority result N8-1 of the bit majority circuit M6-1 is input and one or both of the determination result signal N10 and the determination result signal N12 are “1”, “0” regardless of the value of the majority result N8-1. "1" is output to the "1" correction circuit M18. On the other hand, when both the determination result signal N10 and the determination result signal N12 are “0”, the value of the majority decision result N8-1 is directly output to the “1” correction circuit M18.

  Next, the operation of the “1” correction circuit M18 will be described. The “1” correction circuit M18 includes, for example, a three-input OR circuit, the determination result signal N9 output from the determination circuit M12, the determination result signal N11 output from the determination circuit M14, and the “0” correction circuit M17. When output data is input and one or both of the determination result signal N9 and the determination result signal N11 are “1”, the correction result output N13-1 is set to “1” regardless of the output data of the “0” correction circuit M17. Correct to "" and output. On the other hand, when both the determination result signal N9 and the determination result signal N11 are “0”, the output data of the “0” correction circuit M17 is output as it is to the correction result output N13-1.

  Next, the operation for outputting the correction result output N6 in the majority circuit M4 (FIG. 5) according to the present embodiment will be described. FIG. 6 is a table showing an example of the relationship between the A / D conversion result and the output of the majority circuit according to the present embodiment. Specifically, this figure shows each A / D conversion result when the majority circuit M4 reads the lower 3 bits seven times (sampling; first to seventh times) and the majority circuit. Four examples (Example 1 to Example 4) are shown for the relationship with the output value (corrected output result). Example 1 is an A / D conversion result in a state in which no carry has occurred in the lower 3 bits. Examples 2 to 3 are conversion results in a state where a carry has occurred in the most significant bit in the lower 3 bits. Example 4 shows a conversion result in a state where a carry is generated in the lower 2 bits in the lower 3 bits. In each of the A / D conversion results of Examples 1 to 4, it is assumed that an abnormal value (a value surrounded by a round dotted line) occurs as an example. For the sake of convenience, the same number of bits, the number of sampling times, and the sampling value are used as in the description of Patent Document 1 in FIG.

  When the number of times of sampling is 7, the determination circuits M11 and M13 constituting the majority circuit M4 in FIG. 5 have [(sampling number + 1) to determine that they are near the carry and “carry”. / 2] is set to 4 times, and the determination circuits M12 and M14 are set to [(sampling count−1) / 2] in order to determine that the carry is in the vicinity of the carry and “no carry”. Set 3 times.

  If an abnormal value “000” such as noise occurs in the fourth reading as in Example 1, if all the remaining conversion results are “011”, the number of occurrences of “1” in the third bit from the lower order is 0. The number of occurrences of “1” in the 2nd to 1st bits is 6 times. Therefore, the set value “4 times” of the determination circuits M11 and M13 and the number of occurrences of “1” in the third and second bits do not match, and the set value “three times” of the determination circuits M12 and M14 and the third and second bits. The number of occurrences of “1” does not match. That is, there is no matching bit, and the digital signals N9 to N12 that are the outputs of the determination circuits M11 to M14 are all “0”. As a result, the correction by the “0” correction circuits M15 and M17 and the “1” correction circuits M16 and M18 is not performed. Therefore, the majority circuit M4 outputs “011” as a digital signal N6 as a result of the majority circuit as in the case of Patent Document 1.

  As in Example 2, when “011” and “100” appear three times each in the first to sixth samplings, and “000” due to noise or the like appears as the seventh A / D conversion result, all bits “ 1 "appears 3 times. At this time, the majority circuit M4 outputs “0” as the majority result in the third bit from the lower order as it is as the digital signal N8-3. On the other hand, the number of occurrences of “1” of all bits is 3, and the set values “3 times” of the determination circuits M12 and M14 coincide with each other, so that the digital signals N9 and N11 are “1”. Further, since the set values “4 times” of the determination circuits M11 and M13 do not match, the digital signals N10 and N12 are “0”. Therefore, the “0” correction circuit M15 outputs the input data “0” of the digital signal N8-2 as the majority decision result of the second bit from the lower order as it is. The “1” correction circuit M16 corrects it to “1” and outputs it as a digital signal N13-2. Similarly, the “0” correction circuit M17 outputs the input data “0” of the digital signal N8-1 that is the majority result of the first bit from the lower order. The “1” correction circuit M18 corrects it to “1” and outputs it as a digital signal N13-1.

  That is, in the case of Example 2, in this embodiment, the majority circuit M4 outputs, as its output result, the digital signal N8-3 which is the majority result of the third bit from the lower order and the digital result which is the correction result output of the second bit from the lower order. The signal “N13-2” and the value “011” of the digital signal N13-1 which is the correction result output of the first bit from the lower order are output as the correction result N6.

  In Example 3, “011” and “100” appear three times each in the first, second, and fourth to seventh samplings, and “111” due to noise or the like appears as the third A / D conversion result. The number of occurrences of “1” of the bit is 4. At this time, the majority circuit M4 outputs “1” as the majority result in the third bit from the lower order as it is as the digital signal N8-3. On the other hand, the number of occurrences of “1” of all bits is 4, and the set values “3 times” of the determination circuits M12 and M14 do not match, so the digital signals N9 and N11 are “0”. Since the set values “4 times” of the determination circuits M11 and M13 coincide, the digital signals N10 and N12 are “1”. Therefore, the “0” correction circuit M15 outputs “0” obtained by correcting the digital signal N8-2, which is the majority result of the second bit from the lower order. The “1” correction circuit M16 outputs “0” corrected by the “0” correction circuit M15 as it is as the digital signal N13-2. Similarly, the “0” correction circuit M17 outputs “0” obtained by correcting the digital signal N8-1, which is the majority result of the first bit from the lower order, and the “1” correction circuit M18 is output by the “0” correction circuit M17. The corrected “0” is output as it is as the digital signal N13-1.

  That is, in the case of Example 3, in the present embodiment, the majority circuit M4 outputs, as its output result, the digital signal N8-3 that is the majority result of the third bit from the lower order and the digital result that is the correction result output of the second bit from the lower order. The signal N13-2 and the value “100” of the digital signal N13-1 which is the correction result output of the first bit from the lower order are output as the correction result N6.

In Example 4, “101” and “110” appear three times each in the first to fifth and seventh samplings, and “000” due to noise or the like appears as the sixth A / D conversion result. The number of occurrences of “1” in the second bit is three. At this time, the majority circuit M4 outputs “1” as the majority result as the digital signal N8-3 for the third bit from the lower order. On the other hand, since the set value “3 times” of the determination circuit M12 does not match, the digital signal N9 becomes “0”. Further, since the set value “3 times” of the determination circuit M14 coincides, the digital signal N11 becomes “1”. Further, since the set values “4 times” of the determination circuits M11 and M13 do not match, the digital signals N10 and N12 are “0”. Therefore, the “0” correction circuit M15 outputs “0”, which is the majority decision result of the second bit from the lower order, as the digital signal N8-2. The “1” correction circuit M16 outputs “0” as input data as it is as a digital signal N13-2. However, the “0” correction circuit M17 outputs the input data “0” of the digital signal N8-1, which is the majority result of the first bit from the lower order, but the “1” correction circuit M18 corrects it to “1”. And output as a digital signal N13-1.

  That is, in the case of Example 4, in this embodiment, the majority circuit M4 outputs the digital signal N8-3 that is the majority result of the third bit from the lower order and the digital result that is the output of the majority result of the second bit from the lower order. The signal “N13-2” and the value “101” of the digital signal N13-1 which is the correction result output of the first bit from the lower order are output as the correction result N6.

As described above, in the present embodiment, when the number of samplings is set to 7, the determination circuits M11 and M13 have four times as determination values for determining that they are near the carry and “carry”. In the determination circuits M12 and M14, three times are set as determination values for determining that “no carry” in the vicinity of the carry. Then, the following correction is performed according to the number of occurrences of “1” for each bit.
(A) Number of occurrences of “1”: 0 to 2 “0” is output as it is to the digital signal N6 as a result of the majority circuit.
(B) Number of times “1” appears: 3 times (determination values (setting values) of the determination circuits M12 and M14)
As a result of the majority circuit, “0” is output to the digital signal N6, but all bits lower than the bit that coincides with the third time are corrected to “1” and output to the digital signal N6.
(C) “1” appearance count: 4 times (determination values (setting values) of the determination circuits M11 and M13)
As a result of the majority circuit, “1” is output to the digital signal N6, but all bits lower than the bit that coincides with the fourth time are corrected to “0” and output to the digital signal N6.
(D) “1” appearance frequency: 5-7 times “1” is output as it is to the digital signal N6 as a result of the majority circuit.

  Even when the number of times of sampling is changed, the set number of times of the determination circuits M11 and M13 is set to [(sampling number + 1) / 2] in order to determine that the carry is in the vicinity of the carry and “carries”. The set number of times of the circuits M12 and M14 is set to [(sampling number-1) / 2] in order to determine that the carry is in the vicinity of the carry and “no carry”. Accordingly, in the same manner as in the above (a) to (d), when an abnormal value of the A / D conversion result occurs in the vicinity of the carry occurrence, the correct conversion result can be output from the digital signal N6.

  Next, an operation method (correction method) of the A / D converter M0 according to the embodiment of the present invention will be described. FIG. 7 is a flowchart showing an operation method of the A / D converter M0 according to the embodiment of the present invention.

(1) In step S1, the user sets various registers before starting A / D conversion, and the number of times of sampling “X” for performing the majority decision of the lower bits and “carrying up” is near the carry. [(Sampling count “X + 1) / 2] as a setting value“ Y ”for determination as“ ”and“ (Sampling) as a setting value “Z” for determination as “no carry” near the carry. The number of times “X” −1) / 2] is set.
(2) In step S2, the successive approximation A / D converter M1 starts A / D conversion of the analog input signal N1.
(3) In step S3, the successive approximation A / D converter M1 converts the analog input value into a digital value bit by bit in order from the most significant bit.
(4) In step S4, the successive approximation A / D converter M1 determines whether the conversion to the digital value has been completed up to the least significant bit in the upper bits. If not completed, branch to NO and repeat step S3 up to the least significant bit. After completing the conversion to the digital value up to the least significant bit, the successive approximation A / D converter M1 stores the A / D conversion result N2 of the upper bit in the conversion result register. And it branches to YES and transfers to step S5. For example, if the upper 7 bits and the lower 3 bits are set by 10-bit A / D conversion, step S3 is repeated until the digital value conversion for the upper 7 bits is completed.
(5) In step S5, the parallel A / D converter M2 converts the analog input value into a digital value by the all-bit parallel processing for the lower bits.
(6) In step S6, the parallel A / D converter M2 determines whether or not the conversion of the lower bits into a digital value has been completed. If not completed, the process branches to NO, and step S5 is continued until the conversion is completed. After the conversion to the digital value is completed, the process branches to YES and proceeds to step S7.
(7) In step S7, the parallel A / D converter M2 stores the digital value which is the A / D conversion result N5 of the lower bits implemented in step S5 in the majority circuit M4.
(8) In step S8, the parallel A / D converter M2 subtracts “1” from the number of samplings “X” set in step S1.
(9) In step S9, the parallel A / D converter M2 determines whether or not the number of times of sampling “X” subtracted in step S8 is zero. If it is not zero, the parallel A / D converter M2 repeats the processing from step S5. If it is zero, the process proceeds to step S10.
(10) In step S10, the majority circuit M4 sets the number of “1” reads stored in step S7 and the number of “1” read in step S1 for all bits except the least significant bit in the A / D conversion result N5 of the lower bits. Is compared with the set value “Y” for determining that the carry is in the vicinity of the carry and “carried”. The majority circuit M4 proceeds to step S11 if they match, and proceeds to step S12 if they do not match. At this time, the set value “Y” is set in advance in the determination circuits 11 and 13 in step S1.
(11) In step S11, the majority circuit M4 is lower than the bit that is in the vicinity of the carry set in step S1 and coincides with the set value “Y” for determining “carrying”. All the bits are corrected to “0” by the “0” correction circuit.
(12) In step S12, the majority circuit M4 sets the number of “1” readings stored in step S7 and the number of readings in step S1 for all bits except the least significant bit in the A / D conversion result of the lower bits. The set value “Z” for determining that the carry is in the vicinity and “no carry” is compared. The majority circuit M4 moves to step S13 if they match, and stores the majority result of the lower bits processed in steps S10 and S11 in the conversion result register M5 if they do not match, and performs A / D conversion. finish. At this time, the set value “Z” is preset in the determination circuits 12 and 14 in step S1.
(13) In step S13, the majority circuit M4 is lower than the bit that is near the carry set in step S1 and matches the set value “Z” for determining “no carry”. All the bits are corrected to “1” by the “1” correction circuit. Then, the majority result of the lower bits is stored in the conversion result register M5, and the A / D conversion ends.
That is, in the present embodiment, the result after the correction in steps S10 to S13 is output as the result of the majority circuit M4.

  As described above, the operation method (correction method) of the A / D converter M0 according to the embodiment of the present invention is performed.

According to the present embodiment, the majority circuit for each bit for correcting the A / D conversion result has the number of occurrences of “1” of the A / D conversion result by sampling for every bit except the least significant bit. If it matches [(sampling number + 1) / 2], it is near the carry and is judged as “carrying” and outputs “1”, and is near the carry and Inversion logic of the determination signal output from the determination circuit that determines that “carrying” is performed, and AND logic of the result of the majority circuit that is near the carry and that is lower than the bit that is determined to be “carrying” The lower bits from the bit that is near the carry and determined as “carrying” by taking the “0” correction circuit that corrects the result of the majority circuit to “0”, and all except the least significant bit For each bit, sampling When the number of occurrences of “1” in the A / D conversion result matches [(sampling number−1) / 2], it is determined that the carry is near and “no carry” and “1”. And a determination signal output from a determination circuit that determines that the carry is in the vicinity of the carry and is not carried, and a bit that is determined to be in the vicinity of the carry and is determined to be not carry. "1" correction that corrects the result of the majority circuit to "1" for the lower bits than the bit that is near the carry by taking the OR logic of the result of the majority circuit of the lower bit and "no carry" It has a circuit. As a result, it is possible to detect whether the A / D conversion result is near the carry and whether the carry is completed or not when it is near the carry. The A / D conversion result before and after the carry can be output as the result of the majority circuit without outputting the abnormal value of the A / D conversion result that could not be removed conventionally as the result of the majority circuit.
In other words, this embodiment has an effect that the accuracy of the A / D conversion result can be improved by using a correction technique with respect to an increase in variation in analog characteristics due to miniaturization and noise.

  The A / D converter M1 can be used by being incorporated in a semiconductor device (not shown) exemplified by a semiconductor integrated circuit and a microcomputer.

  The present invention is not limited to the embodiments described above, and it is obvious that the embodiments can be appropriately modified or changed within the scope of the technical idea of the present invention.

M0 A / D converter M1 Successive comparison type A / D converter M2 Parallel type A / D converter M3 Lower bit reference voltage generation circuit M4 Majority circuit M5 Conversion result storage register M6-1 to M6-3 Single-bit majority circuit M7-1 To M7-3 adder circuit M8-1 to M8-3 registers M9-1 to M9-3 bit selection circuits M10-1 to M10-3 flip-flops M11 to M14 determination circuits M15 and M17 “0” correction circuits M16 and M18 “ 1 "correction circuit N1 Analog input signal N2, N5 to N6, N8-1 to N8-3, N9 to N12, N13-1 to N13-2 Digital signal N3 Upper reference voltage N4 Lower reference voltage N7, N14 Clock signal

Claims (8)

An A / D converter that corrects an A / D conversion result based on a majority vote performed for each bit by sampling at an odd number of times of at least 5 times,
A majority voting circuit that determines a value for each bit based on a result of majority voting performed for each bit of the A / D conversion result;
The majority circuit is
For every bit except the least significant bit, if the number of occurrences of “1” in the A / D conversion result by sampling coincides with a predetermined first determination value set in advance, it is near the carry and carries A first determination circuit that determines that the
A first correction circuit that corrects the A / D conversion result to “0” in a lower bit than a bit that is near the carry and is determined to carry;
For every bit except the least significant bit, if the number of occurrences of “1” of the A / D conversion result by the sampling matches a predetermined second determination value set in advance, it is near the carry and A second determination circuit for determining that no carry has been performed;
An A / D converter comprising: a second correction circuit that corrects the A / D conversion result to “1” in a lower bit than a bit determined to be near the carry and not carry. The A / D converter according to claim 1,
An A / D converter in which the first determination value is [(sampling count + 1) / 2] and the second determination value is [(sampling count−1) / 2]. The A / D converter according to claim 1,
The first determination value is a value having a predetermined width from [(sampling number + 1) / 2] to the upper bit side, and the second determination value is lower bit from [(sampling number−1) / 2]. A / D converter having a predetermined width on the side. The A / D converter according to claim 1,
The majority circuit determines a value for each bit based on a result of majority vote performed for each bit with respect to lower bits of the A / D conversion result. An analog signal supply circuit for outputting an analog signal;
A semiconductor device comprising: the A / D converter according to claim 1, which converts the analog signal into a digital signal. A method for correcting an A / D conversion result for correcting an A / D conversion result based on a majority vote performed for each bit by sampling an odd number of times of at least 5 times,
For every bit except the least significant bit, if the number of occurrences of “1” in the A / D conversion result by sampling coincides with a predetermined first determination value set in advance, it is near the carry and carries A step of determining that
Correcting the A / D conversion result in a lower bit than the bit determined to be near the carry and carry;
For every bit except the least significant bit, if the number of occurrences of “1” of the A / D conversion result by the sampling matches a predetermined second determination value set in advance, it is near the carry and Determining that no carry has been performed;
A method of correcting an A / D conversion result, comprising: correcting the A / D conversion result in a bit lower than a bit determined to be near the carry and not carry. The A / D conversion result correction method according to claim 6,
A method for correcting an A / D conversion result, wherein the first determination value is [(sampling number + 1) / 2] and the second determination value is [(sampling number-1) / 2]. The A / D conversion result correction method according to claim 6,
The first determination value is a value having a predetermined width from [(sampling number + 1) / 2] to the upper bit side, and the second determination value is lower bit from [(sampling number−1) / 2]. A method of correcting an A / D conversion result with a value having a predetermined width on the side.

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