JP2012226810A - Replica circuit, high voltage detection circuit, high voltage regulator circuit, and nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a replica circuit capable of correctly replicating current.SOLUTION: The replica circuit includes: a first current path obtained by connecting a first transistor of a first conductive type, a second transistor of the first conductive type, and a third transistor of a second conductive type in series; a second current path obtained by connecting a fourth transistor of the first conductive type configured so as to cause current corresponding to current flowing to the first transistor to flow and a fifth transistor of the second conductive type configured so as to cause current corresponding to current flowing to the third transistor to flow in series; a sixth transistor of the second conductive type configured so as to cause the current corresponding to the current flowing to the third transistor to flow; first control means for controlling gate voltage of the first transistor so as to supply a reference voltage to the drain of the first transistor; and a second control means for controlling gate voltage of the second transistor so as to supply a reference voltage to the drain of the fourth transistor.

Description

The present invention relates to a replica circuit, a high voltage detection circuit, a high voltage regulator circuit, and a nonvolatile semiconductor memory device. In particular, the present invention relates to a replica detection circuit that replicates a reference current by flowing the same current as a reference current flowing in a transistor to another transistor, and a high-voltage detection circuit using the replica detection circuit.

A semiconductor device such as a nonvolatile memory includes a charge pump circuit that boosts the power supply voltage VCC and generates a voltage VP higher than the power supply voltage VCC in order to use it for data writing and erasing operations. In the charge pump, the high voltage of the output is detected. When the voltage is higher than the predetermined voltage, the operation of the charge pump is stopped. When the voltage is lower than the predetermined voltage, the operation of the charge pump is started and negative feedback By performing the control, the high voltage of the output is controlled to a target voltage.

FIG. 8 shows an example of the replica detection circuit portion of the high voltage detection circuit used for controlling the operation of the charge pump.

The PMOS transistor MP0 and the reference resistor Rref are connected in series between the power supply voltage VCC and the ground voltage VSS. In the differential amplifier AMP0, the reference voltage VREF is supplied to the negative input terminal, and the connection point between the PMOS transistor MP0 and the reference resistor Rref, that is, the drain of the PMOS transistor MP0 is connected to the positive input terminal. The output of the differential amplifier AMP0 is connected to the gate of the PMOS transistor MP0.

The PMOS transistor MP1 and the NMOS transistor MN0 are connected in series between the power supply voltage VCC and the ground voltage VSS. The gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP0. The PMOS transistor MP1 and the PMOS transistor MP0 have the same size (gate length and gate width). The gate of the NMOS transistor MN0 is connected to the connection point between the PMOS transistor MP1 and the NMOS transistor MN0, that is, the drain of the NMOS transistor NM0.

A resistance element for detection (having a resistance value obtained by serially connecting n reference resistors Rref. N may not be an integer) and the NMOS transistor MN1 are connected in series between the high voltage terminal VP and the ground voltage VSS. ing. The gate of the NMOS transistor MN1 is connected to the gate of the NMOS transistor MN0. The NMOS transistor MN1 and the NMOS transistor MN0 have the same size (gate length and gate width). A detection terminal VDIV is drawn from a connection point between the detection resistance element and the NMOS transistor MN1.

The operation of this circuit is as follows. The reference current Iref flowing through the PMOS transistor MP0 and the reference resistor Rref is controlled so that a relationship of VREF = Iref × Rref is established by negative feedback control by the differential amplifier AMP0. Since the PMOS transistor MP1 has the same gate as the PMOS transistor MP0 and has the same size, a current close to Iref flows through the current path including the PMOS transistor MP1 and the NMOS transistor MN0. Since the NMOS transistor MN1 has the same gate as the NMOS transistor MN0 and has the same size, a current close to Iref flows through the current path including the detection resistance element and the NMOS transistor MN1. In this way, a current replica is made. As a result, the voltage of VDIV is close to VDIV = VP−n × Iref × Rref = VP−n × VREF. Then, the variation ΔVP of VP and the variation ΔVDIV of VDIV almost coincide with each other, and detection with relatively high accuracy is possible as compared with simple resistance division.

JP 2000-19200 A

However, the circuit shown in FIG. 8 has the following problems. As shown in FIG. 9, Iref1 flows through the current path of the Iref conversion circuit 50, which is a current close to Iref0, but does not completely match. This is because the reference resistor Rref and the NMOS transistor MN0 (the gate and the drain are connected, that is, the diode is connected) have different current / voltage characteristics, so that the PMOS transistor MP0 and the PMOS transistor MP1 have the source voltage and the gate voltage. Is the same, but the drain voltages are different. Similarly, Iref2 flows through the NMOS transistor MN1, which is a current close to Iref1 flowing through the NMOS transistor MN0, but does not completely match. This is because the NMOS transistor MN0 and the NMOS transistor MN1 have the same source voltage and the same gate voltage but different drain voltages. The currents Iref0, Iref1 and Iref2 all have different magnitudes, and they do not completely coincide with each other. As a result, an error occurs in the variation ΔVP of VP and the variation ΔVDIV of VDIV.

Accordingly, the present invention provides a replica circuit capable of accurately replicating a current, a high voltage detection circuit capable of accurately detecting a high voltage using the replica circuit, a high voltage generation circuit using the circuit, and a non-volatile circuit An object is to provide a semiconductor memory device.

In order to solve the above problems, in one embodiment of the present invention, a first conductivity type first transistor, a first conductivity type second transistor, and a second conductivity type third transistor are connected in series. The first current path, the fourth transistor of the first conductivity type configured to flow the current corresponding to the current flowing through the first transistor, and the current corresponding to the current flowing through the third transistor are flowed. A second current path in which the second conductivity type fifth transistor configured in the above is connected in series, and a second conductivity type sixth transistor configured to flow a current corresponding to the current flowing in the third transistor. First control means for controlling the gate voltage of the first transistor so that the drain voltage of the first transistor is substantially equal to the reference voltage, and the drain voltage of the fourth transistor, Replica circuit characterized by comprising a second control means for controlling the gate voltage of the second transistor so that the irradiation voltage are approximately equal, is provided.

In this replica circuit, the gate of the first transistor and the gate of the fourth transistor are connected in common, the drain and gate of the third transistor, the gate of the fifth transistor, and the gate of the sixth transistor. And may be connected in common.

In this replica circuit, the first control means is a first differential amplifier to which a reference voltage and a drain voltage of the first transistor are supplied, and an output is connected to the gate of the first transistor. The control means may be a second differential amplifier to which the reference voltage and the drain voltage of the fourth transistor are supplied and whose output is connected to the gate of the second transistor.

In order to solve the above problem, in another embodiment of the present invention, a reference current path in which a first resistor and a first conductivity type first transistor are connected in series, and a first conductivity type second transistor are provided. A first current path in which a second conductive type third transistor is connected in series, a first conductive type fourth transistor configured to flow a current corresponding to a current flowing through the first transistor, Between the second current path in which the second conductivity type fifth transistor configured to flow a current corresponding to the current flowing through the third transistor is connected in series, and the high voltage terminal and the reference voltage terminal, A third current path in which a second resistor and a sixth transistor of a second conductivity type configured to flow a current corresponding to a current flowing through the third transistor are connected in series; and a drain voltage of the first transistor And reference power The first control means for controlling the gate voltage of the first transistor so that is substantially equal, and the gate voltage of the second transistor is controlled so that the drain voltage of the fourth transistor is substantially equal to the reference voltage And a second control means. A high voltage detection circuit is provided.

In this high voltage detection circuit, the gate of the first transistor and the gate of the fourth transistor are connected in common, the drain and gate of the third transistor, the gate of the fifth transistor, The gates of the transistors may be commonly connected.

In this high voltage detection circuit, the first control means is a first differential amplifier to which a reference voltage and a drain voltage of the first transistor are supplied and whose output is connected to the gate of the first transistor, The second control means may be a second differential amplifier to which a reference voltage and a drain voltage of the fourth transistor are supplied and whose output is connected to the gate of the second transistor.

The high voltage detection circuit may further include a comparison circuit that compares the reference voltage with the drain voltage of the sixth transistor.

In order to solve the above-mentioned problem, in another embodiment of the present invention, the operation is controlled by the output of the high-voltage detection circuit, and the high-voltage detection circuit has a charge pump connected to the high-voltage terminal. There is provided a nonvolatile semiconductor memory device comprising a voltage regulator circuit and a memory cell array having a plurality of memory cells for writing or erasing.

According to the present invention, an accurate current replica can be provided, and an accurate high voltage detection circuit and high voltage generation circuit can be provided.

1 is a functional block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention. It is a functional block diagram of the high voltage regulator circuit which concerns on one Embodiment of this invention. It is a functional block diagram of the high voltage generation circuit which concerns on one Embodiment of this invention. It is a circuit diagram of a charge pump circuit according to an embodiment of the present invention. It is a waveform of the signal which controls the charge pump circuit which concerns on one Embodiment of this invention. 1 is a circuit diagram of a replica detection circuit according to an embodiment of the present invention. FIG. It is a figure explaining operation | movement of the replica detection circuit based on one Embodiment of this invention. It is a circuit diagram of the conventional replica detection circuit. It is a figure explaining operation | movement of the conventional replica detection circuit.

Hereinafter, embodiments for carrying out the present invention will be described as embodiments. The present invention is not limited to the embodiments described below. It is possible to implement the present invention by variously modifying the embodiments described below.

FIG. 1 is a functional block diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention. This nonvolatile semiconductor memory device may have only a so-called memory function, or may be a so-called memory core that is mounted together with a CPU core or the like. This nonvolatile semiconductor memory device operates with a single power supply composed of a power supply voltage VCC (for example, 1.8 V) and a ground voltage VSS. The nonvolatile semiconductor memory device is supplied with an address signal (ADDR), a control signal (CTRL), and the like, and data is input / output through a DQ terminal. The address signal (ADDR) is supplied to an address buffer circuit (ADDR buffers), and among the address signals (ADDR), the row address (X-ADDR) is sent to the row decoder (X-decoders), and the column address (Y-ADDR) is sent Each is supplied to a column decoder (Y-decoders). A memory cell array (Memory Cell Array) is configured by arranging P-type MOS transistors having charge storage layers (floating gates, nitride films, etc.) in a matrix, the control gates of which are connected to word lines, and the word lines are Driven by row decoders (X-decoders). The source of the P-type MOS transistor is connected to the common source line, the drain is connected to the bit line, and the bit line is selected by a column selection gate (Y-select gates). Column select gates (Y-select gates) are driven by column decoders (Y-decoders). The column selection gate (Y-select gates) is a multiplexer circuit, and the voltage (or current flowing through the bit line) selected by this circuit is sensed by the sense amplifier circuit (Sense Amps) to become read data. This is latched in the page buffer circuit (Page buffers), and is input to the DQ terminal by the write data loading circuit (Program Data loading) through the input / output buffer circuit (I / O buffers) according to the page buffer address (Page-ADDR). To be supplied.

The write data supplied from the DQ terminal is latched in the page buffer circuit (Page buffers) through the input / output buffer circuit (I / O buffers), and this is held in the write buffer circuit (Program buffers). The data held here is supplied to the bit line selected by the column selection gate (Y-select gates) and written to the selected memory cell. For writing, by supplying a voltage of 0 V to the bit line, a voltage of VCC or higher to the common source line, a high voltage VP1 to the word line, and a high voltage VP2 to the well, an interband tunnel current is generated and electrons are accumulated. This is done by trapping the layer. Here, the high voltage VP1 and the high voltage VP2 are 7V and 5V, for example.

These read and write operations are controlled by a state transition device (State Machine) and a control circuit (CTRL ckt), which are operated by a control signal (CTRL).

The high voltage regulator circuit (High-Voltage Regulator) is controlled by a state transition device (State Machine) and a control circuit (CTRL ckt), and outputs a high voltage VP1, a high voltage VP2, and a negative voltage VN. The high voltage VP1 and the negative voltage VN are supplied to a row decoder (X-decoders), and the high voltage VP2 is supplied to a well bias control circuit (Well bias CTRL). As described above, at the time of writing, 0 V is supplied to the bit line, VCC or higher voltage is supplied to the common source line, the high voltage VP1 is supplied to the word line, and the high voltage VP2 is supplied to the well.

FIG. 2 is a part of a functional block diagram of a high voltage regulator circuit (High-Voltage Regulator) according to an embodiment of the present invention. When outputting three voltages VP1, VP2, and VN, three similar circuits (in the case of a negative voltage generation circuit, a negative voltage generation circuit in which the PN of the circuit is inverted and the positive / negative of the signal is inverted) are provided. System arrangement.

The high voltage regulator circuit (High-Voltage Regulator) includes a high voltage generation circuit (PUMP), a voltage divider circuit (Voltage divider), a comparison circuit (Comparator), and an oscillator (Oscillator).

In accordance with the circuit activation signal (EN), the high voltage generation circuit (PUMP), the voltage divider circuit (Voltage divider), the comparison circuit (Comparator), and the oscillator (Oscillator) are activated. The comparison circuit (Comparator) compares the reference potential (VREF) supplied from the band gap reference potential generation circuit (Band Gap reference) with the feedback voltage DVIV that is the output of the voltage divider circuit (Voltage divider), and generates an oscillator. The operation of (Oscillator) is controlled. An oscillator (Oscillator) supplies a clock signal (CLK) to a high voltage generation circuit (PUMP). If the output of the high voltage generation circuit (PUMP) rises too much, negative feedback works, the supply of the clock signal (CLK) of the oscillator (Oscillator) is stopped, and the output of the high voltage generation circuit (PUMP) falls below a predetermined value. The clock signal (CLK) supply resumes.

FIG. 3 is a functional block diagram of the high voltage generation circuit (PUMP). The high voltage generation circuit (PUMP) includes a phase shift circuit (Phase shifter), a clock buffer circuit (CLK buffer), and a charge pump circuit (CP).

The clock signal (CLK) is supplied to a phase shift circuit (Phase shifter), and four-phase control signals DCLK10, GCLK10, DCLK20, and GCLK20, which will be described in detail later with reference to FIG. 5, are generated. The phase shift circuit is configured using a plurality of delay circuits. The clock buffer circuit (CLK buffers) receives the control signals DCLK10, GCLK10, DCLK20, and GCLK20 and generates drive signals DCLK1, GCLK1, DCLK2, and GCLK2. The charge pump circuit (CP) receives the drive signals DCLK1, GCLK1, DCLK2, and GCLK2, and generates a high voltage VP (VP1, VP2, etc., which is VN in the case of a negative voltage).

FIG. 4 is a circuit diagram of the charge pump circuit (CP). Transistors T01, T11, T21, T31, and T41 made of NMOS are connected in series between the power supply voltage VCC and a node to which the boosted voltage VP is provided.

Nodes between the transistors T01 and T11, between T11 and T21, between T21 and T31, and between T31 and T41 are CPD1, CPD2, CPD3, and CPD4, respectively. The nodes of the gates of the transistors T01, T11, T21, T31, and T41 are CPG0, CPG1, CPG2, CPG3, and CPG4.

A transistor T02 composed of NMOS is connected between VCC and CPG0, and its gate is connected to CPD1. A transistor T12 made of NMOS is connected between CPD1 and CPG1, and its gate is connected to CPD2. A transistor T22 made of NMOS is connected between CPD2 and CPG2, and its gate is connected to CPD3. A transistor T32 composed of NMOS is connected between CPD3 and CPG3, and its gate is connected to CPD4. A transistor T42 composed of NMOS is connected between CPD4 and CPG4, and its gate is connected to VP.

A capacitor C00 is connected to CPG0, and the counter electrode of this capacitor is driven by a drive signal GCLK2. A capacitor C12 is connected to CPG1, and the counter electrode of this capacitor is driven by a drive signal GCLK1. A capacitor C22 is connected to CPG2, and the counter electrode of this capacitor is driven by a drive signal GCLK2. A capacitor C32 is connected to CPG3, and the counter electrode of this capacitor is driven by a drive signal GCLK1. A capacitor C42 is connected to CPG4, and the counter electrode of this capacitor is driven by a drive signal GCLK2.

A capacitor C11 is connected to CPD1, and the counter electrode of this capacitor is driven by a drive signal DCLK1. A capacitor C21 is connected to CPD2, and the counter electrode of this capacitor is driven by a drive signal DCLK2. A capacitor C31 is connected to CPD3, and the counter electrode of this capacitor is driven by a drive signal DCLK1. A capacitor C41 is connected to CPD4, and the counter electrode of this capacitor is driven by a drive signal DCLK2.

FIG. 5 shows waveforms of control signals DCLK10, GCLK10, DCLK20, and GCLK20 that are used to generate drive signals DCLK1, GCLK1, DCLK2, and GCLK2.

FIG. 6 is a circuit diagram of a replica detection circuit according to an embodiment of the present invention. It is a circuit equivalent to a voltage divider circuit (Voltage divider) in the high-voltage regulator circuit (High-Voltage Regulator) of FIG. The replica detection circuit includes a reference current generation circuit 10, an Iref conversion circuit 20, a high voltage shift circuit 30, and a reference voltage generation circuit 40. The reference voltage generation circuit 40 receives the power supply voltage VCC and the ground voltage VSS and generates a reference voltage VREF to be supplied to the reference current generation circuit 10 and the Iref conversion circuit 20. The reference voltage generation circuit 40 is configured by, for example, a band gap circuit or the like so that the reference voltage VREF that is always a constant voltage can be generated regardless of variations in temperature and the power supply voltage VCC.

The reference current generation circuit 10 includes a PMOS transistor MP0, a reference resistor Rref, and a differential amplifier AMP10. The PMOS transistor MP10 and the reference resistor Rref are connected in series between the power supply voltage VCC and the ground voltage VSS. The differential amplifier AMP10 has a negative input terminal supplied with the reference voltage VREF generated by the reference voltage generation circuit 40, and a positive input terminal connected to a connection point between the PMOS transistor MP10 and the reference resistor Rref, that is, a drain of the PMOS transistor MP10. Has been. The output of the differential amplifier AMP10 is connected to the gate of the PMOS transistor MP10.

The Iref conversion circuit 20 includes PMOS transistors MP11 and MP12, NMOS transistors MN10 and MN11, and a differential amplifier AMP11. The PMOS transistor MP11 and the NMOS transistor MN10 are connected in series between the power supply voltage VCC and the ground voltage VSS. The gate of the PMOS transistor MP11 is connected to the gate of the PMOS transistor MP10. The PMOS transistor MP11 and the PMOS transistor MP10 have the same size (gate length and gate width). The PMOS transistor MP12 and the NMOS transistor MN11 are connected in series between the power supply voltage VCC and the ground voltage VSS. The gate of the NMOS transistor MN11 is connected to the drain thereof, and is also connected to the gate of the NMOS transistor MN10. The NMOS transistor MN11 and the NMOS transistor MN10 have the same size (gate length and gate width). In the differential amplifier AMP11, the reference voltage VREF generated by the reference voltage generation circuit 40 is supplied to the negative input terminal, and the connection point between the PMOS transistor MP11 and the NMOS transistor MN10, that is, the drain of the PMOS transistor MP11 is connected to the positive input terminal. It is connected. The output of the differential amplifier AMP11 is connected to the gate of the PMOS transistor MP12.

The high voltage shift circuit 30 includes a resistance element for detection (having a resistance value in which n reference resistors Rref are connected in series) and an NMOS transistor MN12. The detection resistance element nRef and the NMOS transistor MN12 are connected in series between the high voltage terminal VP and the ground voltage VSS. The gate of the NMOS transistor MN12 is connected to the gate of the NMOS transistor MN11. The NMOS transistor MN11 and the NMOS transistor MN12 have the same size (gate length and gate width). A detection terminal VDIV is drawn from a connection point between the detection resistance element nRef and the NMOS transistor MN12.

Next, the operation of the replica detection circuit shown in FIG. 6 will be described with reference to FIG.

The reference current Iref10 flowing in the current path constituted by the PMOS transistor MP10 and the reference resistor Rref is controlled so that the relationship of VREF = Iref10 × Rref is established by negative feedback control by the differential amplifier AMP10. That is, when the drain voltage of the PMOS transistor MP10 becomes lower than the reference voltage VREF, the output of the differential amplifier AMP10 decreases and the reference current Iref10 increases, thereby raising the drain voltage of the PMOS transistor MP10. On the other hand, when the drain voltage of the PMOS transistor MP10 becomes higher than the reference voltage VREF, the output of the differential amplifier AMP10 increases and the reference current Iref10 decreases, thereby lowering the drain voltage of the PMOS transistor MP10. In this way, the drain voltage of the PMOS transistor MP10 always maintains the reference voltage VREF, and as a result, the reference current Iref10 flowing through this current path is controlled so that the relationship VREF = Iref10 × Rref is satisfied.

Also in the Iref conversion circuit 20, negative feedback control is performed by the differential amplifier AMP11, and the drain voltage of the PMOS transistor MP11 is controlled to be the reference voltage VREF. That is, when the drain voltage of the PMOS transistor MP11 becomes lower than the reference voltage VREF, the output of the differential amplifier AMP11 becomes high, and the current Iref12 flowing through the current path composed of the PMOS transistor MP12 and the NMOS transistor MN11 becomes small. The mirrored current Iref11 is also reduced, raising the drain voltage of the PMOS transistor MP11. On the other hand, when the drain voltage of the PMOS transistor MP11 becomes higher than the reference voltage VREF, the output of the differential amplifier AMP11 becomes low, and the current Iref12 flowing through the current path composed of the PMOS transistor MP12 and the NMOS transistor MN11 becomes large. Is also increased, and the drain voltage of the PMOS transistor MP11 is lowered. In this way, the drain voltage of the PMOS transistor MP11 always maintains the reference voltage VREF.

The PMOS transistor MP11 has a common gate with the PMOS transistor MP10, and both have the same size. In addition, as described above, the drain voltage of the PMOS transistor MP11 is the reference voltage VREF, and the drain voltage of the PMOS transistor MP10 is also the reference voltage VREF. As a result, the current Iref11 flowing through the current path including the PMOS transistor MP11 and the NMOS transistor MN10 is exactly the same magnitude as the reference current Iref10.

Since the NMOS transistor MN12 has the same gate as the NMOS transistors MN10 and MN11 and has the same size, the detection voltage VDIV refers to the current Iref13 that flows through the current path including the resistance element nRref for detection and the NMOS transistor MN12. When it matches the voltage VREF, the current is exactly the same as Iref10. In this way, a current replica is made. As a result, the voltage of VDIV is exactly VDIV = VP−n × Iref × Rref = VP−n × VREF. Then, the variation ΔVP of VP and the variation ΔVDIV of VDIV coincide, and it is possible to detect a high voltage with extremely high accuracy.

Referring to FIG. 2 again, in the high voltage regulator circuit (High-Voltage Regulator), the detection voltage VDVI of the replica detection circuit corresponding to the voltage divider circuit (Voltage divider) is supplied to the comparison circuit (Comparator). The comparison circuit (Comparator) is composed of, for example, a differential amplifier. Then, the detection voltage VDVI is compared with the reference voltage VREF, and the high voltage VP is detected. That is, if VP is higher than VREF × (1 + n), the detection voltage VDVI becomes higher than the reference voltage VREF, and the output of the comparison circuit (Comparator) becomes inactive. On the other hand, if the high voltage VP is lower than VREF × (1 + n), the detection voltage VDVI becomes lower than the reference voltage VREF, and the output of the comparison circuit (Comparator) becomes active. In this manner, a high voltage detection circuit can be obtained by connecting a comparison circuit (Comparator) to a replica detection circuit corresponding to a voltage divider circuit (Voltage divider).

The output of the high voltage detection circuit, that is, the output of the comparison circuit (Comparator) controls the operation of the oscillator (Oscillator). When this is active, the clock CLK becomes the oscillation output, and the high voltage generation circuit (PUMP) is high. It operates to increase the voltage VP. On the other hand, when this is inactive, the oscillation of the clock CLK stops, the high voltage generation circuit (PUMP) stops operating, and the high voltage VP becomes low. In this way, the negative feedback control is performed so that the high voltage VP is maintained at a value of VREF × (1 + n).

As described above, when a high voltage detection circuit is configured using the replica detection circuit of the present invention and used in a high voltage regulator circuit, accurate high voltage control is possible.

As described above, the memory cell array (Memory Cell Array) in FIG. 1 is configured by arranging P-type MOS transistors having charge storage layers (floating gates, nitride films, etc.) in a matrix. The data is written by applying the high voltage VP1 generated by the above-described high voltage regulator circuit (High-Voltage Regulator) to the gate of the P-type MOS transistor, and using the high voltage VP2 generated by the same circuit. The voltage is applied to the well, the ground voltage VSS is applied to the drain, an interband band tunnel current is generated, and the charge is stored in the charge storage layer. When such a writing method is used, it is necessary to use a high voltage detection circuit of the present invention because extremely high voltage control is required.

As described above, in the above embodiment, the description has focused on the high voltage detection circuit that detects a positive high voltage, but the negative voltage that accurately detects the negative voltage by inverting the polarity of the transistor in the replica detection circuit. It is also possible to configure a detection circuit.

In the above embodiment, the PMOS transistors MP10 and MP11 are the same size, and the NMOS transistors MN10, MN11, and MN12 are all assumed to be the same size. However, the transistor sizes, particularly the gate widths are different. It is possible to make a difference in current driving capability. Even in this case, Iref10 and Iref13 maintain a proportional relationship according to the size of the transistor.

DESCRIPTION OF SYMBOLS 10 Reference current generation circuit 20 Iref conversion circuit 30 High voltage shift circuit 40 Reference voltage generation circuit

Claims (9)

A first transistor of a first conductivity type;
A first current path in which a second transistor of the first conductivity type and a third transistor of the second conductivity type are connected in series;
A fourth transistor of a first conductivity type configured to flow a current corresponding to a current flowing through the first transistor, and a second conductive configured to flow a current corresponding to a current flowing through the third transistor. A second current path in series with a fifth transistor of the type;
A second conductivity type sixth transistor configured to flow a current corresponding to a current flowing through the third transistor;
First control means for controlling a gate voltage of the first transistor so that a drain voltage and a reference voltage of the first transistor are substantially equal;
Second control means for controlling the gate voltage of the second transistor so that the drain voltage of the fourth transistor is substantially equal to the reference voltage;
A replica circuit comprising: A gate of the first transistor and a gate of the fourth transistor are connected in common;
2. The replica circuit according to claim 1, wherein a drain and a gate of the third transistor, a gate of the fifth transistor, and a gate of the sixth transistor are connected in common. The first control means is a first differential amplifier to which the reference voltage and the drain voltage of the first transistor are supplied and whose output is connected to the gate of the first transistor;
The second control means is a second differential amplifier to which the reference voltage and the drain voltage of the fourth transistor are supplied and whose output is connected to the gate of the second transistor. The replica circuit according to claim 1. A reference current path in which a first resistor and a first conductivity type first transistor are connected in series;
A first current path in which a second transistor of the first conductivity type and a third transistor of the second conductivity type are connected in series;
A fourth transistor of a first conductivity type configured to flow a current corresponding to a current flowing through the first transistor, and a second conductive configured to flow a current corresponding to a current flowing through the third transistor. A second current path in series with a fifth transistor of the type;
A second resistor and a sixth transistor of the second conductivity type configured to flow a current corresponding to the current flowing through the third transistor are connected in series between a high voltage terminal and a reference voltage terminal. 3 current paths,
First control means for controlling a gate voltage of the first transistor so that a drain voltage and a reference voltage of the first transistor are substantially equal;
Second control means for controlling the gate voltage of the second transistor so that the drain voltage of the fourth transistor is substantially equal to the reference voltage;
A high voltage detection circuit comprising: A gate of the first transistor and a gate of the fourth transistor are connected in common;
5. The high voltage detection circuit according to claim 4, wherein the drain and gate of the third transistor, the gate of the fifth transistor, and the gate of the sixth transistor are connected in common. The first control means is a first differential amplifier to which the reference voltage and the drain voltage of the first transistor are supplied and whose output is connected to the gate of the first transistor;
The second control means is a second differential amplifier to which the reference voltage and the drain voltage of the fourth transistor are supplied and whose output is connected to the gate of the second transistor. The high voltage detection circuit according to claim 4. 5. The high voltage detection circuit according to claim 4, further comprising a comparison circuit that compares the reference voltage with a voltage of a drain of the sixth transistor. 8. A high voltage regulator circuit comprising: a charge pump whose operation is controlled by the output of the high voltage detection circuit according to claim 4 and whose output is connected to the high voltage terminal. 9. A nonvolatile semiconductor memory device comprising a memory cell array having a plurality of memory cells to be written or erased by an output voltage of the high voltage regulator circuit according to claim 8.

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