JP6854714B2 - Semiconductor storage device and writing method to semiconductor storage device - Google Patents

Description

The present invention relates to a method of writing to a semiconductor storage device and a semiconductor storage device, particularly a method of writing to a semiconductor storage device and a semiconductor storage device that controls a read current so as to suppress an error caused by a read current from a memory cell. ..

Conventionally, Patent Document 1 is known as a document relating to current control. The semiconductor integrated circuit disclosed in Patent Document 1 includes a first current control oscillation circuit that outputs an oscillation signal of a first frequency obtained by integrating a first gain with a first control current, and a first control voltage and a first reference voltage. A first voltage-current conversion circuit that applies the first output current, which is the sum of the voltage difference and the second gain, to the first control current, a first reference current circuit that applies a constant current to the first control current, and a variable second output. It has a current output circuit that applies a current to the first control current.

Patent Document 2 is also known. The PLL circuit disclosed in Patent Document 2 includes a phase comparator that compares the phase of an input signal with the phase of a feedback signal to generate a phase error voltage, and a filter output voltage that removes harmonic components of the phase error voltage. A loop filter that generates a loop filter, a voltage-current conversion circuit that converts the filter output voltage into a phase error current, a bias current generation means for generating a bias current, and a control current by adding the phase error current and the bias current. It includes an adder that generates an oscillator, a current control oscillator that generates an oscillation output signal according to the control current, and a counter that generates a feedback signal according to the oscillation output signal.

By the way, in a non-volatile semiconductor storage device, for example, a flash memory, a relatively large voltage is required for writing, so a portion (cell voltage generating unit) for generating a high voltage writing voltage is generally provided. An example of the cell voltage generation unit will be described with reference to FIG.
FIG. 11 is a block diagram showing a cell voltage generation unit 90 included in the semiconductor storage device according to the comparative example. As shown in FIG. 11, the cell voltage generation unit 90 includes a high voltage generation unit 92, a high voltage level detection unit 94, a high voltage level determination unit 96, a reference current generation unit 98, and a high voltage output unit 99. ..

The high voltage generation unit 92 includes a charge pump unit (not shown) for generating an output voltage VH having a high voltage corresponding to a predetermined write voltage. The high voltage level detection unit 94 detects the level of the generated output voltage VH and outputs it as the detection current Idtc. The high voltage level determination unit 96 compares the detected current Idtc with the reference current Iref generated by the reference current generation unit 98, and generates a CPUMP control signal CPUMPEN for controlling the high voltage generation unit 92. The CPUMP control signal CPUMPEN stops the operation of the charge pump unit of the high voltage generating unit 92 when the detected current Idtc becomes equal to or higher than the reference current Iref, and generates a high voltage when the detected current Idtc becomes less than the reference current Iref. This is a signal for restarting the operation of the charge pump unit of the unit 92.

In the graph of FIG. 12A, the relationship between the detected current Idtc of the cell voltage generation unit 90 and the output voltage VH is shown by the curve C2. That is, FIG. 12A shows the output voltage VH on the horizontal axis and the detection current Idtc on the vertical axis, and shows the position of the reference current Iref to show the relationship between them. As shown in FIG. 12A, due to the operation of the cell voltage generation unit 90, the VH at the intersection P3 of the reference current Iref and the detection current Idtc is the cell voltage (write voltage, hereinafter, the cell voltage output from the high voltage output unit 99. (Sometimes referred to as "target voltage") VH0. As is clear from FIG. 12A, the target voltage shifts to the high voltage side when the reference current Iref is increased from the characteristics of the detected current Idtc with respect to the output voltage VH.

Japanese Unexamined Patent Publication No. 2003-209440 Japanese Unexamined Patent Publication No. 10-84278

The output voltage VH0 (target voltage) becomes the write voltage VW, and this output voltage VH0 is applied to the source line of the memory cell array to perform writing. The write voltage VW fluctuates due to the temperature fluctuation characteristics of the memory cell and the cell voltage generation unit. FIG. 12B shows the dependence of the current flowing through the memory cell at the time of reading after writing the data 0 (reading current, referred to as “cell current” in FIG. 12B) with respect to the writing voltage VW. As shown in FIG. 12B, the write voltage dependence of the cell current at an ambient temperature of room temperature in the semiconductor storage device according to the comparative example has the characteristics shown by the solid line curve C3 as an example. When writing data "0" to the memory cell, for example, if the write voltage VW1 is about 7.5V, the cell current can be reduced to about 1n (nano) A (intersection P4 in FIG. 12B). ).

However, when the ambient temperature rises from room temperature to a high temperature, the write voltage dependence of the cell current shifts in the direction in which the write voltage and the cell current increase as shown by the curve C4 shown by the broken line.
Then, as shown in <1> of FIG. 12 (b), the cell current increases to about 4 nA (intersection P5 of FIG. 12 (b)). On the other hand, the output voltage VH of the cell voltage generation unit 90 may also fluctuate depending on the temperature, and for example, as shown in <2> of FIG. 12 (b), it drops to about 7.4 V (intersection point of FIG. 12 (b)). P6). That is, even if the write voltage VW is set to the optimum value of 7.5 V at room temperature, the actual write voltage VW is VW2 ≈ 7.4 V, and the cell current is up to about 10 nA due to the temperature fluctuation characteristics of the cell current. To increase. As a result, there is a concern that an error (an error of outputting the data "0" as "1") may occur due to the flow of this 10 nA current at the time of reading.

As has been common in the past, if the required specifications for rewriting are rewriting in a narrow temperature range, for example, in a factory, it does not matter so much, but in recent years, rewriting by end users in a wide range of temperature conditions has become mainstream. As a result, the above phenomenon may become a problem. That is, even if the rewriting setting is optimized under the room temperature condition, the cell current for the same write voltage VW increases or the output voltage VH of the cell voltage generator 90 changes under the high temperature condition, so that the rewriting under the high temperature condition is incomplete. As a result, an unexpected cell current may flow at the time of reading, which may cause deterioration of reading characteristics (error of reading data).

In this regard, although the current is corrected in Patent Document 1 or Patent Document 2, Patent Document 1 and Patent Document 2 do not have a problem of the read current in the semiconductor storage device.

In view of the above problems, the present invention is a semiconductor storage device in which an error at the time of reading data from a memory cell is suppressed even if the environmental conditions change, as compared with the case where the write voltage is not corrected. And a method of writing to a semiconductor storage device.

The semiconductor storage device according to the present invention is a memory cell array composed of a plurality of memory cells, and a high voltage generation that raises a power supply voltage to generate a high voltage as a cell voltage applied to each of the plurality of memory cells. A unit, a correction current generator that generates a correction current for correcting fluctuations in the cell voltage with respect to the ambient temperature, a detection current that converts the high voltage into a current, and a target current that maintains the high voltage at the target voltage. To generate a control signal for controlling the boosting operation in the high voltage generating unit, and to add the reference current and the correction current, which are the target currents corresponding to room temperature, to obtain the target current. It includes a cell voltage generation unit including a signal generation unit.

On the other hand, the method of writing to the semiconductor storage device according to the present invention is used for correcting the write voltage when writing to the memory cell with the same configuration as the electric current effect transistor type memory cell having a floating gate and the memory cell. In a semiconductor storage device including a dummy cell unit and a high voltage generator that boosts the power supply voltage to generate a high voltage as the write voltage, the read current when predetermined data is written to the memory cell is It is a writing method to a semiconductor storage device that writes while correcting the fluctuation of the writing voltage due to a change in ambient temperature so as to be equal to the read current at room temperature. Is erased, the predetermined data is written in the dummy cell unit, the predetermined data written in the dummy cell unit is read out to acquire a read current, and a correction current is generated based on the read flow. , The boosting operation in the high voltage generating unit is controlled by the comparison result of comparing the detected current obtained by converting the high voltage into a current and the added value of the reference current based on the read current at room temperature and the correction current. The corrected write voltage is acquired, and the corrected write voltage is used to write to the memory cell.

According to the present invention, as compared with the case where the write voltage is not corrected, writing to the semiconductor storage device and the semiconductor storage device in which an error at the time of reading data from the memory cell is suppressed even if the environmental conditions change. It becomes possible to provide a method.

It is a block diagram which shows an example of the structure of the semiconductor storage device which includes the cell voltage generation part which concerns on embodiment. It is a block diagram which shows an example of the structure of the cell voltage generation part which concerns on embodiment. In the cell voltage generation unit according to the embodiment, (a) is a circuit diagram showing an example of a high voltage level detection unit and a high voltage level determination unit, and (b) is a circuit diagram showing an example of a high voltage output unit. It is a block diagram which shows an example of the dummy cell current generation part of the cell voltage generation part which concerns on embodiment. (A) is a flowchart showing a procedure for writing to a semiconductor storage device according to an embodiment, and (b) is a diagram showing a relationship between a control signal and a voltage applied to each terminal. It is a circuit diagram which shows a part of the VWL control circuit which concerns on embodiment. (A) and (b) are circuit diagrams showing a part of the VWL control circuit according to the embodiment. (A) and (b) are circuit diagrams showing an example of the VSL control circuit according to the embodiment. It is a circuit diagram which shows an example of the current mirror circuit which concerns on embodiment. It is a graph explaining the correction of the write voltage of the semiconductor storage device which concerns on embodiment. It is a block diagram which shows the cell voltage generation part which concerns on a comparative example. (A) is a graph showing the relationship between the detected current and the output voltage according to the comparative example, and (b) is a graph explaining the change in the cell current according to the comparative example due to the environmental conditions.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the semiconductor storage device and the method of writing to the semiconductor storage device according to the present embodiment, in the semiconductor storage device provided with the high-voltage cell voltage generator that generates the write voltage, the fluctuation of the write voltage due to the environmental conditions is corrected. ing.

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor storage device (memory) 10 including a cell voltage generation unit 40 according to the present embodiment.

In FIG. 1, the semiconductor storage device 10 is a non-volatile memory such as a flash memory, and includes a memory cell array 1, a controller 2, a row driver 3, and a column driver 4. As an example, the memory cell according to the present embodiment is composed of a MOS FET (Metal Oxide Semiconductor Field Effect Transistor) having a floating gate, and the read current when data “0” is written is almost 0. (As an example, it is 1 nA or less), and the read current when the data "1" is written is about 15 μA. Then, when writing the data "0", a high voltage (about 7.5V in the present embodiment) is applied to the source line of the memory cell array 1 to accumulate electrons in the floating gate, and when writing the data "1", the data "1" is written. do nothing.

A plurality of bit lines and a plurality of word lines intersecting each bit line are juxtaposed in the memory cell array 1, and data is stored (written) in the intersections of these bit lines and word lines. ) A memory cell (not shown) is formed.

The controller 2 supplies the row driver 3 with address information indicating the read or write address in response to the read command or the write command, and also supplies the write or read access signal to which the write voltage or the read voltage should be applied to the memory cell to the column driver. Supply to 4. Further, the controller 2 sends an erase signal ER, a dummy cell write signal DPG, and a memory cell write signal PGM to the dummy cell control unit 60 described later.

The row driver 3 selects a pair of word lines formed in the memory cell array 1 according to the write or read access signal supplied from the controller 2 and the address information, and supplies a predetermined selective voltage. As a result, the memory cells connected to the pair of word lines to which the selective voltage is supplied are subject to data reading or writing.

The column driver 4 applies a read voltage for data read to the bit line of the memory cell array 1 according to the read access signal supplied from the controller 2. Further, the column driver 4 is equipped with a cell voltage generation unit 40 that generates a high voltage for writing data to a memory cell. The column driver 4 generates a write voltage corresponding to the data based on the high voltage generated by the cell voltage generation unit 40 in response to the write access signal supplied from the controller 2, and uses this as the bit line of the memory cell array 1. It is applied to each memory cell via.

Next, the configuration of the cell voltage generation unit 40 will be described with reference to FIG. As shown in FIG. 2, the cell voltage generation unit 40 includes a high voltage generation unit (CPUMP) 42, a high voltage level detection unit (DTEC) 44, a high voltage level determination unit (COMP) 46, and a reference current generation unit (REF). It includes 48, a high voltage output unit 50, and a dummy cell current generation unit 52. In FIG. 2, an addition unit (not shown) is provided at a position where the reference current Iref and the dummy cell write current IrefP are merged. The high voltage level detection unit 44, the high voltage level determination unit 46, the reference current generation unit 48, and the addition unit constitute the "control signal generation unit" according to the present invention.

The high voltage generation unit 42 is a circuit that generates a high voltage output voltage VH that is a write voltage applied to each memory cell of the memory cell array 1. In this embodiment, a charge pump type voltage generation circuit is adopted as an example, and the standard value of the write voltage VW is set to about 7.5V. The generated output voltage VH is taken out via the high voltage output unit 50 described later and applied to the word line of the memory cell array 1. The CPUMP control signal CPUMPEN described later is input to the high voltage generation unit 42, and when the CPUMP control signal CPUMPEN is at a high level (hereinafter, “H”), the boosting operation of the charge pump is stopped, and the low level (hereinafter, “L”) is stopped. ), The boost operation is restarted.

The high voltage level detection unit 44 receives the output voltage VH of the high voltage generation unit 42, and outputs a current corresponding to the output voltage VH as a detection current Idtc.

The high voltage level determination unit 46 receives the detection current Idtc, compares it with the reference current Iref, and generates a CPUMP control signal CPUMPEN that controls the operation of the high voltage generation unit 42 according to the comparison result.

The reference current generation unit 48 generates a reference current Iref which is a reference when comparing with the detection current Idtc. As described in the description of FIG. 12A, the write voltage is basically determined by this reference current Iref.

FIG. 3A shows a circuit diagram for explaining a more detailed configuration of the high voltage level detection unit 44 and the high voltage level determination unit 46. As shown in FIG. 3A, the high voltage level detection unit 44 includes n N-type MOS FETs (hereinafter referred to as “MOS FET transistors”) NM1, NM2, ..., NMn-1, which are connected in series. It is configured to include a level detection circuit 74 made of NMn. The output voltage VH from the high voltage generation unit 42 is connected to the source of the NMOS transistor NM1 of the level detection circuit 74, and the detection current Idtc is output from the drain of the NMOS transistor NMn.

Since the gate and source of each of the NMOS transistors constituting the level detection circuit 74 are connected, a potential difference corresponding to the threshold voltage Vtn is generated between the gate and drain of each MOSFET transistor. As a result, when the output voltage VH becomes (Vtn · n) V (volt) or more, the detection current Idtc flows out. On the contrary, the detection current Idtc does not flow while the output voltage VH is less than (Vtn · n) V. In other words, (Vtn · n) is the breakdown voltage with respect to the output voltage VH.

On the other hand, the high voltage level determination unit 46 includes a current detection circuit 70 and a comparator 72.

The current detection circuit 70 includes an NMOS transistors TN1, TN2, TN3, TN4, and P-type MOS FETs (hereinafter, “MOSFET transistors”) TP1 and TP2 that serve as a constant current source. Then, the detected current Idtc is configured to flow to the GND (ground) via the NMOS transistor TN1, and the reference current Iref input from the reference current generation unit 48 flows to the GND via the NMOS transistor TN4. Each of the detected current Idtc and the reference current Iref is converted into a voltage by the current detection circuit 70 and compared by the comparator 72.

In the comparator 72, the CPUMP control signal CPUMPEN, which is an output when the detection current Idtc is equal to or greater than the reference current Iref, is set to H, and the CPUMP control signal CPUMPEN is set to L when the detection current Idtc is less than the reference current Ireff. To. Of course, the logic of the CPUMP control signal CPUMPEN is an example, and the reverse logic may be used.

As shown in FIG. 2, the CPUMP control signal CPUMPEN is input to the high voltage generation unit 42, and as described above, when the CPUMP control signal CPUMPEN is H, the boosting operation of the charge pump is stopped, and the CPUMP control signal CPUMPEN is L. In that case, the boosting operation of the charge pump is restarted. In the cell voltage generation unit 40 according to the present embodiment, by performing the operation of the charge pump intermittently in this way, the output voltage is reduced while reducing the current consumption in the high voltage generation unit 42, which generally consumes a large amount of current. VH is maintained at the target voltage (constant voltage).

With reference to FIG. 2 again, the high voltage output unit 50 serves as a buffer when the output voltage VH is output to the memory cell array 1. FIG. 3B shows a circuit diagram of the high voltage output unit 50. As shown in FIG. 3B, the high voltage output unit 50 is an inverter composed of a NMOS transistor TP3 and an NMOS transistor TN5.

As shown in FIG. 2, the output voltage VH output from the high voltage generation unit 42 is input to the dummy cell current generation unit 52 via the high voltage output unit 50. The voltage input to the dummy cell current generation unit 52 does not have to be equal to the output voltage VH, and may be, for example, a voltage proportional to the output voltage VH.

The dummy cell current generation unit 52 is a portion that acquires the dummy cell write current IrefP, which is a correction value of the cell current at high temperature, in order to optimize the write voltage to the memory cell at high temperature. As shown in FIG. 2, the dummy cell write current IrefP is combined (added) with the reference current Iref and input to the high voltage level determination unit 46. Therefore, when the dummy cell write current IrefP is output, the reference current shown in FIG. 3A increases from Iref to (Iref + IrefP), so that the output voltage VH output from the high voltage generating unit 42 increases.

Next, the dummy cell current generation unit 52 will be described in more detail with reference to FIG. As shown in FIG. 4, the dummy cell current generation unit 52 includes a dummy cell control unit 60, a dummy cell unit 62, and a current mirror unit 64.

The dummy cell unit 62 is a dummy memory cell provided in addition to the original memory cell and operated when acquiring the dummy cell write current IrefP, which is a correction value of the cell current. The dummy cell unit 62 according to the present embodiment is configured by connecting a plurality of dummy cell DCs in parallel. A word line terminal VWL (hereinafter, "VWL terminal") for applying a word line voltage (hereinafter, referred to as <VWL>) from the dummy cell control unit 60 is connected to the common gate, and a dummy cell is connected to the common source. A source line terminal VSL (hereinafter, “VSL” terminal) for applying a source line voltage (hereinafter, referred to as <VSL>) from the control unit 60 is connected. On the other hand, a dummy bit line terminal DBL (hereinafter, "DBL terminal") for applying a dummy bit line voltage (hereinafter, referred to as <DBL>) from the current mirror unit 64 is connected to the common drain. The number of dummy cells DC connected in parallel may be selected appropriately in consideration of the accuracy at the time of acquiring the read current.
Further, as the dummy cell DC, a redundant cell (a memory cell provided for replacement with a defective cell) provided in the semiconductor storage device 10 may be used.

As shown in FIG. 4, the dummy cell control unit 60 includes a VWL control circuit 66 and a VSL control circuit 68. The erase signal ER from the controller 2, the dummy cell write signal DPG, the memory cell write signal PGM, and the output voltage VH from the high voltage output unit 50 are input to the dummy cell control unit 60. The dummy cell control unit 60 outputs an erase signal ER (hereinafter, “ER signal”), a dummy cell write signal DPG (hereinafter, “DPG signal”), a memory cell write signal PGM (hereinafter, “PGM signal”), and an output voltage VH. Upon receiving, the above-mentioned word line voltage <VWL>, source line voltage <VSL>, and dummy bit line voltage <DBL> are generated.

The current mirror unit 64 mirrors the cell current of the dummy cell unit 62 acquired via the DBL terminal at a predetermined ratio to generate a dummy cell write current IrefP. Further, the current mirror unit 64 generates a dummy bit line voltage <DBL> to be applied to the DBL terminal. An ER signal, a DPG signal, and a PGM signal that control the operation of the current mirror unit 64 are also input to the current mirror unit 64.

Next, the writing process to the memory cell array 1 in the semiconductor storage device 10 according to the present embodiment will be described with reference to FIG. 5A. FIG. 5A shows a flowchart of a write process executed by the dummy cell control unit 60 in response to the erase signal ER from the controller 2, the dummy cell write signal DPG, and the memory cell write signal PGM.

In the semiconductor storage device according to the comparative example including the cell voltage generation unit 90 shown in FIG. 11, when a rewrite instruction is issued according to a normal flow, the memory cell area of the area designated as the rewrite target of the memory cell array 1 is erased. , Writing to the memory cell area is performed. On the other hand, in the writing process according to the present embodiment, writing and reading to the dummy cell unit 62 are performed between erasing and writing the memory cell area. In the flowchart of FIG. 5A, the reference current Iref is set so that the cell current becomes optimum at room temperature. Further, in the flowchart of FIG. 5A, it is assumed that the rewrite command has already been issued by the controller 2.

As shown in FIG. 5A, when the erase signal ER is received in step S100, the memory cell area designated for rewriting and the dummy cell portion 62 are erased in the next step S102. In step S102, each of the word line voltage <VWL>, the source line voltage <VSL>, and the dummy bit line voltage <DBL> is set as follows as an example.
<VWL> = Approximately 11V (output voltage VH)
<VSL> = GND
<DBL> = GND
For <VWL>, an output voltage VH of about 11 V generated by the high voltage generating unit 42 is used.
Further, as described above, the setting of <DBL> is performed in the current mirror unit 64.

When the dummy cell write signal DPG is received in the next step S104, writing to the dummy cell unit 62 is executed in step S106. In the present embodiment, the data to be written to the dummy cell unit 62 is set as data “0”. At the time of writing to the dummy cell unit 62 according to the present embodiment, the output of the dummy cell write current IrefP is cut off in the current mirror unit 64. Therefore, when writing to the dummy cell portion 62, a write voltage VW that provides an optimum cell current at room temperature is applied. In step S106, each of <VWL>, <VSL>, and <DBL> is set as follows as an example.
<VWL> = Approximately 1.4V (Z VDD)
<VSL> = Approximately 7.5V (output voltage VH)
<DBL> = approx. 0.3V
At this time, a current of about 4 μA flows as the cell current of the dummy cell portion 62 including the plurality of dummy cell DCs. Z VDD is a voltage generated in the semiconductor storage device 10.

When the memory cell write signal is received in the next step S108, the target voltage VHt, which is the write voltage VW to the memory cell area, is generated according to the procedure from step S110 to step S114 below. In the present embodiment, steps S110 to S114 are shown in a flow, but these steps are executed as a circuit operation of the cell voltage generation unit 40.

In step S110, the dummy cell unit 62 is read out to generate the dummy cell write current IrefP. At this time, the read current in the dummy cell unit 62 flows from the current mirror unit 64 to the dummy cell unit 62 and the VSL terminal via the DBL terminal, and the dummy cell write current IrefP mirrors the read current at a predetermined ratio. Generate.

In the next step S112, the dummy cell write current IrefP generated in step S110 is combined (added) with the reference current Iref, and the reference current is set to the target current Ireft = (Iref + IrefP). The high voltage level determination unit 46 that has received the target current Ireft generates the CPUMP control signal CPUMPEN based on the target current Ireft.

In the next step S114, the high voltage generation unit 42 that has received the CPUMP control signal CPUMPEN charges up until the output voltage VH reaches the target voltage VHt based on the CPUMP control signal CPUMPEN. The target voltage VHt generated in step S114 is applied to the memory cell area to be written as a write voltage VW via the high voltage output unit 50.

In the next step S116, writing to the target memory cell area is executed. The write voltage VW when writing is performed in step S116 is the target voltage VHt generated in step S114. In step S116, each of <VWL>, <VSL>, and <DBL> is set as follows as an example.
<VWL> = Approximately 2.5V (VD25)
<VSL> = GND
<DBL> = approx. 0.5V
The VD 25 is a voltage generated in the semiconductor storage device 10.
After that, this writing process is terminated.

FIG. 5B shows the relationship between the above-mentioned control signal and the voltage applied to each terminal. In FIG. 5B, for example, when the erasure signal ER is “1” (H) and active, the voltages applied to each terminal are <VWL> = 11.0V, <VSL> = GND (0V), <DBL. > = It means that it is set to GND.

Next, a specific circuit of the dummy cell control unit 60 and the current mirror unit 64 will be described with reference to FIGS. 6 to 9. 6 and 7 show a circuit diagram of the VWL control circuit 66, FIG. 8 shows a circuit diagram of the VSL control circuit 68, and FIG. 9 shows a circuit diagram of the current mirror unit 64.

As shown in FIG. 6, the VWL control circuit 66 includes an OR circuit 100, an inverter 101, an OR circuit 102, an inverter 103, level shift circuits 200 and 201, and a selection circuit 202.

The OR circuit 100, the inverter 101, the OR circuit 102, and the inverter 103 generate logical values for controlling the level shift circuits 200, 201, and the selection circuit 202 based on the ER signal, the DPG signal, and the PGM signal.

The level shift circuit 200 is composed of transistors 104, 105, 106, 107, 108, and 109, and the power supply terminal of the level shift circuit 200 is connected to the output voltage VH of the high voltage generating unit 42 described above. On the other hand, the level shift circuit 201 is composed of transistors 110, 111, 112, 113, 114, and 115, and the power supply terminal of the level shift circuit 201 is connected to the power supply VVV. The power supply VVV is supplied from the VVV generation circuit 208 shown in FIG. 7A, which will be described later.

In the selection circuit 202, the circuit unit for supplying the output voltage VH composed of the transistors 117 and 119 and the circuit unit for supplying the power supply VVV composed of the transistors 118 and 120 share one end with the transistors 121 and 122. It is configured to be connected to the output stage (gate) composed of. The wordline voltage <VWL> is output from the output stage.

As shown in FIG. 7A, the VVV generation circuit 208 includes a level shifter 203, an inverter 130, a transfer gate 204 composed of transistors 131 and 132, and a transfer gate 205 composed of transistors 133 and 134. ing. A power supply ZVDD is connected to the transfer gate 204, and a power supply VD25 is connected to the transfer gate 205. The power supply Z VDD and the power supply VD25 are voltages generated inside the semiconductor storage device 10. As shown in FIG. 5B, the power supply Z VDD gives <VWL> in the dummy cell write mode, and the power supply VD25 is in the memory cell write mode. Gives <VWL> in.

The level shifter 203 is a level shift circuit including an input terminal IN, an output terminal OUT, and a power input VI. FIG. 7B shows the internal circuit of the level shifter 203. As shown in FIG. 7B, the level shifter 203 includes an inverter 140, transistors 141, 142, 143, and 144. As shown in FIG. 7B, the level shifter 203 outputs the voltage input to the power input VI in response to the signal input to the input terminal IN.

As shown in FIG. 7A, a DPG signal or a PGM signal is input to the input terminal IN, and a power supply ZVDD or VD25 is input to the power input VI. When the DPG signal is input, Z VDD is input to the power input VI, and the power supply ZVDD is output from the terminal VVV. On the other hand, when the PGM signal is input, the VD25 is input to the power input VI, and the power supply VD25 is output from the terminal VVV.

The VWL control circuit 66 having the above configuration generates <VWL> shown in FIG. 5B based on each of the ER signal, the DPG signal, and the PGM signal. For example, when the ER signal = 1, the transistors 109 and 115 are turned on, and the transistors 117 and 119 are turned on. At this time, since the gates of the transistors 121 and 122 are L, the transistor 121 is turned on, and the output voltage VH is output from the VWL terminal. That is, the output voltage VH (11.0 V because it is in the erasing mode, see FIG. 5B) is output from the VWL terminal via the transistors 117, 119, and 121.

On the other hand, when the DPG signal = 1, power supply Z VDD (1.4V) is generated from the VVV generation circuit 208 shown in FIG. 7A, and this power supply Z VDD is applied to the level shift circuit 201 and the selection circuit 202 as the power supply VVV. Will be done. When the DPG signal = 1, the transistors 108 and 114 are turned on, and the transistors 118 and 120 are turned on. At this time, since the gates of the transistors 121 and 122 are L, the transistor 121 is turned on, and the power supply VVV, that is, the power supply ZVDD is output from the VWL terminal. That is, the power supply Z VDD (1.4V, see FIG. 5B) is output from the VWL terminal via the transistors 118, 120, and 121.

When the PGM signal = 1, a power supply VD25 (2.5V) is generated from the VVV generation circuit 208 shown in FIG. 7A, and this power supply VD25 is applied to the level shift circuit 201 and the selection circuit 202 as the power supply VVV. Will be done. When the PGM signal = 1, the transistors 108 and 114 are turned on, and the transistors 118 and 120 are turned on. At this time, since the gates of the transistors 121 and 122 are L, the transistor 121 is turned on, and the power supply VVV, that is, the power supply VD25 is output from the VWL terminal. That is, the power supply VD25 (2.5V, see FIG. 5B) is output from the VWL terminal via the transistors 118, 120, 121.

As shown in FIG. 8A, the VSL control circuit 68 is composed of a level shifter 203, a DPG signal is input to the input terminal IN, and an output voltage VH is input to the power input VI.
As a result, as shown in FIG. 8 (b), the output voltage VH is output as <VSL> from the output terminal OUT (VH = 7.5 V because it is a dummy cell write mode, see FIG. 5 (b)).

Next, a circuit example of the current mirror unit 64 will be described with reference to FIG. As shown in FIG. 9, the current mirror unit 64 includes transistors 150, 151, 152, 153, 154, and inverters 160 and 162. A DPG signal is input to the gate of the transistor 150 via the inverter 160, a PGM signal is input to the gate of the transistor 152 via the inverter 162, and an ER signal is input to the gate of the transistor 153.

The connection point between the transistors 150 and 152 and the transistor 153 is a DBL terminal. Further, a current mirror circuit is formed by the transistors 151 and 152 and the transistor 154, and the dummy cell write current IrefP is output from the source of the transistor 154. The mirror ratio in the current mirror unit 64 is set by the ratio of the size of the transistor 151 to the size of the transistor 154. A fixed voltage of 0.3 V is connected to the drain of the transistor 150, and a power supply Vdd is connected to the drain of the transistors 151 and 154.

In the current mirror unit 64 shown in FIG. 9, first, in the erase mode, the ER signal is set to 1 (H) and the transistor 153 is turned on, so that <DBL> becomes GND (see FIG. 5 (b)). .. At this time, since DPG = 0 (L) and PGM = 0 (L), the transistors 150 and 152 are turned off. Therefore, the current mirror circuit does not work.

In the dummy cell write mode, the DPG signal = 1, the PGM signal = 0, and the ER signal = 0, so that the transistor 150 is turned on, the transistors 152, and 153 are turned off, and the transistor 150 is connected to the DBL terminal via the transistor 150. 3V is output (see FIG. 5B). Therefore, the current mirror circuit does not work.

In the memory cell write mode, the PGM signal = 1, the DPG signal = 0, and the ER signal = 0, so the transistor 152 is turned on, the transistors 150 and 153 are turned off, and the DBL terminal is passed through the transistors 151 and 152. The cell current flows from the to the dummy cell DC. At this time, <DBL> is set to 0.5V. In the memory cell write mode, the current mirror circuit operates, a dummy cell write current IrefP flows from the transistor 154 toward the Iref terminal of the current detection circuit 70, and is combined with the reference current Iref (see FIG. 3A).

As described above, when writing to the memory cell area in step S116 shown in FIG. 5A, the dummy cell unit 62 is in the read state, so that when writing to the dummy cell unit 62 in step S106. When the writing is shallow (when the writing voltage VW is low), a cell current (reading current) corresponding to the decrease in the writing voltage VW flows, and the dummy cell writing current IrefP is output from the current mirror unit 64. The dummy cell write current IrefP is combined with the reference current Iref to generate a target current Ireft, and the output voltage VH controlled by the target current Ireft is output as the target voltage VHt to write the memory cell area.

Next, with reference to FIG. 10, the operation of the cell voltage generation unit 40 according to the present embodiment will be described. FIG. 10 shows the relationship between the dependence of the detected current Idtc in the cell voltage generation unit 40 on the output voltage VH (FIG. 10 is shown by the curve C1), the reference current Iref, and the target current Ireft.

In FIG. 10, the output voltage VH0 at the intersection P1 of the detection current Idtc characteristic and the reference current Iref indicates the write voltage at room temperature T0. When the ambient temperature of the semiconductor storage device 10 rises to a temperature Tt equal to or higher than room temperature, the dummy cell current generator 52 sets the dummy cell write current IrefP corresponding to the rise temperature ΔT = (Tt−T0) to the reference current Iref. It is added to obtain the target current Temperature. The higher the temperature Tt, the larger the dummy cell write current IrefP, that is, the target current Ireft, and as a result, the target voltage VHt also shifts to the higher voltage side (intersection point P2 in FIG. 10).

That is, according to the semiconductor storage device and the writing method to the semiconductor storage device according to the present embodiment, the dummy cell unit 62 is always rewritten and read out during the rewriting operation, and the result is reflected. Writing to the corresponding memory cell array 1 is executed. As a result, when the writing to the dummy cell portion 62 is shallow (when the writing voltage VW is low), the dummy cell writing current IrefP increases and is added to the reference current Iref, so that the writing is performed by the output voltage shifted to the high voltage side. be able to. As a result, since writing is always performed by the optimum writing voltage VW for the cell current, deterioration of the reading characteristics from the memory cell array 1 is suppressed.

In the present embodiment, a mode in which the reference current is corrected by constantly writing and reading to the dummy cell unit 62 when writing to the memory cell has been described as an example, but the present invention is not limited to this, and the dummy cell unit is not limited to this. Writing to and reading from 62 may be stopped. In this case, for example, when the dummy cell write current IrefP does not occur in the rewriting to the memory cell a predetermined number of times, the writing to the dummy cell unit 62 is performed in the next rewriting to the memory cell a predetermined number of times. The reading may be stopped.

1 Memory cell array 2 Controller 3 Low driver 4 Column driver 10 Semiconductor storage device 40 Cell voltage generation unit 42 High voltage generation unit 44 High voltage level detection unit 46 High voltage level determination unit 48 Reference current generation unit 50 High voltage output unit 52 Dummy cell current Generation unit 60 Dummy cell control unit 62 Dummy cell unit 64 Current mirror unit 66 VWL control circuit 68 VSL control circuit 70 Current detection circuit 72 Comparator 74 Level detection circuit 90 Cell voltage generation unit 92 High voltage generation unit 94 High voltage level detection unit 96 High voltage Level determination unit 98 Reference current generation unit 99 High voltage output unit 100 OR circuit 101 Inverter 102 OR circuit 103 Inverter 130, 140 Inverter 160, 162 Inverter 200, 201 Level shift circuit 202 Selection circuit 203 Level shifter 204, 205 Transfer gate 208 VVV generation Circuit CPUMPEN CPUMP control signal DC Dummy cell VH, VH0 Output voltage VHt Target voltage VW Write voltage Idtc Detection current Iref Reference current IrefP Dummy cell write current VWL Wordline terminal VSL Source line terminal DBL Dummy bitline terminal DPG Dummy cell write signal ER Signal PGM Memory cell write signal NM1 to NMn NMOS transistor TP1 to TP3 ProLiant transistor TN1 to TN5 NMOS transistor

Claims (7)

A memory cell array composed of multiple memory cells and
A high voltage generator that boosts the power supply voltage and generates a high voltage that is the cell voltage applied to each of the plurality of memory cells.
A correction current generator that generates a correction current for correcting fluctuations in the cell voltage with respect to the ambient temperature.
Then, the detection current obtained by converting the high voltage into a current and the target current for maintaining the high voltage at the target voltage are compared to generate a control signal for controlling the boosting operation in the high voltage generating unit, and at room temperature. A control signal generator that adds the reference current, which is the target current corresponding to, and the correction current to obtain the target current.
With a cell voltage generator
Semiconductor storage device including. The high voltage generating unit includes a charge pump unit that boosts the power supply voltage.
The control signal generation unit is a high voltage level detection unit including a transistor that outputs a current flowing due to the breakdown as the detection current when the high voltage exceeds the breakdown voltage, and a reference current for generating the reference current. The semiconductor storage device according to claim 1, further comprising a generation unit and a high voltage level determination unit that generates a signal for stopping the charge pump unit as the control signal when the detection current is equal to or higher than the target current. The cell voltage is a write voltage applied to the memory cell when writing predetermined data to the memory cell.
The write voltage at which the read current flowing through the memory cell when the target voltage is read after the predetermined data is written to the memory cell when the ambient temperature changes becomes equal to the read current at room temperature. The semiconductor storage device according to claim 1 or 2. The correction current generation unit includes a dummy cell unit including a plurality of dummy cells having the same configuration as the memory cell, a current output unit that outputs the read current in the dummy cell unit by multiplying it by a predetermined coefficient, and the above. Equipped with a dummy cell control unit that controls the operation of the dummy cell unit
When writing data to at least a part of the memory cell area of the memory cell array, the dummy cell control unit writes the predetermined data to the dummy cell unit after erasing the memory cell area and the dummy cell unit. The current output unit is controlled so that the correction current is output based on the read current when the predetermined data written thereafter is read from the dummy cell unit, and the data is output from the high voltage generation unit. The semiconductor storage device according to claim 3, wherein writing to the memory cell area is performed by the corrected target voltage. The memory cell is composed of a field effect transistor having a floating gate.
The semiconductor storage device according to claim 3 or 4, wherein the predetermined data is data in which the read current when read after being written in the memory cell is substantially zero. The relationship between the write voltage of the memory cell and the read current is such that the write voltage that gives the same read current rises as the ambient temperature rises.
The semiconductor storage device according to claim 5, wherein the correction current generation unit generates the correction current according to an increment of the ambient temperature from room temperature. A field-effect transistor type memory cell having a floating gate, a dummy cell portion having the same configuration as the memory cell and used for correcting a write voltage when writing to the memory cell, and a power supply voltage are boosted to obtain the write voltage. In a semiconductor storage device provided with a high voltage generator that generates a high voltage, the read current when a predetermined data is written to the memory cell is equal to the read current at room temperature due to a change in ambient temperature. It is a writing method to a semiconductor storage device that writes while correcting fluctuations in the writing voltage.
When a rewrite instruction is received, the memory cell and the dummy cell portion are erased, and the memory cell and the dummy cell portion are erased.
The predetermined data is written in the dummy cell portion,
The predetermined data written in the dummy cell unit is read out to acquire the read-out current, and the correction current is generated based on the read-out flow.
Based on the comparison result of comparing the detected current obtained by converting the high voltage into a current, the reference current based on the read current at room temperature, and the correction current, the boosting operation in the high voltage generating portion is controlled and corrected. Get the write voltage and
A method of writing to a semiconductor storage device that writes to the memory cell by the corrected write voltage.

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