JP2012223001A - Inverter controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter controller provided with a detector capable of more quickly replacing a value of one phase with an estimated value obtained from detected values in the other two phases when abnormality occurs in the one phase.SOLUTION: An inverter controller is constituted of: an inverter 2; voltage detecting means 5; controlling means 4; and emergency automatic switching means 6 that receives outputs from the voltage detecting means 5, switches to three-phase voltages obtained by calculating other two phases even when one phase of the voltage detecting means 5 is disconnected and provides the controlling means 4 with the three-phase voltages obtained. The emergency automatic switching means 6 includes: voltage magnitude calculating means 61 arranged so as to define outputs from the voltage detecting means 5 for two phases different from each other out of the three-phase voltages as inputs and a value obtained by calculating voltages of the two phases for other one phase as an input and to obtain the sum of voltage magnitude of inputs of three phases; three units of abnormality detecting means for determining to be abnormal when a difference between each of calculation results of the voltage magnitude calculating means 61 and a determination value is not less than a predetermined value; and identifying means for identifying a disconnected phase when two units out of the three units of the abnormality detecting means become abnormal.

Description

  The present invention relates to an inverter control device having a function of detecting an output voltage of an inverter.

  A conventional inverter control device is used, for example, to drive an electric motor at a variable speed, and usually detects at least one of an output voltage and current for controlling the motor or monitoring protection. If the output is three-phase, the detector is usually three-phase, but if one of the three phases is disconnected, the control operation becomes abnormal and the inverter control device stops. there were.

  To solve this problem, identify the phase that became abnormal due to disconnection or the like in the current detection of three phases, and continue operation by obtaining an alternative value by calculation using the other two phase detection values that are normal (For example, refer to Patent Document 1).

Japanese Patent No. 3737370 (page 4-5, FIG. 1)

  The method disclosed in Patent Document 1 includes three current detectors that detect the output current of the inverter, a waveform storage device that stores a waveform to calculate the effective value of the current detector, and a waveform storage device that stores the waveform. An effective value detector that determines the effective value from the measured waveform, and an effective value comparator that detects in which phase the abnormal part occurred by comparing the output current effective value of each phase of the inverter from the effective value detector This is due to the inverter control device having a switch for switching to the calculated current value calculated from the detected current value of the other phase instead of the detected current value of the abnormal phase, but to derive the effective current value Since an AC effective value is used for the current value, a delay time occurs until the current value of the phase that has become abnormal is converted to an effective value. For this reason, the detection of the abnormal current detector is delayed, and in some cases, an abnormal current is detected during this delay time, and the apparatus stops.

  The present invention has been made in order to solve the above-described problems. When there is an abnormality for one phase, the detector can be replaced with the estimated value from the detected values of the other two phases more quickly. It aims at providing the inverter control apparatus provided with.

  In order to achieve the above object, an inverter control device according to the present invention detects a voltage of an inverter that receives a direct current input and converts the direct current into an alternating current and a three-phase output of the inverter, or detects a current to obtain a voltage. The voltage detection means for conversion, the control means for controlling the inverter using the output of the voltage detection means, and the three-phase voltage of the voltage detection means, and one phase of the voltage detection means is disconnected. Is also provided with an automatic switching means for abnormal time that is applied to the control means by switching to the three-phase voltage obtained by calculation from the other two phases, and the automatic switching means for abnormal time is for two different phases of the three-phase voltage. The output of the voltage detection means is used as an input, and the value obtained by calculation from the voltage for these two phases is input for the other one phase, and the sum of the input voltages for these three phases is obtained. 3 units of voltage Three abnormalities that are determined to be abnormal when the absolute value of the difference between the calculation result of each of the magnitude calculation means and the three voltage magnitude calculation means and the predetermined determination value is greater than or equal to a first predetermined value It has a detection means and a means for specifying a phase that is disconnected when two of the abnormality detection means become abnormal.

  According to the present invention, since the abnormality detector capable of instantaneous value detection is used, when there is an abnormality for one phase, the estimated value from the other two-phase detection values can be replaced more quickly. It is possible to provide an inverter control device equipped with a detector capable of performing the above.

The block block diagram of the inverter control apparatus which concerns on Example 1 of this invention. The internal block diagram of the switching circuit at the time of abnormality of the inverter control apparatus which concerns on Example 1 of this invention. The internal block diagram of the switching circuit at the time of abnormality of the inverter control apparatus which concerns on Example 2 of this invention. The internal block diagram of the switching circuit at the time of abnormality of the inverter control apparatus which concerns on Example 3 of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  Hereinafter, an inverter control apparatus according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of an inverter control device according to Embodiment 1 of the present invention, and FIG. 2 is an internal configuration diagram of an abnormal time switching circuit used in the inverter control device according to Embodiment 1 of the present invention.

  In FIG. 1, a DC voltage is applied to a DC capacitor 1 from a DC power source (not shown). The DC voltage smoothed by the DC capacitor 1 is converted into a three-phase AC voltage by the inverter 2, and the AC motor 3 is driven by the three-phase AC voltage. Here, the load of the inverter 2 does not necessarily need to be the AC motor 3, and may be an arbitrary load. The inverter 2 is controlled by the control device 4. Specifically, the switching elements constituting the inverter 2 are on / off controlled by gate pulses supplied from the control device 4 so that the inverter 2 outputs a desired output voltage and output frequency.

  A three-phase voltage detector 5 is provided at the output of the inverter 2. The output of each phase of the voltage detector 5 is given to the control device 4 via the automatic switching circuit 6 at the time of abnormality. Here, the voltage detector 5 may be a current detector. In this case, it is sufficient to convert the current detected by the current detector into a voltage and develop the following discussion.

  The abnormal-time automatic switching circuit 6 includes a voltage magnitude calculation means 61 for detecting the magnitude of the instantaneous voltage, a failure detector 62 for identifying a phase that has failed (disconnected) based on the detected value, and a failure detector 62. And a switch 63 for switching so that the detected voltage of the failed phase is obtained by calculation from the other two phases in accordance with the detection result.

  FIG. 2 shows the internal configuration of the abnormality automatic switching circuit 6. The voltage magnitude calculation means 61 includes three voltage magnitude calculators 61A, 61B and 61C. The voltage magnitude calculator 61A is supplied with voltages Vuv0 and Vvw0 detected by the voltage detector 4 and Vwu ^ calculated by the calculator 61D as inputs. The calculator 61D is supplied with the voltages Vuv0 and Vvw0, and calculates and outputs Vwu ^ = − (Vuv0 + Vvw0). Similarly, the voltage magnitude calculator 61B is supplied with the voltages Vvw0 and Vwu0 detected by the voltage detector 4 and Vuv ^ calculated by the calculator 61E. The calculator 61E is supplied with the voltages Vvw0 and Vwu0, and calculates and outputs Vuv ^ = − (Vvw0 + Vwu0). Similarly, the voltage magnitude calculator 61C is supplied with voltages Vwu0 and Vuv0 detected by the voltage detector 4 and Vvw ^ calculated by the calculator 61F. The calculator 61F is supplied with the voltages Vwu0 and Vuv0, and calculates and outputs Vvw ^ = − (Vwu0 + Vuv0).

  The voltage magnitude calculators 61A, 61B and 61C calculate the magnitudes of the three input voltages, respectively. Here, the magnitude of the voltage is a sum of squares. The magnitude of the voltage in the present invention may be the sum of the magnitudes of the three inputs, for example, the square root of the sum of squares, or the sum of the cubes or the sum of absolute values. However, as described later, the disconnection detection can be performed with higher accuracy by using the square sum or the square root of the square sum as the magnitude of the voltage.

  The calculation outputs of the voltage magnitude calculators 61A, 61B and 61C are given to the failure determiners 62A, 62B and 62C, respectively. The failure determiners 62A, 62B and 62C determine that a failure occurs when the detection signal is different from a predetermined value in a predetermined short time, and the logic signal 1 is determined as AND circuits 63A and 63C, AND circuits 63B and 63A, respectively. Also output to AND circuits 63C and 63B.

  The outputs of the AND circuits 63A, 63B and 63C are given to the changeover switches 63D, 63E and 63F, respectively. The change-over switches 63D, 63E, and 63F always output Vuv0, Vvw0, and Vwu0 to the control device 4 as detection phase voltages Vuv, Vvw, and Vwu, respectively, but when the outputs of the AND circuit are received, The signals Vuv, Vvw and Vwu are switched to Vvw ^, Vwu ^ and Vuw ^, respectively.

Next, the operation will be described. Assume that a three-phase AC detection voltage is given by the following equation.
Vuv0 = sinθ (1)
Vvw0 = sin (θ−120 °) (2)
Vwu0 = sin (θ + 120 °) (3)
At this time, assuming that the voltage magnitude calculator 61 detects the sum of squares, all voltage magnitude calculators detect a constant value regardless of the time as shown in the equation (4) at normal times. is doing.
y = sin ² θ + sin ² (θ−120 °) + sin ² (θ + 120 °)
= 2/3 (4)
In such a state, it is assumed that the detection phase Vuv0 is disconnected. Then
Vuv0 = sin θ = 0 (5)
At this time, the voltage magnitude calculator 61A detects the following.
y = 0 + sin ² (θ−120 °) + {− 0−sin (θ−120 °)} ²
= 2sin ² (θ−120 °) (6)
Similarly, the voltage magnitude calculator 61C detects the following.
y = sin ² (θ + 120 °) +0 + {− 0−sin (θ + 120 °)} ²
= 2sin ² (θ + 120 °) (7)

In the above situation, Vuv0 is not used in the voltage magnitude calculator 61B, and the detected value is given by equation (4). Therefore, the failure determination circuit 62A can make a failure determination by detecting that the expression (6) is different from the expression (4). Similarly, the failure determination circuit 62C can make a failure determination by detecting that the expression (7) is different from the expression (4).

Here, if the disconnection occurs when the equations (6) and (4) are equal, a detection delay occurs. In the equation (6), ² sin ² (θ−120 °) = 3/2 at θ = 0 ° or θ = 60 °. Similarly, in formula (7), ² sin ² (θ−120 °) = 3/2 when θ = 0 ° or θ = −60 °. In the case of θ = 0 °, as shown in the equation (5), since the disconnection occurs when the output is zero in the state where the disconnection does not occur, there is substantially no problem even if there is a detection delay. However, there may be a problem that a detection delay occurs at θ = 60 ° or θ = −60 °. This countermeasure will be described later in Examples 2 and 3.

  At a timing other than the singular point, the failure determination circuit 62A and the failure determination circuit 62C quickly detect a failure at the same time, and the AND circuit 63C outputs 1 to switch the changeover switch 63F, so that the disconnection detection phase Vuv is set to the other two. It is switched to the phase calculation output. In the above description, the case where the detection phase Vuv0 is disconnected has been described. However, it is obvious that the same argument holds even when the detection phase Vvw0 or Vwu0 is disconnected.

  The reason that the voltage magnitude calculator 61 preferably uses the sum of squares or the square root of the sum of squares is that the normal value is a constant value regardless of time as shown in the equation (4). It is to become. In this case, the failure determiner 62 may determine whether the absolute value of the difference between the voltage magnitude calculator 61 and the constant value or the short-time integrated value of the absolute value of the difference exceeds a predetermined value.

  FIG. 3 is an internal configuration diagram of an abnormal time switching circuit of the inverter control device according to the second embodiment of the present invention. In the second embodiment, the same parts as those in the internal configuration diagram of the abnormality switching circuit of the inverter control apparatus according to the first embodiment of the present invention shown in FIG. Also, illustration of set / reset signal lines described below is omitted. The second embodiment is different from the first embodiment in that signal holding circuits 63G, 63H, and 63I are provided at normal input portions of the voltages of the changeover switches 63D, 63E, and 63F, respectively.

  The signal holding circuits 63G, 63H, and 63I are configured to be set / reset. Then, for example, when the input / output is short-circuited to set a reset state and any of the failure determination circuits 62A, 62B and 62C detects a failure, two of the signal holding circuits are set. For example, when the failure determination circuit 62A detects a failure, there is a possibility that Vuv0 or Vvw0 is disconnected, so that the corresponding signal holding circuits 63G and 63I are set. For example, when the failure determination circuit 62C detects a failure after a short time has elapsed, the AND circuit 63C outputs 1 and switches the changeover switch 63F (that is, the disconnection phase in this case is Vuv0). At this time, the signal holding circuit 63G and 63I is reset.

  With the configuration as described above, Vuv0 and Vvw0 are held for the time during which the signal holding circuits 63G and 63I are operating, resulting in detection errors, but the errors are slight, and the problems described in the first embodiment are as follows. Improved. Note that the holding times of 63G, 63H, and 63I are set to be equal to or greater than the maximum value of the detection delay when disconnection occurs near θ = −60 ° or θ = 60 ° when Vuv0 = sin θ as described above. You may comprise so that it may reset automatically, when the holding | maintenance time passes.

  FIG. 4 is an internal configuration diagram of an abnormal time switching circuit of the inverter control device according to the third embodiment of the present invention. In the third embodiment, the same parts as those in the internal configuration diagram of the abnormal state switching circuit of the inverter control device according to the first embodiment of the present invention shown in FIG. Also, illustration of signal lines between failure determiners described below is omitted. The third embodiment is different from the first embodiment in that a phase detection circuit 64 that detects a voltage phase from a three-phase input voltage, outputs a phase synchronization signal, and supplies the phase determination signal to a failure determination circuit is provided.

As described in the first embodiment, when Vuv0 is disconnected at θ = 60 °, the voltage magnitude calculator 61A outputs 2/3, so the determination circuit 62A does not operate. At this time, the output of the voltage magnitude calculator 61C is 2sin ² (θ + 120 °) = 0, and the deviation from the normal value 2/3 is the maximum.

On the other hand, when Vwu0 is disconnected, the output of the voltage magnitude calculator 61C is
y = 0−sin ² θ + 0 + {− 0−sin θ} ² = 2sin ² θ (8)
Is detected. Since this value becomes 0 at θ = 0 ° and 180 °, it can be seen that the detection phase is different from that when Vuv0 is disconnected.

  From the above, when any one of the voltage magnitude calculators 61 detects a failure when the deviation from the normal value 2/3 is near the maximum value, the other two voltage magnitude calculations are performed according to the voltage phase at that time. It is possible to specify which one of the devices should originally detect disconnection. Thus, in FIG. 4, when any one of the voltage magnitude calculators 61 detects a failure when the deviation from the normal value 2/3 is near the maximum value, the other phase is identified from the phase synchronization signal, If the identified other one phase performs the failure determination, it is possible to avoid the fear of an abnormal voltage output as described in the first embodiment.

  Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  For example, the signal holding circuit in the second embodiment may be always inserted as a delay circuit, and it may be possible to prevent disturbance at the time of switching by always holding a signal for a short time. Further, the phase detection circuit according to the third embodiment can employ, for example, a majority-based calculation so as to obtain a correct phase synchronization signal when two phases are normal among three phase voltages.

DESCRIPTION OF SYMBOLS 1 DC capacitor 2 Inverter 3 AC motor 4 Controller 5 Voltage detector 6 Automatic switching circuit 61 at the time of abnormality Voltage magnitude | size calculating means 61A, 61B, 61C Voltage magnitude | size calculator 61C, 61D, 61E Calculator 62 Fault detector 62A, 62B, 62C Failure determiner 63 Switch 63A, 63B, 63C AND circuit 63D, 63E, 63F Changeover switch 63G, 63H, 63I Signal holding circuit 64 Voltage phase detection circuit

Claims (5)

An inverter that receives direct current input and converts this direct current to alternating current;
Voltage detection means for detecting the voltage of the three-phase output of the inverter, or detecting current and converting it to voltage;
Control means for controlling the inverter using the output of the voltage detection means;
An abnormal-time automatic switching means that receives the three-phase voltage of the voltage detection means and switches to the three-phase voltage obtained by calculation from the other two phases even if one phase of the voltage detection means is disconnected, and gives it to the control means Equipped,
The abnormal time automatic switching means,
Among the three-phase voltages, the output of the voltage detection means for two different phases is input, and the other one phase is input by a value obtained by calculation from the voltages for these two phases. Three voltage magnitude calculation means for obtaining the total of the voltage magnitudes of
Three abnormality detection means for determining an abnormality when the absolute value of the difference between the calculation result of each of the three voltage magnitude calculation means and the predetermined determination value is equal to or greater than a first predetermined value;
An inverter control apparatus comprising: means for identifying a phase that is disconnected when two of the abnormality detection means become abnormal.   2. The inverter control apparatus according to claim 1, wherein the voltage magnitude calculation means calculates a square sum of input voltages or a square root of the square sum. The three-phase outputs of the voltage detection means are supplied to the control means via holding means that can be set / reset,
When one of the abnormality detection means becomes abnormal, the holding means for two phases detected by the abnormality detection means is set,
The inverter control device according to claim 1 or 2, wherein when the other one of the abnormality detection means becomes abnormal, the holding means is reset. Voltage phase detection means for detecting the voltage phase of the three-phase output of the inverter;
One of the abnormality detection means becomes abnormal, and the absolute value of the difference between the calculation result of the voltage magnitude calculation means corresponding to the abnormality detection means and the predetermined determination value is greater than or equal to a second predetermined value. When
The abnormal time automatic switching means,
The inverter control device according to claim 1 or 2, wherein a disconnected phase is specified from a detection phase of the voltage phase detection means.   5. The inverter control device according to claim 1, wherein the three-phase output of the voltage detection unit is supplied to the control unit via a short-time delay unit. .

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