JP2012222979A - Dc power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-cost, small-size, and high-efficiency DC power supply device, which converts an extremely large power into a direct current using FETs composed of a wide-bandgap semiconductor, by applying positive and negative driving voltages to each of the FETs by one driving power supply.SOLUTION: A DC power supply device comprises a rush-current protection circuit 1 at an input stage and driving circuits D3 to D6 independent for each of FETs 3 to 6. The FETs 3 and 5 on the high-voltage side are driven by a driving transformer 14. In the FETs 4 and 6 on the low-voltage side, a gate voltage can be supplied by a capacitor 24 for negative bias that is charged by a driving power supply 17 and a current flowing through the FETs 4 and 6.

Description

  The present invention relates to a DC power supply device (DC / DC converter circuit) that converts an input DC voltage into a stable DC voltage that can be used in a load-side connection device, and in particular, gallium nitride (hereinafter referred to as “GaN”) and silicon carbide ( The present invention relates to a compact and low-loss DC power supply device using a wide band gap semiconductor such as “SiC” as a switching element.

Conventionally, a DC power supply device (DC / DC converter circuit) that converts an input DC voltage into a stable DC voltage that can be used in a load device is required to be small, light, and low loss.
As this type of DC power supply device, a DC / DC converter circuit based on a switching system is generally used. In particular, in a circuit using a power semiconductor element using silicon (hereinafter referred to as “Si”), on-resistance and Although a reduction in saturation voltage is required, it is reaching a technical limit, and with this, the circuit efficiency has reached its peak.

  However, in recent years, as a result of research on a wide band gap semiconductor having a value about twice (= 2.2 [eV]) or more than the Si band gap (= 1.12 [eV]). Switching devices using FETs and SiC using GaN, which have a low on-resistance, a high breakdown voltage, a large current, and capable of high-speed switching, are beginning to be used.

In general, it is known that an FET using GaN or SiC can reduce switching loss, and can provide a small and highly efficient DC / DC converter circuit.
However, MOSFETs made of GaN or SiC, which are currently in practical use, occupy most of the elements that are turned on when the gate voltage threshold is low (or when no gate voltage is applied).

  Therefore, in order to drive a MOSFET made of GaN or SiC, a positive power source and a negative power source are prepared, a positive voltage is applied to the FET gate when the FET is on, and a negative voltage is applied to the FET gate when the FET is off. A drive circuit capable of applying a voltage is required.

  In addition, when a MOSFET made of GaN or SiC that may be turned on when no gate voltage is applied is used for a power supply circuit, the input voltage may always be short-circuited. Therefore, a circuit element such as a protective element for preventing a short circuit or a breaker is required, and there is a problem that it cannot be mounted on a small power supply device.

  As described above, when a MOSFET using GaN or SiC that may be turned on when no gate voltage is applied is used in the power supply circuit, a negative voltage is always applied to the FET gate when the power supply circuit is stopped. There was a problem that a separate power source was required to do this.

  In particular, taking a full-bridge switching power supply often used in a power supply circuit with high output power as an example, a power supply capable of outputting both positive and negative voltages is used as a drive power supply for two FETs connected to the high voltage side. Since two sets are required and one power supply that can output both positive and negative voltages is required for the two FETs connected to the low voltage side, a power supply that can output both positive and negative voltages in total is required. Since three sets are also required, it is difficult to reduce the size of the power supply device.

  Therefore, a DC power supply device has been proposed in which only a low-voltage side FET is provided with a separate power supply for applying a negative gate voltage even when the power supply is stopped (see, for example, Patent Document 1).

JP 2004-242475 A

  According to the circuit configuration described in Patent Document 1, the conventional DC power supply device requires a separate negative power source that starts before the input voltage is applied, and a separate power source for operating the control system. Therefore, it is difficult to reduce the size of the power supply device, and in the case of a circuit configuration with only one input power supply, the input power supply is divided into a plurality of semiconductor switches and mechanical switches, and a time difference is set for each power-on procedure. In this case, a sequence circuit for control is required, which further increases the scale of the power supply circuit, which makes it impossible to reduce the size of the entire apparatus.

  In addition, when rectifying and smoothing the output voltage of a three-phase generator used in a power supply system for ships or aircraft with a three-phase bridge circuit, positive and negative power supplies are applied to each of the three FETs on the high voltage side. Since it is necessary to provide a power source with high withstand voltage performance for preventing damage, there is a problem that the entire circuit is further increased in size.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a DC power supply device that can be reduced in price and size while ensuring safety by preventing a short-circuit accident. To do.

  A DC power supply device according to the present invention is a DC power supply device configured by connecting a plurality of FETs made of a wide band gap semiconductor in a full bridge shape, and a drive circuit for driving each of the plurality of FETs, A control IC that controls the on / off ratio and operation timing of each of the plurality of FETs, an inrush current protection circuit that protects an inrush current when each of the plurality of FETs starts to be turned on, and a plurality of FETs A drive power supply for supplying power to drive the first FET that drives the first FET connected to the high voltage side of the plurality of FETs, and the plurality of FETs And a second drive circuit for driving a second FET connected to the low voltage side. The first drive circuit is a drive transistor inserted between the gate and source of the first FET. The second drive circuit includes a positive bias capacitor and a negative bias capacitor inserted in series between both ends of the drive power supply, and the second drive circuit is charged with the negative bias capacitor. The negative bias capacitor is charged by the current flowing through the second FET via the current transformer.

  According to the present invention, for example, in the case of the full bridge method, both the positive and negative gate voltages can be supplied to each FET with one drive power supply for four FETs, which are made of GaN or SiC. In addition, since a MOSFET having a low on-resistance and a low gate threshold voltage can be operated safely without malfunctioning, a very small and low-loss DC power supply device can be obtained at a low price.

It is a block diagram which shows the circuit structure of the DC power supply device which concerns on Embodiment 1 of this invention. 2 is a timing chart showing the circuit operation according to the first embodiment of the present invention with voltage waveforms at various parts in FIG. 2 is a timing chart showing the circuit operation according to the first embodiment of the present invention with voltage waveforms at various parts in FIG. It is a block diagram which shows the circuit structure of the conventional DC power supply device as a comparative example.

Embodiment 1 FIG.
Hereinafter, a DC power supply according to Embodiment 1 of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a circuit configuration according to the first embodiment of the present invention. FIGS. 2 and 3 are timing charts showing circuit operations according to the first embodiment of the present invention with voltage waveforms at respective parts in FIG. is there.

  1, the DC power supply according to Embodiment 1 of the present invention includes an inrush current protection circuit 1 inserted on the input side, and an input inserted between the output terminal of the inrush current protection circuit 1 and the ground GND. FET 3, 4 made of a wide band gap semiconductor inserted in series between the capacitor 2, the output terminal of the inrush current protection circuit 1 and the ground GND, and a wide band gap semiconductor connected in parallel to the FET 3, 4 FET5 and 6 which become.

  Further, the DC power supply device includes a switching transformer 7 having a primary winding inserted between a connection point of FETs 3 and 4 and a connection point of FETs 5 and 6, and the primary winding of the switching transformer 7. A resonance choke coil 8 is inserted into the coil.

Further, the DC power supply device controls the drive circuits D3 to D6 individually connected to the gate terminals of the FETs 3 to 6, the drive power supply 17 that supplies power to the drive circuits D3 to D6, and the drive circuits D3 to D6. And a control IC 32 that controls the drive of the inrush current protection circuit 1 and the drive signal circuit 30.
The drive circuits D3 and D5 have the same configuration, and the drive circuits D4 and D6 have the same configuration.

  The drive circuits D3 and D5 include a capacitor 10, an NPN transistor 11 and a PNP transistor 12 inserted in series between both ends of the capacitor 10, and a DC cut capacitor 13 connected to a connection point between the transistors 11 and 12. The drive transformer 14 having the primary winding connected to the DC cut capacitor 13, the current limiting resistor 15 connected to the secondary winding of the drive transformer 14, and the reverse current connected in the forward direction to the power supply terminal of the capacitor 10 And a prevention diode 16.

A drive signal from the drive signal circuit 30 is applied to the gates of the transistors 11 and 12.
One end of the secondary winding of the drive transformer 14 is connected to the gates of the FETs 3 and 4 via the current limiting resistor 15, and the other end is connected to the sources of the FETs 3 and 4.

  The drive circuits D4 and D6 include a positive bias capacitor 20 and a negative bias capacitor 24 inserted in series between both ends of the drive power supply 17, and an NPN transistor 21 and a PNP inserted in series between both ends of the drive power supply 17. A type transistor 22, a current limiting resistor 23 connected to the connection point of each transistor 21, 22, and a resistor 28 inserted between the gate of each transistor 21, 22 and the negative electrode of the drive power supply 17. Yes.

  The drive circuits D4 and D6 include a current transformer 25 having a primary winding inserted between both ends of the negative bias capacitor 24, a rectifier diode 26 inserted in the primary winding of the current transformer 25, a negative A zener diode 27 inserted between both ends of the bias capacitor 24 is connected.

A drive signal from the drive signal circuit 30 is applied to the gates of the transistors 21 and 22, and the connection point of the transistors 21 and 22 is connected to the gates of the FETs 4 and 6 through the current limiting resistor 23. Yes.
Further, the connection point of the capacitors 20 and 24 is connected to the sources of the FETs 4 and 6 and the secondary winding of the current transformer 25.

  The inrush current protection circuit 1 prevents an excessive current from flowing when the primary power source is turned on while the input capacitor 2 connected to the input side of the DC power supply device has no electric charge, and the DC power supply device operates. When starting the operation, even if the FETs 3 and 4 and the FETs 5 and 6 connected in series are short-circuited to the arm, an excessive short-circuit current flows to protect the FETs 3 to 6 from being damaged. In addition, the input voltage with respect to a DC power supply device is DC270 [Vrms], for example.

  In the DC power supply device shown in FIG. 1, two FETs 3 to 6 are connected in series with each other, and FETs 3 and 6 connected in a hooked manner to the primary winding of the switching transformer 7. In the ON state, a current a (broken arrow) flows through a path of FET3 → resonance choke coil 8 → primary winding of the switching transformer 7 → FET6 → ground GND.

  When the FETs 3 and 6 are turned off and the FETs 4 and 5 are turned on instead, the current b (one point) is obtained through the path of the FET 5 → the primary winding of the switching transformer 7 → the resonance choke coil 8 → the FET 4 → the ground GND. A chain line) flows.

Thereby, on the secondary side of the switching transformer 7, a voltage and a current corresponding to a winding ratio between the primary side and the secondary side are generated to transmit electric power.
The resonance choke coil 8 connected in series to the primary side of the switching transformer 7 constitutes a resonance coil for delaying the current that flows when the FETs 3 to 6 are switched to realize soft switching. .

Here, in the drive circuits D3 and D5 for driving the FETs 3 and 5 on the high voltage side, description will be given focusing on one drive circuit D3.
In the drive circuit D3, two (NPN type and PNP type) transistors 11 and 12 for amplifying a drive signal are connected to a capacitor 10 serving as an energy bank in a totem pole shape.

  As a result, the output signals from the emitters of the two transistors 11 and 12 connected in series are input to the drive transformer 14 via the DC cut capacitor 13, and the output signal from the drive transformer 14 is the current limiting resistor 15. To be input to the gate of the FET 3.

  For example, when the drive signal from the drive signal circuit 30 becomes “High”, the NPN transistor 11 is turned on, and the stored voltage of the capacitor 10 is applied to the primary side of the drive transformer 14, and at the same time, the DC cut is performed. Charge is stored in the capacitor 13.

  Next, when the drive signal becomes “Low”, the NPN transistor 11 is turned off and at the same time the PNP transistor 12 is turned on, and the charge stored in the DC cut capacitor 13 is discharged while the drive transformer 14 is discharged. Is applied to the primary side, and a voltage opposite to that described above is applied.

In this way, when the voltage on the primary side of the drive transformer 14 is swung to both positive and negative, positive and negative voltages proportional to the winding ratio are also generated on the secondary side of the drive transformer 14.
Therefore, when a positive / negative voltage from the secondary side of the drive transformer 14 is applied to the gate of the FET 3, the FET 3 is repeatedly turned on / off alternately.

In the drive circuit D3, the backflow prevention diode 16 connected to the capacitor 10 prevents backflow when the discharge charge of the capacitor 10 consumed when the FET 3 is on is recharged from the drive power supply 17 to replenish. To do.
The drive circuit D5 having the same configuration as the drive circuit D3 drives the FET 5 in the same manner as the operation of the drive circuit D3.

Next, in the drive circuits D4 and D6 for driving the FETs 4 and 6 on the low voltage side, description will be given focusing on one drive circuit D4.
In the drive circuit D4, two (NPN type and PNP type) transistors 21 and 22 for amplifying the drive signal are connected in a totem pole shape to the positive bias capacitor 20 for storing positive charges.

As a result, the output signals from the emitters of the two transistors 21 and 22 connected in series are input to the gate of the FET 4 via the current limiting resistor 23.
At this time, when the NPN transistor 21 is turned on, a positive voltage is applied to the gate of the FET 4 and the FET 4 is turned on.

  On the other hand, the negative bias capacitor 24 for storing negative charges is connected between the source of the FET 4 and the ground GND side of the drive power supply 17 (the collector of the PNP transistor 22). The negative bias capacitor 24 is connected in parallel to the secondary side of the current transformer 25 connected in series to the source of the FET 4.

The primary side of the current transformer 25 is connected in series to the source of the FET 4. When the FET 4 is turned on and a current flows through the primary side, the secondary side has a voltage proportional to the winding ratio, A current that is inversely proportional to the winding ratio is generated.
As a result, the charge is stored in the negative bias capacitor 24 via the rectifier diode 26, and when the charge reaches a predetermined level or more, excess charge is discharged by the Zener diode 27.

Further, when the NPN transistor 21 is turned off and the PNP transistor 22 is turned on, the charge of the FET 4 is increased by the voltage stored in the negative bias capacitor 24 while extracting the charge from the gate of the FET 4 through the current limiting resistor 23. By pulling the gate down to a negative voltage, the FET 4 is maintained in the off state.
Further, the resistor 28 is used to maintain the base potential of each of the transistors 21 and 22 low to turn on the PNP transistor 22 side and maintain the FET 4 in the off state when no drive signal is input. It is.

The drive circuit D6 having the same configuration as the drive circuit D4 drives the FET 6 in the same manner as the operation of the drive circuit D4.
The drive signal circuit 30 receives a control signal from the control IC 32 and generates a drive signal for two (NPN type and PNP type) transistors in each of the drive circuits D3 to D6.

Hereinafter, the operations of the control IC 32 and the FETs 3 to 6 in FIG. 1 will be described in more detail with reference to FIGS.
2 and 3 are timing charts showing the circuit operation according to the first embodiment of the present invention with voltage waveforms at respective portions in FIG.

FIG. 2 shows the gate voltage waveforms (drive waveforms) of the FETs 3 and 4 and the operation timing of the inrush current protection circuit 1.
FIG. 3 shows gate voltage waveforms of the FETs 3 to 6 and a primary voltage waveform applied to the primary side of the switching transformer 7.

2A and 3A show the gate voltage waveform to the FET 3, and FIG. 2B shows the timing when the switch of the inrush current protection circuit 1 is turned on.
2C and 3B show the gate voltage waveform to the FET 4, and FIG. 3C shows the gate voltage waveform to the FET 5.
FIG. 3D shows the gate voltage waveform to the FET 6, and FIG. 3E shows the voltage waveform applied to the primary side of the switching transformer 7 in response to the operation of the FETs 3 to 6.

FIG. 4 is a block diagram showing a circuit configuration of a conventional DC power supply device as a comparative example.
In FIG. 4, the same parts as those described above (see FIG. 1) are denoted by the same reference numerals as those described above, or “′”, “a”, “b” are added after the reference numerals, and detailed description thereof is omitted. To do.

In FIG. 4, each of the drive circuits D3 ′ to D6 ′ of the FETs 3 to 6 has the same configuration, and therefore, description will be given with a focus on one drive circuit D3 ′.
In order to drive the FET 3, the drive circuit D3 ′ replaces the capacitor 10, the DC cut capacitor 13 and the drive transformer 14 described above (FIG. 1) with two drive power supplies 17a that individually output a positive voltage and a negative voltage, 17b.

  In FIG. 4, the source of the FET 3 connected to the high voltage side is connected to the GND via the switching transformer 7 and the FET 4 (ON state) when the FET 3 is in the OFF state. It has become a potential.

  Here, when a “High signal” is output from the drive signal circuit 30 a to the gates of the transistors 11 and 12, the NPN transistor 11 is turned on, and the output voltage of the drive power supply 17 a is applied to the gate of the FET 3. Thus, the FET 3 is turned on.

  When the FET 3 is turned on, the source potential of the FET 3 becomes substantially equal to the input voltage, and the FET 3 cannot be turned off unless the gate potential is made lower than the source potential.

  Subsequently, when a “Low signal” is output from the drive signal circuit 30a, the NPN transistor 11 is turned off, and the PNP transistor 12 is turned on instead. It is lowered to the potential on the low voltage side of 17b.

  At this time, since the driving power supply 17b has the high voltage side connected to the source side of the FET 3, the gate voltage of the FET 3 becomes lower than the source potential by the output voltage of the driving power supply 17b, and the FET 3 is in the OFF state. Become.

By repeating the above operation, the FET 3 is turned on / off according to a control signal from the control IC 32a.
Similarly, the FETs 4 to 6 repeat the on / off operation according to the signal from the control IC 32a.

  At the same time as the activation, the control IC 32a outputs control signals whose phases are shifted from each other by 180 ° to the FETs 3 and 4, and outputs in-phase control signals to the FETs 3 and 5, respectively. In-phase control signals are output.

Thus, when the FET 3 is in the on state, the FETs 4 and 6 are in the off state, and when the FET 5 is in the on state, the FETs 4 and 6 are in the off state, so that a voltage is applied to the switching transformer 7. However, the DC power supply device is in an off state.
The said state is shown by the waveform of the left half in Fig.3 (a)-(e).

  Subsequently, with the passage of time after the start, the phase of the drive signals of the FETs 3 and 4 gradually starts to be delayed, the on-timing of the FET 3 and the on-timing of the FET 6 overlap, and the on-timing of the FETs 5 and 4 also overlap.

  As a result, the gate voltages of the FETs 3 to 6 have the waveforms shown in the right half of FIGS. 3A to 3E. When the FETs 3 and 6 are in the ON state, a current a (broken arrow) flows, and the FET 5 When 4 is in the ON state, a current b (one-dot chain arrow) flows.

By repeating the above operation, the voltage indicated by the right half waveform of FIG. 3E is applied to the primary side of the switching transformer 7.
At this point, power is transmitted to the secondary side of the switching transformer 7 for the first time, and begins to function as a DC power supply.

  Thus, in general, as shown in FIG. 4, in the MOSFET drive circuits D3 ′ to D6 ′ using GaN or SiC, positive and negative voltages are individually applied to the FETs 3 to 6, respectively. In order to apply to the gate, it was necessary to prepare one set of two drive power supplies 17a and 17b, both positive and negative.

On the other hand, according to the first embodiment (FIG. 1) of the present invention, each of the FETs 3 and 5 is driven using the drive transformer 14.
As a result, as shown in FIG. 2A, immediately after startup, all of the output voltage of the drive power supply 17 is applied as a positive voltage to the gate of the FET 3 (FET 5). Immediately thereafter, the drive signal is turned on / off. According to the ratio, the voltage is divided into a positive voltage and a negative voltage and applied to the gate of the FET 3 (FET 5) (see hatching waveform).

  In FIG. 1, the negative bias capacitor 24 provided in the drive circuits D4 and D6 of the FETs 4 and 6 has a current transformer 25 connected to the source side of the FETs 4 and 6 so that a current flows in the FETs 4 and 6 even for a moment. When it flows, the negative bias voltage is charged.

As a result, both positive and negative voltages can be applied to the gate of the FET 4 (FET 6) as shown in the waveform of FIG.
After this state is reached, the phase of the drive signals of the FETs 3 and 4 is gradually delayed so that the waveform in the right half of FIGS. 3 (a) to 3 (e) is obtained, and on the secondary side of the switching transformer 7. It transmits power and functions as a DC power supply.

Therefore, according to the circuit configuration of FIG. 1, only one drive power supply 17 can apply both positive and negative voltages to the four FETs 3 to 6 and operate each FET 3 to 6 as instructed by the control IC 32. it can.
In the circuit operation according to the first embodiment (FIG. 1) of the present invention, the gate voltage waveforms of the FETs 3 to 6 are as shown in FIG.

  Even if the signal from the control IC 32 is interrupted, or even if the drive signal circuit 30 is damaged and no drive signal is input to the drive circuits D4 and D6, the FETs 4 and 6 flow to themselves. Since the OFF state can be maintained by charging the negative bias capacitor 24 with a current, an effect that an arm short circuit can be prevented is also achieved.

  As described above, the DC power supply device according to Embodiment 1 (FIGS. 1 to 3) of the present invention is configured by connecting a plurality of FETs 3 to 6 made of a wide band gap semiconductor in a full bridge shape, Drive circuits D3 to D6 for driving each of the plurality of FETs 3 to 6, a control IC 32 for controlling the on / off ratio and operation timing of each of the plurality of FETs 3 to 6, and each of the plurality of FETs 3 to 6 being driven An inrush current protection circuit 1 that protects an inrush current when it is turned on after the start of operation, and a single drive power supply 17 that supplies power for driving the plurality of FETs 3 to 6 are provided.

  The drive circuits D3 to D6 include first drive circuits D3 and D5 that drive the first FETs 3 and 5 connected to the high voltage side of the plurality of FETs 3 to 6, and the low voltage side of the plurality of FETs 3 to 6 And second driving circuits D4 and D6 for driving the second FETs 4 and 6 connected to each other.

The first drive circuits D3 and D5 include a drive transformer 14 inserted between the gate and source of the first FETs 3 and 5.
The second drive circuits D4 and D6 include a positive bias capacitor 20 and a negative bias capacitor 24 inserted in series between both ends of the drive power supply 17.

A current transformer 25 for charging the negative bias capacitor 24 is connected to the second drive circuits D4 and D6. The negative bias capacitor 24 is connected to the second FETs 4 and 6 via the current transformer 25. It is charged by the current flowing through
The sources of the second FETs 4 and 6 are connected to one end of the negative bias capacitor 24 and the secondary side of the current transformer 25.

  Thus, in order to realize miniaturization and high efficiency, a single drive power supply 17 is used in a DC power supply device that converts very large power into DC using FETs 3 to 6 made of wide band gap semiconductors. Thus, both positive and negative drive voltages are applied to the FETs 3 to 6.

  That is, in the DC power supply device having the inrush current protection circuit 1 at the input stage and the drive circuits D3 to D6 independent of the FETs 3 to 6, the high voltage side is driven by the drive transformer 14. Further, the gate voltage can be supplied to the low voltage side by the negative bias capacitor 24 charged by the driving power supply 17 and the current flowing through the FETs 4 and 6.

Thereby, it is possible to configure a DC power supply device capable of driving a switching device using GaN or SiC that has a very low on-resistance, high breakdown voltage, large current, and high-speed switching with a single drive power supply 17, It is possible to realize a reduction in price and size while ensuring safety by preventing a short circuit accident.
In addition, since a small and highly efficient DC power supply device can be realized at a low price, it is possible to supply a smaller and highly efficient power supply system at a low price.

  For example, in the case of the full bridge system, a single drive power supply 17 can supply both positive and negative gate voltages to four FETs 3 to 6, and an on-resistance made of GaN or SiC can be used. Since a small MOSFET having a low gate threshold voltage can be operated safely and reliably without malfunction, a very small and low-loss DC power supply device can be obtained at a low price. Here, a phase control type full bridge converter called a phase shift method has been described as an example, but it can be easily imagined that the same effect can be obtained with a normal PWM type full bridge converter. .

  The DC power supply according to the first embodiment of the present invention is useful as a DC power supply that can be reduced in price and reduced in size and can convert a DC power supply with high efficiency. It is suitable as a DC power supply device used in this power supply system.

  1 Inrush current protection circuit, 2 input capacitor, 3-6 FET, 7 switching transformer, 8 resonance choke coil, D3-D6 drive circuit, 10 capacitor, 11, 21 NPN transistor, 12, 22 PNP transistor, 13 DC Cut capacitor, 14 Drive transformer, 15, 23 Current limiting resistor, 16 Backflow prevention diode, 17 Drive power supply, 20 Positive bias capacitor, 24 Negative bias capacitor, 25 Current transformer, 26 Rectifier diode, 27 Zener diode, 28 Resistance, 30 drive signal circuit, 32 control IC, GND ground.

Claims (2)

A direct current power supply device configured by connecting a plurality of FETs made of wide band gap semiconductors in a full bridge shape,
A drive circuit for driving each of the plurality of FETs;
A control IC for controlling the on / off ratio and operation timing of each of the plurality of FETs;
An inrush current protection circuit for protecting an inrush current when each of the plurality of FETs starts to be turned on after being driven;
A single drive power supply for supplying power for driving the plurality of FETs, and the drive circuit,
A first drive circuit for driving a first FET connected to a high voltage side of the plurality of FETs;
A second drive circuit for driving a second FET connected to the low voltage side of the plurality of FETs,
The first drive circuit includes a drive transformer inserted between a gate and a source of the first FET,
The second drive circuit includes a positive bias capacitor and a negative bias capacitor inserted in series between both ends of the drive power supply,
A current transformer for charging the negative bias capacitor is connected to the second drive circuit,
The DC power supply device, wherein the negative bias capacitor is charged by a current flowing through the second FET through the current transformer.   2. The DC power supply device according to claim 1, wherein a source of the second FET is connected to one end of the negative bias capacitor and a secondary side of the current transformer.

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