JP2012216985A - Data transfer system and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer system capable of transferring data to a peripheral circuit from a master device without deteriorating system performance.SOLUTION: The data transfer system comprises: master devices M1-M3; a bus bridge 3 to which data D1-D3 outputted via a first bus 2 from the master devices are input and which outputs the data via a second bus 4; and a peripheral circuit 5 having write buffers WB1-WB3 which store the data D1-D3 outputted from the bus bridge 3 and registers R1-R3 which store the data D1-D3 outputted from the write buffers WB1-WB3. The bus bridge 3 and the write buffer operate at a first clock, the register operates at a second clock which is asynchronous with the first clock, and the write buffer and the register are synchronized, thereby transferring the data to the register from the write buffer.

Description

  The present invention relates to a data transfer system and a data transfer method, and more particularly, to a data transfer system and a data transfer method for realizing data transfer between a master and a peripheral circuit operating with asynchronous clocks.

  In recent years, a technique for transferring data at a higher speed between a master and a peripheral circuit operating with asynchronous clocks has become important. For example, in a semiconductor integrated circuit mounted on an automobile, a spread spectrum clock generator (SSCG) is used to drive a CPU in order to suppress noise generation due to electromagnetic interference (EMI). There is. On the other hand, the peripheral system may be operated with a clock asynchronous to the spread spectrum clock in order to satisfy special accuracy requirements. As described above, when the CPU serving as the master and the peripheral system serving as the peripheral circuit (slave) operate asynchronously, a synchronization process is required to access the peripheral system from the CPU.

  Patent Document 1 discloses a technique related to a data transmitting / receiving apparatus capable of performing a write operation or a read operation in as short a time as possible. FIG. 15 is a diagram illustrating a data transmission / reception apparatus disclosed in Patent Document 1. In FIG. 15 includes a master unit 101, a slave unit 140, control signal buses 132 and 136, and a data bus 134, and transmits data from the master unit 101 to the slave unit 140. The master unit 101 includes a master side write control circuit 102 and flip-flop circuits 111 to 114. The slave unit 140 includes a slave side write control circuit 142 and flip-flop circuits 151 to 155.

  The master-side write control circuit 102 synchronizes the WRITE signal indicating the write request with the flip-flop circuit 111 using the master-side operation clock signal, and outputs it to the control signal bus 132. The synchronized WRITE signal is synchronized in the flip-flop circuits 151 and 152 using the slave side operation clock signal, and is taken into the slave side write control circuit 142. Note that the flip-flop circuits 151 and 152 are reset by the WRITE signal whose value synchronized by the flip-flop circuit 111 is “0”.

  The master-side write control circuit 102 synchronizes the write data WRITEDATA in the flip-flop circuit 112 using the master-side operation clock signal, and outputs it to the data bus 134. The synchronized write data WRITEDATA is synchronized in the flip-flop circuits 153 and 154 using the slave side operation clock signal, and is taken into the slave side write control circuit 142. Note that the flip-flop circuits 112, 153, and 154 are reset by the WRITE signal whose value synchronized by the flip-flop circuit 111 is “0”.

  The slave-side write control circuit 142 synchronizes the READY signal with the flip-flop circuit 155 using the slave-side operation clock signal, and outputs it to the control signal bus 136. This READY signal is synchronized in the two-stage flip-flop circuits 113 and 114 using the master side operation clock signal, and is taken into the master side write control circuit 102. Note that the flip-flop circuits 113, 114, and 155 are reset by the WRITE signal whose value synchronized by the flip-flop circuit 111 is “0”.

  FIG. 16 is a timing chart for explaining the operation of the data transmitting / receiving apparatus disclosed in Patent Document 1. The master-side write control circuit 102 confirms that the value of the READY signal synchronized by the flip-flop circuits 113 and 114 is “0”, synchronizes the write data WRITEDATA by the flip-flop circuit 112, and the data bus 134. And the value of the WRITE signal is set to “1” and is output to the control signal bus 132 via the flip-flop circuit 111 (timing t101).

  The slave-side write control circuit 142 detects that the value of the WRITE signal synchronized by the flip-flop circuits 151 and 152 becomes “1”, that is, a write request is made, and writes the write data WRITEDATA to the flip-flop circuit 153. , 154. When the capture of the write data WRITEDATA is completed, the value of the READY signal is set to “1” and output to the control signal bus 136 via the flip-flop circuit 155 (timing t102).

  When the master-side write control circuit 102 detects that the value of the READY signal synchronized by the flip-flop circuits 113 and 114 becomes “1”, that is, that the write data WRITEDATA is received, the master-side write control circuit 102 sets the value of the WRITE signal to “ 0 "and output to the flip-flop circuit 111 (timing t103).

  Then, the WRITE signal whose value is “0” is synchronized by the flip-flop circuit 111 using the master side operation clock signal, and is output to the control signal bus 132. Then, all of the flip-flop circuits 151 to 155 on the slave side are reset by this WRITE signal. That is, the value of the READY signal that is the output of the flip-flop circuit 155 becomes “0” (timing t104). When the write operation is not performed, the values of the WRITE signal and the READY signal are both “0” (timing t105).

  As described above, in the data transmitting / receiving apparatus disclosed in Patent Document 1, the flip-flops 151, 152, and 155 on the slave side are simultaneously reset by the WRITE signal having a value of “0”. Therefore, it is possible to shorten the period from when the value of the WRITE signal is “0” to when the value of the READY signal is “0”, and the write operation can be performed in as short a time as possible.

  Patent Document 2 discloses a technology relating to a bus control method for minimizing a decrease in system performance when a low-speed processor is used. Patent Document 3 discloses a technology related to a bus bridge circuit that can efficiently perform data access between a master and a slave without increasing the circuit scale. Patent Document 4 discloses a technique related to a data processing device that can shorten the access latency and improve the performance when the CPU of the high speed side bus accesses the peripheral module of the low speed side bus such as data reading. It is disclosed. In Patent Document 5, the operation clock of the upper bus and the operation clock of the lower bus operate at different speeds. In a system in which these operation clocks can be changed, both buses can be used at any operation clock and data width. A technology related to a bus adapter device that can transfer data between the devices is disclosed.

JP 2002-33723 A Japanese Patent Laid-Open No. 06-266660 Japanese Patent Laying-Open No. 2005-078146 JP 2006-164119 A JP 2006-195948 A

  In the data transmission / reception apparatus disclosed in Patent Document 1, when the access from the master unit 101 to the slave unit 140 occurs continuously, the value of the READY signal is set to “0” until the first access is completed. Until then, the subsequent access is waited. As described above, in a system in which the master and the peripheral circuit (slave) operate asynchronously, the synchronization processing hinders data transfer, and there is a problem that the system performance deteriorates.

  A data transfer system according to the present invention includes at least one master, and a bus bridge that inputs data output from the at least one master via a first bus and outputs the data via a second bus. The first and second write buffers capable of holding the data output from the bus bridge, and the first and second write buffers are provided corresponding to the first and second write buffers, and output from the first and second write buffers. A peripheral circuit having first and second registers for holding the received data, respectively, wherein the bus bridge and the first and second write buffers operate with a first clock, and the bus bridge The data can be transferred to the first and second write buffers according to the first clock, and the first and second registers can be transferred. The first and second write buffers are synchronized with the first and second registers by operating the second clock asynchronous with the first clock, respectively. The data is transferred from two write buffers to the first and second registers.

  In the data transfer system according to the present invention, a write buffer that is driven by the same clock as the bus bridge is provided between the bus bridge and the register. Therefore, since the access from the bus bridge to the write buffer is performed synchronously, the transfer of data from the bus bridge to the peripheral circuit (actually the write buffer) can be speeded up.

  According to the present invention, at least one master, a bus bridge that receives data output from the at least one master via a first bus and outputs the data via a second bus, and the bus bridge The first and second write buffers that can hold the data output from the first and second write buffers and the first and second write buffers are provided corresponding to the first and second write buffers. A data transfer method in a data transfer system including a peripheral circuit including first and second registers for holding each of the bus bridge and the first and second write buffers with a first clock, Transferring the data from the bus bridge to the first and second write buffers according to the first clock; And the second register are operated with a second clock asynchronous to the first clock, and the first and second write buffers are synchronized with the first and second registers, respectively. The data is transferred from the first and second write buffers to the first and second registers, respectively.

  In the data transfer method according to the present invention, a write buffer that is driven by the same clock as the bus bridge is provided between the bus bridge and the register, and the bus bridge and the write buffer are operated in synchronization. Therefore, the transfer of data from the bus bridge to the peripheral circuit (actually the write buffer) can be speeded up.

  According to the present invention, it is possible to provide a data transfer system and a data transfer method capable of transferring data from a master to a peripheral circuit without degrading system performance.

It is a block diagram for demonstrating an example of the processor system with which the data transfer system concerning this invention is applied. 1 is a block diagram showing a data transfer system according to a first exemplary embodiment; 2 is a block diagram illustrating an example of a peripheral circuit included in the data transfer system according to the first exemplary embodiment; FIG. 3 is a timing chart for explaining an operation of the data transfer system according to the first exemplary embodiment; 3 is a timing chart for explaining an operation of the data transfer system according to the first exemplary embodiment; It is a block diagram which shows the data transfer system concerning a comparative example. It is a timing chart for demonstrating operation | movement of the data transfer system concerning a comparative example. FIG. 3 is a block diagram showing a data transfer system according to a second exemplary embodiment. FIG. 4 is a block diagram illustrating an example of a peripheral circuit included in a data transfer system according to a second exemplary embodiment. 6 is a timing chart for explaining the operation of the data transfer system according to the second exemplary embodiment; 6 is a timing chart for explaining the operation of the data transfer system according to the second exemplary embodiment; FIG. 6 is a block diagram illustrating an example of a peripheral circuit included in a data transfer system according to a third exemplary embodiment. 10 is a timing chart for explaining the operation of the data transfer system according to the third exemplary embodiment; FIG. 10 is a diagram for explaining the effect of the data transfer system according to the third exemplary embodiment. 1 is a diagram illustrating a data transmission / reception device disclosed in Patent Document 1. FIG. 10 is a timing chart showing the operation of the data transmitting / receiving apparatus disclosed in Patent Document 1.

  Before describing a detailed embodiment of the present invention, an outline of a processor system to which the present invention is applied will be described. Although the present invention is applied to a processor system described below, the processor system described is an example, and the present invention can also be applied to other processor systems.

  A schematic diagram of a processor system to which the present invention is applied is shown in FIG. As shown in FIG. 1, the processor system according to the present invention realizes improvement in processing performance by using a plurality of PEs (Processing Elements). In the processor system according to the present invention, the function is classified by three subsystems separately from the function block classification by PE. As shown in FIG. 1, the processor system according to the present invention includes a main PE (Processing Element) subsystem, an IO (Input Output) subsystem, and an HSM (Hardware Security Module) subsystem.

  The main PE subsystem performs specific processing required for a processor system based on a program stored in advance or a program read from the outside. The IO subsystem performs various processes for operating peripheral devices used by the main PE subsystem or the HSM subsystem. The HSM subsystem performs security confirmation processing of processing performed in the processor system. In the processor system according to the present invention, the clock signals CLKa, CLKb, CLKc, and CLKp are supplied to each subsystem. In the example shown in FIG. 1, the main PE subsystem is supplied with a clock signal CLKa, the IO subsystem is supplied with clock signals CLKb and CLKp, and the HSM subsystem is supplied with a clock signal CLKc. These clock signals CLKa, CLKb, and CLKc may have the same frequency or different frequencies depending on the specifications of the overall system configuration. The clock signal CLKp is provided to the peripheral device and is an asynchronous clock signal with respect to the clock signal CLKb provided to the IO subsystem.

  Subsequently, each subsystem will be described more specifically. The main PE subsystem has a main PEa, a main PEb, a first instruction memory, a data memory, and a system bus. In the main PE subsystem, the main PEa, the main PEb, the instruction memory, and the data memory are connected to each other via a system bus. The first instruction memory stores a program. The data memory temporarily stores programs read from the outside and data processed in the processor system. The main PEa and the main PEb execute programs while using an instruction memory, a data memory, and the like, respectively. The main PEa is configured to be able to perform a redundant operation. The redundant operation is an operation that operates as a single processor element in terms of software, but performs a highly reliable operation by a multiplexed configuration or a configuration to which an inspection circuit or the like is added as hardware. As an example of the redundant operation, there is a lock step operation for comparing whether or not the output results of the circuits multiplexed for each clock are the same.

  The IO subsystem has a peripheral bus, IOPE, and peripheral devices. The IOPE performs processing necessary for using the peripheral device. The IOPE may operate based on a program stored in the first instruction memory of the main PE system, or may operate based on a program stored in another storage area. The peripheral bus connects the IOPE and peripheral devices to each other.

  In FIG. 1, a CAN unit, a FLEXRAY unit, an SPI unit, a UART unit, an ADC unit, a WD unit, and a timer are illustrated as peripheral devices. The CAN unit performs communication based on CAN (Controller Area Network), which is one of in-vehicle communication standards for automobiles. The FLEXRAY unit performs communication based on the Flex Ray standard, which is one of in-vehicle communication standards for automobiles. The SPI unit performs SPI (System Packet Interface) standard communication, which is 3-wire or 4-wire serial communication. A UART (Universal Asynchronous Receiver Transmitter) unit converts a serial signal in an asynchronous manner into a parallel signal and performs conversion in the opposite direction. An ADC (Analog to Digital Converter) unit converts an analog signal supplied from a sensor or the like into a digital signal. The WD (Watch Dog) unit provides a watchdog timer function for detecting that a predetermined period has elapsed. The timer performs time measurement, waveform generation, and the like. In the example of FIG. 1, the above unit is a peripheral device, but it is possible to include a unit having another function, or a case where only a part of the unit is included.

  The HSM subsystem has a security PE and a second instruction memory. The security PE is connected to the system bus. The security PE determines the validity of the program executed in the main PE subsystem or the validity of the data obtained by executing the program. A program is stored in the second instruction memory. The second instruction memory is a memory that can be accessed only by the security PE. The second instruction memory may be provided as one storage area together with the first instruction memory, but it is necessary that access control is performed as an area accessible only to the security PE.

  As described above, the processor system to which the present invention is applied realizes high tolerance against problems such as unexpected failures and unexpected program modifications while improving the processing capability by a plurality of PEs. The processor system described so far is an example of a processor system to which the present invention is applied. For example, the arrangement of instruction memory and data memory and the number in the system vary depending on the architecture of the system. Conceivable. In addition, the connection between the memory and each processor element may be, for example, a configuration connected via a plurality of buses, or a configuration connected to a processor element without passing through a bus. Various configurations can be considered depending on the design.

  The above description of the processor system is for explaining the overall configuration of the processor system to which the present invention is applied. However, in the description of the embodiment of the present invention, components not described in the description of the processor system are added as appropriate. A description of the added component is also added.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the data transfer system according to the first exemplary embodiment of the present invention. The data transfer system according to the present embodiment includes at least one master M1 to M3 (1) and write data D1 to D1 output from the masters M1 to M3 (1) via the system bus (first bus) 2. D3 is input and the write bridge data is output to the peripheral circuit 5 via the peripheral bus (second bus) 4 and the write buffers WB1 to WB3 holding the write data output from the bus bridge 3 And a peripheral circuit 5 including registers R1 to R3 that hold the write data output from the write buffers WB1 to WB3. In the data transfer system according to the present embodiment, the bus bridge 3 and the write buffers WB1 to WB3 operate with the clock CLK (first clock), and the bus bridge 3 sends write data to the write buffers WB1 to WB3 according to the clock CLK. Transfer D1-D3. The registers R1 to R3 operate with a clock CLKp (second clock) that is asynchronous with the clock CLK, and the write buffers WB1 to WB3 and the registers R1 to R3 are synchronized with each other from the write buffers WB1 to WB3 to the register R1. The write data D1 to D3 are transferred to .about.R3. The data transfer system according to this embodiment will be described in detail below.

  The masters M1 to M3 are configured to be accessible to the peripheral circuits IP1 to IP3 via the system bus 2, the bus bridge 3, and the peripheral bus 4. The masters M1, M2, and M3 output write data D1, D2, and D3 to the bus bridge 3 via the system bus 2, respectively. Here, the masters M1 to M3 may operate in synchronization with the clock CLK, or may operate with a clock asynchronous with the clock CLK.

  The bus bridge 3 inputs the write data D1 to D3 output from the masters M1 to M3, arbitrates the input write data D1 to D3, and peripherals the write data 41 (D1 to D3) after arbitration one by one. The data is output to the write buffers WB1 to WB3 included in the peripheral circuits IP1 to IP3 via the bus 4. Here, for example, the write data D1 output from the master M1 is output to the write buffer WB1 included in the peripheral circuit IP1, and the write data D2 output from the master M2 is output to the write buffer WB2 included in the peripheral circuit IP2. The write data D3 output from the master M3 is output to the write buffer WB3 provided in the peripheral circuit IP3. The bus bridge 3 operates with the clock CLK.

  Peripheral circuits IP1 to IP3 include write buffers WB1 to WB3 and registers R1 to R3, respectively. The write buffers WB1 to WB3 hold the arbitrated write data D1 to D3 output from the bus bridge 3, respectively. Here, both the bus bridge 3 and the write buffers WB1 to WB3 operate with the same clock CLK. The bus bridge 3 may output an enable signal and an address signal to the write buffers WB1 to WB3 together with the write data D1 to D3 after arbitration.

  The write buffers WB1 to WB3 output a high level signal as the wait signal 42 when the write data D1 to D3 output from the bus bridge 3 is being transferred. That is, when the wait signal is at the high level, the bus bridge 3 waits without outputting the next arbitrated write data to the write buffers WB1 to WB3.

  The registers R1 to R3 operate with a clock CLKp that is asynchronous with the clock CLK. Here, the clock frequency of the clock CLKp and the clock frequency of the clock CLK may be the same, the clock frequency of the clock CLKp may be slower than the clock frequency of the clock CLK, and conversely, the clock frequency of the clock CLKp is It may be faster than the clock frequency of the clock CLK.

  For example, when the write data D1 held in the write buffer WB1 is transferred from the write buffer WB1 to the register R1, the write data D1 can be transferred by synchronizing the write buffer WB1 and the register R1. The same applies to the peripheral circuits IP2 and IP3. In the present embodiment, the data transfer rate from write buffer WB1 to register R1 is sufficiently slower than the data transfer rate from bus bridge 3 to write buffer WB1.

  The peripheral circuits IP1 to IP3 included in the data transfer system according to the present embodiment will be described in detail with reference to FIG. The peripheral circuit IP1 will be described below, but the same applies to the peripheral circuits IP2 and IP3. The configuration of the peripheral circuits IP1 to IP3 described below is an example, and any configuration may be used as long as the circuit operates in the same manner.

  The peripheral circuit IP1 includes a write buffer WB1 (11), an address decoder 12, an enable signal synchronization circuit 13, an enable pulse generation circuit 14, and a register R1 (15). Here, the write buffer WB1 (11) and the address decoder 12 operate with the clock CLK. The enable signal synchronization circuit 13, the enable pulse generation circuit 14, and the register R1 (15) operate with the clock CLKp.

  The address decoder 12 receives the address signal output from the bus bridge 3 and the enable signal EN_BB. When the address signal is an address signal (IP1) designating the peripheral circuit IP1, the address decoder 12 outputs an enable signal EN_WB1 to the write buffer WB1 (11) and the enable signal synchronization circuit 13. The write buffer WB1 (11) takes in the write data D1 output from the bus bridge 3 at the timing when the high-level enable signal EN_WB1 is supplied.

  When the enable signal EN_WB1 at the high level is supplied to the enable signal synchronization circuit 13, the enable signal synchronization circuit 13 synchronizes the write data D1 from the write buffer WB1 (11) to the register R1 (15). Complete signal 19 is generated and output to enable pulse generation circuit 14. When the enable pulse generation circuit 14 receives the synchronization completion signal 19 output from the enable signal synchronization circuit 13, the enable pulse generation circuit 14 outputs a high-level enable signal EN_REG1 to the register R1 (15). When the high level enable signal EN_REG1 is supplied to the register R1 (15), the register R1 (15) takes in the write data D1 held in the write buffer WB1 (11).

  When the data transfer system according to the present embodiment described above is applied to the processor system shown in FIG. 1, the masters M1 to M3 are, for example, the main PEa, the main PEb, the first PE constituting the main PE subsystem shown in FIG. One instruction memory, data memory, and at least one of security PEs included in the HSM subsystem can be used. The system bus 2 and the peripheral bus 4 shown in FIG. 2 correspond to the system bus and the peripheral bus shown in FIG. 1, respectively. Here, the system bus 2 shown in FIG. 2 can be a multi-layer bus capable of transferring data D1 to D3 simultaneously. The bus bridge 3 shown in FIG. 2 can be provided on the IO subsystem side between the system bus and the peripheral bus provided in the processor system shown in FIG. At this time, the bus bridge 3 is configured to operate with the clock CLK. When the system bus shown in FIG. 1 is a multi-layer bus, the bus bridge provided between the system bus and the peripheral bus shown in FIG. 1 can receive a plurality of data from the system bus at the same time. Can be configured.

  The registers R1 to R3 shown in FIG. 2 are provided in, for example, the CAN unit, FLEXRAY unit, SPI unit, UART unit, ADC unit, WD unit, and timer shown in FIG. The write buffers WB1 to WB3 shown in FIG. 2 are provided between each peripheral device (CAN unit, FLEXRAY unit, SPI unit, UART unit, ADC unit, WD unit, timer) and the peripheral bus. Here, the registers R1 to R3 operate with the clock CLKp, and the write buffers WB1 to WB3 operate with the clock CLK. For example, when the CAN shown in FIG. 1 corresponds to the peripheral circuit IP1 shown in FIG. 2, the register R1 is provided in the CAN unit shown in FIG. 1, and the write buffer WB1 is provided between the peripheral bus and the CAN unit. At this time, the write buffer WB1 operates with the clock CLK, and the CAN unit and the register R1 provided in the CAN unit operate with CLKp.

  Next, the operation of the data transfer system according to this exemplary embodiment will be described. FIG. 4 is a timing chart for explaining the operation of the data transfer system according to the present embodiment. 4, the upper stage shows the operation of the bus bridge 3, and the lower stage shows the operation of the write buffers WB1 to WB3 provided in the peripheral circuit. As shown in FIG. 4, the bus bridge 3 and the write buffers WB1 to WB3 operate in synchronization with the clock CLK.

  At the timing T1, the bus bridge 3 outputs the enable signal EN_BB and the address signal (IP1) to the address decoder 12 included in the peripheral circuit IP1, and the write data D1 to the write buffer WB1.

  At the timing T2, the address decoder 12 included in the peripheral circuit IP1 outputs a high-level enable signal EN_WB1 to the write buffer WB1. Thereafter, the write buffer WB1 takes in the write data D1 output from the bus bridge 3 at the timing of T3. When the write data D1 is held in the write buffer WB1, the transaction of the bus bridge 3 ends.

  At the timing T3, the bus bridge 3 outputs the enable signal EN_BB and the address signal (IP2) to the address decoder 12 included in the peripheral circuit IP2, and the write data D2 to the write buffer WB2. That is, after transferring the write data D1 to the write buffer WB1, the bus bridge 3 arbitrates the next write data D2 regardless of whether or not the transfer of the write data D1 from the write buffer WB1 to the register R1 is completed. Output.

  At timing T4, the address decoder 12 included in the peripheral circuit IP2 outputs a high-level enable signal EN_WB2 to the write buffer WB2. Thereafter, at the timing of T5, the write buffer WB2 takes in the write data D2 output from the bus bridge 3.

  At time T5, the bus bridge 3 outputs the enable signal EN_BB and the address signal (IP3) to the address decoder 12 provided in the peripheral circuit IP3, and the write data D3 to the write buffer WB3.

  At timing T6, the address decoder 12 included in the peripheral circuit IP3 outputs a high-level enable signal EN_WB3 to the write buffer WB3. Thereafter, at the timing of T7, the write buffer WB3 takes in the write data D3 output from the bus bridge 3.

  As shown in FIG. 4, for example, when the write data D1 is transferred from the bus bridge 3 to the write buffer WB1, the write buffer WB1 takes in the write data D1 after two clocks after the bus bridge 3 transfers the write data D1. Yes. The same applies to the write data D2 and D3. In this case, data transfer from the bus bridge 3 to the write buffers WB1 to WB3 is performed without waiting for data transfer to the registers R1 to R3. In addition, the wait signal is at a low level from T1 to T7. This is because the data transfer from the bus bridge 3 to the write buffers WB1 to WB3 is completed in two clocks, and therefore it is not necessary for the bus bridge 3 to enter a wait state when transferring write data to the write buffers WB1 to WB3. is there.

  Next, an operation when write data is transferred from the write buffers WB1 to WB3 to the registers R1 to R3 will be described with reference to FIG. FIG. 5 shows only the case where write data is transferred from the write buffer WB1 to the register R1, but when write data is transferred from the write buffer WB2 to the register R2, the write data is transferred from the write buffer WB3 to the register R3. The same applies to the case where is transferred.

  As shown in FIG. 5, the write buffers WB1 to WB3 operate with the clock CLK, and the registers R1 to R3 operate with the clock CLKp that is asynchronous with the clock CLK. The enable signal EN_WB1 becomes high level at the timing T2, and the write data D1 is held in the write buffer WB1 at the timing T3. Further, the enable signal EN_WB1 at the high level is supplied to the enable signal synchronization circuit 13 at the timing of T2. After the timing T2, the enable signal synchronization circuit 13 generates a synchronization completion signal 19 indicating the timing for transferring the write data D1 from the write buffer WB1 (11) to the register R1 (15). At time T8, the enable signal synchronization circuit 13 outputs a synchronization completion signal 19 to the enable pulse generation circuit 14.

  The enable pulse generation circuit 14 outputs a high-level enable signal EN_REG1 to the register R1 (15) at a timing T9 one clock after the timing T8 when the synchronization completion signal 19 becomes a high level. When the high-level enable signal EN_REG1 is supplied to the register R1 (15), the register R1 (15) takes in the write data D1 held in the write buffer WB1 (11) at the timing of T10. By such an operation, write data is transferred from the write buffer WB1 to the register R1 (15).

  As described above, in the data transfer system according to the present embodiment, each write data is transferred from the bus bridge 3 driven by the clock CLK to the registers R1 to R3 driven by the clock CLKp asynchronous with the clock CLK. Write data is transferred to write buffers WB1 to WB3 provided corresponding to the registers R1 to R3 and driven by the same clock as the bus bridge 3. Thereafter, the write data is transferred from the write buffers WB1 to WB3 to the registers R1 to R3 by synchronizing the write buffers WB1 to WB3 and the registers R1 to R3. Therefore, since the access from the bus bridge 3 to the write buffers WB1 to WB3 is performed synchronously, the transfer of data from the bus bridge 3 to the peripheral circuits IP1 to IP3 (actually, the write buffers WB1 to WB3) is speeded up. Can do. In other words, by providing the write buffers WB1 to WB3, the registers R1 to R3 can be concealed when viewed from the bus bridge 3, so that the data transfer to the peripheral circuits IP1 to IP3 can be speeded up.

  A comparative example of the present invention will be described with reference to FIGS. FIG. 6 is a block diagram showing a data transfer system according to a comparative example. The data transfer system according to the comparative example shown in FIG. 6 is different from the data transfer system shown in FIG. 1 in that the peripheral circuit does not include a write buffer. The rest of the configuration is basically the same as that of the data transfer system shown in FIG.

  That is, in the data transfer system according to the comparative example shown in FIG. 6, the masters M101 to M103 are configured to be accessible to the peripheral circuits IP101 to IP103 via the bus bridge. Masters M101, M102, and M103 output write data D101, D102, and D103 to the bus bridge via the system bus, respectively. The bus bridge inputs the write data D101 to D103 from the masters M101 to M103, arbitrates the input write data D101 to D103, and the arbitrated write data D101 to D103 one by one through the peripheral bus IP1. ˜Output to registers R101 to R103 included in IP3. Here, the bus bridge operates with the clock CLK, and the peripheral circuits IP1 to IP3 (registers R101 to R103) operate with the clock CLKp asynchronous with the clock CLK.

  FIG. 7 is a timing chart for explaining the operation of the data transfer system according to the comparative example shown in FIG. In FIG. 7, the upper part shows the operation of the bus bridge, and the lower part shows the operation of the registers R101 to R103 provided in the peripheral circuit. As shown in FIG. 7, the bus bridge operates with the clock CLK, and the registers R101 to R103 operate with the clock CLKp asynchronous with the clock CLK.

  At the timing of T111, the bus bridge outputs the enable signal EN_BB, the address signal (IP101), and the write data D101 to the peripheral circuit IP101. At the timing of T102, the peripheral circuit IP101 outputs a high level wait signal 122 to the bus bridge. After the timing of T111, the bus bridge continues to occupy the peripheral bus to transfer data to the peripheral circuit IP101.

  When the bus bridge and the peripheral circuit are synchronized at the timing of T113, data is transferred from the bus bridge to the register R101 of the peripheral circuit IP101. Thereafter, the wait signal becomes low level at the timing of T114, and the bus bridge becomes ready to transfer the next write data. At this timing, the bus bridge outputs the write data D102 to the peripheral circuit IP102. Thereafter, the same operations as in T111 to T114 are repeated.

  In this way, in the data transfer system according to the comparative example shown in FIG. 6, the bus bridge and the registers R101 to R103 operate with different clocks, so that the bus bridge transfers data to the registers R101 to R103. It was necessary to synchronize the bridge and the registers R101 to R103. For this reason, it takes time to transfer write data from the bus bridge to the registers R101 to R103, and there is a problem that it takes a long time to occupy the peripheral bus when the bus bridge transfers one write data. Therefore, in order for the bus bridge to transfer the write data D102 next to the write data D101, it is necessary to wait for the completion of the transfer of the write data from the bus bridge to the register R101, and from the bus bridge to the registers R101 to R103. There was a problem that it took time to transfer the write data.

  In contrast, in the data transfer system according to the present embodiment, write buffers WB1 to WB3 that are driven by the same clock as the bus bridge 3 are provided between the bus bridge 3 and the registers R1 to R3. Therefore, since the access from the bus bridge 3 to the write buffers WB1 to WB3 is performed synchronously, the transfer of data from the bus bridge 3 to the peripheral circuits IP1 to IP3 (actually, the write buffers WB1 to WB3) is speeded up. Can do. In other words, by providing the write buffers WB1 to WB3, the registers R1 to R3 can be concealed when viewed from the bus bridge 3, so that the data transfer to the peripheral circuits IP1 to IP3 can be speeded up. That is, the time required for the bus bridge 3 included in the data transfer system according to the present embodiment to transfer one write data (T1 to T3 in FIG. 4, that is, two clocks CLK) is a comparative example. The time required for the bus bridge provided in such a data transfer system to transfer one write data is significantly shorter than the time required from T111 to T114 in FIG.

  As described above, the invention according to this embodiment can provide a data transfer system and a data transfer method that can transfer data from a master to a peripheral circuit without degrading system performance.

Embodiment 2
Next, a second embodiment of the present invention will be described. FIG. 8 is a block diagram showing the data transfer system according to the present embodiment. In the data transfer system according to the present embodiment, the peripheral circuit IP11 includes a plurality of write buffers WB11 to WB13 and a plurality of registers R11 to R13 corresponding to the write buffers WB11 to WB13, respectively. Different. The data transfer system according to this embodiment will be described in detail below.

  The master M11 (6) is configured to be accessible to the peripheral circuit IP11 (10) via the system bus 7, the bus bridge 8, and the peripheral bus 9. The master M11 outputs write data D11, D12, and D13 to the bus bridge 8 via the system bus 7, respectively. Here, the master M11 may operate in synchronization with the clock CLK, or may operate with a clock asynchronous with the clock CLK.

  The bus bridge 8 inputs the write data D11 to D13 output from the master M11, and outputs the input write data D11 to D13 one by one to the write buffers WB11 to WB13 included in the peripheral circuit IP11 via the peripheral bus 9. To do. Here, for example, the write data D11 is output to the write buffer WB11, the write data D12 is output to the write buffer WB12, and the write data D13 is output to the write buffer WB13. The bus bridge 8 operates with the clock CLK.

  Peripheral circuit IP11 includes write buffers WB11-WB13 and registers R11-R13. The write buffers WB11 to WB13 hold the write data D11 to D13 output from the bus bridge 8, respectively. Here, both the bus bridge 8 and the write buffers WB11 to WB13 operate with the same clock CLK. The bus bridge 8 may output an enable signal and an address signal together with the write data D11 to D13 to the write buffers WB11 to WB13.

  The write buffers WB11 to WB13 output a high-level signal as the wait signal 92 when the write data D11 to D13 output from the bus bridge 8 is in the middle of transfer. That is, when the wait signal is at the high level, the bus bridge 8 waits without outputting the next write data to the write buffers WB11 to WB13.

  The registers R11 to R13 operate with a clock CLKp that is asynchronous with the clock CLK. Here, the clock CLKp can be a slower clock than the clock CLK. For example, when the write data D11 held in the write buffer WB11 is transferred from the write buffer WB11 to the register R11, the write data D11 can be transferred by synchronizing the write buffer WB11 and the register R11. The same applies to the write buffers WB12 and WB13. Note that the data transfer rate from the write buffer WB11 to the register R11 is sufficiently lower than the data transfer rate from the bus bridge 8 to the write buffer WB11.

  The peripheral circuit IP11 provided in the data transfer system according to the present embodiment will be described in detail with reference to FIG. Note that the configuration of the peripheral circuit IP11 described below is an example, and any configuration may be used as long as the circuit operates in the same manner.

  The peripheral circuit IP11 includes write buffers WB11 to WB13 (21_1 to 21_3), an address decoder 22, an enable signal synchronization circuit 23, an enable pulse generation circuit 24, and registers R11 to R13 (25_1 to 25_3). In the present embodiment, one peripheral circuit IP11 includes a plurality of write buffers WB11 to WB13 (21_1 to 21_3) and a plurality of registers R11 to R13 (25_1 to 25_3). Here, the write buffers WB11 to WB13 (21_1 to 21_3) and the address decoder 22 operate with the clock CLK. The enable signal synchronization circuit 23, the enable pulse generation circuit 24, and the registers R11 to R13 (25_1 to 25_3) operate with the clock CLKp.

  The address decoder 22 receives the address signals (WB11 to WB13) output from the bus bridge 8 and the enable signal EN_BB. Then, the address decoder 22 outputs enable signals EN_WB11 to EN_WB13 to the write buffers WB11 to WB13 (21_1 to 21_3) and the enable signal synchronization circuit 23 corresponding to the input address signals (WB11 to WB13). The write buffers WB11 to WB13 (21_1 to 21_3) take in the write data D11 to D13 output from the bus bridge 8 at the timing when the high level enable signals EN_WB11 to EN_WB13 are supplied.

  Specifically, when receiving the address signal (WB11), the address decoder 22 outputs a high-level enable signal EN_WB11 to the write buffer WB11 (21_1). The write buffer WB11 (21_1) takes in the write data D11 output from the bus bridge 8 at the timing when the high level enable signal EN_WB11 is supplied. Similarly, when an address signal (WB12) is input, the address decoder 22 outputs a high-level enable signal EN_WB12 to the write buffer WB12 (21_2). The write buffer WB12 (21_2) takes in the write data D12 output from the bus bridge 8 at the timing when the high level enable signal EN_WB12 is supplied. Similarly, when an address signal (WB13) is input, the address decoder 23 outputs a high-level enable signal EN_WB13 to the write buffer WB13 (21_3). The write buffer WB13 (21_3) takes in the write data D13 output from the bus bridge 8 at the timing when the high level enable signal EN_WB13 is supplied.

  Further, when the high level enable signals EN_WB11 to EN_WB13 are supplied to the enable signal synchronization circuit 23, the enable signal synchronization circuit 23 starts from the write buffers WB11 to WB13 (21_1 to 21_3) to the registers R11 to R13 (25_1 to 25_3). ) Generates a synchronization completion signal 29 indicating the timing for transferring the write data D11 to D13, and outputs it to the enable pulse generation circuit 24. When receiving the synchronization completion signal 29 output from the enable signal synchronization circuit 23, the enable pulse generation circuit 24 outputs high level enable signals EN_REG11 to EN_REG13 to the registers R11 to R13 (25_1 to 25_3). When high level enable signals EN_REG11 to EN_REG13 are supplied to the registers R11 to R13 (25_1 to 25_3), the registers R11 to R13 (25_1 to 25_3) are held in the write buffers WB11 to WB13 (21_1 to 21_3). Data D11-D13 is taken in.

  Next, the operation of the data transfer system according to this exemplary embodiment will be described. FIG. 10 is a timing chart for explaining the operation of the data transfer system according to the present embodiment. 10, the upper stage shows the operation of the bus bridge 8, and the lower stage shows the operation of the write buffers WB11 to WB13 provided in the peripheral circuit IP11. As shown in FIG. 10, the bus bridge 8 and the write buffers WB11 to WB13 operate in synchronization with the clock CLK.

  At the timing of T11, the bus bridge 8 outputs the enable signal EN_BB and the address signal (WB11) to the address decoder 12 provided in the peripheral circuit IP11 and the write data D11 to the write buffer WB11.

  At timing T12, the address decoder 12_1 included in the peripheral circuit IP11 outputs a high level enable signal EN_WB11 to the write buffer WB11. Thereafter, the write buffer WB11 takes in the write data D11 output from the bus bridge 8 at the timing of T13.

  At the timing of T13, the bus bridge 8 outputs the enable signal EN_BB and the address signal (WB12) to the address decoder 12 included in the peripheral circuit IP11 and the write data D12 to the write buffer WB12.

  At the timing T14, the address decoder 12 included in the peripheral circuit IP11 outputs a high-level enable signal EN_WB12 to the write buffer WB12. Thereafter, the write buffer WB12 takes in the write data D12 output from the bus bridge 8 at the timing of T15.

  At time T15, the bus bridge 8 outputs the enable signal EN_BB and the address signal (WB3) to the address decoder 12 provided in the peripheral circuit IP11 and the write data D13 to the write buffer WB13.

  At timing T16, the address decoder 12 included in the peripheral circuit IP11 outputs a high-level enable signal EN_WB13 to the write buffer WB13. Thereafter, the write buffer WB13 takes in the write data D13 output from the bus bridge 8 at the timing of T17.

  Next, an operation when data is transferred from the write buffers WB11 to WB13 to the registers R11 to R13 will be described with reference to FIG. Although FIG. 11 shows only the case where data is transferred from the write buffer WB11 to the register R11, when data is transferred from the write buffer WB12 to the register R12, data is transferred from the write buffer WB13 to the register R13. This also applies to the case where

  As shown in FIG. 11, the write buffers WB11 to WB13 operate with a clock CLK, and the registers R11 to R13 operate with a clock CLKp that is asynchronous with the clock CLK. The enable signal EN_WB11 becomes high level at the timing T12, and the write data D11 is held in the write buffer WB11 at the timing T13. Further, the enable signal EN_WB11 having a high level is supplied to the enable signal synchronization circuit 13 at the timing of T12. After the timing T12, the enable signal synchronization circuit 13 generates a synchronization completion signal 29 indicating the timing for transferring the write data D11 from the write buffer WB11 to the register R11. Then, at the timing of T18, the enable signal synchronization circuit 13 outputs a synchronization completion signal 29 to the enable pulse generation circuit 14.

  The enable pulse generation circuit 14 outputs a high-level enable signal EN_REG11 to the register R11 at a timing T19 one clock after the timing T18 when the synchronization completion signal 29 becomes a high level. When the high-level enable signal EN_REG11 is supplied to the register R11, the register R11 takes in the write data D11 held in the write buffer WB11 at the timing of T20. With this operation, data is transferred from the write buffer WB11 to the register R11.

  As described above, in the data transfer system according to the present embodiment, when data is transferred from the bus bridge 8 driven by the clock CLK to the registers R11 to R13 driven by the clock CLKp asynchronous with the clock CLK, each register is transferred. Data is transferred to write buffers WB11 to WB13 provided corresponding to R11 to R13 and driven by the same clock as the bus bridge 8. Thereafter, by synchronizing the write buffers WB11 to WB13 and the registers R11 to R13, data is transferred from the write buffers WB11 to WB13 to the registers R11 to R13. Therefore, since access from the bus bridge 8 to the write buffers WB11 to WB13 is performed in synchronization, the data transfer from the bus bridge 8 to the write buffers WB11 to WB13 included in the peripheral circuit IP11 can be speeded up. In other words, by providing the write buffers WB11 to WB13, the registers R11 to R13 can be concealed when viewed from the bus bridge 8, so that the data transfer to the peripheral circuit IP11 can be speeded up.

  As described above, the invention according to this embodiment can provide a data transfer system and a data transfer method that can transfer data from a master to a peripheral circuit without degrading system performance.

Embodiment 3
Next, a third embodiment of the present invention will be described. In the data transfer system according to the present embodiment, the configuration of the peripheral circuit is different from that in the first embodiment. Since other than this is the same as in the case of the first embodiment, the same components are denoted by the same reference numerals, and redundant description is omitted. The invention according to the present embodiment can also be applied to the second embodiment.

  In the data transfer system according to the first embodiment, the time required to transfer write data from the write buffer to the register depends on the time required to synchronize the write buffer and the register. It was not possible to arbitrarily set the order in which In addition, the master cannot confirm whether or not the write data is transferred from the write buffer to the register. In the data transfer system according to the present embodiment, the master can confirm completion of data transfer by providing a synchronization flag setting circuit indicating whether or not write data is transferred from the write buffer to the register. become able to. Furthermore, by providing a synchronization flag setting circuit, it is possible to arbitrarily set the order in which write data is transferred from the master to the register.

  FIG. 12 is a block diagram showing peripheral circuits included in the data transfer system according to the present embodiment. The peripheral circuit shown in FIG. 12 is different from the peripheral circuit (see FIG. 3) included in the data transfer system according to the first embodiment in that it includes a synchronization flag setting circuit 31 and a completion signal synchronization circuit 32. The peripheral circuit IP1 will be described below, but the same applies to the peripheral circuits IP2 and IP3.

  When the high-level enable signal EN_WB1 is output from the address decoder 12, the synchronization flag setting circuit 31 sets the synchronization flag to “1” (high level). Further, the synchronization flag setting circuit 31 outputs the synchronization flag “1” to the enable signal synchronization circuit 13. When the synchronization flag “1” is supplied to the enable signal synchronization circuit 13, the enable signal synchronization circuit 13 synchronizes the write data D1 from the write buffer WB1 (11) to the register R1 (15). Complete signal 19 is generated and output to enable pulse generation circuit 14. When the enable pulse generation circuit 14 receives the synchronization completion signal 19 output from the enable signal synchronization circuit 13, the enable pulse generation circuit 14 outputs a high-level enable signal EN_REG1 to the register R1 (15). When the high level enable signal EN_REG1 is supplied to the register R1 (15), the register R1 (15) takes in the write data D1 held in the write buffer WB1 (11).

  Further, the completion signal synchronization circuit 32 inputs the synchronization completion signal 19 output from the enable signal synchronization circuit 13. Here, the synchronization completion signal 19 is a signal indicating completion of transfer of write data from the write buffer WB1 (11) to the register R1 (15). The completion signal synchronization circuit 32 having received the synchronization completion signal 19 has completed the transfer of the write data from the write buffer WB1 (11) to the register R1 (15), and therefore sets the synchronization flag of the synchronization flag setting circuit 31. Reset to “0”.

  That is, when the synchronization flag of the synchronization flag setting circuit 31 is in the set state “1”, it indicates that the transfer of the write data from the write buffer WB1 (11) to the register R1 (15) is not completed. . On the other hand, when the synchronization flag of the synchronization flag setting circuit 31 is in the reset state “0”, it indicates that the transfer of the write data from the write buffer WB1 (11) to the register R1 (15) is completed. The synchronization flag of the synchronization flag setting circuit 31 provided in each peripheral circuit IP1 to IP3 is output to each master M1 to M3. As a result, each of the masters M1 to M3 can confirm whether or not the write data has been transferred to each of the registers R1 to R3.

  FIG. 13 is a flowchart for explaining the operation of the data transfer system according to this embodiment. The flowchart shown in FIG. 13 shows a case where write data is transferred from the master M1 to the register R1 of the peripheral circuit IP1.

  At the timing T21, the bus bridge 3 outputs the enable signal EN_BB and the address signal (IP1) to the address decoder 12 provided in the peripheral circuit IP1, and the write data D1 to the write buffer WB1.

  At timing T22, the address decoder 12 included in the peripheral circuit IP1 outputs a high level enable signal EN_WB1 to the write buffer WB1. When the high-level enable signal EN_WB1 is output from the address decoder 12, the synchronization flag setting circuit 31 sets the synchronization flag to “1”. Further, the synchronization flag setting circuit 31 outputs the synchronization flag “1” to the enable signal synchronization circuit 13. Thereafter, the write buffer WB1 takes in the write data D1 output from the bus bridge 3 at the timing of T23.

  After the timing T22, the enable signal synchronization circuit 13 generates a synchronization completion signal 19 indicating the timing for transferring the write data D1 from the write buffer WB1 (11) to the register R1 (15). Then, at the timing of T24, the enable signal synchronization circuit 13 outputs a synchronization completion signal 19 to the enable pulse generation circuit 14.

  At the timing of T25, the completion signal synchronization circuit 32 sets the synchronization flag of the synchronization flag setting circuit 31 to “0” because the synchronization completion signal 19 output from the enable signal synchronization circuit 13 becomes high level. Reset to.

  The enable pulse generation circuit 14 outputs a high level enable signal EN_REG1 to the register R1 (15) at a timing T26 one clock after the timing T24 when the synchronization completion signal 19 becomes a high level. When the high level enable signal EN_REG1 is supplied to the register R1 (15), the register R1 (15) takes in the write data D1 held in the write buffer WB1 (11) at the timing of T27.

  FIG. 14A is a diagram for explaining the operation of the data transfer system according to the first embodiment, and FIG. 14B is a diagram for explaining the operation of the data transfer system according to the present embodiment. It is.

  In the data transfer system according to the first embodiment that does not have the synchronization flag setting circuit 31, the write data is transferred from the master M1 to the write buffer WB1 at the timing T30, and the write data is transferred from the master M2 to the write buffer WB2 at the timing T31. And the write data is transferred from the master M3 to the write buffer WB3 at the timing of T32. Further, after the write data is transferred from the master M1 to the write buffer WB1, the write buffer WB1 and the register R1 are synchronized, whereby the write data D1 is transferred to the register R1 (T33). Similarly, after write data is transferred from the master M2 to the write buffer WB2, the write buffer WB2 and the register R2 are synchronized, whereby the write data D2 is transferred to the register R2 (T36). Similarly, after write data is transferred from the master M3 to the write buffer WB3, the write buffer WB3 and the register R3 are synchronized, whereby the write data D3 is transferred to the register R3 (T35).

  Here, the timing at which each write buffer and each register is synchronized differs depending on each write buffer and each register. For this reason, the time during which write data is transferred from each write buffer to each register is also different. In addition, each master could not confirm whether or not write data was transferred from the write buffer to the register. Therefore, in the data transfer system according to the first exemplary embodiment, the order in which write data is transferred from the master to the register cannot be set.

  In contrast, in the data transfer system according to the present embodiment, since the peripheral circuit includes the synchronization flag setting circuit 31, the order of data transfer to the registers can be set. The operation of the data transfer system according to the present embodiment including the synchronization flag setting circuit 31 will be described with reference to FIG. In the example shown in FIG. 14B, it is assumed that the write data is set to be transferred from the master M3 to the register R3 after the write data is transferred to the register R2.

  Write data is transferred from the master M1 to the write buffer WB1 at timing T40, and write data is transferred from the master M2 to the write buffer WB2 at timing T41. At the timing T42, since the data transfer from the write buffer WB2 to the register R2 is not completed, the synchronization flag of the synchronization flag setting circuit 31 of the peripheral circuit IP2 becomes “1”. At this time, the master M3 stands by without outputting the write data D3 to the write buffer WB3 because the synchronization flag of the synchronization flag setting circuit 31 of the peripheral circuit IP2 is “1”. On the other hand, since the master M1 can transfer the write data to the register R1 regardless of the transfer order of the write data, the write data is transferred from the master M1 to the write buffer WB1 at the timing of T44. Thereafter, the master M3 waits without transferring the write data D3 until the synchronization flag of the synchronization flag setting circuit 31 of the peripheral circuit IP2 becomes “0”.

  When the write data D2 is transferred from the write buffer WB2 to the register R2 at the timing T46, the synchronization flag of the synchronization flag setting circuit 31 of the peripheral circuit IP2 becomes “0”. Then, the write data D3 is transferred from the master M3 to the write buffer WB3 at the timing of T47, and the write data D3 is transferred to the register R3 at the timing of T49.

  In the data transfer system according to the present embodiment, for example, in an application for which the order of access (data transfer) is to be set, software is checked so as to check the synchronization flag of the synchronization flag setting circuit 31 before issuing the next access. May be used.

  As described above, in the data transfer system according to the present embodiment, the synchronization flag setting circuit 31 indicating whether or not the write data is transferred from the write buffer to the register is provided in the peripheral circuit. The master can confirm the completion of. Furthermore, by providing the synchronization flag setting circuit 31, the order of transferring write data from the master to the register can be arbitrarily set.

  In the data transfer system according to the present embodiment, when the synchronization flag is “1”, the master waits without transferring the write data, so the transfer speed of the write data from the master to the register is the same as the embodiment. 1 is slower than the data transfer system according to 1. However, in the data transfer system according to the present embodiment, other masters can access the write buffer while the synchronization flag is “1” and the master is waiting without accessing the write buffer. 14B, since the synchronization flag is “1” at the timing of T42, the master M3 waits without accessing the write buffer WB3. The master M1 can access the write buffer WB1 at the timing T44 when the master M3 is waiting. Therefore, data can be transferred from the master to the peripheral circuit without degrading the system performance.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and can be made by those skilled in the art within the scope of the invention of the claims of the claims of the present application. It goes without saying that various modifications, corrections, and combinations are included.

1, 6 Master 2, 7 System bus 3, 8 Bus bridge 4, 9 Peripheral bus 5, 10 Peripheral circuit 11, 21 Write buffer 12, 22 Address decoder 13, 23 Enable signal synchronization circuit 14, 24 Enable pulse generation circuit 15 , 25 Registers 19, 29 Synchronization completion signal 31 Synchronization flag setting circuit 32 Completion signal synchronization circuit

Claims (9)

With at least one master,
A bus bridge that inputs data output from the at least one master via a first bus and outputs the data via a second bus;
The first and second write buffers capable of holding the data output from the bus bridge, and the first and second write buffers are provided corresponding to the first and second write buffers, and are output from the first and second write buffers. A peripheral circuit comprising first and second registers for holding the data respectively,
The bus bridge and the first and second write buffers operate with a first clock, and the bus bridge can transfer the data to the first and second write buffers according to the first clock. Yes,
The first and second registers operate with a second clock asynchronous to the first clock, and synchronize the first and second write buffers with the first and second registers, respectively. Transferring the data from the first and second write buffers to the first and second registers,
Data transfer system.   After transferring data to the first write buffer, the bus bridge transfers the next data regardless of whether the transfer of the data from the first write buffer to the first register is completed or not. The data transfer system according to claim 1, wherein the data transfer system outputs to the second write buffer.   3. The data transfer system according to claim 1, wherein the bus bridge transaction ends when the data is held in one of the first and second write buffers. 4. The first and second write buffers hold the data output from the bus bridge at a timing when the first clock rises,
The first and second registers hold the data at a timing when the second clock rises after the first and second write buffers output the data,
The data transfer system according to any one of claims 1 to 3.   The peripheral circuit includes a synchronization flag setting circuit that sets a synchronization flag indicating whether or not data has been transferred from the first and second write buffers to the first and second registers. The data transfer system as described in any one of thru | or 4.   6. The data transfer system according to claim 5, wherein at least one of the masters determines whether to output the data to the bus bridge according to a state of the synchronization flag. The master is composed of at least one of a main PE, an instruction memory, a data memory, and a security PE,
The peripheral circuit includes at least one of a CAN unit, a FLEXRAY unit, an SPI unit, a UART unit, an ADC unit, a WD unit, and a timer.
The first and second registers are provided in at least one of the CAN unit, the FLEXRAY unit, the SPI unit, the UART unit, the ADC unit, the WD unit, and the timer,
The first and second write buffers include at least one of the CAN unit, the FLEXRAY unit, the SPI unit, the UART unit, the ADC unit, the WD unit, the timer, and the second bus. Between
At least one of the CAN unit, the FLEXRAY unit, the SPI unit, the UART unit, the ADC unit, the WD unit, the timer, and the first and second registers operate with the second clock. ,
The data transfer system according to any one of claims 1 to 6. A data transfer method in a data transfer system, comprising:
The data transfer system includes:
With at least one master,
A bus bridge that inputs data output from the at least one master via a first bus and outputs the data via a second bus;
The first and second write buffers capable of holding the data output from the bus bridge, and the first and second write buffers are provided corresponding to the first and second write buffers, and are output from the first and second write buffers. A peripheral circuit comprising first and second registers for holding the data respectively,
Operating the bus bridge and the first and second write buffers with a first clock, transferring the data from the bus bridge to the first and second write buffers according to the first clock;
The first and second registers are operated with a second clock that is asynchronous with the first clock, and the first and second write buffers and the first and second registers are synchronized, respectively. The data is transferred from the first and second write buffers to the first and second registers, respectively.
Data transfer method.   After the bus bridge transfers data to the first write buffer, the next data is transferred to the first register regardless of whether the transfer of the data from the first write buffer to the first register is completed or not. The data transfer method according to claim 8, wherein the data is output to the write buffer of 2.

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