JP2012209522A - Retainer for semiconductor chip, and its usage - Google Patents

Retainer for semiconductor chip, and its usage Download PDF

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JP2012209522A
JP2012209522A JP2011076014A JP2011076014A JP2012209522A JP 2012209522 A JP2012209522 A JP 2012209522A JP 2011076014 A JP2011076014 A JP 2011076014A JP 2011076014 A JP2011076014 A JP 2011076014A JP 2012209522 A JP2012209522 A JP 2012209522A
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adhesive
semiconductor chip
semiconductor
holding layer
support substrate
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JP5717502B2 (en
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Kiyofumi Tanaka
清文 田中
Noriyoshi Hosono
則義 細野
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Shin Etsu Polymer Co Ltd
Shin Etsu Chemical Co Ltd
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Shin Etsu Polymer Co Ltd
Shin Etsu Chemical Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To provide a retainer for a semiconductor chip capable of improving productivity, preventing deterioration of a product rate, and also reducing manufacturing costs, and its usage.SOLUTION: In this retainer, an adhesive holding layer 10 is laminated on a supporting substrate 1, and plural semiconductor chips 2 jointed to a semiconductor wafer in line with each other are detachably and adhesively held. The supporting substrate 1 is formed into an approximately same size as that of the semiconductor wafer, and plural working holes 3 for the semiconductor chips 2 are bored on the supporting substrate 1. The adhesive holding layer 10 is provided with flexibility. One part of the adhesive holding layer 10 serves as an adhesion region 11 to the supporting substrate 1, and the remaining part of the adhesive holding layer 10 serves as a non-adhesion region 13 not adhered to the supporting substrate 1. Plural holding parts 15 for the semiconductor chips 2 are aligned and formed on the non-adhesion region 13, and each holding part 15 is blocked to be larger than the semiconductor chip 2. Each holding part 15 is opposed to the working holes 3 of the supporting substrate 1.

Description

本発明は、半導体の製造工程で半導体チップの積層や搬送等に使用される半導体チップ用保持具及びその使用方法に関するものである。   The present invention relates to a semiconductor chip holder used for stacking and transporting semiconductor chips in a semiconductor manufacturing process and a method for using the same.

近年、半導体の製造工程では、三次元LSI(大規模集積回路)の量産化に対応するため、半導体の三次元積層化技術が重視されている。この半導体の三次元積層化技術には、(1)半導体ウェーハ同士を直接ハンダ等により張り合わせて接合するウェハオンウェハ方式、(2)半導体ウェーハや半導体チップ上に良品の半導体チップを一個ずつハンダ等で接合するチップオンウェハ方式がある(特許文献1、2、3、4参照)。   2. Description of the Related Art In recent years, in a semiconductor manufacturing process, a semiconductor three-dimensional stacking technique is emphasized in order to cope with mass production of a three-dimensional LSI (large scale integrated circuit). This semiconductor three-dimensional stacking technology includes (1) a wafer-on-wafer method in which semiconductor wafers are directly bonded to each other with solder, etc., and (2) soldering good semiconductor chips one by one on the semiconductor wafer or semiconductor chip. There are chip-on-wafer systems that are bonded together (see Patent Documents 1, 2, 3, and 4).

(1)のウェハオンウェハ方式の場合には、優れた生産性が期待できるという特徴がある。また、(2)のチップオンウェハ方式は、製品率を向上させることができるという利点がある。   In the case of the wafer-on-wafer method (1), there is a feature that excellent productivity can be expected. Further, the chip-on-wafer method (2) has an advantage that the product rate can be improved.

特開2005−203657号公報JP 2005-203657 A 特開2008−153499号公報JP 2008-153499 A 特開2008−91696号公報JP 2008-91696 A 特開2004−273899号公報JP 2004-273899 A

しかしながら、(1)のウェハオンウェハ方式の場合には、生産性に優れるものの、半導体ウェーハ内に不良品が増大すると、複数枚の半導体ウェーハの張り合わせや積層に伴い、急激な製品率の低下を招くので、現実的ではなく、コストの削減を図ることもできないという問題がある。   However, in the case of the wafer-on-wafer method of (1), although the productivity is excellent, when the number of defective products increases in the semiconductor wafer, the product ratio is drastically decreased due to the bonding and lamination of a plurality of semiconductor wafers. Therefore, there is a problem that it is not realistic and the cost cannot be reduced.

これに対し、(2)のチップオンウェハ方式の場合には、急激な製品率の低下を防止することができるものの、生産性に劣るという問題がある。例えば、一枚の半導体ウェーハに500個の半導体チップが接合される場合、(1)のウェハオンウェハ方式では、一回の接合作業で完了するのに対し、(2)のチップオンウェハ方式では、接合作業を500回繰り返す必要があるので、生産性の向上が期待できない。   On the other hand, in the case of the chip-on-wafer method (2), there is a problem that the productivity is inferior although it is possible to prevent a rapid decrease in the product rate. For example, when 500 semiconductor chips are bonded to one semiconductor wafer, the wafer-on-wafer method (1) completes with one bonding operation, whereas the chip-on-wafer method (2) Since it is necessary to repeat the joining operation 500 times, improvement in productivity cannot be expected.

係る問題に対処するため、ウェハボンダを使用して生産性を改善する一括チップオンウェハ方式が提唱されている。しかしながら、この方式には、専用のチップ保持具が必要となるが、現在そのようなチップ保持具は全く存在しないので、採用することができず、現実性に乏しいという問題がある。   In order to cope with such a problem, a collective chip-on-wafer method using a wafer bonder to improve productivity has been proposed. However, this system requires a dedicated chip holder. However, since there is no such chip holder at present, there is a problem that it cannot be adopted and is not realistic.

本発明は上記に鑑みなされたもので、生産性の向上と製品率の低下防止を図ることができ、しかも、製造コストを削減することのできる半導体チップ用保持具及びその使用方法を提供することを目的としている。   The present invention has been made in view of the above, and it is possible to provide a semiconductor chip holder and a method of using the same that can improve productivity and prevent a reduction in product rate and can reduce manufacturing costs. It is an object.

本発明においては上記課題を解決するため、支持基板に粘着保持層を積層し、この粘着保持層に、半導体ウェーハに接合される複数の半導体チップを着脱自在に保持させる保持具であって、
支持基板を半導体ウェーハと略同サイズに形成し、粘着保持層に可撓性を付与してその一部を支持基板に対する接着領域とするとともに、粘着保持層の残部を支持基板に接着しない非接着領域とし、この非接着領域の表面に半導体チップ用の複数の保持部を形成して各保持部を半導体チップよりも大きく区画し、支持基板と粘着保持層の複数の保持部のいずれかに、半導体チップ用の複数の作業孔を穿孔したことを特徴としている。
In the present invention, in order to solve the above-mentioned problem, an adhesive holding layer is laminated on a support substrate, and this adhesive holding layer is a holding tool for detachably holding a plurality of semiconductor chips bonded to a semiconductor wafer,
The support substrate is formed to be approximately the same size as the semiconductor wafer, and the adhesive holding layer is made flexible so that a part thereof becomes an adhesive region to the support substrate, and the remaining part of the adhesive holding layer is not bonded to the support substrate. As a region, a plurality of holding portions for semiconductor chips are formed on the surface of the non-adhesive region, and each holding portion is partitioned larger than the semiconductor chip, and one of the plurality of holding portions of the support substrate and the adhesive holding layer, It is characterized by drilling a plurality of working holes for semiconductor chips.

なお、支持基板に複数の作業孔を穿孔して各作業孔の幅を半導体チップよりも小さくし、支持基板の作業孔に粘着保持層の保持部の略中央を対向させることができる。
また、支持基板と粘着保持層の接着領域とを両面粘着テープにより接着し、支持基板と粘着保持層の非接着領域との間に、支持基板の作業孔に連通する隙間を区画形成することができる。
A plurality of work holes can be drilled in the support substrate so that the width of each work hole is smaller than that of the semiconductor chip, and the substantially center of the holding portion of the adhesive holding layer can be opposed to the work hole of the support substrate.
In addition, the support substrate and the adhesive holding layer may be bonded to each other with a double-sided adhesive tape, and a gap communicating with the work hole of the support substrate may be defined between the support substrate and the non-adhesive region of the adhesive holding layer. it can.

また、支持基板の作業孔から隙間の空気を外部に排気することにより、非接着領域の保持部を支持基板に密接させることもできる。
また、粘着保持層の複数の保持部を、半導体ウェーハに並べて接合される複数の半導体チップの配列に対応するよう配列することも可能である。
Further, the holding portion in the non-adhesion region can be brought into close contact with the support substrate by exhausting the air in the gap from the work hole of the support substrate to the outside.
It is also possible to arrange the plurality of holding portions of the adhesive holding layer so as to correspond to the arrangement of a plurality of semiconductor chips that are aligned and bonded to the semiconductor wafer.

さらに、本発明においては上記課題を解決するため、請求項1、2、又は3記載の保持具の使用方法であって、
支持基板に粘着保持層の複数の保持部を密接して複数の保持部に半導体チップを保持させ、半導体ウェーハと半導体チップ用保持具とを少なくとも加圧することにより、半導体ウェーハに複数の半導体チップを一括して接合し、その後、各半導体チップから粘着保持層の保持部を剥離することを特徴としている。
Furthermore, in order to solve the above-mentioned problem in the present invention, the method of using the holder according to claim 1, 2, or 3,
A plurality of holding parts of the adhesive holding layer are brought into close contact with the support substrate, the semiconductor chips are held in the holding parts, and the semiconductor wafer and the semiconductor chip holder are pressed at least, whereby the plurality of semiconductor chips are put on the semiconductor wafer. It is characterized in that it is bonded together and then the holding part of the adhesive holding layer is peeled off from each semiconductor chip.

ここで、特許請求の範囲における支持基板は、半導体ウェーハと同サイズか、あるいは半導体ウェーハとおおよそ同じサイズであることが好ましい。半導体ウェーハには、少なくともφ200、300、450mmのシリコンウェーハ等からなる半導体ウェーハが含まれる。また、粘着保持層は、対向する支持基板の対向面の全面を被覆しても良いが、支持基板の対向面の周縁部等を除く面を被覆しても良い。この粘着保持層は、単層構造でも良いし、多層構造とすることもできる。   Here, the supporting substrate in the claims is preferably the same size as the semiconductor wafer or approximately the same size as the semiconductor wafer. The semiconductor wafer includes a semiconductor wafer made of at least φ200, 300, 450 mm silicon wafer or the like. In addition, the adhesive holding layer may cover the entire surface of the opposing surface of the supporting substrate, but may cover the surface excluding the peripheral portion of the opposing surface of the supporting substrate. The adhesion holding layer may have a single layer structure or a multilayer structure.

作業孔は、半導体チップよりも狭い幅であれば、円形、矩形、多角形等の形状を特に問うものではなく、気体の排気やピンの出し入れ等の作業に利用することができる。さらに、本発明に係る半導体チップ用保持具は、複数の半導体チップが接合される半導体ウェーハに加圧されたり、場合によっては加熱される事態が予想されるので、耐加圧性や耐熱性を有することが好ましい。さらに、搬送の便宜を図る観点から、トップオープンボックスタイプやフロントオープンボックスタイプ(例えば、FOSB等)の基板収納容器に収納可能であることが望ましい。   If the working hole has a width narrower than that of the semiconductor chip, the working hole is not particularly limited to a circular shape, a rectangular shape, a polygonal shape or the like, and can be used for work such as gas exhaustion and pin insertion / removal. Furthermore, since the semiconductor chip holder according to the present invention is expected to be pressurized or heated in some cases to a semiconductor wafer to which a plurality of semiconductor chips are bonded, it has pressure resistance and heat resistance. It is preferable. Furthermore, from the viewpoint of convenience of transport, it is desirable that the container can be stored in a substrate storage container of a top open box type or a front open box type (for example, FOSB).

本発明によれば、半導体チップ用保持具を使用して複数の半導体チップを保持し、この複数の半導体チップを半導体ウェーハに接合する場合には、先ず、支持基板に粘着保持層の複数の保持部を密接し、この複数の保持部に半導体チップを粘着保持させる。この際、支持基板あるいは粘着保持層の作業孔を利用してこれらの間の気体を外部に排気すれば、支持基板に粘着保持層の複数の保持部を簡単に密接することができる。このように支持基板に粘着保持層の保持部が密接するので、粘着保持層が半導体チップの粘着により厚さ方向に撓んだり、伸びることが少ない。   According to the present invention, when holding a plurality of semiconductor chips using a semiconductor chip holder, and bonding the plurality of semiconductor chips to a semiconductor wafer, first, a plurality of holding adhesive layers on the support substrate. The parts are brought into close contact with each other, and the semiconductor chip is adhered and held by the plurality of holding parts. At this time, if the gas between them is exhausted to the outside using the working holes of the support substrate or the adhesive holding layer, the plurality of holding portions of the adhesive holding layer can be easily brought into close contact with the support substrate. As described above, since the holding portion of the adhesive holding layer is in close contact with the support substrate, the adhesive holding layer is unlikely to bend or extend in the thickness direction due to the adhesion of the semiconductor chip.

粘着保持層の複数の保持部に半導体チップを保持させたら、半導体ウェーハと半導体チップ用保持具とを少なくとも加圧することにより、半導体ウェーハに複数の半導体チップを一括して接合した後、各半導体チップから粘着保持層の保持部を剥離すれば、複数の半導体チップを半導体ウェーハに接合することができる。この際、半導体チップ用保持具の支持基板が半導体ウェーハと略同サイズの大きさなので、半導体ウェーハと半導体チップ用保持具とを容易に位置合わせすることができる。   After the semiconductor chips are held by the plurality of holding portions of the adhesive holding layer, the semiconductor wafers are bonded to the semiconductor wafer at a time by at least pressurizing the semiconductor wafer and the semiconductor chip holder, and then each semiconductor chip. If the holding part of the adhesive holding layer is peeled off, a plurality of semiconductor chips can be bonded to the semiconductor wafer. At this time, since the support substrate of the semiconductor chip holder is approximately the same size as the semiconductor wafer, the semiconductor wafer and the semiconductor chip holder can be easily aligned.

本発明によれば、生産性の向上と製品率の低下防止を図ることができ、しかも、製造コストを削減することができるという効果がある。   According to the present invention, it is possible to improve productivity and prevent a reduction in product rate, and to reduce manufacturing costs.

また、請求項2記載の発明によれば、支持基板の作業孔の幅が半導体チップよりも小さいので、保持部に保持された半導体チップのエッジ等を突き出しピン等により突いたり、損傷させるおそれが少ない。また、支持基板の作業孔が保持部の略中央に対向するので、突き出しピン等により半導体チップの偏った端部ではなく、略中央を突くことができ、半導体チップと粘着保持層の保持部とを適切に剥離することができる。   According to the second aspect of the present invention, since the width of the working hole of the support substrate is smaller than that of the semiconductor chip, there is a risk that the edge of the semiconductor chip held in the holding portion will be protruded by a protruding pin or damaged. Few. In addition, since the working hole of the support substrate faces approximately the center of the holding portion, it is possible to protrude the approximate center instead of the biased end portion of the semiconductor chip by a protruding pin or the like, and the holding portion of the semiconductor chip and the adhesive holding layer Can be appropriately peeled off.

さらに、請求項3記載の発明によれば、複数の保持部の配列が半導体ウェーハに並べて接合される複数の半導体チップの配列と対応するので、半導体ウェーハに複数の半導体チップを一度にまとめて接合することが可能となる。   Furthermore, according to the invention described in claim 3, since the arrangement of the plurality of holding portions corresponds to the arrangement of the plurality of semiconductor chips to be bonded to the semiconductor wafer, the plurality of semiconductor chips are bonded to the semiconductor wafer all at once. It becomes possible to do.

本発明に係る半導体チップ用保持具の実施形態を模式的に示す平面説明図である。It is a plane explanatory view showing typically an embodiment of a holder for semiconductor chips concerning the present invention. 本発明に係る半導体チップ用保持具及びその使用方法の実施形態を模式的に示す断面説明図である。It is a section explanatory view showing typically an embodiment of a holding fixture for semiconductor chips concerning the present invention, and a method for using the same.

以下、図面を参照して本発明の実施形態を説明すると、本実施形態における半導体チップ用保持具は、図1や図2に示すように、支持基板1に変形可能な粘着保持層10を積層し、この粘着保持層10に、半導体ウェーハに接合される複数の半導体チップ2を保持させる保持具であり、支持基板1に、半導体チップ2用の作業孔3を穿孔し、粘着保持層10の一部を接着領域11とするとともに、粘着保持層10の残部を非接着領域13とし、この非接着領域13に半導体チップ2用の複数の保持部15を形成するようにしている。   DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. A semiconductor chip holder in this embodiment includes a deformable adhesive holding layer 10 laminated on a support substrate 1 as shown in FIGS. 1 and 2. The adhesive holding layer 10 is a holder for holding a plurality of semiconductor chips 2 to be bonded to the semiconductor wafer. The support substrate 1 is punched with work holes 3 for the semiconductor chips 2. A part of the adhesive holding layer 10 is used as a part, and the remaining part of the adhesive holding layer 10 is used as a non-adhesive area 13, and a plurality of holding parts 15 for the semiconductor chip 2 are formed in the non-adhesive area 13.

支持基板1は、複数の半導体チップ2が並べてパターン実装される半導体ウェーハ(図示せず)と同サイズの半導体ウェーハ、あるいはこの半導体ウェーハと略同サイズの平坦なガラス基板等により平面円形に形成され、好ましくは基板収納容器の容器本体内に相対向する複数の支持片を介して収納される。各半導体チップ2は、粘着保持層10の保持部15よりもやや小さい平面略矩形に形成され、シリコンウェーハ等からなる半導体ウェーハのパターン面に250℃程度の高温の環境下でハンダ等により接合される。   The support substrate 1 is formed in a planar circle by a semiconductor wafer having the same size as a semiconductor wafer (not shown) on which a plurality of semiconductor chips 2 are arranged and mounted in a pattern, or a flat glass substrate having the same size as the semiconductor wafer. Preferably, it is accommodated in the container main body of the substrate storage container via a plurality of opposing support pieces. Each semiconductor chip 2 is formed in a substantially rectangular plane that is slightly smaller than the holding portion 15 of the adhesive holding layer 10 and is bonded to a pattern surface of a semiconductor wafer made of a silicon wafer or the like by solder or the like in a high temperature environment of about 250 ° C. The

支持基板1は、半導体チップ2が粘着保持層10に保持された状態で半導体ウェーハに加圧してハンダ接合されたり、場合により加熱接合されるので、耐加圧性や少なくとも250℃程度の耐熱性を有することが好ましい。   Since the support substrate 1 is pressed and soldered to the semiconductor wafer while the semiconductor chip 2 is held on the adhesive holding layer 10, or is optionally heat-bonded, it has a pressure resistance and a heat resistance of at least about 250 ° C. It is preferable to have.

支持基板1の厚さ方向には図1や図2に示すように、複数の作業孔3が貫通して穿孔され、各作業孔3が粘着保持層10に保持された半導体チップ2の減圧による位置決めや突き出しピン20による突き上げ剥離に利用される。各作業孔3は、半導体チップ2よりも小さい円形の縮径に穿孔される。これは、作業孔3が半導体チップ2よりも大きい拡径の場合には、半導体チップ2の剥離時に半導体チップ2のエッジ等を突き出しピン20が粘着保持層10を介して突き上げ、損傷させるおそれがあるからである。   In the thickness direction of the support substrate 1, as shown in FIGS. 1 and 2, a plurality of work holes 3 are drilled through, and each work hole 3 is caused by decompression of the semiconductor chip 2 held by the adhesive holding layer 10. This is used for positioning and push-up peeling by the push pin 20. Each work hole 3 is drilled to a circular reduced diameter smaller than that of the semiconductor chip 2. This is because, when the work hole 3 has a larger diameter than the semiconductor chip 2, the edge of the semiconductor chip 2 is protruded when the semiconductor chip 2 is peeled off, and the pins 20 may be pushed up through the adhesive holding layer 10 to be damaged. Because there is.

粘着保持層10は、所定の材料を使用して支持基板1の全表面を覆う可撓性の平面円形に形成され、支持基板1の平坦な表面に部分的に接着固定されており、半導体ウェーハに並べて接合される複数の半導体チップ2を着脱自在に粘着保持するよう機能する。この粘着保持層10の材料としては、例えば自己粘着性を有するポリオレフィン系エラストマーやウレタンゴム、耐熱性に優れるシリコーン系やフッ素系のエラストマー等が使用される。粘着保持層10は、粘着性を有しないフィルムの表面にアクリル系の粘着剤等が塗布して積層された薄膜構造でも良い。   The adhesive holding layer 10 is formed in a flexible planar circle that covers the entire surface of the support substrate 1 using a predetermined material, and is partially bonded and fixed to the flat surface of the support substrate 1. The plurality of semiconductor chips 2 to be joined side by side function so as to be detachably adhered. Examples of the material for the adhesive holding layer 10 include self-adhesive polyolefin elastomers and urethane rubbers, and silicone and fluorine elastomers having excellent heat resistance. The adhesive holding layer 10 may have a thin film structure in which an acrylic adhesive or the like is applied and laminated on the surface of a film having no adhesiveness.

粘着保持層10には、好ましくは柔軟性と大きな延伸性とが付与される。これは、粘着保持層10が柔軟性や延伸性を有しない場合には、粘着保持層10に粘着保持された半導体チップ2の剥離が困難になるおそれがあるからである。   The adhesive holding layer 10 is preferably provided with flexibility and large stretchability. This is because if the adhesive holding layer 10 does not have flexibility or stretchability, it may be difficult to peel off the semiconductor chip 2 that is adhesively held on the adhesive holding layer 10.

粘着保持層10は、その狭い一部が支持基板1の表面に対する接着領域11とされるとともに、広い残部が支持基板1の表面に接着しない非接着領域13とされ、この非接着領域13に半導体チップ2用の複数の保持部15が所定のパターンで配列形成される。接着領域11は、例えば支持基板1の作業孔3に干渉しない粘着保持層10の周縁部と複数の保持部15の間からなり、裏面が支持基板1の表面に接着される。この接着領域11の接着は、図2に示すように、例えばリング形や線条の両面粘着テープ12の接着等により実現される。   The adhesive holding layer 10 has a narrow part as an adhesion region 11 to the surface of the support substrate 1 and a wide remaining part as a non-adhesion region 13 that does not adhere to the surface of the support substrate 1. A plurality of holding portions 15 for the chip 2 are arranged in a predetermined pattern. The adhesion region 11 is formed, for example, between the peripheral edge portion of the adhesive holding layer 10 that does not interfere with the work hole 3 of the support substrate 1 and the plurality of holding portions 15, and the back surface is bonded to the surface of the support substrate 1. As shown in FIG. 2, the adhesion of the adhesion region 11 is realized by, for example, adhesion of a ring-shaped or linear double-sided pressure-sensitive adhesive tape 12.

但し、支持基板1の表面と粘着保持層10の接着領域裏面との接着は、両面粘着テープ12による接着に限定されるものではない。例えば、支持基板1の表面に粘着保持層10をその自己粘着性を利用して積層接着することもできる。また、支持基板1表面の接着領域11に対応する箇所に接着剤や粘着剤をディスペンサ等で塗布したり、あるいはスクリーン印刷し、その後、支持基板1の表面に粘着保持層10を積層して接着することもできる。   However, the adhesion between the front surface of the support substrate 1 and the back surface of the adhesion region of the adhesion holding layer 10 is not limited to the adhesion with the double-sided adhesive tape 12. For example, the adhesive holding layer 10 can be laminated and bonded to the surface of the support substrate 1 using its self-adhesiveness. Further, an adhesive or a pressure-sensitive adhesive is applied to a portion corresponding to the adhesion region 11 on the surface of the support substrate 1 with a dispenser or the like, or screen-printed, and then the adhesion holding layer 10 is laminated on the surface of the support substrate 1 for adhesion. You can also

ここで使用する接着剤や粘着剤としては、特に限定されるものではないが、例えばアクリル系、ウレタン系、エポキシ系、シリコーンゴムやスチレンゴム、フッ素ゴム等からなるゴム系のタイプがあげられる。但し、250℃程度で溶融するハンダバンプで半導体チップ2を接合する場合には、ハンダの溶融温度まで均一に加熱することが必要になるので、エポキシ系、シリコーンゴム系、フッ素系の耐熱性を有する接着剤や粘着剤を使用することが好ましい。   The adhesive or pressure-sensitive adhesive used here is not particularly limited, and examples thereof include rubber-based types made of acrylic, urethane, epoxy, silicone rubber, styrene rubber, fluorine rubber, and the like. However, when the semiconductor chip 2 is bonded with solder bumps that melt at about 250 ° C., it is necessary to uniformly heat up to the melting temperature of the solder, so that it has heat resistance such as epoxy, silicone rubber, and fluorine. It is preferable to use an adhesive or a pressure-sensitive adhesive.

粘着保持層10の非接着領域13は、図2に示すように、支持基板1の表面に裏面が粘着しないよう非粘着処理され、支持基板1の表面に両面粘着テープ12分の僅かな隙間14をおいて対向しており、この隙間14が支持基板1の作業孔3に連通する。また、複数の保持部15は、半導体ウェーハのパターン面に並べて接合される複数の半導体チップ2の配列に対応するよう、非接着領域13表面のXY方向に両面粘着テープ12分の間隔をおいて配列される。   As shown in FIG. 2, the non-adhesion region 13 of the adhesive holding layer 10 is non-adhesive treated so that the back surface does not adhere to the surface of the support substrate 1, and a slight gap 14 of double-sided adhesive tape 12 on the surface of the support substrate 1. The gap 14 communicates with the work hole 3 of the support substrate 1. In addition, the plurality of holding portions 15 are spaced by a double-sided adhesive tape 12 minutes in the XY direction on the surface of the non-adhesive region 13 so as to correspond to the arrangement of the plurality of semiconductor chips 2 that are aligned and bonded to the pattern surface of the semiconductor wafer. Arranged.

各保持部15は、半導体チップ2を安定した姿勢で確実に粘着保持することができるよう、半導体チップ2の周縁部よりも大きい平面矩形に区画され、中央が支持基板1の作業孔3に隙間14をおいて対向する。このような保持部15は、支持基板1の作業孔3から空気が外部に排気(図2の矢印参照)されることにより、断面略U字形に僅かに凹んで支持基板1の表面に密接することとなる。   Each holding portion 15 is partitioned into a planar rectangle larger than the peripheral portion of the semiconductor chip 2 so that the semiconductor chip 2 can be securely adhered and held in a stable posture, and the center is a gap in the work hole 3 of the support substrate 1. 14 opposite each other. Such a holding portion 15 is indented slightly in a substantially U-shaped cross section and is in close contact with the surface of the support substrate 1 when air is exhausted to the outside from the work hole 3 of the support substrate 1 (see the arrow in FIG. 2). It will be.

なお、粘着保持層10については、粘着保持層10の弾性変形領域内において、使用温度領域における線膨張分よりも予め大きく延伸した状態で支持基板1の表面に部分的に接着固定することができる。このようにすれば、使用温度領域の高温下で粘着保持層10が伸びた場合にも、保持部15で粘着保持層10が撓むのを防ぐことができ、保持部15における半導体チップ2の位置ずれを有効に防止することができる。   The adhesive holding layer 10 can be partially bonded and fixed to the surface of the support substrate 1 in the elastic deformation region of the adhesive holding layer 10 in a state in which the adhesive holding layer 10 is stretched to be larger than the linear expansion in the operating temperature region. . In this way, even when the adhesive holding layer 10 is stretched at a high temperature in the operating temperature range, the holding portion 15 can prevent the adhesive holding layer 10 from being bent, and the semiconductor chip 2 in the holding portion 15 can be prevented from bending. Misalignment can be effectively prevented.

上記構成において、半導体チップ用保持具を使用して複数の半導体チップ2を粘着保持し、この複数の半導体チップ2を半導体ウェーハに接合する場合には、先ず、図示しないバキューム装置を備えた吸着テーブル上に半導体チップ用保持具を配置し、支持基板1の複数の作業孔3を利用して減圧することにより、支持基板1の表面と粘着保持層10の非接着領域13との隙間14の空気を外部に排気するとともに、支持基板1に粘着保持層10の各保持部15を撓ませて密接し、粘着保持層10の複数の保持部15に選別した良品の半導体チップ2を順次粘着保持させる。   In the above configuration, when a plurality of semiconductor chips 2 are adhered and held using a semiconductor chip holder, and the plurality of semiconductor chips 2 are bonded to a semiconductor wafer, first, a suction table provided with a vacuum device (not shown). A semiconductor chip holder is arranged on the top and the pressure is reduced using the plurality of work holes 3 of the support substrate 1, whereby the air in the gap 14 between the surface of the support substrate 1 and the non-adhesive region 13 of the adhesive holding layer 10. The holding portions 15 of the adhesive holding layer 10 are bent and brought into close contact with the support substrate 1, and the selected good semiconductor chips 2 are sequentially held in an adhesive state by the plurality of holding portions 15 of the adhesive holding layer 10. .

この際、支持基板1の表面に粘着保持層10の保持部15が僅かに凹んで密接するので、粘着保持層10が半導体チップ2の粘着により厚さ方向に撓んだり、伸びることがない。これにより、半導体チップ2の位置ずれを防止することができるので、複数の保持部15に半導体チップ2を高精度に整列保持することができる。複数の保持部15に半導体チップ2を整列保持したら、バキューム装置を停止して粘着保持層10を元の非接触、非密接の状態に復帰可能とする。   At this time, since the holding portion 15 of the adhesive holding layer 10 is slightly recessed and brought into close contact with the surface of the support substrate 1, the adhesive holding layer 10 does not bend or extend in the thickness direction due to the adhesion of the semiconductor chip 2. Thereby, since the position shift of the semiconductor chip 2 can be prevented, the semiconductor chip 2 can be aligned and held in the plurality of holding portions 15 with high accuracy. When the semiconductor chip 2 is aligned and held in the plurality of holding portions 15, the vacuum device is stopped and the adhesive holding layer 10 can be returned to the original non-contact and non-contact state.

粘着保持層10の複数の保持部15に半導体チップ2をそれぞれ粘着保持させたら、半導体ウェーハのパターン面にハンダを塗布し、高温の環境下で半導体ウェーハに半導体チップ用保持具を重ねて少なくとも加圧することにより、半導体ウェーハのパターン面に複数の半導体チップ2を一括してハンダ接合し、その後、半導体ウェーハから半導体チップ用保持具を引き離して各半導体チップ2から粘着保持層10の保持部15を剥離すれば、複数の半導体チップ2を半導体ウェーハに完全に接合することができる。   After the semiconductor chip 2 is adhered and held on the plurality of holding portions 15 of the adhesive holding layer 10, solder is applied to the pattern surface of the semiconductor wafer, and at least the semiconductor chip holder is stacked on the semiconductor wafer in a high temperature environment. By pressing, the plurality of semiconductor chips 2 are collectively soldered to the pattern surface of the semiconductor wafer, and then the semiconductor chip holder is pulled away from the semiconductor wafer and the holding portion 15 of the adhesive holding layer 10 is removed from each semiconductor chip 2. If it peels, the several semiconductor chip 2 can be joined to a semiconductor wafer completely.

この際、半導体チップ用保持具の支持基板1が半導体ウェーハと略同サイズの大きさなので、半導体ウェーハと半導体チップ用保持具とを容易に位置合わせすることが可能となる。また、複数の保持部15の配列が半導体ウェーハに並べて接合される複数の半導体チップ2の配列と整合するので、複数の半導体チップ2を一回の作業でハンダ接合することが可能となる。また、半導体ウェーハから半導体チップ用保持具を引き離すと、粘着保持層10がある程度伸びるので、半導体チップ2の周縁部から粘着保持層10の保持部15を容易に剥離することができ、半導体チップ2の接合を破壊することがない。   At this time, since the support substrate 1 of the semiconductor chip holder is approximately the same size as the semiconductor wafer, the semiconductor wafer and the semiconductor chip holder can be easily aligned. In addition, since the arrangement of the plurality of holding portions 15 matches the arrangement of the plurality of semiconductor chips 2 that are aligned and bonded to the semiconductor wafer, the plurality of semiconductor chips 2 can be solder-bonded in one operation. Further, when the semiconductor chip holder is pulled away from the semiconductor wafer, the adhesive holding layer 10 extends to some extent, so that the holding part 15 of the adhesive holding layer 10 can be easily peeled from the peripheral edge of the semiconductor chip 2, and the semiconductor chip 2. Will not break the joint.

なお、半導体チップ2から粘着保持層10の保持部15を容易に剥離することができない場合には、支持基板1の作業孔3に突き出しピン20を下方等から挿入して保持部15の裏面に圧接し、半導体チップ2を保持部15を介して突き上げれば良い。こうすれば、支持基板1の作業孔3が保持部15の中央に対向するので、半導体チップ2裏面の略中央を突き上げることができ、半導体チップ2と粘着保持層10の保持部15とを確実に剥離することが可能となる。   When the holding part 15 of the adhesive holding layer 10 cannot be easily peeled from the semiconductor chip 2, the protruding pin 20 is inserted into the work hole 3 of the support substrate 1 from below or the like on the back surface of the holding part 15. The semiconductor chip 2 may be pushed up through the holding portion 15 by pressure contact. In this way, since the work hole 3 of the support substrate 1 faces the center of the holding portion 15, it is possible to push up substantially the center of the back surface of the semiconductor chip 2, and the semiconductor chip 2 and the holding portion 15 of the adhesive holding layer 10 can be securely connected. It becomes possible to peel.

上記構成によれば、半導体ウェーハ上に良品の半導体チップ2を一個ずつ接合するのではなく、半導体ウェーハのパターン面に複数の半導体チップ2をまとめてハンダ接合するので、生産性の向上が大いに期待できる。また、粘着保持層10の複数の保持部15に選別した良品の半導体チップ2を粘着保持させるので、製品率の低下を招くことが全くなく、大幅なコスト削減を図ることもできる。さらに、半導体ウェーハから半導体チップ用保持具を引き剥がせば、ハンダ接合した半導体チップ2と粘着保持層10の保持部15とを簡単に分離することができ、歩留まりと生産性の両立とを図ることができる。   According to the above configuration, a plurality of semiconductor chips 2 are collectively bonded to the pattern surface of the semiconductor wafer, rather than bonding good semiconductor chips 2 one by one on the semiconductor wafer, so that improvement in productivity is greatly expected. it can. In addition, since the non-defective semiconductor chips 2 selected by the plurality of holding portions 15 of the adhesive holding layer 10 are adhesively held, the product rate is not lowered at all, and a significant cost reduction can be achieved. Furthermore, if the semiconductor chip holder is peeled off from the semiconductor wafer, the solder-bonded semiconductor chip 2 and the holding portion 15 of the adhesive holding layer 10 can be easily separated to achieve both yield and productivity. be able to.

なお、上記実施形態では支持基板1に複数の作業孔3を穿孔したが、何らこれに限定されるものではない。例えば、粘着保持層10の複数の保持部15に作業孔3をそれぞれ穿孔し、この粘着保持層10の複数の作業孔3を利用することにより、支持基板1の表面と粘着保持層10の非接着領域13との隙間14の空気を外部に排気し、支持基板1に粘着保持層10の各保持部15を密接しても良い。   In the above embodiment, a plurality of work holes 3 are drilled in the support substrate 1, but the present invention is not limited to this. For example, the working holes 3 are respectively drilled in the plurality of holding portions 15 of the adhesive holding layer 10, and the plurality of working holes 3 of the adhesive holding layer 10 are used, whereby the surface of the support substrate 1 and the non-adhesive holding layer 10 can be removed. The air in the gap 14 with the adhesive region 13 may be exhausted to the outside, and the holding portions 15 of the adhesive holding layer 10 may be in close contact with the support substrate 1.

また、上記実施形態の粘着保持層10には、表面に適当な粘着性を確保したり、必要な物性や耐熱性等を得るため、各種の処理を施すことができる。例えば、化学エッチング法やガスによるエッチング法とレジスト印刷法との組み合わせにより、粘着保持層10の任意の部分を粘着性にしたり、非粘着性にすることができる。   In addition, the adhesive holding layer 10 of the above embodiment can be subjected to various treatments in order to ensure appropriate adhesiveness on the surface and to obtain necessary physical properties, heat resistance, and the like. For example, an arbitrary portion of the adhesive holding layer 10 can be made sticky or non-sticky by a combination of a chemical etching method, a gas etching method, and a resist printing method.

本発明に係る半導体チップ用保持具及びその使用方法は、半導体の製造分野で使用することができる。   The semiconductor chip holder and the method of using the same according to the present invention can be used in the field of semiconductor manufacturing.

1 支持基板
2 半導体チップ
3 作業孔
10 粘着保持層
11 接着領域
12 両面粘着テープ
13 非接着領域
14 隙間
15 保持部
20 突き出しピン
DESCRIPTION OF SYMBOLS 1 Support substrate 2 Semiconductor chip 3 Work hole 10 Adhesive holding layer 11 Adhesive area 12 Double-sided adhesive tape 13 Non-adhesive area 14 Gap 15 Holding part 20 Extrusion pin

Claims (4)

支持基板に粘着保持層を積層し、この粘着保持層に、半導体ウェーハに接合される複数の半導体チップを着脱自在に保持させる半導体チップ用保持具であって、
支持基板を半導体ウェーハと略同サイズに形成し、粘着保持層に可撓性を付与してその一部を支持基板に対する接着領域とするとともに、粘着保持層の残部を支持基板に接着しない非接着領域とし、この非接着領域の表面に半導体チップ用の複数の保持部を形成して各保持部を半導体チップよりも大きく区画し、支持基板と粘着保持層の複数の保持部のいずれかに、半導体チップ用の複数の作業孔を穿孔したことを特徴とする半導体チップ用保持具。
An adhesive holding layer is laminated on a support substrate, and this adhesive holding layer is a semiconductor chip holder for detachably holding a plurality of semiconductor chips bonded to a semiconductor wafer,
The support substrate is formed to be approximately the same size as the semiconductor wafer, and the adhesive holding layer is made flexible so that a part thereof becomes an adhesive region to the support substrate, and the remaining part of the adhesive holding layer is not bonded to the support substrate. As a region, a plurality of holding portions for semiconductor chips are formed on the surface of the non-adhesive region, and each holding portion is partitioned larger than the semiconductor chip, and one of the plurality of holding portions of the support substrate and the adhesive holding layer, A semiconductor chip holder comprising a plurality of working holes for a semiconductor chip.
支持基板に複数の作業孔を穿孔して各作業孔の幅を半導体チップよりも小さくし、支持基板の作業孔に粘着保持層の保持部の略中央を対向させた請求項1記載の半導体チップ用保持具。   2. The semiconductor chip according to claim 1, wherein a plurality of working holes are drilled in the support substrate so that the width of each work hole is smaller than that of the semiconductor chip, and the substantially center of the holding portion of the adhesive holding layer is opposed to the work hole of the support substrate. Retaining tool. 粘着保持層の複数の保持部を、半導体ウェーハに並べて接合される複数の半導体チップの配列に対応するよう配列した請求項1又は2記載の半導体チップ用保持具。   The semiconductor chip holder according to claim 1 or 2, wherein the plurality of holding portions of the adhesive holding layer are arranged so as to correspond to an arrangement of the plurality of semiconductor chips bonded and bonded to the semiconductor wafer. 請求項1、2、又は3記載の半導体チップ用保持具の使用方法であって、支持基板に粘着保持層の複数の保持部を密接して複数の保持部に半導体チップを保持させ、半導体ウェーハと半導体チップ用保持具とを少なくとも加圧することにより、半導体ウェーハに複数の半導体チップを一括して接合し、その後、各半導体チップから粘着保持層の保持部を剥離することを特徴とする半導体チップ用保持具の使用方法。   4. The method of using a semiconductor chip holder according to claim 1, wherein a plurality of holding portions of the adhesive holding layer are brought into close contact with the support substrate to hold the semiconductor chips on the plurality of holding portions. A semiconductor chip characterized in that a plurality of semiconductor chips are collectively bonded to a semiconductor wafer by at least pressurizing the semiconductor chip holder and the holding part of the adhesive holding layer is peeled off from each semiconductor chip. How to use the holder.
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