JP2012205456A - Electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a conventional electronic circuit having a plurality of drive modes and a plurality of step-up voltages in which, when the need of the step-up voltages is partially eliminated according to the drive mode, the corresponding step-up circuit is stopped, and the stopped step-up circuit leads to a waste space to reduce an area efficiency.SOLUTION: An electronic circuit includes: a plurality of step-up circuits each having a predetermined step-up magnification; a control circuit capable of changing the step-up magnification (a step-up stage number) of each of the set-up circuits; and a selection circuit for suitably selecting outputs of the plurality of step-up circuits. Accordingly, even when the step-up circuit that stops according to a drive mode is included, the circuit allows the stopped step-up circuit to operate in parallel connection with the other step-up circuits, eliminating waste in circuit area due to an operation stop to prevent reduction in circuit area efficiency, and allowing an increase in charge current to reduce an arrival time of the step-up voltage and a recovery time of the step-up voltage reduced by load drive.

Description

  The present invention relates to an electronic circuit including a booster circuit that boosts a predetermined voltage, and more particularly, to an electronic circuit including a plurality of booster circuits that generate a voltage necessary for a circuit operating at a high voltage.

  With the recent development of portable devices, various types of built-in electronic circuits exist. Since they are mainly battery-powered, they are mainly driven by a single power supply voltage, but depending on the intended use, multiple voltages may be required. A plurality of voltages are generated using a step-down circuit.

  In some cases, a plurality of step-up circuits and step-down circuits are provided in one electronic circuit, and a plurality of voltages higher or lower than a single power supply voltage are generated.

  Although many proposals are seen as an electronic circuit incorporating a plurality of booster circuits, a proposal for use in a memory has been proposed (for example, see Patent Document 1).

The prior art disclosed in Patent Document 1 will be described with reference to FIG.
FIG. 8 has been rewritten to the extent that it does not depart from the gist of the prior art shown in Patent Document 1 so that it can be easily explained. In FIG. 8, 111 is a first booster circuit, 112 is a second booster circuit, 113 is an auxiliary booster circuit, 114 is a timing control circuit, 115 is an oscillator, and 116 is a detection circuit.

The first booster circuit 111 and the second booster circuit 112 are booster circuits having the same boosting capability, and the auxiliary booster circuit 113 is inferior to these in boosting capability. The auxiliary booster circuit 113 is provided to guarantee the boosted voltage when the first booster circuit 111 and the second booster circuit 112 are in the standby state. The oscillator 115 is provided to drive the auxiliary booster circuit 113.
The detection circuit 116 detects a boosted voltage, and the first booster circuit 111 and the second booster circuit 112 are driven in a distributed manner by the timing control circuit 114 based on the detection result.

  The conventional semiconductor integrated circuit disclosed in Patent Document 1 has a plurality of booster circuits, that is, a first booster circuit 111 and a second booster circuit 112, and the timing control circuit 114 causes them to perform a distributed operation with each other. Therefore, the boosting operation synchronized with the power consumption timing of the driven circuit can be realized, and the boosting operation can be performed efficiently.

Japanese Patent Laid-Open No. 2001-250381 (pages 7 to 12, FIG. 1)

  Incidentally, an electronic circuit having a plurality of booster circuits known from the prior art switches the booster circuit according to the operation timing of the driven circuit. However, the operation sequence and operation mode (hereinafter referred to as driving) of the driven circuit are switched. Depending on the mode, some boosted voltages may be unnecessary. For this reason, the booster circuit that generates the corresponding boosted voltage may be stopped. For example, an electronic circuit used in a liquid crystal display device.

  In general, having a plurality of drive modes broadens the range of applications of electronic circuits, and by increasing compatibility, it is possible to reduce the chip cost when electronic circuits are made into semiconductor chips. It is desirable that a booster circuit necessary for a plurality of drive modes be provided in advance in the electronic circuit.

On the other hand, since the booster circuit is required to have a low on-resistance, the circuit area is larger than that of other circuit blocks, which is a cause for increasing the chip area when an electronic circuit is formed as a semiconductor chip.
Designing with an operation margin such as stability of boost voltage and securing boost capability tends to increase the circuit area and increase the chip size. In view of the trade-off relationship, it is difficult to design the chip cost as low as possible. In particular, the tendency becomes more prominent as the number of necessary boosted voltages increases.

  As described above, the electronic circuit may stop the booster circuit depending on the drive mode of the driven circuit, but such a state is that the stopped booster circuit is wasted due to the configuration of the electronic circuit. State.

  As described above, in order to reduce the chip cost, it is desirable to previously provide a plurality of booster circuits in the electronic circuit corresponding to the drive mode, but the plurality of booster circuits are stopped depending on the drive mode. Then, since the useless area increases, the area of the chip cannot be effectively used.

  Since the prior art disclosed in Patent Document 1 performs a distributed operation of a plurality of booster circuits in synchronization with the power consumption timing of the driven circuit, such a stopped booster circuit cannot be effectively used. .

  The present invention has been made to solve the above problems. When an electronic circuit having a plurality of booster circuits is provided in advance in a plurality of booster circuits corresponding to a plurality of drive modes by combining a booster circuit that is not required depending on the drive mode with another booster circuit. Even so, it is possible to provide an electronic circuit having no useless circuit area.

  In order to achieve the above object, the electronic circuit of the present invention adopts the following structure.

Power supply means for supplying current, a booster block having at least one capacitor and a switch element, the switch element is controlled, the power supply means and the capacitor are connected to charge the capacitor, and discharge of the charged capacitor is used. A booster circuit that outputs a boosted voltage at a predetermined boosting ratio, and includes a plurality of such booster circuits, inputs the outputs of all the booster circuits, and selects the output of one of the booster circuits. In an electronic circuit comprising a selection circuit for output,
A control circuit is provided that controls the switching element and connects the boost blocks of different boost circuits in parallel to output the outputs of the plurality of boost circuits to the selection circuit.

  With such a configuration, a booster circuit that is unnecessary depending on the drive mode can be combined with another booster circuit, and a useless circuit area can be eliminated.

The control circuit may be configured to connect booster blocks of different booster circuits having the same boost ratio in parallel.

  By adopting such a configuration, the booster circuits can be connected in parallel without the booster block remaining, so that it is possible to further eliminate useless circuit area.

  The booster circuits may output boosted voltages having different boosting ratios.

  With such a configuration, various booster blocks can be combined in accordance with the drive mode, and the stopped booster circuit can be used more effectively.

  The electronic circuit of the present invention can be combined with a boosting circuit in operation and a boosting circuit in operation. With such a configuration, it is possible to improve the boosting capability of the operating booster circuit. Since the stopped booster circuit is not wasted, the area use efficiency of the booster circuit can be increased.

It is a conceptual diagram explaining the outline | summary of this invention. It is a conceptual diagram explaining the outline | summary of this invention. It is a block diagram explaining the application example of this invention. It is a block diagram explaining the pressure | voltage rise block of this invention. It is a figure explaining the control signal of the pressure | voltage rise block of this invention. It is a block diagram explaining another example of the pressure | voltage rise block of this invention. It is a figure explaining the selection circuit of this invention. It is a figure which shows the electronic circuit of the prior art shown in patent document 1. FIG.

  The electronic circuit of the present invention includes a control circuit that includes a plurality of booster circuits, and when the booster circuit is stopped depending on the drive mode of the driven circuit, the stopped booster circuit is connected in parallel to the operating booster circuit. Have. Next, an outline of the electronic circuit will be described with reference to conceptual diagrams shown in FIGS. In the description, the same number is assigned to the same configuration, and a duplicate description is omitted.

First, the example of FIG. 1 will be described.
As shown in FIG. 1, the electronic circuit includes, for example, three boosting circuits, that is, a boosting circuit 51 having a boosting factor of up to 4 times, a boosting circuit 53 of up to 3 times, and a boosting circuit 55 of up to 2 times, and a control circuit 70. Suppose you are. Each booster circuit has as many booster blocks 21 as necessary for the maximum boost magnification.
The step-up block 21 is a circuit block having a capacitor and a switch element. Each booster circuit is equipped with a capacitor for storing the voltage boosted by each booster block (not shown). In this example, the boosting magnification of all boosting blocks 21 is the same.

  Each booster circuit operates in a predetermined boost cycle. During this step-up operation, the voltage output from each step-up block is charged to the storage capacitor. When the predetermined boosting magnification is reached, the boosted voltage is taken out from the storage capacitor.

Here, assuming that a voltage of 4 times boost and a voltage of 2 times boost are necessary depending on the driving mode, the boost circuit 53 of up to 3 times has been stopped in the past, but the boost circuit 53 of up to 3 times has been stopped. Is used for double boosting.
As shown in FIG. 1, the control circuit 70 controls the switch elements of the booster block 21 constituting the booster circuit so that the maximum booster circuit 53 is connected in parallel with the booster circuit 55 that is twice as much as the maximum.
For example, if two booster blocks 21 output a double boosted voltage among the booster blocks of the booster circuit 53 of up to three times, the two booster block groups 22 are connected to a booster circuit 55 of up to two times. Connect in parallel.

  As a result, a boosted voltage of 4 times is obtained from the booster circuit 51 of up to 4 times, and a boosted voltage of 2 times is obtained from the booster circuit 53 of up to 3 times and the booster circuit 55 of up to 2 times.

  In this way, there is no step-up booster circuit, and there is no waste of area, and in order to obtain a double boost voltage, the storage capacitor can be charged with a double charge current, so the boost operation starts. In some cases, the time required to reach the boosted voltage can be shortened, and the boosting capability can be shortened by shortening the recovery time of the boosted voltage when the boosted voltage is lowered due to load driving.

Next, the example of FIG. 2 will be described.
The example shown in FIG. 2 is a case where the boosting magnifications of all the boosting blocks 21 are not the same. As shown in FIG. 2, the boosting magnification of the boosting block 23 constituting the boosting circuit 51 of up to 4 times is different from the other boosting blocks 21 and is, for example, 2 times. The up to 4 times booster circuit 51 outputs a boosted voltage up to 4 times at the two booster blocks 23.

Here, as in the example of FIG. 1, it is assumed that a voltage of 4 times boost and a voltage of 2 times boost are necessary depending on the drive mode. In this example, the control circuit 70 performs control so that the maximum three-fold booster circuit 53 is connected in parallel to the four-fold booster circuit 51 and the maximum two-fold booster circuit 55.
For example, if two boosting blocks 21 output a double boosted voltage among the boosting blocks of the boosting circuit 53 of up to three times, the two boosting block groups 22 are connected to the boosting circuit 51 of up to four times. The remaining one booster block 21 is connected in parallel with the booster circuit 55 having a maximum of 2 times.

As a result, the booster circuit 51 having a maximum of 4 times obtains a boosted voltage of 4 times and obtains a boosted voltage of 2 times from the booster circuit 55 having a maximum of 2 times. However, as shown in FIG. The booster blocks 21 of the double booster circuit 55 and the maximum triple booster circuit 53 are connected in parallel, so that the maximum double booster circuit 55 obtains a double boosted voltage by double charge current. Since the storage capacitor can be charged, the time required to reach the boost voltage at the start of the boost operation can be shortened.
In the booster circuit 53 having a maximum of three times, the booster block 21 whose operation is stopped is eliminated, so there is no waste.

  In the electronic circuit of the present invention, even if the booster circuit is not stopped, the control circuit can also control the predetermined booster circuit to be connected in parallel to another booster circuit.

For example, it is assumed that there are a total of three boosting circuits, one boosting circuit with a maximum boosting factor of 4 and two boosting circuits with a maximum boosting factor of 2. At this time, the control circuit controls the switch elements of the booster block constituting the booster circuit so that the two booster circuits having a maximum of two times are connected in parallel.
As a result, a boosted voltage of 4 times is obtained from a booster circuit of up to 4 times, and a boosted voltage of 2 times is obtained from two boosters of a maximum of 2 times.

  In this way, since the booster circuits can be connected in parallel without any additional booster block, there is also an advantage that a useless circuit area can be eliminated.

Embodiments for carrying out the present invention will be described below with reference to the drawings. As an embodiment, an example will be described in which three booster circuits are provided, and the three booster circuits output boosted voltages having different boosting factors.
In the description, like the description using FIG. 1 and FIG. 2, the same number is assigned to the same configuration, and redundant description is omitted. Note that the description will be given with reference to the drawings to be referred to, but other drawings should also be referred to as appropriate.

[Description of Application Examples of Electronic Circuits: FIGS. 1, 2, and 3]
Next, application examples of electronic circuits will be described mainly with reference to FIG. FIG. 3 is a circuit block diagram illustrating an application example of an electronic circuit. The electronic circuit 100 includes booster circuits 1, 3, and 5, a control circuit 7, and selection circuits 9a to 9n. Reference numeral 200 denotes another electronic circuit or electronic device, for example, a driving circuit for a liquid crystal display panel. The drive circuit 200 has input terminals 11a to 11n for inputting the outputs of the selection circuits 9a to 9n.
The booster circuits 1, 2, and 3 shown in FIG. 3 correspond to the booster circuits 51, 53, and 55 shown in FIGS. 2 and 2, respectively, and the control circuit 7 similarly corresponds to the control circuit 70.

  FIG. 3 shows a case where there are three booster circuits, and up to three types of boosted voltages can be generated. The outputs of the booster circuits 1, 3, and 5 are input to the selection circuits 9a to 9n. On the other hand, the control signal of the control circuit 7 is inputted to the booster circuits 1, 3, 5 and the selection circuits 9a to 9n. Outputs of the selection circuits 9a to 9n are connected to input terminals 11a to 11n of the drive circuit 200.

  The outputs of the booster circuits 1, 3, and 5 are input to the drive circuit 200 and become a plurality of power supply voltages for driving the liquid crystal display panel.

Next, the operation of the electronic circuit 100 will be described.
The booster circuits 1, 3, and 5 have a booster block composed of a switch element and a capacitor, and a booster circuit is configured by combining them. Each of the booster circuits 1, 3, and 5 performs a boost operation by the control circuit 7. The outputs of the booster circuits 1, 3 and 5 and the control signal of the control circuit 7 are input to the selection circuit 9, and the selection circuit 9 switches and outputs a plurality of boosted voltages according to the control signal of the control circuit 7.

  The electronic circuit 100 illustrated in FIG. 3 includes three booster circuits and can generate a maximum of three types of boosted voltages. However, depending on the driving mode, only two types of boosted voltages may be required. At this time, one of the three boosting circuits is not suspended, but the control circuit 7 operates so that two of the three boosting circuits generate the same boosted voltage. For example, the control is performed as shown in FIGS. In this way, the booster circuit that has been paused in the past is effectively utilized.

  The boosting circuit during operation can be combined with the operating boosting circuit, and the boosting circuit during operation such as shortening the arrival time of the boosting voltage and shortening the recovery time when the boosting voltage drops due to load driving due to the increase in charging current. This makes it possible to increase the operating margin of the chip and to effectively utilize the chip area.

[Explanation of Booster Circuit Operation 1: FIGS. 3, 4, and 5]
Next, the configuration and operation of the booster circuits 1, 3, and 5 will be described with reference to FIGS.
First, the configuration of the booster circuit will be described. The booster circuits 1, 3, and 5 have a booster block including at least one capacitor and a switch element. A booster circuit is configured by combining them. Here, a booster block that can be switched between a booster circuit having a booster multiplier of 3 times and a booster circuit having a booster multiplier of 2 times will be described in detail.

  FIG. 4 is a diagram for explaining the operation of a specific circuit configuration of the booster block. This step-up block has N channel transistors MN1 to MN3, P channel transistors MP1 to MP6, and capacitors C1 to C3. Symbol V1 is a reference power source, V3 is a boost power source, and VSS is a ground power source. Further, the control signals CNT1 to CNT5 are control signals which are output signals of the control circuit 7 of FIG. 2, and 21 is a boosting block having them.

  The N-channel transistors MN1 to MN3 and the P-channel transistors MP1 to MP6 are switch elements, and can be configured by MOSFETs, for example.

The source terminals and bulk terminals of the N-channel transistors MN1 and MN2 are connected to the ground power supply VSS, and the gate terminals are connected to the control signal CNT1.
The source terminals and bulk terminals of the P-channel transistors MP1 and MP2 are connected to the reference power source V1, and the gate terminals are connected to the control signal CTN2.
Both terminals of the capacitor C1 are connected to the drain terminal of the N-channel transistor MN1 and the drain terminal of the P-channel transistor MP1, respectively. Both terminals of the capacitor C2 are connected to the drain terminal of the N-channel transistor MN2 and the P-channel transistor MP2. Each is connected to the drain terminal.

  The source terminal of the N-channel transistor MN3 is connected to the connection point between the capacitor C1 and the drain terminal of the N-channel transistor MN1, and the connection point between the capacitor C2 and the drain terminal of the N-channel transistor MN2 The drain terminal is connected. The bulk terminal of the N-channel transistor MN3 is connected to the ground power supply VSS, and the gate terminal is connected to the control signal CNT3.

  The source terminal of the P-channel transistor MP3 is connected to the connection point between the capacitor C1 and the drain terminal of the P-channel transistor MP1, and the connection point between the capacitor C2 and the drain terminal of the P-channel transistor MP2 is connected to the connection point of the P-channel transistor MP3. The drain terminal is connected. The bulk terminal of the P-channel transistor MP3 is connected to the boost power supply V3, and the gate terminal is connected to the control signal CNT4.

  A source terminal and a bulk terminal of the P-channel transistor MP4 are connected to a connection point between the capacitor C1 and the drain terminal of the P-channel transistor MP1, and a P-channel is connected to a connection point between the capacitor C2 and the drain terminal of the N-channel transistor MN2. The drain terminal of the transistor MP4 is connected. The gate terminal of the P-channel transistor MP4 is connected to the control signal CNT5.

  The drain terminal of the P-channel transistor MP5 is connected to the connection point between the capacitor C1 and the drain terminal of the N-channel transistor MN1, the source terminal and bulk terminal of the P-channel transistor MP5 are connected to the reference power source V1, and the gate terminal is It is connected to the control signal CNT1.

The drain terminal of the P-channel transistor MP6 is connected to the connection point between the capacitor C2 and the drain terminal of the P-channel transistor MP2, the source terminal and bulk terminal of the P-channel transistor MP6 are connected to the boost power supply V3, and the gate terminal is It is connected to the control signal CNT1.
A capacitor C3 is connected between the boost power source V3 and the ground power source VSS.

Next, the operation of the booster circuit will be described with reference to FIG.
FIG. 5 is a diagram showing a time chart of control signals CNT1 to CNT5 for driving the booster block 21 shown in FIG. FIG. 5A is a time chart when the booster block 21 generates a boosted voltage three times that of the reference power source V1, while FIG. 5B shows that the booster block 21 is twice that of the reference power source V1. It is a time chart in the case of generating a boosted voltage. The boosted voltage is generated by alternately repeating the charging period and the boosting period.

First, the operation when the booster block 21 generates a triple boosted voltage will be described.
5A, the N-channel transistors MN1 and MN2 and the P-channel transistors MP1 and MP2 shown in FIG. 4 are turned on, and the N-channel transistor MN3 and the P-channel transistors MP3 to MP6 are turned off. Thus, the capacitors C1 and C2 are connected in parallel between the reference power source V1 and the ground power source VSS, and are charged.

5A, the N-channel transistors MN1 to MN3 and the P-channel transistors MP1 to MP3 shown in FIG. 4 are turned off, and the P-channel transistors MP4 to MP6 are turned on.
Capacitor C1 and capacitor C2 are connected in series by a P-channel transistor MP4. The low voltage side of the capacitor C1 is connected to the reference power source V1 by the P channel transistor MP5, and the high potential side of the capacitor C2 is connected to the boost power source V3 by the P channel transistor MP6.
For this reason, a boosted voltage three times that of the reference power supply V1 is generated in the boosted power supply V3 together with the voltages charged in the capacitors C1 and C2. The boosted voltage is held by the capacitor C3.

Next, the operation when the boosting block 21 generates a double boosted voltage will be described.
5B, the N-channel transistors MN1 and MN2 and the P-channel transistors MP1 and MP2 shown in FIG. 4 are turned on, and the N-channel transistor MN3 and the P-channel transistors MP3 to MP6 are turned off. Thus, the capacitors C1 and C2 are connected in parallel between the reference power source V1 and the ground power source VSS, and are charged. This operation is the same as the case of generating the triple boosted voltage already described.

5B, the N-channel transistors MN1, MN2 and the P-channel transistors MP1, MP2, MP4 shown in FIG. 4 are turned off, and the N-channel transistor MN3 and the P-channel transistors MP3, MP5 are turned off. , MP6 is turned on.
Capacitor C1 and capacitor C2 are connected in parallel by P-channel transistor MP3 and N-channel transistor MN3. The low voltage side of the capacitors C1 and C2 is connected to the reference power supply V1 by the P channel transistor MP5, and the high potential side of the capacitors C1 and C2 is connected to the boost power supply V3 by the P channel transistor MP6.
For this reason, in combination with the voltages charged in the capacitors C1 and C2, a boosted voltage twice that of the reference power supply V1 is generated in the boosted power supply V3. The boosted voltage is held by the capacitor C3.

  As described above, by turning on or off the P-channel transistor and the N-channel transistor that are switch elements, the capacitor C1 and the capacitor C2 are connected in series or in parallel to obtain a predetermined boosted voltage. The boosted voltage can be switched twice or three times by turning on or off these switch elements.

  In the above description, a booster block that uses two capacitors and can generate a boost voltage up to three times has been described. However, by increasing the number of capacitors and switch elements, a higher boost voltage can be generated and various boost voltages can be generated. A booster circuit that can be generated can be configured.

[Explanation of Booster Circuit Operation 2: FIG. 6]
Next, another example of the boosting block will be described with reference to FIG. In FIG. 6, a booster block that can be switched between a booster circuit with a boosting factor of 4 and a booster circuit with a booster multiplier of 3 will be described in detail.

  FIG. 6 is obtained by adding new components to the boost block shown in FIG. New components of the boost block are an N-channel transistor MN4, P-channel transistors MP7 and MP8, and a capacitor C4. Reference numeral 25 denotes a booster block having these components.

  The N-channel transistor MN4 and the P-channel transistors MP7 and MP8 are switch elements, and can be configured by MOSFETs, for example, as with other transistors.

The source terminal and bulk terminal of the N-channel transistor MN4 are connected to the ground power supply VSS, and the gate terminal is connected to the control signal CNT1.
The source terminal and bulk terminal of the P-channel transistor MP7 are connected to the reference power source V1, and the gate terminal is connected to the control signal CTN2.
Both terminals of the capacitor C4 are connected to the drain terminal of the N-channel transistor MN4 and the drain terminal of the P-channel transistor MP7, respectively.

  The source terminal and bulk terminal of the P-channel transistor MP8 are connected to the connection point between the capacitor C2 and the drain terminal of the P-channel transistor MP2, and the connection point between the capacitor C4 and the drain terminal of the N-channel transistor MN4 is connected to the P-channel. The drain terminal of the transistor MP8 is connected. The gate terminal of the P-channel transistor MP8 is connected to the control signal CNT1.

  Unlike FIG. 4, the drain terminal of the P-channel transistor MP6 is connected to the connection point between the capacitor C4 and the drain terminal of the P-channel transistor MP7, and the source terminal and bulk terminal of the P-channel transistor MP6 are connected to the boost power supply V3. The gate terminal is connected to the control signal CNT1.

Next, the operation of the booster circuit will be described with reference to FIG.
FIG. 5 is a time chart of the control signals CNT1 to CNT5 for driving the booster block 21 shown in FIG. 4, and the booster block 25 shown in FIG. 6 can be driven with the same control signal. FIG. 5A is a time chart when the booster block 25 generates a boosted voltage four times that of the reference power source V1, while FIG. 5B shows that the booster block 25 has three times the reference power source V1. It is a time chart in the case of generating a boosted voltage. The boosted voltage is generated by alternately repeating the charging period and the boosting period.

First, the operation in the case where the boost block 25 generates a four times boosted voltage will be described.
5A, the N-channel transistors MN1, MN2, and MN4 and the P-channel transistors MP1, MP2, and MP7 shown in FIG. 6 are turned on, and the N-channel transistor MN3 and the P-channel transistors MP3 to MP6, By turning off MP8, the capacitors C1, C2, and C4 are connected in parallel between the reference power source V1 and the ground power source VSS, and are charged.

5A, the N channel transistors MN1 to MN4 and the P channel transistors MP1 to MP3 and MP7 shown in FIG. 6 are turned off, and the P channel transistors MP4 to MP6 and MP8 are turned on.
Capacitor C1, capacitor C2, and capacitor C4 are connected in series by P-channel transistors MP4 and MP8. The low voltage side of the capacitor C1 is connected to the reference power source V1 by the P channel transistor MP5, and the high potential side of the capacitor C4 is connected to the boost power source V3 by the P channel transistor MP6.
For this reason, a boosted voltage four times that of the reference power supply V1 is generated in the boosted power supply V3 together with the voltages charged in the capacitors C1, C2, and C4. The boosted voltage is held by the capacitor C3.

Next, the operation when the boost block 25 generates a triple boosted voltage will be described.
5B, the N-channel transistors MN1, MN2, and MN4 and the P-channel transistors MP1, MP2, and MP7 shown in FIG. 6 are turned on, and the N-channel transistor MN3 and the P-channel transistors MP3 to MP6, By turning off MP8, the capacitors C1, C2, and C4 are connected in parallel between the reference power source V1 and the ground power source VSS, and are charged. This operation is the same as that in the case of generating the four times boosted voltage already described.

5B, the N-channel transistors MN1, MN2, and MN4 and the P-channel transistors MP1, MP2, MP4, and MP7 shown in FIG. 6 are turned off, and the N-channel transistor MN3 and the P-channel are turned on. The transistors MP3, MP5, MP6 and MP8 are turned on.
Capacitor C1 and capacitor C2 are connected in parallel by P-channel transistor MP3 and N-channel transistor MN3. The low voltage side of the capacitors C1 and C2 is connected to the reference power source V1 by the P channel transistor MP5, and the high potential side of the capacitors C1 and C2 is connected to the low potential side of the capacitor C4 by the P channel transistor MP8. The high potential side of the capacitor C4 is connected to the boost power supply V3 by the P-channel transistor MP6.
For this reason, a boosted voltage three times that of the reference power supply V1 is generated in the boosted power supply V3 together with the voltages charged in the capacitors C1, C2, and C4. The boosted voltage is held by the capacitor C3.

  In the above description, the case where the maximum boost is four times has been described. However, by increasing the number of capacitors and switch elements, a higher boost voltage can be generated, and a boost circuit capable of generating various boost voltages can be configured. .

[Description of Selection Circuit: FIG. 7]
Next, the selection circuit 9 shown in FIG. 3 will be described with reference to FIG. First, the configuration of the selection circuit 9 will be described.
The selection circuit 9 includes inverters 24, 25, and 26 and transmission gates TG1, TG2, and TG3. Reference numerals 31, 33, and 35 are control signals output from the control circuit 7.

Control signals 31, 33, and 35 are output from the control circuit 7, and are connected to the inverter and the transmission gate.
The control signal 31 is connected to the normal input terminal of the transmission gate TG1 and the input terminal of the inverter 24. The output terminal of the inverter 24 is connected to the inverting input terminal of the transmission gate TG1.
The control signal 33 is connected to the normal input terminal of the transmission gate TG2 and the input terminal of the inverter 25. The output terminal of the inverter 25 is connected to the inverting input terminal of the transmission gate TG2.
The control signal 35 includes a forward input terminal of the transmission gate TG3 and the inverter 26.
Is connected to the input terminal. The output terminal of the inverter 26 is connected to the inverting input terminal of the transmission gate TG3.

The input terminal of the transmission gate TG1 is connected to the booster circuit 1, the input terminal of the transmission gate TG2 is connected to the booster circuit 3, and the input terminal of the transmission gate TG3 is connected to the booster circuit 5. The output terminals of the transmission gates TG1, TG2, and TG3 are all connected to the output terminal 99.
That is, the boost output of each booster circuit is input to each transmission gate, and each boosted voltage is output to the output terminal 99 by opening and closing each transmission gate.

[Description of operation of selection circuit: FIG. 7]
Next, the operation of the selection circuit 9 will be described with reference to FIG.
The selection circuit 9 selects the boosted voltage generated by the booster circuits 1, 3, and 5 by the control signals 31, 33, and 35 of the control circuit 7 and outputs the selected voltage to the output terminal 99. In the following description, it is assumed that the booster circuit 1 generates a boosted voltage of up to 4 times, the booster circuit 3 generates a boosted voltage of up to 3 times, and the booster circuit 5 generates a boosted voltage of up to 2 times.

First, a driving mode using three types of boosted voltages, that is, four times, three times, and two times boosted voltages will be described.
The booster circuits 1, 3, and 5 generate different boosted voltages. Next, the control circuit 7 controls only one of the output control signals 31, 33, and 35 to be output to a high level. The selection circuit 9 to which such a control signal is input operates so as to turn on only one of the transmission gates TG1, TG2, and TG3.
In this way, the selection circuit 9 selects one boosted voltage from the three types of boosted voltages and outputs it to the output terminal 99.

Next, a driving mode using two types of boosted voltages, for example, four times and two times boosted voltages will be described.
The booster circuit 1 is controlled by the control circuit 7 so as to generate a boosted voltage of 4 times, the booster circuit 3 of 2 times, and the booster circuit 5 of 2 times. Next, the control circuit 7 controls so that the output control signals 33 and 35 are simultaneously turned on or off. The selection circuit 9 to which such a control signal is input operates so that the transmission gates TG2 and TG3 are simultaneously turned on or off.
In this way, the selection circuit 9 connects the outputs of the booster circuits 3 and 5 and outputs them to the output terminal 99 when the booster circuits 3 and 5 are in the drive mode in which the same boosted voltage is generated.

  By adopting such a configuration, for example, even in a drive mode in which a triple boosted voltage is not required, the booster circuit 3 having a maximum boost multiple of 3 is controlled to output a boost voltage of double boost, Further, by connecting the boosted voltage to the boosted voltage of the booster circuit 5 having a maximum boosting factor of 2 times, it is possible to increase the charging current of the boosted voltage that is doubled output from the selection circuit 9, and to reach the boosted voltage arrival time. The operating margin can be expanded, for example, shortening the recovery time and shortening the recovery time when the boosted voltage drops due to load driving.

The control circuit 7 generates a booster circuit control signal and a selection circuit control signal as shown in FIG. 5 by using a general logic circuit based on an external setting signal or a setting signal from a storage device. To do.
Note that FIG. 5 illustrates an example in which the switching timings of the boosting period and the charging period are all switched at the same time. However, by using a delay circuit or the like to shift the switching timing, the charge of the capacitor is transferred to the power source or the like. It is also possible to prevent escape and increase the boosting efficiency.

  In the electronic circuit of the present invention, a booster circuit that is unnecessary depending on the drive mode can be combined with another booster circuit. As a result, the operation margin of the booster circuit can be expanded, and the chip area when the semiconductor chip is formed can be effectively utilized.

  The electronic circuit of the present invention includes a plurality of booster circuits, and even if it has a plurality of drive modes, there is no booster circuit that is wasted by being stopped. Therefore, it is suitable for a circuit for generating a high writing voltage of a memory circuit and a circuit for a liquid crystal driving device required for application.

1, 3, 5, 51, 53, 55 Booster circuit
DESCRIPTION OF SYMBOLS 7 Control circuit 9 Selection circuit 11 Input terminal 21 of drive circuit 21, 23, 25 Boost block 22 Boost block group 24, 25, 26 Inverter 31, 33, 35 Control signal 51 Boost circuit of up to 4 times 53 Boost circuit of up to 3 times 55 Maximum double boosting circuit 70 Control circuit C1 to C4 Capacitors MN1 to MN4 N channel transistors MP1 to MP8 P channel transistors TG1 to TG3 Transmission gate V1 Reference power supply V3 Boost power supply VSS Ground power supply CNT1 to CNT5 Control signal 99 Output terminal 100 Electron Circuit 111 First booster circuit 112 Second booster circuit 113 Auxiliary booster circuit 114 Timing control circuit 115 Oscillator 116 Detection circuit 200 Drive circuit

Claims (3)

Power supply means for supplying current;
A boost block having at least one capacitor and a switch element;
A boosting circuit that controls the switch element, connects the power supply means and the capacitor, charges the capacitor, and outputs a boosted voltage having a predetermined boosting ratio using discharge of the charged capacitor; And
A plurality of the booster circuits;
In an electronic circuit including a selection circuit that inputs the outputs of all the booster circuits and selects and outputs the output of one of the booster circuits,
An electronic circuit comprising: a control circuit that controls the switch element and connects the boost blocks of different boost circuits in parallel to output the selection circuits in combination with the outputs of the boost circuits .   2. The electronic circuit according to claim 1, wherein the control circuit connects the boost blocks of the boost circuits having the same boost magnification in parallel. 3. The electronic circuit according to claim 1, wherein the booster circuits output boosted voltages having different boosting ratios.

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