JP2012203918A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device having high reliability, high speed access and operation current reduction.SOLUTION: In a majority mode, the same write data is written in a plurality of RAMs 0-0, 1-0 and 2-0 or RAMs 0-1, 1-1 and 2-1, and in an ECC mode, write data with an ECC code added is written in any of the plurality of RAMs 0-0, 1-0, 2-0, 0-1, 1-1 and 2-1. The semiconductor storage device includes a majority circuit 16 for outputting a majority result of data written in the plurality of RAMs during reading in the majority mode, ECC generation circuits 12-1 to 12-3 for generating an ECC code for write data during writing in the ECC mode, and ECC error correction circuits 14-1 to 14-3 for executing error correction of write data with the ECC code added stored in the RAMs during reading in the ECC mode.

Description

  The present invention relates to a semiconductor memory device, and more particularly to a technique for realizing low power consumption in a RAM (Random Access Memory) that enables high-speed access built in a microcomputer.

  A microcomputer built-in RAM (Random Access Memory) is equipped with an ECC (Error Check and Correct) circuit as a countermeasure against a soft error. It is necessary to use a transistor having However, when a transistor with a low threshold value is used, there is a problem that current consumption, particularly leakage current at a high temperature, becomes large and does not fall within the target specification.

  Therefore, it is desirable to use a transistor having an intermediate threshold value or a high threshold value with a small leakage current. However, in the case of using a transistor having an intermediate threshold value or a high threshold value, in order to realize zero wait access, ECC However, it is necessary to use a ternary majority circuit having a short calculation time.

FIG. 2 is a diagram showing a configuration using a ternary (3-bit) majority circuit.
FIG. 3 is a diagram showing the relationship between the input (IN) and the output (OUT) of the ternary (3-bit) majority circuit.

  As shown in FIG. 2, in the configuration using the ternary majority circuit, the same data is written in the three RAMs 20-1 to 20-3. At the time of reading, data output from the three RAMs 20-1 to 20-3 is sent to the ternary majority circuit 22. The ternary majority circuit 22 outputs the result of the majority vote of each bit of the data output from the three RAMs 20-1 to 20-3. For example, when certain bits of data output from the RAMs 20-1, 20-2, and 20-3 are “0”, “0”, and “1”, the ternary majority circuit 22 outputs “ "0" is output.

  FIG. 4A shows an access at the time of writing. FIG. 4B shows an access at the time of reading.

  The majority circuit as shown in FIG. 2 has the advantage of simple logic and small delay. Therefore, even if a transistor having an intermediate threshold value or a high threshold value is used, FIG. 4 (a) and FIG. As shown in FIG. 4B, read and write operations at 160 MHz are possible.

  Patent Document 1 (Japanese Patent Laid-Open No. 6-52697) also discloses the following configuration using a majority circuit. The semiconductor memory described in Patent Document 1 includes an error correction function including a memory cell array unit having three or more odd number of memory cells for one bit of one address and a data output unit having a majority circuit And a selector for switching the memory cell to be written in the normal mode and the high reliability mode, and a multiplexer for switching the read memory data and the output data from the majority circuit.

JP-A-6-52697

  However, in the memory using the majority circuit disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 6-52697), the error correction does not function in the normal mode, so the reliability decreases.

Further, when a ternary majority circuit is used, there are the following problems.
Since 3 bits of RAM are used for 1 bit of data, a large-capacity RAM is required. For example, in a system using an ECC circuit, if 7 bits are added for ECC to 32 bits, the memory capacity to be used is increased by 22%, whereas a ternary majority circuit is used. In the method using, the memory capacity to be used is tripled, an increase of 200%.

  Further, in the configuration of FIG. 2, since the memory cell at three addresses is always accessed in one read or write access, the current consumption of the RAM is large despite the low speed (for example, 80 MHz or less). Does not decrease.

  In addition, there is a problem that error correction does not function when a mode for storing 1 bit of RAM with respect to 1 bit of data is provided as in the normal mode configuration described in Patent Document 1.

  Therefore, an object of the present invention is to provide a semiconductor memory device that combines high reliability, high-speed access, and reduced operating current.

  In order to solve the above-described problem, an embodiment of the present invention is a semiconductor memory device capable of selecting either an ECC mode or a majority voting error correction mode, and a plurality of RAMs and writing in the majority voting mode. Sometimes the same write data is written to a plurality of RAMs, and in the ECC mode, at the time of writing, the control unit for writing the write data with the ECC code added to any of the plurality of RAMs and in the majority mode, at the time of reading A majority circuit for outputting a majority result of data written in a plurality of RAMs, an ECC generation circuit for generating an ECC code for write data at the time of writing in the ECC mode, and storage in the RAM at the time of reading in the ECC mode And an ECC error correction circuit that performs error correction of the write data to which the ECC code is added.

  According to an embodiment of the present invention, by providing a majority mode and an ECC circuit mode, it is possible to combine high reliability, high speed access, and reduction of current consumption.

It is a figure showing the structure of the semiconductor memory device of embodiment of this invention. It is a figure showing the structure using a ternary (3 bits) majority circuit. It is a figure showing the relationship between the input (IN) and output (OUT) of a ternary (3-bit) majority circuit. (A) is a figure showing the access at the time of writing. (B) is a diagram showing access at the time of reading.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

  This semiconductor memory device includes a control logic 10, ECC generation circuits 12-1 to 12-3, RAM 0-0, 0-1, 1-0, 1-1, 2-0, 2-1, ECC error. Correction circuits 14-1 to 14-3, a ternary majority circuit 16, and multiplexers 18-1 to 18-3 are provided.

Each capacity of the RAM 0-0, 0-1, 1-0, 1-1, 2-0, 2-1 is 16 KB.
The RAMs 0-0, 1-0, 2-0 are selected by a control signal (upper order). The RAMs 0-1, 1-1, and 2-1 are selected by a control signal (lower order).

  This semiconductor memory device can be operated in the ternary majority mode when high speed operation is required, and can be operated in the ECC mode at medium speed and low speed operation where high speed operation is not required. The control logic 10 receives an instruction from the outside about which of the majority mode and the ECC mode to operate in error correction mode, and sets the error correction mode based on this instruction.

(Operation in ternary majority mode)
In the ternary majority mode, three memory mats (RAM0-0, RAM1-0, RAM2-0) are assigned to the same memory address as the lower memory address, and another three memory mats (RAM0-1, RAM0, RAM1-1 and RAM2-1) are assigned to the same memory address. The three memory mats (RAM0-0, RAM1-0, RAM2-0) or the three memory mats (RAM0-1, RAM1-1, RAM2-1) are asserted simultaneously by the control signal (upper / lower).

Therefore, in the ternary majority mode, the user usable capacity is 32 KB.
At the time of writing, the same data is written into RAM0-0, RAM1-0, RAM2-0 or RAM0-1, RAM1-1, RAM2-1.

  At the time of reading, the ternary majority circuit 16 outputs 32 bits of the 39 bits output from RAM0-0, RAM1-0, RAM2-0, or is output from RAM0-1, RAM1-1, RAM2-1. The result of majority vote of each bit of 32 bits data out of 39 bits is output.

  In the ternary majority mode, no weight is inserted at the time of reading and writing, and high-speed access can be realized.

(Operation in ECC mode)
In the ECC mode, three memory mats (RAM0-0, RAM1-0, RAM2-0) are assigned to consecutive lower memory addresses, and three memory mats (RAM0-1, RAM1-1 are assigned to upper memory addresses). , RAM 2-1) are assigned to consecutive separate memory addresses. Any one of RAM0-0, RAM1-0, RAM2-0, RAM0-1, RAM1-1, and RAM2-1 is asserted by the control signal (upper / lower).

Therefore, in the ECC mode, the user usable capacity is 96 KB.
At the time of writing, any one of RAM0-0, RAM1-0, RAM2-0, RAM0-1, RAM1-1, and RAM2-1 is selected.

  The 32-bit write data is sent to the selected RAM and is also sent to the corresponding ECC generation circuits 12-1 to 12-3. The ECC generation circuits 12-1 to 12-3 receive 32-bit data and output a 7-bit ECC code. As a result, a total of 39 bits of data of upper 32 bits of write data and lower 7 bits of ECC code are written into the selected RAM.

  At the time of reading, 39-bit data output from any of RAM0-0, RAM1-0, RAM2-0, RAM0-1, RAM1-1, and RAM2-1 to the ECC error correction circuits 14-1 to 14-3 ( 32-bit write data and 7-bit ECC code) are input. The ECC error correction circuits 14-1 to 14-3 perform error correction of 32-bit write data and output it.

  In the ECC mode, since a wait is inserted at the time of reading and writing, it cannot be accessed at high speed.

  Note that by arranging a register for switching between the ternary majority mode and the ECC mode, the operation mode may be switched according to the application.

  As described above, in the embodiment of the present invention, by providing the majority mode and the ECC mode, it is possible to combine high reliability, high-speed access, and reduction in operating current.

  In the ECC mode, since the RAM3 mats are arranged at consecutive addresses, the usable RAM space can be increased three times.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  0-0, 0-1, 1-0, 1-1, 2-0, 2-1 RAM, 10 control logic, 12-1 to 12-3 ECC generation circuit, 14-1 to 14-3 ECC error correction Circuit, 16, 22 3-valued majority circuit, 18-1 to 18-3 multiplexer, 20-1 to 20-3 RAM.

Claims (1)

A semiconductor memory device capable of selecting an error correction mode of either an ECC mode or a majority decision mode,
A plurality of RAMs;
A control unit for writing the same write data to the plurality of RAMs at the time of writing in the majority mode, and writing the write data with an ECC code added to any of the plurality of RAMs at the time of writing in the ECC mode; ,
A majority circuit for outputting a majority result of data written in the plurality of RAMs at the time of reading in the majority mode;
An ECC generation circuit for generating an ECC code for write data at the time of writing in the ECC mode;
A semiconductor memory device comprising: an ECC error correction circuit for performing error correction of write data to which an ECC code stored in the RAM is added at the time of reading in the ECC mode.

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