JP2012203655A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a microcomputer capable of efficiently processing interruption.SOLUTION: When detecting occurrence of reception of data, timer interruption and continuous detection of an active level of input signals or the like to be a factor of generating interruption to a CPU 2 in an initial stage, peripheral circuits 8-10 output interruption notice signals to an interruption controller 7 beforehand, and outputs interruption signals in the stage of completion of occurrence of the event. When the interruption notice signals are inputted, the interruption controller 7 performs lookahead processing of loading an interruption vector and an interruption handler corresponding to the notice signals from a ROM 3 to an instruction cache 5.

Description

  The present invention relates to interrupt processing of a microcomputer.

  Various techniques for efficiently executing interrupt processing performed by a CPU in a microcomputer have been proposed. For example, in Patent Document 1, in a configuration that allows a prefetch buffer to prefetch instructions in parallel with an instruction fetch from a cache memory, when an interrupt occurs, a register value before the CPU shifts to an interrupt processing program. A technique is disclosed in which a leading address of an interrupt processing program is set and prefetched using a period during which data is saved.

  The technique of Patent Document 1 is effective when the time required for prefetching the interrupt processing program falls within the period until the CPU shifts to the interrupt processing program. However, since the size of the interrupt processing program is large, if the time required for prefetch does not fall within the above transition period, the CPU processing is stagnated.

  Further, in Patent Document 2, when an interrupt occurs, if the interrupt handler (processing program) is not loaded in the cache memory (cache miss), an interrupt request is issued to the CPU when the loading of the interrupt handler is completed. Techniques to do this are disclosed. As a result, the CPU can continue normal processing while the cache memory prefetches the interrupt handler, so that it is possible to prevent a reduction in processing efficiency.

JP-A-8-212270 (see FIG. 1) JP 2001-306335 A (see FIG. 1)

However, according to the technique of Patent Document 2, it is possible to prevent the CPU processing efficiency from being lowered, but the time from when the interrupt occurs until the CPU starts executing the interrupt handler, that is, interrupt responsiveness, the cache memory This is the same as when the interrupt handler is not prefetched. Further, if a cache miss occurs during execution of normal processing in the CPU while the cache memory is prefetching the interrupt handler, the processing of the CPU stagnate until prefetching is completed.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a microcomputer that can process interrupts more efficiently.

  According to the microcomputer of claim 1, when the peripheral circuit detects the occurrence of an event that causes the CPU to generate an interrupt at an initial stage, the peripheral circuit outputs an interrupt notice signal to the interrupt controller in advance. When the occurrence of the event is completed, an interrupt signal is output. Then, when an interrupt notice signal is input, the interrupt controller performs a prefetch process for loading an interrupt handler corresponding to the notice signal from the program memory into the instruction cache, and then an interrupt corresponding to the interrupt notice signal is generated. If the prefetch process is not completed at this stage, the interrupt generation notification to the CPU is suspended.

  With this configuration, the interrupt controller starts the prefetch process for loading the interrupt handler into the instruction cache from the time when the interrupt notice signal is output, so the prefetch process is performed until the corresponding interrupt signal is output. As soon as the interrupt signal is output, the CPU can proceed to interrupt processing and start execution of the interrupt handler. Therefore, it is possible to improve the responsiveness from the time when the interrupt occurs until the interrupt is processed. In addition, if the prefetch process is not completed when the interrupt signal corresponding to the notice signal is input, the interrupt controller holds the interrupt notification to the CPU. Can start the execution of the interrupt handler, and can prevent a reduction in the processing efficiency of the CPU.

  According to the microcomputer of the second aspect, the peripheral circuit having the communication function outputs the interrupt notice signal after starting the reception processing of the data transmitted from the outside until the reception processing is completed. To do. In other words, if there is data transmission from the outside, an interrupt will be generated for the CPU when reception of the transmitted data is completed, so after the reception process is started until the reception process is completed. If an interrupt notice signal is output in the meantime, the interrupt controller can be notified of the occurrence of the interrupt.

  According to the microcomputer of the third aspect, the peripheral circuit having the timer function outputs the interrupt notice signal at a timing that goes backward by a predetermined period from the timing at which the timer interrupt signal is generated. In other words, when a timer interrupt is generated at a certain period, the timing for generating the interrupt is determined by the count value of the timer. Therefore, referring to the count value, the interrupt is performed at a timing that goes backward from the timing for generating the timer interrupt signal. A warning signal can be output.

  According to another aspect of the microcomputer of the present invention, the peripheral circuit that determines that the signal has become active and generates an interrupt signal when the active state of the input signal level is continuously detected m times or more is generated. An interrupt notice signal is output when the active level continues for n (<m) times or more. In general, in the peripheral circuit configured as described above, the level of the input signal may be affected by noise. Therefore, in order to eliminate the influence, the active state is continuously detected more than m times. ing. Therefore, even if the active level continues for n (<m) times or more, it can be said that there is a high probability that the input signal will be determined to be active after that. If an interrupt notice signal is output at that time, an interrupt will be sent to the interrupt controller. The occurrence can be foretold.

  According to the microcomputer of claim 5, when a high-priority interrupt notification signal is input during execution of the prefetch process, the interrupt controller stops the prefetch process being executed and the priority is high. Start prefetch processing of the interrupt handler corresponding to the interrupt. Therefore, the handler corresponding to the interrupt scheduled to be processed first by the CPU can be loaded into the instruction cache first.

  According to another aspect of the microcomputer of the present invention, when the peripheral circuit generates an interrupt, the interrupt controller suspends the interrupt generation notification to the CPU, and the interrupt handler corresponding to the interrupt is transferred from the program memory to the instruction cache. Performs prefetch processing to be loaded. When a cache miss occurs in the access from the CPU during execution of the prefetch process, the cache controller preferentially executes the prefetch process if the CPU is in the interrupt enabled state at that time, and prefetches if the CPU is in the interrupt disabled state. The processing is stopped and the instruction to be fetched by the CPU is loaded into the instruction cache.

  That is, even if a cache miss occurs during execution of the prefetch process, if the CPU is in the interrupt enabled state, the CPU can cause the CPU to execute the interrupt process early by giving priority to the prefetch process. If the CPU is in the interrupt disabled state, the interrupt processing is not started immediately, so that the instruction to be fetched by the CPU is first loaded into the instruction cache, and the currently executing process is given priority. Therefore, the processing efficiency can be improved according to the state of correspondence to the interrupt on the CPU side.

  According to the microcomputer of claim 7, when the cache controller preferentially executes the prefetch process, the cache controller immediately notifies the interrupt controller of the completion of the prefetch process, and the interrupt controller is notified. Since the interrupt notification is sent to the CPU, the CPU can immediately shift to the interrupt processing.

  According to the microcomputer of claim 8, the interrupt controller stops the prefetching process when an interrupt having a higher priority occurs during execution of the prefetching process, and sets an interrupt handler corresponding to the interrupt having a high priority. Start prefetch processing. Therefore, prefetching of the interrupt handler can be performed corresponding to the priority of the interrupt.

Functional block diagram showing the configuration of the microcomputer according to the first embodiment Functional block diagram showing the internal configuration of the interrupt controller Functional block diagram showing the internal structure of the instruction cache The figure which shows the structural example in case a peripheral circuit is provided with a communication function Operation timing chart The figure which shows the structural example in case a peripheral circuit is provided with a timer function Figure equivalent to FIG. The figure which shows the structural example in case a peripheral circuit is provided with an input capture function Figure equivalent to FIG. Flow (sequence) diagram showing the flow of processing between components FIG. 10A is a timing chart corresponding to the flow of FIG. 10 in the case of the conventional configuration, and FIG. Timing chart showing the operation of the second embodiment Partial equivalent diagram of FIG. This is a third embodiment, where (a) shows the operation in the case of the conventional configuration, and (b) shows a timing chart showing the operation in the case of the configuration of the embodiment (part 1). Same timing chart (Part 2)

(First embodiment)
The first embodiment will be described below with reference to FIGS. FIG. 1 is a functional block diagram showing the configuration of the microcomputer. The microcomputer 1 is composed of a CPU 2, a ROM 3, RAM 4, which is a program memory, an instruction cache 5, a data cache 6, an interrupt controller 7, peripheral circuits 8 to 10, and the like. The CPU 2, the instruction cache 5, and the ROM 3 are connected by a dedicated bus, and the RAM 4, the data cache 6, the interrupt controller 7, and the peripheral circuits 8 to 10 are connected to a system bus (general-purpose bus) 11. The CPU 2 accesses the RAM 4 and the peripheral circuits 8 to 10 connected to the system bus 11 via the data cache 6.

  The peripheral circuits 8 to 10 output an interrupt signal to the interrupt controller 7 and output an interrupt notice signal described later before the time when the interrupt signal is output. The interrupt controller 7 outputs an interrupt request signal and a signal for notifying the interrupt request number (interrupt request number notification) to the CPU 2, and the CPU 2 outputs an interrupt request acceptance signal to the interrupt controller 7. . The interrupt controller 7 outputs the interrupt request number notification to the instruction cache 5 as an interrupt processing prefetch request. Then, the instruction cache 5 outputs a prefetch completion notification or a prefetch stop notification to the interrupt controller 7.

  FIG. 2 is a functional block diagram showing the internal configuration of the interrupt controller 7. In the priority specification register 12, the CPU 2 writes and specifies the priority for each interrupt request number, and the specified priority data is output to the priority determination units 13 and 14. An interrupt signal and an interrupt notice signal from the peripheral circuits 8 to 9 are input to the priority determination units 13 and 14, respectively. Then, when a plurality of interrupt signals and interrupt notice signals are input simultaneously, the priority determination units 13 and 14 compare them with the priority data provided from the priority specification register 12 for each signal, Select and output the interrupt signal or interrupt notice signal that has the higher priority.

  The interrupt notice signal output via the priority determination unit 14 is input to the prefetch control unit 15, and the interrupt signal output via the priority determination unit 13 includes the prefetch control unit 15, the prefetch completion control unit 16, Input to the interrupt request control unit 17. The prefetch control unit 15 outputs an interrupt request number corresponding to the input interrupt notice signal as an interrupt processing prefetch request. When the prefetch completion notification is input, the prefetch completion control unit 16 resets the interrupt processing prefetch request output by the prefetch control unit 15 at that time. The interrupt request control unit 17 outputs an interrupt request number corresponding to the input interrupt signal as an interrupt request. When an interrupt request acceptance signal is input, the interrupt request output at that time is reset.

  FIG. 3 is a functional block diagram showing the internal configuration of the instruction cache 5. The instruction cache 5 includes a cache memory 18 configured by a plurality of ways (lines), and an input address is input to the ROM 3 side via a control circuit (configured by a cache controller and hardware logic) 19. The data is output and input to the cache memory 18 and the cache tag comparison unit 20. In the cache memory 19, an instruction (instruction data) read from the ROM 3 is written. The cache tag comparison unit 20 compares the input higher address side with the tag attached to each way of the cache memory 18 and outputs a selection signal to the multiplexer 21 for selecting one of the ways. The instruction of the way selected by the multiplexer 21 is output to the CPU 2.

  The interrupt request number given from the interrupt controller 7 is input to the vector address generation circuit 22, and the vector address generation circuit 22 stores a vector in which an instruction for branching the CPU 2 to the start address of the interrupt handler is stored according to the interrupt request number. The address is output to the control circuit 19 and the handler address generator 23. The handler address generation unit 23 generates an interrupt handler address corresponding to the input vector address and outputs it to the control circuit 19. The handler address generation unit 23 receives an instruction read from the ROM 3 and written to the cache memory 18, and the handler address generator 23 extracts the branch destination address included in the branch instruction read by the vector address. Generate an address. In addition, an interrupt permission state signal from the CPU 2 and an interrupt processing prefetch request from the interrupt controller 7 are input to the control circuit 19. Further, the control circuit 19 outputs a prefetch completion notice and a prefetch stop notice to the interrupt controller 7.

  As an outline of the operation of the microcomputer 1 in this embodiment, the peripheral circuits 8 to 9 generally output an interrupt notice signal at a stage earlier than the timing at which the interrupt signal is output, according to the generated interrupt factor. It is configured as follows. Then, the interrupt controller 7 performs a prefetch process for loading the vector and handler for performing the corresponding interrupt process from the ROM 3 to the instruction cache 5. Next, a specific configuration example of the peripheral circuits 8 to 10 that output the interrupt notice signal will be described with reference to FIGS.

  FIG. 4 shows a configuration example when the peripheral circuit 8 has a communication function. FIG. 4A corresponds to a UART (Universal Asynchronous Receiver Transmitter), and FIG. 4B corresponds to a CAN (Controller Area Network). In addition, the description regarding a general communication function is abbreviate | omitted, and only the part based on the summary of this invention is demonstrated. For the peripheral circuit 8A shown in FIG. 4A, the control circuit 24 that performs control associated with detection of the start / stop bit included in the received data and control associated with detection of the parity bit outputs the interrupt notice signal and the interrupt signal. Output. For the peripheral circuit 8B shown in FIG. 4B, it is determined in which of the plurality of message buffers received data (message) is stored, ACK (acknowledge) control and CRC (Cyclic Redundancy Check) control are performed. The control circuit 25 to perform outputs an interrupt notice signal and an interrupt signal. The communication function is not limited to UART or CAN, but may be other communication protocols.

  FIGS. 5A and 5B show an example of the timing at which an interrupt notice signal is output corresponding to the configuration of FIGS. 4A and 4B. In the case of the UART shown in FIG. 5A, data transmission is started when a start bit is output on the communication bus, and then 8-bit data is transmitted serially. When the stop bit is output following the parity bit (P), the transmission is completed. In general, an interrupt signal when such data is received is output after a stop bit is output. In this embodiment, the peripheral circuit 8A receives the start bit (this corresponds to detecting the occurrence of an event that causes an interrupt at an initial stage) and before the stop bit is output. An interrupt notice signal is output at the timing.

  Here, a specific numerical value is used to calculate how much time can be secured from the output of the interrupt notice signal to the output of the interrupt signal. Assuming that the baud rate is 10 Kbps, the interrupt notice signal is output after receiving the parity bit (P). In this case, the margin time for performing the prefetch process is 100 μs corresponding to a 1-bit transmission period, but if the operation clock frequency of the CPU 2 is 50 MHz, there is an interval of 5000 cycles (periods). Therefore, sufficient time can be secured in the instruction cache 5 for prefetching an interrupt handler of about several hundred bytes, for example. It is also possible to output an interrupt notice signal after receiving the data D7 or after receiving the start bit. In this case, a further margin can be secured.

  In the case of the CAN shown in FIG. 5B, data transmission is started when SOF (Start Of Frame) is output on the communication bus, and then ID, data, CRC, ACK, etc. are serially transmitted. The Then, when EOF (End Of Frame) is output, transmission ends, and data transfer in the peripheral circuit 8B is started in the subsequent IFS (Inter Frame Space). In general, the interrupt signal in the reception mode is output after the internal data transfer is completed. In this embodiment, the peripheral circuit 8B outputs an interrupt notice signal at a timing after receiving, for example, DLC (Data Length Code) and before outputting EOF.

  Here, as in the case of FIG. 5A, it is calculated how much time can be secured from the output of the interrupt notice signal to the output of the interrupt signal. Assuming that the baud rate is 500 Kbps and the interrupt notice signal is output after receiving ACK, the margin time is 20 μs, and there is an interval of 1000 cycles (periods). Therefore, in this case, sufficient time can be secured for prefetching the interrupt handler. It is also possible to output an interrupt notice signal after receiving DLC, during or after receiving data, after receiving CRC, etc. In this case, a further margin can be secured. For example, since the length of the received data is determined by DLC, it is possible to set the number of bytes after receiving the data.

  For example, if a reception error occurs due to a CRC check, an interrupt for notifying the CPU 2 of the reception error is generated. In this case, the statuses of the instruction cache 5 and the interrupt controller 7 are reset, and the CPU 2 performs processing corresponding to the reception error.

  FIG. 6 is a configuration example when the peripheral circuit 9 has a timer function, and FIG. 7 is an operation timing chart. Also for this, description of well-known components is omitted. Since the timer interrupt signal is output when the count value of the down counter 26 becomes zero (all bits 0), an interrupt notice signal is output before the count value becomes zero (for example, the count value is 0x00F; the lower 4 bits are all 1). Is output. In this case as well, when the time that can be secured is calculated, if the counter clock cycle is 0.5 μs, the count value is 8 μs at 0x00F, and there is an interval of 400 cycles. Therefore, in this case, sufficient time can be secured for prefetching the interrupt handler. It is also possible to output an interrupt notice signal with a count value greater than 0x00F.

  FIG. 8 shows a configuration example when the peripheral circuit 10 has an input capture function, and FIG. 9 is an operation timing chart. When it is detected that the signal of the external input terminal becomes active (for example, high) continuously for four cycles of the sampling clock (circle numerals 1 to 4 in the figure; coincidence four times; m = 4), the signal is An interrupt signal is output when it is determined that it has become active. In general, the peripheral circuit 10 configured in this manner may detect the active state a plurality of times continuously in order to eliminate the influence of the input signal level because the level of the input signal may be affected by the noise. Yes. Then, the interrupt notice signal is output when it is detected continuously for two cycles (twice coincidence; n = 2). Also in this case, when the time that can be secured is calculated, if the period of the counter clock is 1 μs, it becomes 2 μs, and there is an interval of 100 cycles. Therefore, in this case, sufficient time can be secured for prefetching the interrupt handler.

  For example, if the bus size for transferring data from the ROM 3 to the instruction cache 5 is 64 bits and the capacity of the interrupt handler is 256 bytes, the number of times of data transfer is 32, so 3 cycles are required for one transfer. Even in this case, transfer is possible in 2 μs. If the data transfer bus size is 128 bits, the number of data transfers is halved. Therefore, the operation clock frequency and the like may be adjusted as appropriate according to the actual capacity of the interrupt handler.

  Next, the effect | action of a present Example is demonstrated with reference to FIG.10 and FIG.11. FIG. 10 is a flow (sequence) diagram showing the flow of processing among the CPU 2, instruction cache 5, interrupt controller 7, and peripheral circuits 8-10. When the CPU 2 is executing normal processing other than interrupt processing, if any one or more of the peripheral circuits 8 to 10 outputs an interrupt notice signal (S1), the interrupt controller 7 responds to the interrupt notice signal. The interrupt request number is output to the instruction cache 5 (S2). Here, when a plurality of interrupt notice signals are input simultaneously, the interrupt request number with the higher priority is output as described above.

  The instruction cache 5 generates a vector address corresponding to the input interrupt request number and outputs it to the ROM 3, and the control circuit 19 loads the corresponding branch instruction into the cache memory 18 (S3). Subsequently, the address of the interrupt handler corresponding to the vector address is output to the ROM 3, and the interrupt handler is loaded into the cache memory 18 (S4). These S3 and S4 correspond to the “prefetching process”. When the prefetch process is completed, a prefetch completion notice is output to the interrupt controller 7 (S5), and the interrupt controller accepts the notice (S6). And it will be in a standby state until an interrupt signal is output from the corresponding peripheral circuit.

  When the peripheral circuit that has output the interrupt notice signal outputs an interrupt signal (S7), the interrupt controller 7 sets the interrupt request (interrupt request) according to the interrupt signal on the condition that the prefetching of the corresponding interrupt handler has been completed. The occurrence notification) is output to the CPU 2 (S8). That is, if the prefetching is not completed at the stage when the interrupt signal is input, the interrupt controller 7 suspends the output of the interrupt request to the CPU 2. Also in this case, when a plurality of interrupt signals are input simultaneously, the interrupt signal having the higher priority is output as described above. If the CPU 2 permits acceptance of the interrupt, the CPU 2 outputs a signal notifying that the interrupt signal has been accepted to the interrupt controller 7 (S9). Then, a transition is made to prepare for executing the interrupt handler (saving the program counter value, flag value, etc.).

  When the interrupt acceptance notification from the CPU 2 is input, the interrupt controller 7 outputs a corresponding interrupt request number to the CPU 2 (S10). Then, the CPU 2 outputs a vector address corresponding to the interrupt request number, accesses the instruction cache 5 (S11), and hits, so that a branch instruction which is an interrupt vector is read from the instruction cache 5 (S12). Here, from S11, the CPU 2 enters an interrupt processing execution state. By executing the read branch instruction, the CPU 2 outputs the start address of the corresponding interrupt handler and accesses the instruction cache 5 (S13). Then, the instruction of the interrupt handler is read from the instruction cache 5 (S14), and the CPU 2 executes the read instruction (S15).

FIG. 11B shows the processing shown in FIG. 10 in a timing chart. The numbers shown on the horizontal axis indicate, as a guideline, an interrupt signal (S8 in FIG. 10; “interrupt that the interrupt controller 7 outputs to the CPU 2”). This corresponds to the number of cycles based on the point in time when “request output” is output. It is not related to the specific numerical examples given in the description of the peripheral circuits 8 to 10 described above. FIG. 11A shows a case of a general conventional configuration for comparison.
In FIG. 11B, when the interrupt notice signal is output 15 cycles before, the prefetch processing of the interrupt vector and the interrupt handler by the instruction cache 5 starts from that point (including the preprocessing (S2) of the interrupt controller 7). Is done. When the prefetch process is completed, the interrupt controller 7 outputs an interrupt request to the CPU 2, and the CPU 2 starts an interrupt transition process. The subsequent hatched part is the execution period of the vector instruction, and the different hatched part following it indicates the execution period of the interrupt handler.

  On the other hand, in the case of the conventional configuration shown in FIG. 11 (a), when an interrupt signal is output, reading of the interrupt vector and interrupt handler into the instruction cache starts from that point, so that the CPU performs interrupt processing. Waiting to be executed. Then, since the CPU shifts to interrupt processing when reading into the instruction cache is completed, the CPU processing is stagnated during that time.

  As described above, according to the present embodiment, the peripheral circuits 8 to 10 receive the data that causes the CPU 2 to generate an interrupt, the timer interrupt, the continuous detection of the active level of the input signal, and the like in the initial stage. Is detected in advance, an interrupt notice signal is output to the interrupt controller 7 in advance, and an interrupt signal is output when the occurrence of the event is completed. Then, when an interrupt notice signal is input, the interrupt controller 7 performs a prefetch process for loading an interrupt vector and an interrupt handler corresponding to the notice signal from the ROM 3 to the instruction cache 5.

  Therefore, the prefetch processing to the instruction cache 5 can be completed during the period until the corresponding interrupt signal is output, and when the interrupt request is input from the interrupt controller 7, the CPU 2 immediately proceeds to interrupt processing. The execution of the interrupt handler can be started, and the responsiveness from when the interrupt occurs until the interrupt is processed can be improved. Further, if the prefetch process is not completed at the stage when the interrupt signal corresponding to the notice signal is input, the interrupt controller 7 suspends the interrupt generation notification to be performed to the CPU 2, so that the prefetch process is completed. It is possible to cause the CPU 2 to start execution of the interrupt handler, and to prevent a reduction in processing efficiency.

  When the peripheral circuit 8 has a communication function, an interrupt notice signal is output after the reception process of data transmitted from the outside is started until the reception process is completed. In other words, if there is data transmission from the outside, an interruption is generated for the CPU 2 when the reception of the transmitted data is completed, so that the reception process is completed after the reception process is started. If an interrupt notice signal is output in the meantime, the interrupt controller 7 can be notified of the occurrence of the interrupt.

  Further, when the peripheral circuit 9 has a timer function, the interrupt notice signal is output at a timing that goes back a predetermined period from the timing at which the timer interrupt signal is generated. That is, since the timing at which an interrupt is generated is determined by the count value of the down counter 26, by referring to the count value, it is possible to output an interrupt notice signal at a timing going backward from the timing at which a timer interrupt signal is generated.

  When the peripheral circuit 10 has an input capture function for determining that the signal has become active when an input signal level is detected to be active four times in succession and generating an interrupt signal, the peripheral circuit 10 An interrupt notice signal is output when the level continues twice. That is, even if the active level is continued twice, it can be said that there is a high probability that the input signal is subsequently determined to be active. Therefore, if an interrupt notice signal is output at that time, the interrupt controller 7 is notified of the occurrence of the interrupt. be able to.

(Second embodiment)
12 and 13 show a second embodiment. The same parts as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. Hereinafter, different parts will be described. The configuration of the second embodiment is basically the same as that of the first embodiment, and shows processing when an interrupt having a higher priority occurs while the instruction cache 5 is executing prefetching of an interrupt handler. FIG. 12 is a timing chart showing the processing, and FIG. 13 is a partial equivalent diagram of FIG.

  There are two peripheral circuits (1) and (2), and an interrupt from the peripheral circuit (1) has a higher priority. First, when the peripheral circuit (2) outputs an interrupt notice signal (S1a), the interrupt controller 7 outputs a prefetch request as in the first embodiment (S2a), and the instruction cache 5 stores the corresponding interrupt vector and The prefetching process of the interrupt handler is started (S3a, S4a). In the second embodiment, the prefetch request output from the interrupt controller 7 to the instruction cache 5 and the content (data value) of the response notification returned from the instruction cache 5 to the interrupt controller are clearly shown.

  As shown in FIG. 12, the prefetch request is composed of 8-bit data, and the seventh and sixth bits indicate an operation instruction (00: no instruction / 01: prefetch start / 11: prefetch stop). The 0 bit indicates an interrupt number. The lower the interrupt number, the higher the priority. The response notification is composed of 2-bit data, and the first and 0th bits indicate the operation result (00: operation stopped / 01: prefetching / 10: normal end / 11: forced end). Therefore, the data value of the prefetch request output in S2a is 0x42.

  If the peripheral circuit (1) outputs an interrupt notice signal while the instruction cache 5 is executing the prefetch process in response to the prefetch request (S1b), the interrupt controller 7 instructs the instruction cache 5 to stop prefetching (S2b). ; 0xC2). Then, the instruction cache 5 ends the prefetching process at that time, and notifies the interrupt controller 7 to that effect (S16; 0x3).

  Upon receiving the notification, the interrupt controller 7 outputs a prefetch request corresponding to the interrupt notice signal of the peripheral circuit (1) (S2c; 0x41), and the interrupt controller 7 starts prefetching corresponding to the request (S3b). , S4b). When prefetching is completed, a prefetch completion notification is output (S5b; 0x2), and the interrupt controller 7 receives the notification (S6b). Thereafter, processing is performed in the same manner as in the first embodiment.

  As described above, according to the second embodiment, the interrupt controller 7 suspends the prefetching process being executed and inputs the priority when the interrupt notification signal having a high priority is inputted during the prefetching process. The prefetch processing of the interrupt handler corresponding to the interrupt with high is started. Therefore, the handler corresponding to the interrupt scheduled to be processed first by the CPU 2 can be loaded into the instruction cache 5 first.

(Third embodiment)
FIGS. 14 and 15 show a third embodiment, and different parts from the first embodiment will be described. The third embodiment relates to control for adjusting the conflict between the two when a cache miss occurs due to an access from the CPU 2 while the instruction cache 5 is executing prefetching regarding interrupt processing. The prefetching process in this case may be premised on a configuration in which the peripheral circuits 8 to 10 output an interrupt notice signal as in the first and second embodiments, or applied to a configuration in which no interrupt notice signal is output. Also good.

  FIG. 14 shows a case where the CPU 2 permits the acceptance of an interrupt in the above-described conflict state, and (a) shows a general conventional configuration. However, for comparison, it is assumed that the timing at which the instruction cache starts prefetching is the same as that of the third embodiment. In the conventional configuration, even if a cache miss occurs in the access from the CPU while the instruction cache is prefetching the interrupt process, the prefetch process is continued until the prefetch process is completed. When the prefetch process is completed, the interrupt controller is notified of completion, and the interrupt controller gives an interrupt request to the CPU, so that the CPU starts the transition to the interrupt process from that point.

  On the other hand, in the case of the third embodiment shown in FIG. 14B, when the control circuit 19 of the instruction cache 5 recognizes the occurrence of a cache miss, it notifies the interrupt controller 7 of “prefetch completion” at that time. Processing continues. When the interrupt controller 7 receives the “prefetch completion notification”, it outputs an interrupt request to the CPU 2 when an interrupt signal is input, and the CPU 2 shifts to interrupt processing from that point.

  FIG. 15 shows a case where the CPU 2 prohibits acceptance of an interrupt in the same contention state as FIG. In the conventional configuration shown in (a), even if a cache miss occurs in the access from the CPU, the prefetch process is continued in the same manner as in FIG. 14, and a completion notification is given when the prefetch process is completed. Subsequently, an error occurs in the normal process to start loading an instruction. When the load is completed, the normal process that the CPU has been waiting for is resumed.

  In the case of the third embodiment shown in FIG. 15B, when the control circuit 19 of the instruction cache 5 recognizes the occurrence of a cache miss, it stops the prefetch process at that time and notifies the interrupt controller 7 of “prefetch stop”. To do. Then, the load of the instruction in which a cache miss has occurred in the normal process is started immediately, and when the load is completed, the normal process that the CPU 2 has been waiting for is resumed. Therefore, since the CPU 2 prohibits the acceptance of interrupts, prefetching regarding unnecessary interrupt processing is immediately stopped and the loading of the normal processing is started, so that the period during which the CPU 2 is in a standby state can be reduced accordingly.

  As described above, according to the third embodiment, when the peripheral circuit 8 to 10 generates an interrupt, the interrupt controller 7 suspends the interrupt generation notification to the CPU 2 and sets an interrupt handler corresponding to the interrupt. A prefetching process for loading the instruction cache 5 from the ROM 3 is performed. Then, if a cache miss occurs in the access from the CPU 2 during execution of the prefetch process, the control circuit 19 of the instruction cache 5 preferentially executes the prefetch process if the CPU 2 is in the interrupt enabled state at that time and prohibits interrupts. If it is in the state, the prefetch process is stopped and the instruction to be fetched by the CPU 2 is loaded into the instruction cache 5.

That is, if the CPU 2 is in the interrupt enabled state, the prefetching process is prioritized so that the CPU 2 can execute the interrupt process early. Further, if the CPU 2 is in the interrupt disabled state, the interrupt processing is not started immediately, so that the instruction to be fetched by the CPU 2 is loaded into the instruction cache 5 to give priority to the normal processing currently being executed. Therefore, the processing efficiency can be improved according to the state of correspondence to the interrupt on the CPU 2 side.
When the control circuit 19 preferentially executes the prefetch process, the control circuit 19 immediately notifies the interrupt controller 7 of the completion of the prefetch process, and the interrupt controller 7 interrupts the CPU 2 when the notification is made. Therefore, the CPU 2 can immediately shift to interrupt processing.

The present invention is not limited to the embodiments described above or shown in the drawings, and can be modified or expanded as follows.
For example, if the start address of an interrupt handler is fixed, there is no need to perform prefetch processing for the interrupt vector. For example, when an interrupt request number is given, the CPU immediately outputs an interrupt handler corresponding to the interrupt request number. It may be configured.
The interrupt controller may output the interrupt signal early for the period until the CPU shifts to interrupt processing.
The function of the peripheral circuit is not limited to that shown in the embodiment, and any function may be used as long as it is required as a specification of the microcomputer. Further, the number of peripheral circuits may be determined as appropriate according to individual design.

The program memory may be a rewritable flash memory or the like.
The configuration of the second embodiment may be combined with the configuration of the third embodiment.
In the instruction cache 5, an address management information flag storage area is provided in the cache memory 18, the flag is set when prefetching is completed, and the flag of the address accessed and read (hit) by the CPU 2 is reset. May be overwritten. Thereby, when the interrupt request is suspended because the CPU 2 prohibits the acceptance of the interrupt, it is possible to prevent the prefetched instruction from being overwritten and to prevent the occurrence of a cache miss.
The cache memory that prefetches instructions for normal processing and the cache memory that prefetches instructions for interrupt processing may be separated so that, for example, ways (lines) are different. As a result, it is possible to avoid overwriting an instruction for normal processing when prefetch processing related to interrupt processing is performed during normal processing.

  In the drawings, 1 is a microcomputer, 2 is a CPU, 3 is a ROM (program memory), 5 is an instruction cache, 7 is an interrupt controller, 8 to 10 are peripheral circuits, and 19 is a control circuit (cache controller).

Claims (8)

CPU,
One or more peripheral circuits that generate an interrupt to the CPU;
An interrupt controller for controlling the interrupt generated by the peripheral circuit and causing the CPU to process the interrupt;
A program memory for storing an interrupt handler for the CPU to process the interrupt;
An instruction cache into which a part of the program memory is loaded,
When the peripheral circuit detects an occurrence of an event that causes an interrupt to the CPU at an initial stage, the peripheral circuit outputs an interrupt notice signal to the interrupt controller, and interrupts when the occurrence of the event is completed. Output signal,
When the interrupt notice signal is input, the interrupt controller performs a prefetch process for loading an interrupt handler corresponding to the notice signal from the program memory into the instruction cache, and then interrupts corresponding to the interrupt notice signal. If the prefetching process is not completed at the stage when the signal is input, the microcomputer interrupts the interrupt generation notification to the CPU. The peripheral circuit has a communication function,
2. The microcomputer according to claim 1, wherein the interrupt notice signal is output after the reception process of data transmitted from the outside is started until the reception process is completed. The peripheral circuit has a timer function,
3. The microcomputer according to claim 1, wherein the interrupt notice signal is output at a timing that is retroactive by a predetermined period from a timing at which the timer interrupt signal is generated. When the peripheral circuit continuously detects that the level of the input signal is active m times or more, it generates an interrupt signal due to the fact that the signal is active,
4. The microcomputer according to claim 1, wherein the interrupt notice signal is output when the active level of the input signal continues n times (<m; n and m are natural numbers) or more times. .   The interrupt controller stops the prefetching process and inputs a prefetching process of an interrupt handler corresponding to the interrupt having a high priority when an interrupt notification signal having a higher priority is input during execution of the prefetching process. 5. The microcomputer according to claim 1, wherein the microcomputer is started. CPU,
One or more peripheral circuits that generate an interrupt to the CPU;
An interrupt controller for controlling the interrupt generated by the peripheral circuit and causing the CPU to process the interrupt;
A program memory for storing an interrupt handler for the CPU to process the interrupt;
A cache memory in which a part of the program memory is loaded, and an instruction cache including a cache controller that controls writing and reading to the cache memory;
When the peripheral circuit generates an interrupt, the interrupt controller holds the interrupt generation notification to the CPU and loads an interrupt handler corresponding to the interrupt from the program memory to the instruction cache. And
When a cache miss occurs during access from the CPU during execution of the prefetch process, the cache controller preferentially executes the prefetch process if the CPU is in an interrupt enabled state at that time, When the CPU is in an interrupt disabled state, the prefetching process is stopped, and an instruction to be fetched by the CPU is loaded from the program memory into the instruction cache. When the cache controller preferentially executes the prefetch process, the cache controller immediately notifies the interrupt controller of the completion of the prefetch process,
7. The microcomputer according to claim 6, wherein when the completion of the prefetch process is notified, the interrupt controller notifies the CPU of the occurrence of the interrupt.   The interrupt controller stops the prefetch process when an interrupt with a higher priority occurs during execution of the prefetch process, and starts the prefetch process of the interrupt handler corresponding to the interrupt with the higher priority. The microcomputer according to claim 6 or 7.

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