JP2012199664A - Differential amplifier circuit and integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a differential amplifier circuit and an integrated circuit device that suppress generation of an output offset voltage by maximally preventing occurrence of NBTI in two PMOS transistors constituting a differential pair.SOLUTION: A differential amplifier circuit 1 includes: a PMOS transistor 10 (example of a first PMOS transistor) into which a first signal is input; a PMOS transistor 20 (example of a second PMOS transistor) into which a second signal is input; a PMOS transistor 14 (example of a first switch section) for selecting whether or not to bring a gate and a back gate of the PMOS transistor 10 to the same potential according to a control signal XSTB; and a PMOS transistor 24 (example of a second switch section) for selecting whether or not to bring a gate and a back gate of the PMOS transistor 20 to the same potential according to the control signal XSTB.

Description

  The present invention relates to a differential amplifier circuit and an integrated circuit device.

  A differential amplifier circuit (op-amp) that amplifies and outputs a differential signal is used in various analog circuits as a basic circuit. In particular, in the design of an integrated circuit device (IC), a differential amplifier circuit is often configured using a MOS transistor. However, the normal function as a differential amplifier circuit may be lost due to deterioration of the MOS transistor, Countermeasures are important. NBTI (Negative Bias Temperature Instability) is known as one of the deterioration factors of MOS transistors. This is a phenomenon in which the threshold voltage of the PMOS transistor changes with time due to the formation of a channel over a long period of time due to the influence of the voltage and temperature applied to the gate.

  In Patent Document 1, it has been experimentally found that, in an LSI prototyped in a certain manufacturing process, the PMOS transistor undergoes a greater change in threshold voltage with time in the PBTI (Positive Bias Temperature Instability) mode than in the NBTI mode. Therefore, in the standby mode, the NBTI mode is set by applying a predetermined potential to the back gate of the PMOS transistor. As a result, the deterioration of the MOS transistor due to the stability characteristic occurring in the standby mode is suppressed, and the characteristic deterioration of the operational amplifier circuit can be avoided. Note that the difference between the NBTI mode and the PBTI mode is due to the difference in the direction of the gate electric field of the PMOS transistor.

JP 2005-354142 A

  However, in the method of Patent Document 1, in the standby mode, NBTI is generated depending on the gate voltage values of the two PMOS transistors constituting the input differential pair, so that the difference between the potentials of the two differential input signals is different. If there is, there is a possibility that the shift amount of the threshold voltage of the two PMOS transistors is different. If the shift amounts of the threshold voltages of the two PMOS transistors are different, an offset voltage is generated at the output of the operational amplifier circuit, and the normal function as the differential amplifier circuit is lost. Therefore, the method of Patent Document 1 cannot reliably avoid deterioration of the characteristics of the operational amplifier circuit.

  The present invention has been made in view of the above problems, and according to some aspects of the present invention, output offset is prevented by preventing occurrence of NBTI in two PMOS transistors constituting a differential pair. A differential amplifier circuit and an integrated circuit device that can suppress voltage generation can be provided.

  (1) The present invention is a differential amplifier circuit that differentially amplifies a first signal and a second signal, wherein the first PMOS transistor to which the first signal is input, and the second signal Is input to the second PMOS transistor, a first switch unit for selecting whether the gate and the back gate of the first PMOS transistor have the same potential based on the control signal, and the control signal And a second switch unit for selecting whether or not the gate and the back gate of the second PMOS transistor have the same potential.

  According to the present invention, based on the control signal, the gate and back gate of the first PMOS transistor can be set to the same potential, and the gate and back gate of the second PMOS transistor can be set to the same potential. In other words, according to the present embodiment, it is possible to prevent channels from being formed in both the first PMOS transistor and the second PMOS transistor based on the control signal, thereby suppressing the occurrence of NBTI in these PMOS transistors. can do. Thereby, generation | occurrence | production of the output offset voltage of the differential amplifier circuit resulting from NBTI can be suppressed.

  (2) In the differential amplifier circuit, the control signal is a signal indicating whether or not the standby mode is set, and the first switch unit is configured to output the first PMOS transistor when the control signal indicates the standby mode. The gate and back gate of the second PMOS transistor may be set to the same potential, and the second switch unit may set the gate and back gate of the second PMOS transistor to the same potential when the control signal indicates a standby mode.

  In general, in the normal operation mode, the potential of the first signal and the potential of the second signal become the same due to a virtual short circuit. Therefore, even if NBTI occurs, the shift amount of the threshold voltage of the first PMOS transistor Since the threshold voltage shift amounts of the two PMOS transistors are the same, no offset voltage is generated at the output of the differential amplifier circuit. On the other hand, in the standby mode, the gate and back gate of the first PMOS transistor have the same potential, and the gate and back gate of the second PMOS transistor have the same potential. Therefore, a channel is formed in both of these PMOS transistors. Not. Therefore, in the standby mode, the occurrence of NBTI in these PMOS transistors can be prevented, and the generation of the output offset voltage of the differential amplifier circuit can be suppressed.

  (3) In this differential amplifier circuit, a first potential is supplied to the back gate of the first PMOS transistor and the back gate of the second PMOS transistor, and the first switch unit outputs the control signal to the control signal. Based on the control signal, the second switch unit selects whether to supply the first potential to the gate of the first PMOS transistor based on the control signal. Whether to supply the first potential may be selected.

  In this way, the gate and back gate of the first PMOS transistor and the gate and back gate of the second PMOS transistor can all be set to the first potential based on the control signal. Thereby, since a channel is not formed in these PMOS transistors, it is possible to suppress the generation of the output offset voltage of the differential amplifier circuit due to NBTI.

  (4) In the differential amplifier circuit, the first switch unit selects whether to connect a gate and a back gate of the first PMOS transistor based on the control signal, and The switch unit may select whether to connect the gate and the back gate of the second PMOS transistor based on the control signal.

  According to this configuration, the gate and back gate of the first PMOS transistor can be set to the same potential, and the gate and back gate of the second PMOS transistor can be set to the same potential based on the control signal. Thereby, since a channel is not formed in these PMOS transistors, it is possible to suppress the generation of the output offset voltage of the differential amplifier circuit due to NBTI.

  (5) The differential amplifier circuit connects the back gate and the source of the first PMOS transistor and connects the back gate and the source of the second PMOS transistor based on the control signal. A third switch for selecting whether to supply a first potential to the back gate of the first PMOS transistor and the back gate of the second PMOS transistor; Based on the control signal, the second switch unit selects whether to supply the first potential to the gate of the first PMOS transistor based on the control signal. Whether to supply the first potential may be selected.

  In this way, based on the control signal, the gate and back gate of the first PMOS transistor can be set to the first potential, and the gate and back gate of the second PMOS transistor can be set to the first potential. it can. Thereby, since a channel is not formed in these PMOS transistors, it is possible to suppress the generation of the output offset voltage of the differential amplifier circuit due to NBTI.

  In this way, the back gate and source of the first PMOS transistor can be set to the same potential and the back gate and source of the second PMOS transistor can be set to the same potential based on the control signal. Thereby, the back gate bias effect (substrate effect) in the first PMOS transistor and the second PMOS transistor is not generated, and the upper limit of the input voltage range can be increased.

  (6) The differential amplifier circuit includes a fourth switch unit that selects whether to supply the first signal to the gate of the first PMOS transistor based on the control signal, and the control signal. And a fifth switch unit for selecting whether or not to supply the second signal to the gate of the second PMOS transistor.

  In this way, based on the control signal, the first signal is prevented from being input to the gate of the first PMOS transistor, and the second signal is prevented from being input to the gate of the second PMOS transistor. be able to. Therefore, regardless of the potential of the first signal or the potential of the second signal, the gate and back gate of the first PMOS transistor are surely set to the same potential, and the gate and back gate of the second PMOS transistor are surely set. To the same potential. Thereby, since a channel is not formed in these PMOS transistors, it is possible to suppress the generation of the output offset voltage of the differential amplifier circuit due to NBTI.

  (7) The present invention is an integrated circuit device including any of the differential amplifier circuits described above.

The block diagram of the differential amplifier circuit of 1st Embodiment. The block diagram of the differential amplifier circuit of the modification of 1st Embodiment. The block diagram of the differential amplifier circuit of 2nd Embodiment. The block diagram of the differential amplifier circuit of 3rd Embodiment. The block diagram of the differential amplifier circuit of the modification of 3rd Embodiment. The figure which shows the structural example of the angular velocity detection apparatus (gyro sensor) using the IC for angular velocity detection which is an example of an integrated circuit device.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Differential Amplifier Circuit (1) First Embodiment FIG. 1 is a configuration diagram of a differential amplifier circuit according to a first embodiment. The differential amplifier circuit 1 according to the first embodiment includes PMOS transistors 10, 14, 20, 24, 30, 40, 50 and NMOS transistors 12, 22, 42, 52.

  The source of the PMOS transistor 30 and the source of the PMOS transistor 40 are connected to a power source. The gate and drain of the PMOS transistor 60 are connected to the gate of the PMOS transistor 30 and the gate of the PMOS transistor 40, and a constant current source 62 is connected between the drain of the PMOS transistor 60 and the ground. A PMOS transistor 50 is connected between the gate of the PMOS transistor 30 (gate of the PMOS transistor 40) and the power supply.

  The gate of the PMOS transistor 10 (an example of the first PMOS transistor) is connected to the NIN input terminal. Further, a PMOS transistor 14 (an example of a first switch unit) is connected between the gate of the PMOS transistor 10 and the power source.

  The gate of the PMOS transistor 20 (an example of a second PMOS transistor) is connected to the PIN input terminal. A PMOS transistor 24 (an example of a second switch unit) is connected between the gate of the PMOS transistor 20 and the power source.

  Both the back gate of the PMOS transistor 10 and the back gate of the PMOS transistor 20 are connected to a power source, and are supplied with a power source potential (an example of a first potential).

  The source of the PMOS transistor 10 and the source of the PMOS transistor 20 are commonly connected to the drain of the PMOS transistor 30.

  The drain of the PMOS transistor 10 is connected to the gate and drain of the NMOS transistor 12 and the gate of the NMOS transistor 22, and the drain of the PMOS transistor 20 is connected to the drain of the NMOS transistor 22 and the gate of the NMOS transistor 42. The source of the NMOS transistor 12 and the source of the NMOS transistor 22 are connected to the ground.

  The source of the NMOS transistor 42 is connected to the ground, and the drain of the NMOS transistor 42 and the drain of the PMOS transistor 40 are commonly connected to the OUT output terminal. An NMOS transistor 52 is connected between the gate of the NMOS transistor 42 and the ground.

  The differential amplifier circuit 1 of the present embodiment receives control signals STB and XSTB indicating whether or not the standby mode is set, and is set to either the normal operation mode (non-standby mode) or the standby mode. The control signal STB is a signal that is set to a high level during the standby mode and a low level during the normal operation mode, and the control signal XSTB is a signal that is set to a low level during the standby mode and a high level during the normal operation mode.

  The control signal STB is input to the gate of the NMOS transistor 52, and the control signal XSTB is input to the gates of the PMOS transistors 14, 24, and 50.

  In the normal operation mode, since the control signal STB is at a low level and the control signal XSTB is at a high level, the NMOS transistor 52 and the PMOS transistors 14, 24, and 50 are all turned off. Accordingly, the PMOS transistor 60 and the PMOS transistor 30 form a current mirror circuit, and a constant current flows through the PMOS transistor 30. Similarly, the PMOS transistor 60 and the PMOS transistor 40 form a current mirror circuit, and a constant current flows through the PMOS transistor 40.

  In the normal operation mode, the first signal is input to the gate of the PMOS transistor 10 via the NIN input terminal, and the second signal is input to the gate of the PMOS transistor 20 via the PIN input terminal. . The PMOS transistor 10 and the PMOS transistor 20 are supplied with respective currents in which the constant current flowing through the PMOS transistor 30 is distributed according to the potential difference between the first signal and the second signal. That is, the PMOS transistor 10 and the PMOS transistor 20 function as a differential pair that detects a potential difference between the first signal and the second signal. The NMOS transistor 12 and the NMOS transistor 22 function as a current mirror pair, and the PMOS transistor 40 and the NMOS transistor 42 constitute an output stage. As a result, a signal obtained by differentially amplifying the first signal and the second signal is output to the output terminal OUT.

  On the other hand, in the standby mode, since the control signal XSTB is at a low level, the PMOS transistor 50 is turned on. Therefore, the power supply potential is forcibly supplied to the gate of the PMOS transistor 30. As a result, the PMOS transistor 30 is turned off, and the supply of current to the PMOS transistor 10 and the PMOS transistor 20 is stopped. When the PMOS transistor 50 is turned on, the power supply potential is forcibly supplied also to the gate of the PMOS transistor 40. In the standby mode, since the control signal STB is at a high level, the ground potential is forcibly supplied to the gate of the NMOS transistor 42. As a result, both the PMOS transistor 40 and the NMOS transistor 42 are turned off, and the current flowing from the power supply to the ground is stopped. Therefore, in the standby mode, the power consumption of the differential amplifier circuit 1 is reduced.

  Further, in the standby mode, since the control signal XSTB is at a low level, the PMOS transistor 14 is turned on, and the power supply potential is forcibly supplied to the gate of the PMOS transistor 10. As a result, the gate and back gate of the PMOS transistor 10 have the same potential (power supply potential), and no channel is formed in the PMOS transistor 10. Similarly, the PMOS transistor 24 is turned on, and the power supply potential is forcibly supplied to the gate of the PMOS transistor 20. As a result, the gate and back gate of the PMOS transistor 20 have the same potential (power supply potential), and no channel is formed in the PMOS transistor 20.

  Therefore, according to the present embodiment, occurrence of NBTI in the PMOS transistor 10 and the PMOS transistor 20 can be suppressed in the standby mode. Thereby, the differential amplifier circuit 1 of the present embodiment can prevent the generation of the output offset voltage due to the NBTI in the PMOS transistor 10 or the PMOS transistor 20.

  In general, in the normal operation mode, since the NIN input terminal and the PIN input terminal are used in a virtual short-circuit state, the potential difference between the back gate and the gate of the PMOS transistor 10 and the potential difference between the back gate and the gate of the PMOS transistor 20 are equal. Therefore, even if NBTI occurs in both the PMOS transistor 10 and the PMOS transistor 20, the shift amount of the threshold voltage is the same, so that no output offset voltage is generated in the differential amplifier circuit 1.

[Modification]
FIG. 2 is a configuration diagram of a differential amplifier circuit according to a modification of the first embodiment. The differential amplifier circuit 1 according to the modification of the first embodiment has a configuration in which a switch composed of a PMOS transistor 16 and an NMOS transistor 18 and a switch composed of a PMOS transistor 26 and an NMOS transistor 28 are added to the configuration shown in FIG. 2, the same components (elements) as those in FIG. 1 are denoted by the same reference numerals, and only differences from FIG. 1 will be described.

  A switch (an example of a fourth switch unit) by the PMOS transistor 16 and the NMOS transistor 18 is connected between the NIN terminal and the gate of the PMOS transistor 10. A control signal STB is input to the gate of the PMOS transistor 16, and a control signal XSTB is input to the gate of the NMOS transistor 18.

  A switch (an example of a fifth switch unit) formed by the PMOS transistor 26 and the NMOS transistor 28 is connected between the PIN terminal and the gate of the PMOS transistor 20. A control signal STB is input to the gate of the PMOS transistor 26, and a control signal XSTB is input to the gate of the NMOS transistor 28.

  In the normal operation mode, since STB is at a low level and XSTB is at a high level, both the PMOS transistor 16 and the NMOS transistor 18 are turned on, and the first signal is input from the NIN terminal to the gate of the PMOS transistor 10. Similarly, both the PMOS transistor 26 and the NMOS transistor 28 are turned on, and the second signal is input to the gate of the PMOS transistor 20 from the PIN terminal.

  On the other hand, in the standby mode, since STB is high level and XSTB is low level, both the PMOS transistor 16 and the NMOS transistor 18 are turned off and the PMOS transistor 14 is turned on, so that the PMOS transistor 10 is turned on regardless of the potential of the NIN input terminal. The gate becomes the power supply potential. Similarly, since both the PMOS transistor 26 and the NMOS transistor 28 are turned off and the PMOS transistor 24 is turned on, the gate of the PMOS transistor 20 becomes the power supply potential regardless of the potential of the PIN input terminal. As a result, in the standby mode, the gate and back gate of the PMOS transistor 10 are always at the same potential (power supply potential), and therefore no channel is formed in the PMOS transistor 10. Similarly, since the gate and back gate of the PMOS transistor 20 are always at the same potential (power supply potential), no channel is formed in the PMOS transistor 20.

  Therefore, according to the present embodiment, occurrence of NBTI in the PMOS transistor 10 and the PMOS transistor 20 can be reliably suppressed in the standby mode. Therefore, the differential amplifier circuit 1 according to the present modification can reliably prevent the generation of the output offset voltage due to the NBTI in the PMOS transistor 10 or the PMOS transistor 20.

(2) Second Embodiment FIG. 3 is a configuration diagram of a differential amplifier circuit according to a second embodiment. The differential amplifier circuit 1 of the second embodiment is different from the configuration of FIG. 1 in that the PMOS transistor 14 and the PMOS transistor 24 are eliminated, a switch composed of the PMOS transistor 70 and the NMOS transistor 72, a PMOS transistor 80, and an NMOS transistor. A switch 82 is added. 3, the same components (elements) as those in FIG. 1 are denoted by the same reference numerals, and only differences from FIG. 1 will be described.

  A switch (an example of a first switch unit) formed by the PMOS transistor 70 and the NMOS transistor 72 is connected between the gate and the back gate of the PMOS transistor 10. A control signal XSTB is input to the gate of the PMOS transistor 70, and a control signal STB is input to the gate of the NMOS transistor 72. Further, the back gate and the source of the PMOS transistor 10 are connected.

  A switch (an example of a second switch unit) constituted by the PMOS transistor 80 and the NMOS transistor 82 is connected between the gate and the back gate of the PMOS transistor 20. A control signal XSTB is input to the gate of the PMOS transistor 80, and a control signal STB is input to the gate of the NMOS transistor 82. Further, the back gate and the source of the PMOS transistor 20 are connected.

  In the normal operation mode, since the STB is low level and the XSTB is high level, both the PMOS transistor 70 and the NMOS transistor 72 are off. Similarly, both the PMOS transistor 80 and the NMOS transistor 82 are off. Therefore, the PMOS transistor 10 and the PMOS transistor 20 function as a differential pair that detects a potential difference between the first signal input from the NIN terminal and the second signal input from the PIN terminal. The NMOS transistor 12 and the NMOS transistor 22 function as a current mirror pair, and the PMOS transistor 40 and the NMOS transistor 42 constitute an output stage. As a result, a signal obtained by differentially amplifying the first signal and the second signal is output to the output terminal OUT.

By the way, the voltage between the gate and the source of the NMOS transistor 12 is vgsn1, the voltage between the drain and the source of the PMOS transistor 10 is vdsp1, the voltage between the gate and the source of the PMOS transistor 10 is vgsp1, and the voltage between the drain and the source of the PMOS transistor 30 is. Assuming that the voltage is vdsp2 and the power supply potential is vdd, the minimum input voltage Vin _L and the maximum input voltage Vin _H of the first signal input through the NIN input terminal are expressed by Expression (1) and Expression (2), respectively. Is done.

In the differential amplifier circuit of the first embodiment shown in FIG. 1, the PMOS transistor 10 has a back gate connected to the power supply and a source connected to the drain of the PMOS transistor 30, whereas FIG. In the differential amplifier circuit of the second embodiment, the back gate and the source of the PMOS transistor 10 are connected. In the circuit of FIG. 1, the back gate potential of the PMOS transistor 10 is higher than the source potential. Due to the back gate bias effect (substrate effect), the absolute value of the threshold value of the PMOS transistor 10 is higher than that of the circuit of FIG. It is high. That is, since the absolute value | vgsp1 | of the gate-source voltage of the PMOS transistor 10 is higher in the circuit of FIG. 1, Vin _L and Vin _H are lower than those in the equations (1) and (2). In other words, with the circuit configuration of FIG. 3, Vin _L and Vin _H are higher, so that the input range of the first signal can be shifted upward. The same applies to the input range of the second signal input via the PIN input terminal.

  On the other hand, in the standby mode, since STB is at a high level and XSTB is at a low level, both the PMOS transistor 70 and the NMOS transistor 72 are turned on, and the gate and back gate of the PMOS transistor 10 have the same potential. Similarly, both the PMOS transistor 80 and the NMOS transistor 82 are turned on, and the gate and back gate of the PMOS transistor 20 have the same potential. As a result, no channel is formed in the PMOS transistor 10 and the PMOS transistor 20 in the standby mode.

  Therefore, according to the present embodiment, occurrence of NBTI in the PMOS transistor 10 and the PMOS transistor 20 can be reliably suppressed in the standby mode. Therefore, the differential amplifier circuit 1 of the present embodiment can prevent the generation of the output offset voltage due to NBTI in the PMOS transistor 10 or the PMOS transistor 20.

(3) Third Embodiment FIG. 4 is a configuration diagram of a differential amplifier circuit according to a third embodiment. In the differential amplifier circuit 1 of the third embodiment, a switch (an example of a third switch unit) by a PMOS transistor 90, an NMOS transistor 92, and a PMOS transistor 94 is added to the configuration of FIG. 4, the same reference numerals are given to the same components (elements) as in FIG. 1, and only differences from FIG. 1 will be described.

  In this embodiment, the back gate of the PMOS transistor 10 and the back gate of the PMOS transistor 20 are connected. The PMOS transistor 90 and the NMOS transistor 92 are connected between the back gate and the source of the PMOS transistor 10 (the back gate and the source of the PMOS transistor 20). A control signal STB is input to the gate of the PMOS transistor 90, and a control signal XSTB is input to the gate of the NMOS transistor 92.

  The PMOS transistor 94 is connected between the back gate of the PMOS transistor 10 (back gate of the PMOS transistor 20) and the power supply. A control signal XSTB is input to the gate of the PMOS transistor 94.

  In the normal operation mode, since STB is at a low level and XSTB is at a high level, both the PMOS transistor 90 and the NMOS transistor 92 are on, and the PMOS transistor 94 is off. As a result, the back gate and source of the PMOS transistor 10 have the same potential, and the back gate and source of the PMOS transistor 20 also have the same potential. Therefore, the PMOS transistor 10 and the PMOS transistor 20 function as a differential pair that detects a potential difference between the first signal input from the NIN terminal and the second signal input from the PIN terminal. The NMOS transistor 12 and the NMOS transistor 22 function as a current mirror pair, and the PMOS transistor 40 and the NMOS transistor 42 constitute an output stage. As a result, a signal obtained by differentially amplifying the first signal and the second signal is output to the output terminal OUT.

  4, the back gate and the source of the PMOS transistor 10 are set to the same potential, and the back gate and the source of the PMOS transistor 20 are set to the same potential, similarly to the differential amplifier circuit of FIG. 3. The input range of the first signal and the second signal can be shifted upward.

  On the other hand, in the standby mode, since STB is high level and XSTB is low level, both the PMOS transistor 90 and the NMOS transistor 92 are turned off and the PMOS transistor 94 is turned on. Is forcibly supplied with a power supply potential.

  Further, in the standby mode, since the control signal XSTB is at a low level, the PMOS transistor 14 is turned on, and the power supply potential is forcibly supplied to the gate of the PMOS transistor 10. Similarly, the PMOS transistor 24 is turned on, and the power supply potential is forcibly supplied to the gate of the PMOS transistor 20. As a result, in the standby mode, the gate and back gate of the PMOS transistor 10 have the same potential (power supply potential), and therefore no channel is formed in the PMOS transistor 10. Similarly, since the gate and back gate of the PMOS transistor 20 have the same potential (power supply potential), no channel is formed in the PMOS transistor 20.

  Therefore, according to the present embodiment, occurrence of NBTI in the PMOS transistor 10 and the PMOS transistor 20 can be suppressed in the standby mode. Therefore, the differential amplifier circuit 1 of the present embodiment can prevent the generation of the output offset voltage due to NBTI in the PMOS transistor 10 or the PMOS transistor 20.

[Modification]
FIG. 5 is a configuration diagram of a differential amplifier circuit according to a modification of the third embodiment. In the differential amplifier circuit 1 of the modification of the third embodiment, a switch by a PMOS transistor 16 and an NMOS transistor 18 and a switch by a PMOS transistor 26 and an NMOS transistor 28 are added to the configuration of FIG. 5, the same components (elements) as those in FIG. 4 are denoted by the same reference numerals, and only differences from FIG. 1 will be described.

  A switch (an example of a fourth switch unit) by the PMOS transistor 16 and the NMOS transistor 18 is connected between the NIN terminal and the gate of the PMOS transistor 10. A control signal STB is input to the gate of the PMOS transistor 16, and a control signal XSTB is input to the gate of the NMOS transistor 18.

  A switch (an example of a fifth switch unit) formed by the PMOS transistor 26 and the NMOS transistor 28 is connected between the PIN terminal and the gate of the PMOS transistor 20. A control signal STB is input to the gate of the PMOS transistor 26, and a control signal XSTB is input to the gate of the NMOS transistor 28.

  In the normal operation mode, since STB is at a low level and XSTB is at a high level, both the PMOS transistor 16 and the NMOS transistor 18 are turned on, and the first signal is input from the NIN terminal to the gate of the PMOS transistor 10. Similarly, both the PMOS transistor 26 and the NMOS transistor 28 are turned on, and the second signal is input to the gate of the PMOS transistor 20 from the PIN terminal.

  On the other hand, in the standby mode, since STB is high level and XSTB is low level, both the PMOS transistor 16 and the NMOS transistor 18 are turned off and the PMOS transistor 14 is turned on, so that the PMOS transistor 10 is turned on regardless of the potential of the NIN input terminal. The gate becomes the power supply potential. Similarly, since both the PMOS transistor 26 and the NMOS transistor 28 are turned off and the PMOS transistor 24 is turned on, the gate of the PMOS transistor 20 becomes the power supply potential regardless of the potential of the PIN input terminal. Further, since the PMOS transistor 94 is turned on, both the back gate of the PMOS transistor 10 and the back gate of the PMOS transistor 20 are at the power supply potential. As a result, in the standby mode, the gate and back gate of the PMOS transistor 10 are always at the same potential (power supply potential), and therefore no channel is formed in the PMOS transistor 10. Similarly, since the gate and back gate of the PMOS transistor 20 are always at the same potential (power supply potential), no channel is formed in the PMOS transistor 20.

  Therefore, according to the present embodiment, occurrence of NBTI in the PMOS transistor 10 and the PMOS transistor 20 can be reliably suppressed in the standby mode. Therefore, the differential amplifier circuit 1 according to the present modification can reliably prevent the generation of the output offset voltage due to the NBTI in the PMOS transistor 10 or the PMOS transistor 20.

2. Integrated Circuit Device FIG. 6 is a diagram illustrating a configuration example of an angular velocity detection device (gyro sensor) using an angular velocity detection IC which is an example of an integrated circuit device. The angular velocity detection device 2 according to the present embodiment includes an angular velocity detection IC 100 and a sensor element 110.

  In the sensor element 110 of the present embodiment, two drive electrodes and two detection electrodes are formed on a so-called double T-type crystal vibrating piece having two drive vibration arms and one detection vibration arm therebetween, and is not shown. The package is sealed.

  When an AC voltage signal is given as a drive signal, the two drive vibration arms of the sensor element 110 perform bending vibration (excitation vibration) in which the tips of the sensor element 110 repeat approach and separation due to the inverse piezoelectric effect. If the amplitudes of the bending vibrations of the two driving vibrating arms are equal, the two driving vibrating arms always bend and vibrate in a line-symmetric relationship with respect to the detection vibrating arm, so that the detecting vibrating arm does not vibrate.

  In this state, when an angular velocity having an axis perpendicular to the excitation vibration surface of the sensor element 110 as a rotation axis is applied, the two drive vibration arms are subjected to Coriolis force in a direction perpendicular to both the bending vibration direction and the rotation axis. Get. As a result, the symmetry of the bending vibration of the two drive vibrating arms is lost, and the detection vibrating arm performs bending vibration so as to maintain a balance. The phase of the bending vibration of the detection vibrating arm and the bending vibration (excitation vibration) of the driving vibrating arm due to the Coriolis force is shifted by 90 °.

  However, actually, even if no Coriolis force is applied, the amplitudes of the bending vibrations of the two drive vibrating arms are slightly different, so that the detection vibrating arms slightly bend and vibrate so as to maintain a balance. This bending vibration is called leakage vibration and is in phase with the drive signal. Then, AC charges having opposite phases (phases differ by 180 °) based on these bending vibrations are generated in the two detection electrodes by the piezoelectric effect. The AC charge generated based on the Coriolis force changes according to the magnitude of the Coriolis force (in other words, the angular velocity applied to the sensor element 110), whereas the AC charge generated based on the leakage vibration is It is constant irrespective of the magnitude of the angular velocity applied to the sensor element 110.

  The two drive electrodes of the sensor element 110 are connected to the external output terminal 101 and the external input terminal 102 of the angular velocity detection IC 100, respectively. The two detection electrodes of the sensor element 110 are connected to the external input terminals 103 and 104 of the angular velocity detection IC 100, respectively.

  The angular velocity detection IC 100 includes a drive circuit 200, a detection circuit 300, a power supply circuit 400, and a reference circuit 500. The angular velocity detection IC 100 oscillates and drives the sensor element 110, and based on the detection signal of the sensor element 110, A process of generating a voltage signal (angular velocity signal) corresponding to the magnitude is performed.

  The power supply circuit 400 generates a power supply voltage inside the angular velocity detection IC 100 from a power supply voltage supplied from the external input terminal 105.

  The reference circuit 500 generates a reference voltage or a constant current from the power supply voltage generated by the power supply circuit 400 and supplies it to the drive circuit 200 and the detection circuit 300.

  The drive circuit 200 includes an I / V conversion circuit (current / voltage conversion circuit) 210, a comparator 220, an AGC (Automatic Gain Control) circuit 230, and the like.

  The I / V conversion circuit 210 receives a crystal current generated in one drive electrode by the excitation vibration of the sensor element 110 via the external input terminal 102, and converts this crystal current into an AC voltage signal.

  The AC voltage signal output from the I / V conversion circuit 210 is input to the comparator 220 and the AGC circuit 230. The comparator 220 converts the voltage of the input AC voltage signal into a binarized signal (square wave voltage signal) and outputs it.

  The AGC circuit 230 changes the amplitude of the binarized signal output from the comparator 220 in accordance with the amplitude of the AC voltage signal output from the I / V conversion circuit 210 so that the crystal current is held constant. To do. The binarized signal output from the comparator 220 is supplied to the other drive electrode of the sensor element 110 via the external output terminal 101.

  As described above, the sensor element 110 continuously excites predetermined driving vibration by the oscillation loop through the driving circuit 200.

  The detection circuit 300 includes charge amplifiers 310 and 312, a differential amplifier 314, a high-pass filter 316, an amplifier 318, a synchronous detection circuit 320, an amplifier 322, a low-pass filter 324, and an amplifier 326.

  An AC charge including an angular velocity component and a vibration leakage component is input to the charge amplifier 310 from one detection electrode of the sensor element 110 via the external input terminal 103. Similarly, AC charge including an angular velocity component and a vibration leakage component is input to the charge amplifier 312 from the other detection electrode of the sensor element 110 via the external input terminal 104. The charge amplifiers 310 and 312 convert the input AC charges into AC voltage signals. The phases of the output signal of the charge amplifier 310 and the output signal of the charge amplifier 312 are opposite to each other (shifted by 180 °).

  The differential amplifier 314 differentially amplifies the output signal of the charge amplifier 310 and the output signal of the charge amplifier 312. The differential amplifier 314 cancels the in-phase component and adds and amplifies the anti-phase component.

  The high pass filter 316 cancels the DC component included in the output signal of the differential amplifier 314, and the amplifier 318 amplifies the output signal of the high pass filter 316.

  The synchronous detection circuit 320 performs synchronous detection on the output signal of the amplifier 318 using the binary signal output from the comparator 220. For example, the synchronous detection circuit 320 selects the output signal of the amplifier 318 as it is when the voltage level of the binarized signal is higher than the reference voltage, and the amplifier 318 when the voltage level of the binarized signal is lower than the reference voltage. Can be configured as a switch circuit that selects a signal obtained by inverting the output signal with respect to the reference voltage.

  The output signal of the amplifier 318 includes an angular velocity component and a vibration leakage component. This angular velocity component is in phase with the binarized signal output from the comparator 220, whereas the vibration leakage component is in reverse phase. It is. Therefore, the angular velocity component is detected by the synchronous detection circuit 320, but the vibration leakage component is not detected.

  The amplifier 322 amplifies or attenuates the output signal of the synchronous detection circuit 320 and outputs a signal having a desired voltage level. The low-pass filter 324 removes a high-frequency component contained in the output signal of the amplifier 322 and a frequency range determined by specifications. Signal is extracted.

  The output signal of the low-pass filter 324 is amplified or attenuated to a signal having a desired voltage level by the amplifier 326. The output signal of the amplifier 326 is a voltage level signal (angular velocity signal) corresponding to the angular velocity, and is output to the outside via the external output terminal 106.

  For example, by using the differential amplifier circuit of this embodiment for the I / V conversion circuit 210, the charge amplifiers 310 and 312, the differential amplifier 314, the amplifiers 318, 322, and 326, a stable detection operation can be performed over a long period of time. A highly reliable integrated circuit device and angular velocity detection device can be realized.

  In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 Differential amplifier circuit, 2 Angular velocity detection apparatus, 10 PMOS transistor, 12 NMOS transistor, 14 PMOS transistor, 16 PMOS transistor, 18 NMOS transistor, 20 PMOS transistor, 22 NMOS transistor, 24 PMOS transistor, 26 PMOS transistor, 28 NMOS transistor 30 PMOS transistor, 40 PMOS transistor, 42 NMOS transistor, 50 PMOS transistor, 52 NMOS transistor, 60 PMOS transistor, 62 constant current source, 70 PMOS transistor, 72 NMOS transistor, 80 PMOS transistor, 82 NMOS transistor, 90 PMOS transistor 92 NMOS transistor, 94 PMOS transistor, 100 angular velocity detection IC, 110 sensor element, 101 external output terminal, 102, 103, 104, 105 external input terminal, 106 external output terminal, 200 drive circuit, 210 I / V conversion circuit ( Current-voltage conversion circuit), 220 comparator, 230 AGC circuit, 300 detection circuit, 310, 312 charge amplifier, 314 differential amplifier, 316 high-pass filter, 318 amplifier, 320 synchronous detection circuit, 322 amplifier, 324 low-pass filter, 326 amplifier , 400 Reference circuit, 500 Power supply circuit

Claims (7)

A differential amplifier circuit for differentially amplifying a first signal and a second signal,
A first PMOS transistor to which the first signal is input;
A second PMOS transistor to which the second signal is input;
A first switch unit that selects whether or not the gate and the back gate of the first PMOS transistor have the same potential based on a control signal;
And a second switch unit that selects whether or not the gate and back gate of the second PMOS transistor have the same potential based on the control signal. In claim 1,
The control signal is
It is a signal indicating whether it is in standby mode,
The first switch unit includes:
When the control signal indicates a standby mode, the gate and back gate of the first PMOS transistor are set to the same potential,
The second switch unit includes:
A differential amplifier circuit for setting the gate and back gate of the second PMOS transistor to the same potential when the control signal indicates a standby mode. In claim 1 or 2,
A first potential is supplied to a back gate of the first PMOS transistor and a back gate of the second PMOS transistor;
The first switch unit includes:
Selecting whether to supply the first potential to the gate of the first PMOS transistor based on the control signal;
The second switch unit includes:
A differential amplifier circuit that selects whether to supply the first potential to the gate of the second PMOS transistor based on the control signal. In claim 1 or 2,
The first switch unit includes:
Based on the control signal, selecting whether to connect the gate and back gate of the first PMOS transistor,
The second switch unit includes:
A differential amplifier circuit that selects whether to connect a gate and a back gate of the second PMOS transistor based on the control signal. In claim 1 or 2,
Based on the control signal, the back gate and the source of the first PMOS transistor are connected and the back gate and the source of the second PMOS transistor are connected, or the back gate and the first of the first PMOS transistor are connected. A third switch for selecting whether to supply the first potential to the back gate of the two PMOS transistors;
The first switch unit includes:
Selecting whether to supply the first potential to the gate of the first PMOS transistor based on the control signal;
The second switch unit includes:
A differential amplifier circuit that selects whether to supply the first potential to the gate of the second PMOS transistor based on the control signal. In claim 3 or 5,
A fourth switch unit for selecting whether to supply the first signal to the gate of the first PMOS transistor based on the control signal;
And a fifth switch section for selecting whether to supply the second signal to the gate of the second PMOS transistor based on the control signal.   An integrated circuit device comprising the differential amplifier circuit according to claim 1.

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