JP2012199573A - Silicon carbide single crystal wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide single crystal wafer capable of increasing a wafer area portion available for device manufacturing, and avoiding increasing working load in response to increase of wafer diameter.SOLUTION: A silicon carbide single crystal wafer comprises a working missing part whose total area size is small, or a working missing part which has a notch like shape with an asymmetric shape at a specific direction end of the wafer.

Description

  The present invention relates to a silicon carbide single crystal wafer. The silicon carbide single crystal wafer of the present invention is mainly used as a substrate for manufacturing various electronic devices and the like.

  Silicon carbide (SiC) is attracting attention as a substrate material for various semiconductor devices including power devices for high power control, due to its excellent semiconductor properties, heat resistance, mechanical strength, and the like. GaN-based blue light-emitting diodes and Schottky barrier diodes have been developed using SiC single crystal wafers that have been cut and polished from SiC single crystal ingots. Some of these have already been commercialized. Has reached the point. On the other hand, gallium nitride (GaN) -based high-frequency devices, power devices with low loss, such as MOSFETs, etc. are being prototyped. A SiC single crystal ingot having a diameter of 2 inches (about 50 mm) or more suitable for manufacturing such various devices is currently manufactured by a sublimation recrystallization method called an improved Rayleigh method. It has become mainstream (Non-Patent Document 1).

One of the requirements for manufacturing power devices with excellent breakdown voltage characteristics and operational reliability is that the wafers used have high crystallinity, that is, the density of dislocation defects that have a fatal effect on device characteristics. It needs to be small. In the case of SiC single crystal, micropipe defects are known as characteristic defects. A micropipe defect is a microscopic hole penetrating in the center of a screw dislocation with a large Burgers vector, and the presence of this defect causes current leakage under high voltage application. This will seriously affect the characteristics. Therefore, in the case of a SiC single crystal, it is important for manufacturing a device to reduce the micropipe defect density as much as possible. In recent years, with respect to single crystal production, stable production techniques have progressed, and high-quality single crystals having a number of micropipe defects per unit area (1 cm ² ) or less have been reported (Non-patent Document 2). ).

  On the other hand, for SiC Schottky barrier diodes, etc., where development progress toward commercialization is remarkable, production including the cost of devices can be achieved by increasing the number of diodes manufactured from one wafer as much as possible in one manufacturing process. It becomes important from the viewpoint of sex. The number of normally functioning devices manufactured from one wafer is determined by the number of devices that can be taken from one wafer and the ratio of the number of normally functioning devices. The former is determined by the device dimensions designed from the performance characteristics required for the device, and one way to increase the number of wafers is to increase the wafer diameter. In recent years, SiC single crystal manufacturing technology has progressed, and an increase in SiC crystal diameter of 4 inches (about 100 mm) is being realized (Non-patent Document 3). On the other hand, the ratio of the number of normally functioning devices is generally referred to as device yield. To improve the yield, the density of various dislocation defects that can seriously affect device characteristics is reduced as much as possible. Is important.

Yu. M. Tairov and V. F. Tsvetkov, Journal of Crystal Growth, vol.52 (1981) pp.146 A. H. Powell, et al., Material Science Forum, vol.457-460 (2004) pp.41 C. H. Carter, et al., FED Journal, vol.11 (2000) pp.7

  Increasing the diameter of a wafer is an effective means of improving the number of devices that can be obtained per wafer. A large-diameter SiC single crystal with a diameter of 4 inches (about 100 mm) can be used for its crystal quality, for example, a diameter of 2 inches. There is a situation that a high crystal quality equivalent to the level currently realized in a SiC single crystal (about 50 mm) cannot always be realized sufficiently stably. In other words, in SiC single crystal manufacturing performed in a high temperature region exceeding 2000 ° C., control is performed so that the radial temperature distribution during single crystal growth is optimized as the diameter of the growing SiC single crystal increases. It is easy to realize restrictions on manufacturing conditions, such as making it extremely difficult, and for this reason, it is difficult to stably realize a reduction in the density of various dislocation defects including micropipe defects. Because there is. If a large-diameter wafer in which high-quality crystals are not sufficiently realized is used, crystal defects such as residual micropipe defects will cause problems in device characteristics. A sufficient improvement effect cannot always be obtained with respect to the number of devices that can be operated, but this may occur in a SiC single crystal.

  On the other hand, in the case of a silicon (Si) wafer, a large-diameter single crystal wafer having a diameter of 300 mm has already been put into practical use. For Si wafers, when the wafer diameter is about 8 inches (200 mm), as a method of identifying the crystal orientation of a single crystal wafer, a half-moon shaped defect, that is, orientation flat (abbreviation of orientation flat) is given by processing The method to do was adopted. However, as the diameter of the crystal increases, for the purpose of reducing the processing load during orientation flat processing, for large-diameter single crystal wafers up to 300 mm, a processing defect called a notch is added to the end of the wafer with a specific crystal orientation. Is almost done. Standard specifications have been proposed for these shape and dimensional specifications, and details are specified in, for example, SEMI (Semiconductor Equipments and Materials International) Standards (for example, BOOK OF SEMI STANDARDS 1999 Volume Materials / Traceability / FDP, p.1-57).

The method described above can also be applied to a SiC single crystal wafer. However, in the case of a SiC single crystal, there are circumstances that should be considered in terms of materials that are not found in a Si single crystal.
Since SiC is a polar crystal, for example, from a SiC single crystal made of 4H or 6H polytype having a hexagonal crystal structure, a crystal plane perpendicular to the c-axis ([0001] axis), that is, c-plane ({0001 } When a single crystal wafer is cut so that the wafer surface becomes the wafer surface, one wafer surface is composed of a Si surface terminated with silicon (Si) atoms, and the other surface is composed of a C surface terminated with carbon (C) atoms. It is known that the physical and chemical properties of each wafer surface are different (WF Nippenberg, Philips Res. Reports, 18 (1963) p.161). A similar phenomenon can also occur for a crystal plane perpendicular to the <111> axis of a 3C polytype having a cubic crystal structure. As an example of such different properties, for example, etching can be performed by immersing a 4H or 6H polytype C-plane single crystal wafer in potassium hydroxide (KOH) heated and melted to about 500 ° C. The aspect exhibits surface polarity dependence reflecting the difference in the atomic plane structure. In particular, for the purpose of determining the type of dislocation and examining its density dispersion, etching of the Si surface is effective, and different etch pits appear depending on the type of dislocation defect. (S. Amelinckx, et al., J. Appl. Phys. 31 (1990) p. 1359). As another example, surface polarity dependence exists even when an SiC single crystal thin film is epitaxially grown by chemical vapor deposition (CVD) or the like, for example, incorporation of nitrogen impurities into the film during film formation. The amount generally increases when the film is formed on the C surface (T. Kimoto, et al., Appl. Phys. Lett. 67 (1995) p.2385). Such a property reflecting that SiC itself is a polar crystal is almost the same even when a wafer is cut with the normal direction of the wafer surface inclined from the c-axis, that is, a wafer with an off-angle.

  Therefore, in SiC single crystal wafers, for example, a 4 ° or 8 ° off c-plane 4H-SiC single crystal wafer, which is often used for power device applications, is a mark that can distinguish the Si surface from the C surface. It is common to give a defect part to the peripheral edge of the wafer, and at present, the first orientation flat is produced in the [1-100] direction as shown in FIG. Second orientation flats with different sizes are further produced in the [11-20] direction, and the Si and C planes can be distinguished from the relative position relative to the first orientation flat (for example, SEMI M55.1 -0304, SEMI 2004, SPECIFICATION FOR 50.8mm ROUND POLISHED MONOCRYSTALLINE 4H AND 6H SILICON CARBIDE WAFERS).

According to the above SEMI M55.1-0304, in the case of a 50.8 mm diameter wafer (diameter 50.8 ± 0.25 mm), the length of the first orientation flat and the second orientation flat is 15.8 ± 1.6 mm and 8.0 ± 1.6 mm, respectively. However, the general specifications for 2 inch wafers currently being manufactured and sold are about 50.8 ± 0.38mm, 15.88 ± 1.65mm, and about the wafer diameter, first orientation flat, and second orientation flat length, respectively. 8.0 ± 1.65mm (e.g. Cree, Silicon carbide substrates and epitaxy, Product Specifications, MAT-CATALOG.00H, 1998-2006, www.cree.com, and SiCrystal AG, Silicon Carbide Product Specifications, version 060307, 2005, www.sicrystal.de, etc.). This is calculated using the case where the wafer diameter, the first orientation flat length, and the second orientation flat length are 50.8 mm, 15.88 mm, and 8.0 mm, respectively. , The area surrounded by the straight line and dotted line of the orientation flat part) is about 0.152 cm ² and the total area of the wafer (hereinafter referred to as a perfect circle wafer) when the wafer is assumed to be a perfect circle including the missing wafer area part. The area of both defect parts is 0.735 to 0.769% when the tolerance of the wafer diameter (± 0.38mm) is taken into account, and this wafer part is removed by grinding etc. Is meant to be. In such a situation, especially when the SiC single crystal has a large diameter, the area of the crystal part to be ground and removed increases, so that the processing load also increases in parallel. Therefore, not only an increase in processing cost but also an increase in the area of the processing removal part causes a problem that the area loss of the wafer part usable for device fabrication increases with the increase in the diameter of the SiC single crystal.

  For the reasons described above, there has been a demand for a method capable of improving the number of devices that can be taken from one SiC single crystal wafer and suppressing the processing load that increases with the increase in the diameter of the SiC single crystal.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a SiC single crystal wafer that can solve the above-described problems.

The present invention relates to a silicon carbide single crystal wafer,
(1) There are two processing defects at a specific crystal orientation end, the total area of the processing defects is 0.38% or less compared to the total area of the complete circular wafer, and the area of the two processing defects is Silicon carbide single crystal wafer, characterized by being different,
(2) The silicon carbide single crystal wafer according to (1), wherein the diameter of the silicon carbide single crystal wafer is 50 mm or more,
(3) The silicon carbide single crystal wafer according to (1) or (2), wherein the wafer comprises a single polytype silicon carbide single crystal wafer,
(4) The silicon carbide single crystal wafer according to ( 3 ), wherein the polytype of the wafer is either 4H, 6H, or 15R,
(5) The silicon carbide single crystal wafer according to (3) or (4), wherein an angle formed by the surface normal of the wafer and the c-axis of the crystal is 0 to 30 °,
(6) A silicon carbide single crystal epitaxial wafer formed by epitaxially growing a silicon carbide thin film on the silicon carbide single crystal wafer according to any one of (3) to (5),
(7) A heteroepitaxial structure obtained by epitaxially growing a thin film of gallium nitride, aluminum nitride, indium nitride, or a mixed crystal thereof on the silicon carbide single crystal wafer according to any one of (3) to (5) Wafer,
It is.

  According to the present invention, it is possible to improve the number of devices that can be taken from one SiC single crystal wafer, and to avoid a processing load that increases as the diameter of the SiC single crystal increases.

Diagram showing position and shape of general orientation flat of SiC single crystal wafer Figure showing the orientation flat shape and position of the present invention for a 3 inch (about 75 mm) SiC single crystal wafer (Example 1) Diagram showing notch shape and position of the present invention for a 3 inch (about 75 mm) SiC single crystal wafer (Example 2) Diagram showing notch shape and position of the present invention for a 4-inch (about 100 mm) SiC single crystal wafer (Example 3) Diagram explaining the principle of the improved Rayleigh method (sublimation recrystallization method)

  For a disk-shaped wafer, if one of the wafer surfaces and the other wafer surface are almost the same in appearance and cannot be visually discriminated, grinding can be performed as one of the means for visually discriminating. For example, a processing defect portion that can serve as a mark for identification is given to the wafer so as to be asymmetric in the circumferential direction of the wafer. That is, in principle, a processing defect portion may be provided so that the wafer does not become symmetrical with respect to the straight line regardless of the straight line passing through the wafer center. Here, the wafer center is defined as a circle center when the wafer is regarded as a complete circle including a processing defect portion. A processing defect portion that is asymmetric in the wafer circumferential direction is a processing defect portion that is asymmetrical with respect to the center line passing through the center of the wafer.

  In particular, in the SiC single crystal wafer, as described above, it is necessary to improve the number of devices that can be taken from one wafer and to avoid the processing load that increases with the increase in diameter. Such a processing defect portion serving as a mark should be as close to the circumferential edge of the wafer as possible and its total area as small as possible. Examples are shown in FIGS. These examples show specific examples that satisfy the gist of the present invention, and the present invention is not limited to these examples. Note that the processing defect portion in the present invention includes a half-moon-shaped orientation flat and a V-shaped notch conventionally used in, for example, a Si wafer, and may have a shape other than these. Further, the area of the processing defect portion means the area of the portion that is lost by the processing defect portion when it is assumed that the wafer is a perfect circle.

  In FIG. 2, the lengths of the first orientation flat and the second orientation flat are 15.0 mm and 7.0 mm, respectively, for a SiC single crystal wafer having a diameter of 3 inches. In the current SEMI standard, in the case of a SiC single crystal wafer with a diameter of 76.2 mm corresponding to a 3-inch wafer, the wafer diameter, the first orientation flat length, and the second orientation flat length are 76.2 ± 0.25 mm, 22.0 ± 2.0 mm, and The current commercial product specifications are 76.2 ± 0.38mm, 22.22 ± 3.17mm, and 11.18 ± 1.52mm (Cree, Silicon carbide substrates and epitaxy, Product Specifications, MAT-CATALOG, respectively) .00H, 1998-2006, www.cree.com), 76.2 ± 0.38mm, 22.0 ± 2.0mm, and 11.0 ± 1.5mm (SiCrystal AG, Silicon Carbide Product Specifications, version 060307, 2005, www.sicrystal.de ). Thus, in the case of a commercial product specification, the total area of the processing defect portion due to orientation flat is about 0.387 to 0.898% in terms of the area ratio to the total area of the complete circular wafer. As shown in Figure 2, by reducing the length of each of the first and second orientation flats compared to the commercial product specifications, the total area of the machining defect part with respect to the complete circle total area for a SiC wafer with a diameter of 76.2 ± 0.38 mm The ratio is 0.178 to 0.183%, and it can be seen that a significant reduction is realized even when compared with the current commercial product specifications of 0.387 to 0.898% as described above. In this way, with the current commercial product specifications, the ratio of the total area of the processing defect portion to the total area of the complete circular wafer is 0.387% or more, so it can be used for device manufacturing by changing to the orientation flat having the shape of the present invention. The possible wafer area can be improved. As a result, the merit that the number of devices can be increased can be enjoyed, and at the same time, the processing load for providing the orientation flat can be reduced. Therefore, from the above viewpoint, the ratio of the total area of the processing defect portions may be 0.38% or less, desirably 0.30% or less, and more desirably 0.20% or less, the effect becomes remarkable.

  In addition, when the wafer diameter is 100 mm, the wafer dimensions of the current commercial product specifications are 100.0 to 100.5 mm, 32.5 ± 2.0 mm, and 18.0 ± 2.0 mm for the wafer diameter, the first orientation flat, and the second orientation flat length, respectively. Yes (Cree, Silicon carbide substrates and epitaxy, Product Specifications, MAT-CATALOG.00H, 1998-2006, www.cree.com). In this case, the area ratio of the defective area due to orientation flat addition to the total area of the complete circular wafer. Is 0.711 to 1.069%. Therefore, particularly when the wafer diameter is limited to 100 mm or more, the ratio of the total area of the processing defect portion may be 0.71% or less, preferably 0.38% or less for the effect of the present invention to be effective. More desirably, if the content is 0.20% or less, the effect becomes remarkable.

  As another example of the present invention, in FIG. 3, not the half-moon-shaped orientation flat as shown in FIG. 2, but notch-shaped processing defect portions having different sizes are provided in the [1-100] direction and [11- Processing is given to the circumferential edge in the [20] direction. For example, as shown in FIG. 3, the notch size is 2.0 mm and the notch diameter depth (a in FIG. 3) for notches in the [1-100] direction and [11-20] direction, respectively. Assuming 1.0 mm, the total area of the machining defect due to the notch is about 0.110% in terms of the area ratio to the total area of the complete circular wafer having a diameter of 76.2 mm. As described above, in the case of FIG. 3, the area portion usable for the device further increases as compared with FIG. 2, and at the same time, the processing removal portion can be similarly reduced, so that the processing load can be further reduced. Here, the angle of the notch tip is ideally 90 °, but in such a case, a crack may easily propagate from the notch tip to the inside of the wafer, and the occurrence of such a crack is suppressed. For the purpose, it may be relaxed by giving a curved shape having a radius of about 0.2 mm to the tip.

As another example of the invention, in FIG. 4, the shape of the notch itself is asymmetric with respect to the circumferential direction of the wafer, that is, the shape of the notch is symmetrical with respect to the straight line with respect to any straight line passing through the center of the wafer. We propose a structure that does not become. By adopting such a notch shape, and providing only one notch in the [1-100] direction of the wafer, the processing area load that increases the area that can be used for the device and the orientation flat is further increased. Can be reduced. In the case of the present invention example shown in FIG. 4, the effect becomes particularly remarkable in the case of a SiC single crystal wafer having a diameter of 100 mm (about 4 inches) or more, and the notch having the shape shown in FIG. By giving it to only one location, the defect area of the notch portion is about 0.012 cm ² , and the area ratio to the total area of the complete circular wafer having a diameter of 100 mm is 0.015%. As mentioned above, in the current dimensions of commercially available 100mm wafers (wafer diameter, first orientation flat and second orientation flat are 100.0 to 100.5mm, 32.5 ± 2.0mm and 18.0 ± 2.0mm respectively), the defect area due to orientation flat application Since the area ratio of the portion to the total area of the complete circular wafer is 0.711 to 1.069%, it is possible to sufficiently exhibit the effect of the present invention by providing a processing defect portion having a notch structure as shown in FIG. It turns out that it is.

  Further, as a secondary derivation effect of the present invention, it is possible to easily discriminate the wafer surface on which the device structure is manufactured by providing the above-described processing defect portions such as orientation flats and notches. In general, depending on the type of device required and the manufacturing process, the wafer surface on which the device structure is manufactured may require a highly planarized polishing surface. In many cases, the wafer surface to be polished is subjected to high-precision polishing such as CMP (Chemical Mechanical Polishing) or the like than the other surface. In such a case, according to the wafer of the present invention, by if separately specify whether subjected to precision polishing such as described above in advance either side, giving the the present invention the orientation flat or notch, Precision grinding It is possible to easily discriminate the wafer surface subjected to. Therefore, it is sufficient not only for the purpose of distinguishing between the Si and C planes, but also for other crystal plane wafers (for example, (11-20) plane wafers, (1-100) plane wafers, etc.) that do not exhibit outstanding plane polarity. It can be said that the present invention is an effective invention capable of simultaneously determining the device surface and increasing the wafer area usable for device manufacture. Therefore, from the above, in the case of a single polytype SiC single crystal wafer whose wafer polytype is 4H, 6H, or 15R, the angle between the wafer surface normal and the crystal c-axis is 0-30 °. In a wafer of 0 to 15 °, more noticeably, the surface polarity-dependent nature of the SiC single crystal is easily manifested. In such a case, the present invention is extremely effective, but in other SiC single crystal wafers as well. In view of the fact that the secondary effects as mentioned above can be affected, even when the present invention is widely applied to SiC single crystal wafers including other polytypes, the effects of the present invention are sufficiently realized. It can be said that it is possible.

  Such an SiC single crystal wafer having an orientation flat or notch structure according to the present invention can be applied to all SiC single crystal wafers produced by an SiC single crystal ingot manufacturing method using a seed crystal. Examples thereof include an improved Rayleigh method (sublimation recrystallization method), a high temperature CVD method, a liquid phase growth method, and the like. A SiC single crystal ingot produced by these methods is first processed into a cylindrical shape or a disk shape. At this time, the normal line of the desired crystal plane is made parallel to the central axis of the cylinder or the disk. . After giving the processing defect portion having the orientation flat or notch structure of the present invention as shown in FIGS. 2 to 4 to the specific orientation surface on the outer peripheral side surface of the ingot thus processed in advance by grinding or the like, the wire The SiC single crystal wafer of the present invention can be manufactured by cutting with a saw or the like and further polishing. As a specific method for producing the orientation flat or notch structure of the present invention, if the shape is a half-moon shape like orientation flat, an ingot is used by using a grinding wheel having a flat end face and using a normal surface grinding machine or the like. It is possible by grinding while applying to a predetermined position. In the case of a notch structure, a grinding wheel having a structure similar to that of the notch is prepared at the tip, and this grindstone can be produced using a normal surface grinder in the same manner as described above. . Note that the above-described columnar or disk-like processing of the ingot is not essential, but is preferably performed in order to maintain the wafer shape accuracy and the like. Further, the orientation flat or notch of the present invention may be applied after cutting or after polishing.

  In addition, the SiC single crystal wafer of the present invention is sufficiently compatible with the diameter of 50 to 300 mm, but there is no technical reason to set an upper limit in particular, considering the manufacturing method as described above. it is obvious.

  Furthermore, a homo- or hetero-epitaxial substrate is produced by epitaxially growing a thin film of SiC, gallium nitride, aluminum nitride, indium nitride, etc. on these SiC single crystal wafers by chemical vapor deposition (CVD) or the like. Can do. This epitaxial substrate can be used as a substrate for manufacturing various electronic devices.

  Examples of the present invention will be described below.

(Example 1)
First, an n-type SiC single crystal ingot having a diameter of 3 inches (about 76.2 mm) made of a single 4H polytype was fabricated by an improved Rayleigh method (sublimation recrystallization method). FIG. 5 shows an outline of a single crystal production apparatus used for ingot production.

  A crucible 3 mainly made of graphite was filled with SiC crystal powder raw material 2, and a 4H—SiC single crystal substrate having a c-plane with a diameter of 77 mm was used as a seed crystal 1 and attached to the opposing surface in the crucible. The graphite crucible 3 is placed inside a double quartz tube 4 on a support rod made of graphite, and the periphery of the crucible is covered with a heat insulating material 5 for heat shield. After evacuating the inside of the quartz tube, current was passed through the work coil 7 to raise the surface temperature of the upper part of the crucible to 1700 ° C. Thereafter, high-purity Ar gas (purity 99.9995%) was introduced as an atmospheric gas, and the temperature was raised to the target temperature of 2250 ° C. while maintaining the pressure in the quartz tube at about 80 kPa. The growth pressure was reduced to 1.3 kPa over about 30 minutes, and then the growth was continued for about 30 hours. Nitrogen was employed as the n-type dopant, and nitrogen atoms were introduced into the grown crystal by mixing a predetermined amount of nitrogen gas into the atmospheric gas during growth. When the growth crystal was taken out from the crucible after the growth was completed, the diameter of the crystal was 79 mm, and the growth rate calculated from the height of the growth crystal was about 0.9 mm / h.

  This ingot was processed into a cylindrical shape using a surface grinder and a cylindrical grinder. The aperture was 76.18 mm when measured to actual size. It should be noted that the center axis of the cylinder was adjusted using an X-ray diffractometer so that the center axis of the cylinder was parallel to a direction inclined 4 ° in the [11-20] direction from the c-axis of the SiC crystal during processing. Subsequently, using a surface grinder, the notches shown in FIG. 3 were applied to the surfaces of the cylinder in the [11-20] direction and [1-100] direction, respectively. The depth in the diameter direction of the notch is the same as that shown in FIG. 3, and the first notch and the second notch are 2.0 mm and 1.0 mm, respectively. As a processing method, a grinding wheel having a structure capable of processing the notch shown in FIG. 3 was prepared in advance, and the notch structure was imparted by applying the grinding wheel to a predetermined position on the outer surface of the ingot. The grinding work time required to give the notch at this time was about 0.55 hours. Next, a cylindrical ingot was sliced and cut by a multi-wire saw, and further polished to produce a mirror wafer having a diameter of 76.18 mm and a thickness of about 360 μm having a plane orientation of 4 ° off (0001).

  When all the obtained wafers were examined closely for the shape of the notch portion, it was confirmed that the notch having the shape shown in FIG. 3 was formed. Assuming that the shape of the tip of this notch is ideally ground so as to be 90 °, the ratio of the total area of the processing defect part to the complete circular wafer area with a diameter of 76.18 mm was calculated to be 0.110. %Met.

(Reference Example 2)
In addition, a cylindrical grind 4 ° off SiC single crystal ingot with a diameter of 76.22 mm and tilted 4 ° from the c-axis of the SiC crystal 4 ° to the [11-20] direction was prepared using a surface grinder as shown in FIG. The one notch shown in FIG. 1 was applied to a part of the surface (outer peripheral surface) in the [1-100] direction of the cylinder. Fig. 4 exemplifies a notch given to a 4-inch (about 100 mm) SiC wafer, but a notch structure (depth 1.0 mm) having the same dimensions is formed on the side surface of a cylindrical ingot having a diameter of 76.22 mm. The processing was given to the position. As a processing method, a grinding wheel having a structure capable of processing the notch shown in FIG. 4 was prepared in advance, and the notch structure was imparted to the ingot by applying the grindstone to a predetermined position on the surface of the ingot. The grinding work time required to give the notch at this time was about 0.25 hours. Next, the cylindrical ingot was cut with a multi-wire saw, and further polished to produce a mirror wafer with a diameter of 76.22 mm and a thickness of about 360 μm having a 4 ° off (0001) plane orientation. Assuming that the angle of the tip of this notch is ideally 90 °, the ratio of the total area of the processing defect part to the complete circular wafer area with a diameter of 76.22 mm was calculated to be 0.025% Met.

(Comparative Example 1)
As a comparative example, an orientation flat having a shape as shown in FIG. 2 was applied to a SiC single crystal ingot produced in the same manner as described above by grinding. However, the wafer diameter, the first orientation flat length, and the second orientation flat length were 76.27 mm, 22.41 mm, and 11.45 mm, respectively, when the actual dimensions were measured after all processing was completed, and the current 3-inch (about 75 mm) SiC It was confirmed that the wafer shape was within the range of the single crystal wafer commercial product specifications. In the case of this comparative example, the ratio of the total area of the processing defect portion to the complete circular wafer area having a diameter of 76.27 mm is 0.625%. Further, the grinding operation time at this time was about 4.5 hours.

  As shown in Example 1, Reference Example 2 and Comparative Example 1 above, for the 3-inch SiC single crystal wafer, the notch structure shown in FIGS. 3 and 4 and the orientation flat structure of the comparative example which is currently commercial product specifications 3 and 4, it can be seen that the shortening of the grinding operation corresponding to about 1/8 and about 1/18 is realized in FIGS. 3 and 4, respectively. In addition, in the case of the present invention corresponding to FIG. 3, the Si surface and the C surface of the wafer are discriminated from the relative positional relationship of the notches having different sizes, and in the case of FIG. 4, from the asymmetry of the notch structure. It is easy to see that the wafer area that can be used for the device has also increased.

  A SiC single crystal thin film is epitaxially grown on the SiC single crystal wafer shown in FIGS. 3 and 4 thus obtained by chemical vapor deposition (CVD), and the SiC single crystal epitaxial substrate is formed on the SiC single crystal wafer. Prepared on the surface. In order to investigate the crystallinity of the epitaxial substrate, the surface of the epitaxial substrate was etched by being immersed in a molten KOH solution. As a result, in both SiC single crystal wafers, there was no abnormality in the SiC single crystal thin film particularly near the notch, and the good crystal that the SiC single crystal wafer had over almost the entire surface of the wafer. It was confirmed that the quality was inherited in the SiC single crystal thin film.

In addition, a gallium nitride (GaN) thin film was epitaxially grown by the metal organic chemical vapor deposition method (MOCVD method) on the above-mentioned two types of SiC single crystal wafers separately produced. The growth conditions for the GaN thin film were as follows: growth temperature of 1050 ° C., trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) flow rates of 55 × 10 ⁻⁶ mol / min, 4 for each wafer. The liter / min was 23 × 10 ⁻¹¹ mol / min, and the growth pressure was atmospheric pressure. It was confirmed that the n-type GaN thin film had grown to a thickness of about 3 μm after about 1 hour of growth.

  When the epitaxial thin film thus obtained was observed with a Nomarski optical microscope, a high-quality GaN epitaxial thin film with excellent flatness and good morphology was formed over almost the entire surface of the substrate including the vicinity of the notch. It has been confirmed that.

  In addition, a SiC single crystal ingot was prepared in the same manner as described above, and a cylindrical shape machined so that the center axis of the cylinder was parallel to a direction tilted 4 ° from the c axis of the SiC crystal to the [11-20] direction. Even when the notch processing shown in Figs. 3 and 4 is performed on the disk obtained by cutting with a wire saw, it can be processed in a shorter time than the conventional orientation flat processing, and the total number of processing defects on the complete circular wafer area The area ratio was the same as in the above example.

1 seed crystal (SiC single crystal)
2 SiC crystal powder raw material
3 Graphite crucible
4 Double quartz tube (water cooling)
5 Insulation
6 Vacuum exhaust system
7 Work coil
8 Temperature measuring window
9 Two-color thermometer (radiation thermometer)

Claims (7)

  There are two processing defects at a specific crystal orientation end, the total area of the processing defects is 0.38% or less of the total area of the complete circular wafer, and the areas of the two processing defects are different. A featured silicon carbide single crystal wafer.   The silicon carbide single crystal wafer according to claim 1, wherein the diameter of the silicon carbide single crystal wafer is 50 mm or more.   The silicon carbide single crystal wafer according to claim 1 or 2, wherein the wafer comprises a single polytype.   The silicon carbide single crystal wafer according to claim 3, wherein the polytype of the wafer is any one of 4H, 6H, and 15R.   The silicon carbide single crystal wafer according to claim 3 or 4, wherein an angle formed by a surface normal of the wafer and a c-axis of the crystal is 0 to 30 °.   A silicon carbide single crystal epitaxial wafer obtained by epitaxially growing a silicon carbide thin film on the silicon carbide single crystal wafer according to any one of claims 3 to 5.   A heteroepitaxial wafer formed by epitaxially growing a thin film of gallium nitride, aluminum nitride, indium nitride, or a mixed crystal thereof on the silicon carbide single crystal wafer according to any one of claims 3 to 5.

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