JP2012196092A - Power supply circuit and operation control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a switching regulator type DC/DC converter to perform high frequency operation with high power conversion efficiency and short minimum on-time while suppressing spike noise.SOLUTION: In a time portion when a switching waveform Lx is changed from a high level to a low level, an output control circuit 14 outputs a gate voltage NG at a low current capacity. A waveform detection circuit 15 detects the fact that the switching waveform Lx is gradually changed from the high level to the low level. Upon receipt of a detection signal Pup thereof, the output control circuit 14 immediately raises the gate voltage NG to the high level by applying the gate voltage NG to an output driver M1 at a high current capacity. In a time portion when the switching waveform Lx is changed from the low level to the high level, the waveform detection circuit 15 detects the fact that the gate voltage NG is changed from the high level to a mode switching reference value Va. Upon receipt of a detection signal Pup thereof, the output control circuit 14 switches the application of the gate voltage NG to the output driver M1 to the application at a low current capacity.

Description

  The present invention relates to a power supply circuit and an operation control method thereof, and more particularly to a power supply circuit that converts an input voltage input from an input terminal into a predetermined voltage and outputs the voltage as an output voltage from an output terminal, and an operation control method thereof. . The power supply circuit and its operation control method of the present invention are applied to, for example, a switching regulator type DC / DC converter.

As a power supply circuit that converts an input voltage input from an input terminal into a predetermined voltage and outputs it as an output voltage from an output terminal, for example, there is a switching regulator type DC / DC converter.
In a switching regulator type DC / DC converter, it is necessary to smooth high-frequency components of a switching waveform in order to suppress spike noise.

  For example, a step-up DC / DC converter will be described as an example. The drive capability of a CMOS inverter (hereinafter referred to as a pre-driver) for driving an NMOS driver composed of an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) (hereinafter referred to as a pre-driver). It is already known that the high-frequency component is smoothed when the switching waveform changes from a high level to a low level and when the switching waveform changes from a low level to a high level by reducing the current driving capability.

  For example, for the purpose of suppressing spike noise, the transition time of the drive signal when the switching element is shifted from the off state to the on state, rather than the transition time of the drive signal when the drive switching element is shifted from the on state to the off state It has been proposed to generate a drive signal so that the length of the signal becomes longer (see Patent Document 1). Specifically, the current drive capability of the PMOS (P-channel MOS) of the CMOS inverter that generates the drive signal for the drive element is larger than that of the NMOS, and the NMOS of the CMOS inverter that generates the drive signal for the rectifier element. Patent Document 1 discloses a configuration in which spike noise is reduced by making the current driving capability larger than that of PMOS.

  However, in the method of reducing the drive capability of the CMOS inverter for driving the NMOS driver, the gate voltage of the NMOS driver is low and the on-resistance is high, so that the power conversion efficiency is lowered and the minimum on-time is increased. was there.

  Specifically, the changing part of the switching waveform from the high level to the low level will be described. When the gate voltage exceeds the threshold voltage of the NMOS driver from 0V, the NMOS driver gradually turns from off to on. It gradually goes from high level to low level. Thereby, spike noise can be suppressed. However, the time until the gate voltage goes from the threshold voltage to the high level is generally longer, and the gate voltage of the NMOS driver is lowered from the threshold voltage to the high level. Therefore, the power conversion efficiency is lowered.

  Explaining when the switching waveform changes from the low level to the high level, the NMOS driver gradually turns from on to off when the gate voltage falls below the threshold voltage of the NMOS driver from the high level, and the switching waveform gradually changes to the low level. To high level. Thereby, spike noise can be suppressed. However, the time until the gate voltage changes from the high level to the threshold voltage is generally longer, and the gate voltage of the NMOS driver is low until the gate voltage changes from the high level to the threshold voltage. Since the operation is performed in a state higher than the resistance, the efficiency is lowered.

Furthermore, if the driver is used as a resistor for overcurrent protection and backflow prevention monitoring, there is a risk of erroneous detection that the resistance value is high. Preventive monitoring is not possible, and the minimum on-time becomes long.
In recent years, in order to reduce the size of external components, DC / DC converters have a tendency to increase the frequency, and improvement is necessary for that purpose.

  An object of the present invention is to provide a power supply circuit capable of operating at high frequency with high power conversion efficiency and a short minimum on-time while suppressing spike noise with respect to a switching regulator type DC / DC converter, and a control method thereof. To do.

  A power supply circuit according to the present invention is a power supply circuit that converts an input voltage input from an input terminal into a predetermined voltage and outputs the voltage as an output voltage from an output terminal, and performs an operation according to a control signal to output the output voltage. An output transistor for controlling the output, an error amplifying circuit for amplifying and outputting a voltage difference between a predetermined reference voltage and a feedback voltage proportional to the output voltage, and the output voltage based on the output of the error amplifying circuit. A control circuit unit that outputs a gate voltage as the control signal to the output transistor so as to be constant at the predetermined voltage, and the control circuit unit monitors the gate voltage of the output transistor. A waveform detection circuit; and an output control circuit for applying the gate voltage with a variable current capacity. The waveform detection circuit includes a threshold value of the output transistor. The gate voltage is monitored using a mode switching reference value set higher than the voltage, and when the gate voltage is equal to or higher than the reference value, the output control circuit is connected to the output control circuit when the gate voltage is lower than the reference value. It is operated with a higher current capacity than

  An operation control method for a power supply circuit according to the present invention includes an output transistor for controlling an output voltage by performing an operation according to a control signal, converting the input voltage input from an input terminal into a predetermined voltage, and An operation control method for a power supply circuit that outputs from an output terminal, wherein the output is based on an output from an error amplification circuit that amplifies and outputs a voltage difference between a predetermined reference voltage and a feedback voltage proportional to the output voltage. The operation of the output transistor is controlled so that the voltage becomes constant at the predetermined voltage, and the gate voltage of the output transistor is set using a mode switching reference value set higher than the threshold voltage of the output transistor. When the gate voltage is higher than the reference value, the output transistor has a higher current capacity than when the gate voltage is lower than the reference value. Applying a gate voltage as the control signal.

  The power supply circuit and operation control method of the present invention monitor the gate voltage of the output transistor and change the allowable current for the gate voltage to be applied in accordance with the gate voltage level.

The power supply circuit and operation control method of the present invention are applied to, for example, a switching regulator type DC / DC converter. However, the application target of the power supply circuit and the operation control method of the present invention is not limited to this.
In one aspect of the power supply circuit of the present invention, the output transistor is switched according to the control signal, the inductor is charged by the input voltage by the switching of the output transistor, and the output transistor is turned off to be cut off. A rectifying element that discharges the inductor when the output transistor becomes, the control circuit unit, based on the output of the error amplifier circuit, the output transistor so that the output voltage becomes constant at the predetermined voltage Switching control is performed.

  In one aspect of the operation control method of the power supply circuit of the present invention, the output transistor performs switching according to the control signal, the power supply circuit is charged by the input voltage by switching of the output transistor, And a rectifying element that discharges the inductor when the output transistor is turned off and is in a cut-off state, and the control circuit unit is configured such that the output voltage is the predetermined voltage based on the output of the error amplifier circuit. The switching of the output transistor is controlled so as to be constant.

  In this embodiment and aspect, a description will be given of a portion of the switching waveform of the DC / DC converter when it changes from a high level to a low level. A gate voltage is applied to the output driver with a relatively low current capacity. The threshold voltage is exceeded and the output driver is slowly turned on from off. In this aspect and aspect, after detecting that the switching waveform has gradually changed from the high level to the low level by using the mode switching reference value, the gate voltage is applied to the output driver with a relatively high current capacity. Immediately set to high level.

  Describing the portion of the switching waveform when it changes from the low level to the high level, this mode and aspect is that the gate voltage is applied from the high level to the output driver while the gate voltage is applied to the output driver with a relatively high current capacity. It is detected that the reference value for mode switching is slightly higher than the threshold voltage. Switching the gate voltage application to the output driver to a relatively low current capacity. The output driver gradually turns from on to off, and the switching waveform gradually changes from low level to high level.

  In the power supply circuit of the present invention, an example of the output control circuit includes a low current drive capability inverter and a high current drive capability inverter having a higher current drive capability than the low current drive capability inverter. When the gate voltage is equal to or higher than the reference value, the low current drive capability inverter and the high current drive capability inverter are turned on. When the gate voltage is less than the reference value, only the low current drive capability inverter is turned on. . However, in the power supply circuit of the present invention, the configuration of the output control circuit is not limited to this, and the output control circuit may have any configuration as long as the gate voltage can be applied with a variable current capacity. .

In the power supply circuit of the present invention, an example of the waveform detection circuit is formed by a comparator that compares the gate voltage with the reference value.
In the power supply circuit of the present invention, another example of the waveform detection circuit is formed of a CMOS inverter having the output voltage as a power supply and the reference value as a threshold value.
However, in the power supply circuit of the present invention, the configuration of the waveform detection circuit is not limited to these, and the gate voltage of the output transistor can be monitored using a mode switching reference value set higher than the threshold voltage of the output transistor. Any configuration may be used as long as it is configured.

  A power supply circuit and an operation control method thereof according to the present invention include a power supply circuit that converts an input voltage input from an input terminal into a predetermined voltage and outputs the output voltage as an output voltage from the output terminal, and an operation control method for the output transistor. The gate voltage of the output transistor is monitored using a mode switching reference value set higher than the threshold voltage. When the gate voltage of the output transistor is equal to or higher than the reference value, the gate voltage is lower than the reference value. Since the gate voltage is applied to the output transistor with a higher current capacity, the allowable current can be changed for the applied gate voltage in accordance with the gate voltage level. Thus, when the present invention is applied to a switching regulator type DC / DC converter and its operation control method, the DC / DC converter operates at high frequency with high power conversion efficiency and a short minimum on-time while suppressing spike noise. Can be made.

  In the power supply circuit of the present invention, the output control circuit includes a low current drive capability inverter and a high current drive capability inverter having a higher current drive capability than the low current drive capability inverter, and the gate voltage is equal to or higher than a mode switching reference value. When the low current drive capability inverter and the high current drive capability inverter are turned on, and only the low current drive capability inverter is turned on when the gate voltage is less than the reference value, the output control circuit can be configured with a simple configuration. Can be formed.

  In the power supply circuit of the present invention, the waveform detection circuit is formed by a comparator that compares a gate voltage with a reference value, or is formed by a CMOS inverter that uses an output voltage as a power supply and uses the reference value as a threshold value. In this way, the waveform detection circuit can be formed with a simple configuration.

It is a circuit diagram for demonstrating an Example. It is a circuit diagram for demonstrating an example of the output control circuit in the Example. It is a circuit diagram for demonstrating an example of the NG waveform detection circuit in the Example. 3 is a timing chart for explaining operations of an output control circuit and an NG waveform detection circuit in the same embodiment. It is a circuit diagram for demonstrating the other example of a NG waveform detection circuit.

FIG. 1 is a circuit diagram for explaining an embodiment of a power supply circuit.
In FIG. 1, a power supply circuit 1 is an asynchronous rectification type boosting switching regulator that boosts an input voltage Vi input to an input terminal Vin to a predetermined constant voltage and outputs the boosted voltage as an output voltage Vo from an output terminal Vout. .
The power supply circuit 1 includes an NMOS driver M1 made of NMOSFET and a rectifying diode D1.

  Further, the power supply circuit 1 includes output voltage detection resistors R1 and R2, an inductor L1, an output capacitor Co, a phase compensation resistor R1 and a capacitor C1, an error amplification circuit 11, a PWM comparator 12, an oscillation circuit 13, and an output control circuit. 14, an NG waveform detection circuit 15 and a reference voltage generation circuit 16 are provided. A symbol Cd is a drain-gate capacitance of the NMOS driver M1. A symbol D2 is a body diode of the NMOS driver M1.

  In the power supply circuit 1, each circuit except the NMOS driver M1, the diode D1, the inductor L1, and the output capacitor Co is formed in the semiconductor chip 10. Here, one or both of the NMOS driver M1 and the diode D1 may be formed in the semiconductor chip 10.

  In FIG. 1, the NMOS driver M1 is an output transistor, the diode D1 is a rectifier, an error amplifier circuit 11, a PWM comparator 12, an oscillation circuit 13, an output control circuit 14, an NG waveform detection circuit, and a reference voltage generation circuit. 16, resistors Ra, Rb, R1 and capacitor C1 form a control circuit section.

  The reference voltage generation circuit 16 generates and outputs a predetermined reference voltage Vref and a mode switching reference value Va. The reference voltage Vref and the mode switching reference value Va may be different from each other or the same value. The output voltage detection resistors R1 and R2 divide the output voltage Vo to generate and output a feedback voltage Vfb. The error amplifier circuit 11 amplifies the voltage difference between the input feedback voltage Vfb and the reference voltage Vref to generate and output an error voltage Ve. The oscillation circuit 13 generates and outputs a predetermined triangular wave signal TW. The PWM comparator 12 generates and outputs a pulse signal Drvon for performing PWM control from the error voltage Ve from the error amplifier circuit 11 and the triangular wave signal TW from the oscillation circuit 13. The pulse signal Drvon is input to the gate of the NMOS driver M1 via the output control circuit 14.

The NG waveform detection circuit 15 monitors the gate voltage NG of the NMOS driver M1 using the mode switching reference value Va from the reference voltage generation circuit 11, and the Lx waveform L level detection signal Pup corresponding to the height of the gate voltage NG. Is output. The NG waveform detection circuit 15 outputs a high level signal when the gate voltage NG is equal to or higher than the mode switching reference value Va, and outputs a low level signal when the gate voltage NG is lower than the mode switching reference value Va. The mode switching reference value Va is set to a value higher than the threshold voltage Vth of the NMOS driver M1.
The output control circuit 14 applies a gate voltage NG to the gate of the NMOS driver M1 with a variable current capacity based on the pulse signal Drvon from the PWM comparator 12 and the Lx waveform L level detection signal Pup from the NG waveform detection circuit 15. .

An inductor L1 is connected between the input terminal Vin and the drain of the NMOS driver M1. The source of the NMOS driver M1 is connected to the ground voltage GND.
The anode of the diode D1 is connected to the connection between the inductor L1 and the NMOS driver M1. The cathode of the diode D1 is connected to the output terminal Vout.
An output capacitor Co is connected between the output terminal Vout and the ground voltage GND, and resistors Ra and Rb are connected in series. The voltage between the resistor Ra and the resistor Rb becomes the feedback resistor Vfb.

In the error amplifier circuit 11, the feedback voltage Vfb is input to the inverting input terminal, and the reference voltage Vref is input to the non-inverting input terminal. The output terminal of the error amplifier circuit 11 is connected to the non-inverting input terminal of the PWM comparator 12. A series circuit of a resistor R1 and a capacitor C1 is connected between the output terminal of the error amplifier circuit 11 and the ground voltage GND.
A triangular wave signal TW is input to the inverting input terminal of the PWM comparator 12. The pulse signal Drvon output from the PWM comparator 12 is input to the output control circuit 14.
The output control circuit 14 applies a gate voltage to the NMOS driver M1 with a variable current capacity based on the pulse signal Drvon from the PWM comparator 12 and the Lx waveform L level detection signal Pup from the NG waveform detection circuit 15.

FIG. 2 is a circuit diagram for explaining an example of the output control circuit 14.
The output control circuit 14 includes NOT circuits 21 and 22, an OR circuit 23, an AND circuit 24, and inverters 25 and 26.
The Lx waveform L level detection signal Pup is input to the NOT circuit 21. The pulse signal Drvon is input to the NOT circuit 22. The output of the NOT circuit 21 and the output of the NOT circuit 22 are input to the OR circuit 22. The AND circuit 24 receives the Lx waveform L level detection signal Pup and the output of the NOT circuit 22.

  The low current capacity inverter 25 includes a PMOS transistor M21 and an NMOS transistor M22 connected in series between the input voltage Vi and the ground potential GND. The output of the NOT circuit 22 is input to the gates of the transistors M21 and M22. The output of the low current capacity inverter 25 is output as a gate voltage NG applied to the gate of the NMOS driver M1.

  The high current capacity inverter 26 includes a PMOS transistor M23 and an NMOS transistor M24 connected in series between the input voltage Vi and the ground potential GND. The output of the OR circuit 23 is input to the gate of the transistor M23. The output of the AND circuit 24 is input to the gate of the transistor M24. The output of the high current capacity inverter 26 is output as a gate voltage NG applied to the gate of the NMOS driver M1.

  The current drive capability of the high current capacity inverter 26 is higher than the current drive capability of the low current capacity inverter 25. For example, the PMOS transistor M21 of the high current capacity inverter 26 has about 10 times the current drive capacity of the PMOS transistor M23 of the low current capacity inverter 25, and the NMOS transistor M22 of the high current capacity inverter 26 is Compared with the current driving capability of the NMOS transistor M24 of the low current capacity inverter 25, the current driving capability is about 10 times.

The output control circuit 14 outputs a signal obtained by further inverting the signal obtained by inverting the pulse signal Drvon by the NOT circuit 22 by the inverters 25 and 26 as the gate voltage NG.
When both the pulse signal Drvon and the detection signal Pup are at a low level, the MOS transistor M22 is turned on, the MOS transistors M21, M23, and M24 are turned off, and the gate voltage NG is connected to the ground potential GND with a relatively high current capacity.
When the pulse signal Drvon is high and the detection signal Pup is low, the MOS transistor M21 is turned on, the MOS transistors M22, M23, and M24 are turned off, and the gate voltage NG is connected to the input voltage Vi with a relatively low current capacity. .
When both the pulse signal Drvon and the detection signal Pup are at a high level, the MOS transistors M21 and M23 are turned on, the MOS transistors M22 and M24 are turned off, and the gate voltage NG is connected to the input voltage Vi with a relatively high current capacity.
When the pulse signal Drvon is low level and the detection signal Pup is high level, the MOS transistors M22 and M24 are turned on, the MOS transistors M21 and M23 are turned off, and the gate voltage NG is connected to the ground potential GND with a relatively low current capacity. .

FIG. 3 is a circuit diagram for explaining an example of the NG waveform detection circuit 15.
The NG waveform detection circuit 15 is formed of a comparator 31 that compares the gate voltage NG with the mode switching reference value Va. In the comparator 31, the gate voltage NG is input to the inverting input terminal, and the mode switching reference value Va is input to the non-inverting input terminal. The comparator 31 outputs a high level signal when the gate voltage NG is equal to or higher than the mode switching reference value Va, and outputs a low level signal when the gate voltage NG is lower than the mode switching reference value Va.

The operation of the power supply circuit 1 will be described with reference to FIG.
The error amplifier circuit 11 of the power supply circuit 1 amplifies the voltage difference between the reference voltage Vref and the feedback voltage Vfb to generate an error voltage Ve, and outputs the error voltage Ve to the non-inverting input terminal of the PWM comparator 12. The PWM comparator 12 outputs a high level signal when the voltage of the triangular wave signal TW is less than the error voltage Ve, and outputs a low level signal when the voltage of the triangular wave signal TW is equal to or higher than the error voltage Ve. That is, the PWM comparator 12 changes the duty cycle of the pulse signal Drvon to be output according to the error voltage Ve.

  The NMOS driver M1 is turned on when the gate is at a high level and becomes conductive, and is turned off and turned off when the gate is at a low level. When the NMOS driver M1 is on, a current flows from the input terminal Vin through the inductor L1 and the NMOS driver M1 to the ground voltage GND, and energy is stored in the inductor L1. When the NMOS driver M1 is turned off, the voltage Lx at the connection between the inductor L1 and the NMOS driver M1 becomes higher than the input voltage Vi due to the influence of the counter electromotive force of the inductor L1. The energy stored in the inductor L1 charges the output capacitor Co through the diode D1 and is supplied to the load connected to the output terminal Vout.

  When the output voltage Vo decreases and the feedback voltage Vfb decreases, the error voltage Ve from the error amplifier circuit 11 increases. Since the error voltage Ve is input to the non-inverting input terminal of the PWM comparator 12, when the error voltage Ve rises, the high level time of the pulse signal Drvon output from the PWM comparator 12 becomes longer and the low level time becomes shorter. . For this reason, the time during which the NMOS driver M1 is turned on becomes longer and the energy stored in the inductor L1 increases, so the output voltage Vo rises. Conversely, when the output voltage Vo rises and the feedback voltage Vfb rises, the error voltage Ve decreases. Then, the high level time of the pulse signal Drvon output from the PWM comparator 12 is shortened and the low level time is lengthened. For this reason, the time for which the NMOS driver M1 is turned on is shortened, and the energy stored in the inductor L1 is also reduced, so that the output voltage Vo is lowered. By repeating such an operation, the output voltage Vo is maintained at a predetermined voltage.

FIG. 4 is a timing chart for explaining operations of the output control circuit 14 and the NG waveform detection circuit 15.
t0:
When the pulse signal Drvon changes from the low level to the high level. Since the gate voltage NG is less than the mode switching reference value Va, the Lx waveform L level detection signal Pup is at the low level. The MOS transistor M21 of the output control circuit 14 is turned on, the MOS transistors M22, 23, and 24 are turned off, and the ability to drive the node of the gate voltage NG is kept low.

t0 to t1:
Since the ability to drive the node of the gate voltage NG is low, the gate voltage NG rises gently, and when the threshold voltage Vth of the NMOS driver M1 is exceeded, the NMOS driver M1 is turned on, and the Lx waveform changes from the high level. It begins to fall.

t1-t2:
Since the gate voltage NG of the NMOS driver M1 is near the threshold voltage Vth, the NMOS driver operates in the saturation region. Although the gate voltage NG tends to rise above the threshold voltage Vth, the drain-gate capacitance Cd appears to be a large capacitance due to the Miller effect, so it is very close to the threshold voltage Vth until the Lx waveform becomes low level. It rises with a gentle slope. Thereby, the high frequency component of the Lx waveform is suppressed, and spike noise can be suppressed. On the other hand, the resistance value of the NMOS driver M1 is very high, and the power conversion efficiency decreases during this period.

t2 to t3:
When the Lx waveform becomes low level, the drain-gate capacitance Cd is not required to be charged, the gate voltage NG gradually rises, and reaches the mode switching reference value Va.

t3: Since the gate voltage NG is equal to or higher than the mode switching reference value Va, the detection signal Pup of the NG waveform detection circuit 15 is changed from the low level to the high level. In the output control circuit 14, the MOS transistors M <b> 22 to M <b> 24 become operable from the state in which the MOS transistor M <b> 21 is on and the MOS transistors M <b> 22, 23, and 24 are off. At this time, since the pulse signal Drvon is at the high level, only the MOS transistor M23 is turned on among the MOS transistors M22 to M24, and the gate voltage NG is suddenly raised to the high level. As a result, the NMOS driver M1 becomes a linear region and the resistance value is originally low, and the power conversion efficiency is not affected.
In the prior art circuit, the resistance value of the NMOS driver M1 increases while the gate voltage NG gradually rises to a high level, so that the power conversion efficiency is reduced or the NMOS driver M1 is used as a current detection resistor. Although it has been a cause of erroneous detection when used, the present invention can solve these problems.

t4:
When the pulse signal Drvon changes from the high level to the low level. At this time, since the detection signal Pup is at a high level and the output control circuit 14 has a high ability to drive the node of the gate voltage NG, the NMOS driver M1 is in a linear region, and the gate voltage NG decreases sharply.
In the case of the conventional circuit, the resistance value of the NMOS driver M1 is increased while the gate voltage NG is gradually lowered to the low level, so that the power conversion efficiency is lowered. The present invention can solve this problem.
When the gate voltage NG becomes less than the mode switching reference value Va, the detection signal Pup becomes low level, the ability to drive the node of the gate voltage NG is suppressed to a low level, and the gate voltage NG gradually decreases to near the threshold voltage Vth.

t5 to t6:
When approaching the vicinity of the threshold voltage Vth of the NMOS driver M1, the NMOS driver M1 operates in the saturation region. Although the gate voltage NG tends to fall below the threshold voltage Vth, the drain-gate capacitance Cd appears as a large capacitance due to the Miller effect. Therefore, the gate voltage NG is extremely near the threshold voltage Vth until the Lx waveform becomes high level. Descent with a gentle slope. As a result, the high frequency component of the Lx waveform is suppressed, and spike noise can be suppressed. On the other hand, the resistance value of the NMOS driver M1 is very high, and the efficiency decreases during this time.

t7:
When the Lx waveform becomes high level, the drain-gate capacitance Cd is not required to be charged, and the gate voltage NG gradually decreases and reaches the low level.
As described above, according to the present invention, a switching type DC / DC converter can be operated at a high frequency with high power conversion efficiency and a short minimum on-time while suppressing spike noise.

FIG. 5 is a circuit diagram for explaining another example of the NG waveform detection circuit 15.
The NG waveform detection circuit 15 is formed of a CMOS inverter 51 that uses the output voltage Vo as a power source. The threshold value of the CMOS inverter 51 is set to the mode switching reference value Va. For example, by setting the current driving capability of the NMOS transistor M52 to be several times or more that of the PMOS transistor M51, the threshold value of the CMOS inverter 51 exceeds the threshold voltage of the NMOS driver M1, and a desired mode switching reference value. What is necessary is just to set to Va.
The CMOS inverter 51 outputs a high level Lx waveform L level detection signal Pup when the gate voltage NG becomes equal to or higher than the mode switching reference value Va.

  In the above embodiment, the asynchronous rectification type switching regulator has been described as an example. However, this is only an example, and the present invention is not limited to this, and can be applied to a synchronous rectification type switching regulator. . In this case, for example, the synchronous rectification transistor composed of a PMOS transistor is used instead of the diode D1 in FIG. 1, and the synchronous rectification transistor performs a switching operation contrary to the NMOS driver M1. These gates may be connected to the gate of the NMOS driver M1, respectively.

In the above embodiment, the switching regulator in the case of performing the PWM control has been described as an example. However, this is an example, and the present invention is not limited to this, and the switching regulator in the case of performing the PFM control or the like. It can also be applied to.
In the above-described embodiment, the step-up switching regulator has been described as an example. However, this is an example, and the present invention is not limited to this. A step-down switching regulator, an inverting switching regulator, a series regulator, etc. It can also be applied to linear regulators.

As described above, the present invention generates the feedback voltage Vfb by dividing the output voltage Vout, and uses the error amplifying circuit based on the feedback voltage Vfb so that the output voltage Vout becomes constant at a predetermined voltage. The present invention can be applied to a power supply circuit configured to perform the operation control.
Furthermore, the present invention detects the inductor current flowing through the inductor L1, and uses the error amplifying circuit based on the detected inductor current to control the operation of the output transistor so that the output voltage Vout becomes constant at a predetermined voltage. The present invention can also be applied to a current mode control type switching regulator configured to perform the above.

  The embodiments of the present invention have been described above, but the circuit configuration, arrangement, size, numerical values, and the like are examples, and the present invention is not limited to these, and the scope of the present invention described in the claims. Various modifications can be made within.

  The present invention can be applied to a power supply circuit that converts an input voltage input from an input terminal into a predetermined voltage and outputs the voltage as an output voltage from the output terminal and an operation control method thereof, for example, a DC / DC converter and an operation control method thereof.

DESCRIPTION OF SYMBOLS 1 Power supply circuit 11 Differential amplifier circuit 14 Output control circuit 15 NG waveform detection circuit 25 Low current drive capability inverter 26 High current drive capability inverter 31 Comparator 51 CMOS inverter D1 Rectifier element L1 Inductor M1 Output transistor Vin Input terminal Vout Output terminal Drvon Control Signal NG Gate voltage Va Mode switching reference value Vi Input voltage Vo Output voltage Vref Reference voltage Vfb Feedback voltage

JP 2010-178555 A

Claims (7)

In the power supply circuit that converts the input voltage input from the input terminal into a predetermined voltage and outputs it as an output voltage from the output terminal,
An output transistor for controlling the output voltage by performing an operation according to a control signal;
An error amplification circuit that amplifies and outputs a voltage difference between a predetermined reference voltage and a feedback voltage proportional to the output voltage;
A control circuit unit that outputs a gate voltage as the control signal to the output transistor so that the output voltage becomes constant at the predetermined voltage based on the output of the error amplifier circuit;
The control circuit unit includes a waveform detection circuit for monitoring the gate voltage of the output transistor, and an output control circuit for applying the gate voltage with a variable current capacity,
The waveform detection circuit monitors the gate voltage using a mode switching reference value set higher than a threshold voltage of the output transistor, and when the gate voltage is equal to or higher than the reference value, the output control A power supply circuit, wherein the circuit is operated with a higher current capacity than when the gate voltage is less than the reference value. The output transistor performs switching according to the control signal,
An inductor charged by the input voltage by switching of the output transistor;
A rectifying element that discharges the inductor when the output transistor is turned off and is cut off;
With
The power supply circuit according to claim 1, wherein the control circuit unit performs switching control of the output transistor so that the output voltage becomes constant at the predetermined voltage based on an output of the error amplifier circuit.   The output control circuit includes a low current drive capability inverter and a high current drive capability inverter having a higher current drive capability than the low current drive capability inverter, and the low current drive when the gate voltage is equal to or higher than the reference value. 3. The power supply circuit according to claim 1, wherein the capacity inverter and the high current drive capacity inverter are turned on, and only the low current drive capacity inverter is turned on when the gate voltage is less than the reference value.   4. The power supply circuit according to claim 1, wherein the waveform detection circuit is formed by a comparator that compares the gate voltage with the reference value. 5.   4. The power supply circuit according to claim 1, wherein the waveform detection circuit is formed of a CMOS inverter that uses the output voltage as a power supply and uses the reference value as a threshold value. 5. In an operation control method for a power supply circuit, comprising an output transistor for controlling an output voltage by performing an operation according to a control signal, converting the input voltage input from an input terminal into a predetermined voltage and outputting the voltage from the output terminal ,
Based on an output from an error amplification circuit that amplifies and outputs a voltage difference between a predetermined reference voltage and a feedback voltage proportional to the output voltage, the output transistor is configured so that the output voltage becomes constant at the predetermined voltage. Control the operation of
The gate voltage of the output transistor is monitored using a mode switching reference value set higher than the threshold voltage of the output transistor, and when the gate voltage is equal to or higher than the reference value, the gate voltage is An operation control method for a power supply circuit, wherein a gate voltage as the control signal is applied to the output transistor with a higher current capacity than when it is less than a reference value. The output transistor performs switching according to the control signal,
The power supply circuit includes an inductor that is charged by the input voltage by switching of the output transistor, and a rectifier that discharges the inductor when the output transistor is turned off to be cut off.
The power supply circuit according to claim 6, wherein the control circuit unit performs switching control of the output transistor so that the output voltage becomes constant at the predetermined voltage based on an output of the error amplifier circuit. Operation control method.

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