JP5094512B2 - Switching regulator - Google Patents

Description

  The present invention relates to a switching regulator.

  In a conventional switching regulator, an error amplifier amplifies an error between a reference voltage and a voltage based on an output voltage of the switching regulator, and a PWM [Pulse Width Modulation] comparator compares the output voltage of the error amplifier with a triangular wave to generate a PWM signal. Is generally used, and the switching element in the DC-DC converter is controlled on / off based on the PWM signal (see, for example, Patent Document 1 and Patent Document 2). However, in the switching regulator having such a configuration, since the error amplifier provided in the feedback portion performs an amplification operation, it cannot perform a high-speed operation.

  Further, a current mode control switching regulator can be cited as a switching regulator capable of high-speed operation. The current mode control switching regulator compares the variable voltage offset according to the difference between the reference voltage and the voltage based on the output voltage of the switching regulator with the voltage according to the output current of the switching regulator. This is a switching regulator that generates a pulse signal with a corresponding duty and controls on / off of a switching element in the DC-DC converter based on the pulse signal (see, for example, Patent Document 3).

Patent Document 4 discloses and proposes a switching regulator capable of high-speed operation without using an error amplifier or current mode control.
JP 2003-219638 A Japanese Patent Laid-Open No. 10-25105 JP 2003-319643 A JP 2006-141191 A

  Certainly, with the current mode control switching regulator described above, a certain degree of high-speed operation is possible compared to a configuration using an error amplifier.

  However, in a current mode control switching regulator, feedback for generating a variable voltage that is offset according to the difference between the reference voltage and the voltage based on the output voltage of the switching regulator is applied, so that it is difficult to operate at a speed higher than a certain level. It is. For example, in a current mode control switching regulator disclosed in Patent Document 3, a transconductance amplifier (gm amplifier) offsets a variable voltage according to a difference between a reference voltage and an output voltage of the switching regulator, and the gm Since the amplifier performs an amplifying operation according to the output voltage of the switching regulator, it is difficult to perform a high-speed operation beyond a certain level.

  Note that the switching regulator described in Patent Document 4 can operate at extremely high speed without using an error amplifier or current mode control. However, the output fluctuation caused by the input fluctuation or the load fluctuation can be further improved. Had room.

  In view of the above problems, the present invention provides a switching regulator control signal generation circuit that enables high-speed operation of a switching regulator while suppressing output fluctuation due to input fluctuation and load fluctuation, and a switching regulator capable of high-speed operation. The purpose is to provide.

  In order to achieve the above object, a control signal generation circuit for a switching regulator according to the present invention includes a comparator that compares an output voltage of a switching regulator with a reference voltage; a flip-flop set by the output of the comparator; A pulse control circuit that resets the flip-flop when a predetermined on-period has elapsed since the signal was set; monitoring the output voltage and varying the reference voltage so that its voltage level matches a desired target voltage A reference voltage control circuit that controls the output voltage of the flip-flop as a control signal for the switching element (first configuration).

  In the switching regulator control signal generation circuit having the first configuration, the reference voltage control circuit includes an amplifier that amplifies a difference between the output voltage and the target voltage to generate the reference voltage. (A second configuration).

  In the switching regulator control signal generation circuit having the second configuration, the amplifier operates to lower the reference voltage when the output voltage is higher than the target voltage, and conversely, the output voltage When the voltage is lower than the target voltage, a configuration that operates to increase the reference voltage (third configuration) may be used.

  In addition, a switching regulator according to the present invention includes a DC-DC converter, a control signal generation circuit that generates a control signal according to the output voltage of the DC-DC converter, and the DC-DC converter based on the control signal. And a driver circuit for driving the switching element, wherein the control signal generation circuit is a switching regulator control signal generation circuit having any one of the first to third configurations (fourth configuration) ).

  According to the present invention, it is possible to realize a switching regulator control signal generation circuit capable of high-speed operation of a switching regulator and a switching regulator capable of high-speed operation while suppressing output fluctuation due to input fluctuation and load fluctuation. Therefore, for example, it is possible to cope with an increase in current.

  First, before describing the characteristic configuration of the switching regulator according to the present invention, the basic configuration and operation of the switching regulator according to the present invention will be described in detail with reference to FIGS.

  FIG. 1 is a diagram showing a basic configuration of a switching regulator according to the present invention.

The switching regulator shown in FIG. 1 includes a control signal generation circuit 1, a driver logic circuit 2, N-channel MOS [Metal Oxide Semiconductor] field effect transistors (hereinafter referred to as NMOS or NMOS transistors) 3 and 4, and a Zener diode 5 And a capacitor 6, a coil 7, and an output capacitor 8. Note that the input voltage V _IN is higher than the drive voltage V _DD of the circuit elements forming the control signal generation circuit 1. In FIG. 1, the input voltage V _IN is +25 [V], and the drive voltage V _DD is +5 [V]. In FIG. 1, a DC-DC converter including NMOSs 3 and 4, a coil 7, and an output capacitor 8 converts an input voltage V _IN into an output voltage V _O. Therefore, the output voltage V _O is not only the output voltage of the switching regulator shown in FIG. 1 but also the output voltage of the DC-DC converter.

The control signal generation circuit 1 receives the output signal V _O , generates a pulse signal (control signal) V _Q and sends it to the driver logic circuit 2. The driver logic circuit 2 performs on / off control of the NMOSs 3 and 4 based on the pulse signal V _Q output from the control signal generation circuit 1.

When the NMOS 3 is turned off and the NMOS 4 is turned on complementarily, a charging current flows into the capacitor 6 from the terminal to which the drive voltage V _DD is applied via the Schottky diode 5, and the voltage across the capacitor 6 is about +5 [V]. Thereafter, when the NMOS 3 is turned on and the NMOS 4 is turned off complementarily, the voltage at the connection point between the capacitor 6 and the NMOS 3 becomes +25 [V], and the voltage at the connection point between the capacitor 6 and the Schottky diode 5 is about +30. [V]. Then, about +30 [V] generated at the connection point between the capacitor 6 and the Schottky diode 5 is supplied to the driver logic circuit 2.

  The driver logic circuit 2 uses +30 [V] supplied from the connection point between the capacitor 6 and the Schottky diode 5 to shift the level of the pulse signal output from the control signal generation circuit 1 to the high potential side. The first drive signal based on the level-shifted signal is supplied to the gate of the NMOS 3, the pulse signal output from the control signal generation circuit 1 is inverted, and the second drive signal based on the inverted signal is supplied to the gate of the NMOS 4. To supply.

The voltage at the connection point between the NMOS 3 and the NMOS 4 is smoothed by the coil 7 and the output capacitor 8 to become the output voltage V _O.

  Next, the control signal generation circuit 1 will be described in detail. The control signal generation circuit 1 includes a comparator 10, a reference voltage source 11, a flip-flop 12, and a pulse control circuit 13.

The comparator 10 compares the output voltage V _O with the reference voltage V _REF output from the reference voltage source 11, and supplies the comparison output to the set terminal (S) of the flip-flop 12 as the set signal Vs. The pulse control circuit 13 receives the input voltage V _IN , the reference voltage V _REF2 , and the inverted output of the flip-flop 12 as input, and satisfies the following expression (1) so that the input voltage V _IN and the reference voltage V are satisfied. The ON period T _ON of the pulse signal V _Q output from the control signal generation circuit 1 is set according to the ratio of _{REF 2} (V _REF2 / V _IN ), and the pulse signal V _Q output from the control signal generation circuit 1 is the signal of the frequency f for resetting the flip-flop 12 when the oN period T _oN from the rise has passed as the reset signal V _R, and supplies the reset terminal of the flip-flop 12 (R). The pulse signal V _Q output from the flip-flop 12 is supplied to the driver logic circuit 2. The reference voltage V _REF2 may be set by a band gap circuit or the like, or the output voltage V _O may be used.

One configuration example of the control signal generation circuit 1 is shown in FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The pulse control circuit 13 included in the control signal generation circuit 1 shown in FIG. 2 includes resistors R1 and R2 that divide the input voltage V _IN , an npn bipolar transistor Q3, a resistor R3 through which an emitter current of the transistor Q3 flows, A high-speed amplifier AMP1 that amplifies the difference between the divided voltage V _IN and the voltage across the resistor R3 and supplies it to the base of the transistor Q3, a capacitor C1, and pnp bipolar transistors Q1 and Q2, and the emitter current of the transistor Q3 A current mirror circuit that supplies the same value or a predetermined charging current to the capacitor C1, an N-channel MOS field effect transistor Q4 that switches charging / discharging of the capacitor C1 according to the inverted output of the flip-flop 12, and a reference voltage V _REF2 Voltage dividing resistors R4 and R5, and reference voltage V _REF2 voltage divider and capacitor The comparator COM1 compares the voltage across the capacitor C1 and supplies the comparison output to the reset terminal (R) of the flip-flop 12.

  Subsequently, a time chart of each voltage or current of the switching regulator shown in FIG. 1 and the control signal generation circuit 1 shown in FIG. 2 is shown in FIG. 3, and the switching regulator shown in FIG. The operation of the control signal generation circuit 1 will be described.

When the pulse signal V _Q supplied from the output terminal of the flip-flop 12 (Q) to the driver logic circuit 2 is Low level, NMOS 3 is off, because NMOS4 are complementarily turned on, the current flowing through the coil 7 I _L and the output voltage V _O gradually decrease. At this time, since the inverted output of the flip-flop 12 is at a high level, the NMOS transistor Q4 is on and the voltage V _C1 across the capacitor _C1 is zero. Therefore, the reset signal V _R supplied from the comparator COM1 to the reset terminal (R) of the flip-flop 12 is at the low level.

When the output voltage V _O becomes smaller than the reference voltage V _{REF, the} set signal V _S supplied from the comparator 10 to the set terminal (S) of the flip-flop 12 is switched from the Low level to the High level. As a result, the pulse signal V _Q is switched from the Low level to the High level, the NMOS 3 is turned on, and the NMOS 4 is complementarily turned off, so that the output voltage V _O becomes higher than the reference voltage V _REF . Accordingly, the set signal V _S immediately returns to the low level. At this time, since the inverted output of the flip-flop 12 is switched from the High level to the Low level, the NMOS transistor Q4 is turned off and the charging current starts to be supplied to the capacitor C1.

Thereafter, while the pulse signal V _Q is the output of the flip-flop 12 is High level, the current I _L flowing through the coil 7, the output voltage V _O, and the voltage across V _C1 of the capacitor C1 gradually increases.

When the voltage across V _C1 of the capacitor C1 reaches the threshold V _TH (the same value as the voltage at the node between resistors R4 and R5), the reset signal V _R is switched from Low level to High level. Thus, pulse signal V _Q is switched from High level to Low level. When the pulse signal V _Q becomes Low level, NMOS transistor Q4 is turned on the inverted output of the flip-flop 12 becomes the High level, since the voltage across V _C1 of the capacitor C1 becomes zero, the reset signal V _R is immediately Return to Low level.

Control signal generating circuit 1 shown in switching regulator and 2 shown in FIG. 1, since the above operation, the ON period T _ON of the pulse signal V _Q coincides with the charging time of capacitor C1. Therefore, the ON period T _ON of the pulse signal V _Q can be expressed by the following equation (2). However, C ₁ represents the capacitance of the capacitor C1, i represents the charging current of the capacitor C1, R ₁ ~R ₅ shows the resistance R1~R5 the resistance values.

Here, in a switching regulator having a step-down DC-DC converter, an ON period T _{ON of a} pulse signal used for on / off control of a switching element in the DC-DC converter (energy is stored in a coil in the DC-DC converter). is period), so expressed by equation (1) above, the product of the resistance value R ₃ of the capacitance C ₁ and the resistor R3 of the capacitor C1, the frequency f of the pulse signal V _Q. Thereby, even if the value of the input voltage V _IN is changed, the frequency f of the control signal V _Q can be fixed.

In the switching regulator shown in FIG. 1, since the feedback part mainly performs the comparison operation between the output voltage V _O and the reference voltage V _REF and the comparison operation between the charging voltage V _C1 and the reference voltage V _REF2 , high-speed operation is possible. . Accordingly, it can be sufficiently used as a power source for digital home appliances and personal computers whose operating speed has been remarkably increased in recent years.

Meanwhile, in the switching regulator consisting essentially above configuration, the average value of the output voltage V _O, as indicated by (3) below, with respect to the reference voltage V _REF, the ripple voltage occurring in the output voltage V _O The voltage value is obtained by adding 1/2 of ΔV. The relationship between the output voltage V _O , the reference voltage VREF, and the ripple voltage ΔV generated in the output voltage V _O is shown in FIG.

On the other hand, the ripple voltage ΔV generated in the output voltage V _O can be obtained by the following equation (4). In the following equation (4), the parameter L, the parameter f, and the parameter ESR are respectively an inductance value of the coil 7, a driving frequency of the switching elements 3 and 4, and an equivalent series resistance value of the output capacitor 8 ( ESR [Equivalent Series Resistance]). Also, the following equation (4) shows a case where the output voltage V _O is used as the reference voltage V _REF2 .

As can be seen from the above equation (4), the ripple voltage ΔV generated in the output voltage V _O is caused by input fluctuation (fluctuation of the input voltage V _IN ) or load fluctuation (fluctuation of the ON period T _ON of the output transistor 3). As a result, the size varies. Therefore, in the switching regulator having the above basic configuration, when the ripple voltage ΔV generated in the output voltage V _O is increased or decreased due to input fluctuation or load fluctuation, the output voltage V _O varies depending on this. There was a problem that.

The behavior when the input changes will be specifically described. As described above, the magnitude of the ripple voltage ΔV generated in the output voltage V _O depends on the input voltage V _IN . Therefore, when the input voltage V _IN varies, the ripple voltage ΔV generated in the output voltage V _O is increased or decreased, and consequently the output voltage V _O varies.

For example, when V _O = 1.8 [V], L = 2.5 [μH], f = 300 [kHz] and ESR = 15 [mΩ], when V _IN = 25 [V], ΔV = 33.4 [mV], but when V _IN = 5 [V], ΔV = 23.0 [mV]. That is, the ripple voltage ΔV generated in the output voltage V _O varies by 10.4 [mV], and the output voltage V _O varies by 5.2 [mV] depending on this.

Next, the behavior when the load fluctuates will be specifically described. As mentioned earlier, since the switching regulator consisting essentially above configuration, the pulse control circuit 13, so as to fix the frequency f of the pulse signal V _Q, the frequency control of the pulse signal V _Q is performed, The ON period T _ON of the output transistor 3 forming the DC-DC converter should be basically constant without depending on input fluctuation or load fluctuation. However, in practice, when the synchronous rectification transistor 4 forming the DC-DC converter is turned off, whether or not the current I _L flowing through the coil 7 is larger than a zero value (by extension, whether the load is light or heavy). Depending on whether it is a load or not, the ON period T _ON of the output transistor 3 varies.

FIG. 4 is a timing chart showing how the _ON period T _ON of the output transistor 3 varies due to load variation. In the upper part of FIG. 4, the coil current I _L at the time of light load, the gate voltage of the output transistor 3, and the gate voltage of the synchronous rectification transistor 4 are shown in order from the top. In the lower part of FIG. 4, the coil current I _L at the time of heavy load, the gate voltage of the output transistor 3, and the gate voltage of the synchronous rectification transistor 4 are shown in order from the top.

As shown in the upper part of FIG. 4, the load is light, when the synchronous rectification transistor 4 is turned off, when the current I _L flowing through the coil 7 is less than the zero value, simultaneous OFF period of the output transistor 3 and the synchronous rectification transistor 4 In T _D (dead time), the gate voltage of the output transistor 3 does not become low level, and the ON period T _ON of the output transistor 3 is substantially extended. On the other hand, as shown in the lower part of FIG. 4, the load is heavy, when the synchronous rectification transistor 4 is turned off, when the current I _L flowing through the coil 7 is greater than zero value, simultaneous output transistor 3 and the synchronous rectification transistor 4 in the off period T _D, the gate voltage of the output transistor 3 becomes low level, does not oN period T _oN of the output transistor 3 is extended.

Therefore, as can be seen by comparing the upper stage and the lower stage of FIG. 4, the ON period T _ON of the output transistor 3 fluctuates when the load fluctuates (particularly when the light load is changed to the heavy load). The ripple voltage ΔV generated in VO is increased or decreased, and as a result, the output voltage V _O varies.

For example, V _IN = 12 [V], V _O = 1.2 [V], L = 1.5 [μH], T _ON = 140 [nsec], ESR = 30 [mΩ], TD = 30 [nsec] In this case, ΔV = 38.9 [mV] at a light load, whereas ΔV = 32.4 [mV] at a heavy load. That is, the ripple voltage ΔV generated in the output voltage V _O varies by 6.5 [mV], and the output voltage V _O varies by 3.2 [mV] depending on this.

As described above, in the switching regulator having the above basic configuration, the ripple voltage ΔV generated in the output voltage V _O is increased or decreased due to the input fluctuation or the load fluctuation, and as a result, the output voltage V V depends on this. There was a problem that it fluctuated to _O.

  In the following, the characteristic configuration of the switching regulator according to the present invention will be described in detail based on the above points to be improved.

  FIG. 5 is a diagram showing a characteristic configuration of the switching regulator according to the present invention. The configuration of this figure is substantially the same as that of FIG. 1, and is characterized in that a reference voltage control circuit 14 is provided in the control signal generation circuit 1 instead of the reference voltage source 11. Therefore, the same components as those described above are denoted by the same reference numerals as those in FIG. 1, and redundant description is omitted. Hereinafter, the configuration and operation of the reference voltage control circuit 14 will be described mainly. To do.

The reference voltage control circuit 14 is means for monitoring the output voltage V _O and variably controlling the reference voltage V _REF so that the voltage level matches the desired target voltage V _TARGET . In the example of FIG. An amplifier AMP2 that amplifies the difference between the output voltage V _O input to the inverting input terminal (−) and the target voltage V _TARGET input to the non-inverting input terminal (+) to generate the reference voltage V _REF It is set as the composition which consists of.

Here, as shown in FIG. 6, the amplifier AMP2 operates so as to lower the reference voltage V _REF when the output voltage V _O is higher than the target voltage V _TARGET , and conversely, the output voltage V _O becomes equal to the target voltage V _TARGET. When the voltage is lower than the threshold voltage, the reference voltage VREF is increased.

Thus, instead of directly inputting the target voltage V _TARGET to the comparator 10, the amplifier AMP2 is used to generate the reference voltage V _REF corresponding to the difference between the output voltage V _O and the target voltage V _TARGET, and By adopting a configuration for inputting to the comparison unit 10, the state of the output voltage V _O is always monitored, and when the output voltage V _O decreases, the reference voltage V _REF is raised, and conversely, the output voltage V _O increases. Since the reference voltage V _REF can sometimes be lowered, even if the ripple voltage ΔV generated in the output voltage V _O increases or decreases due to input fluctuations or load fluctuations, the output voltage V _O can be set to the target voltage without depending on this. It becomes possible to match V _TARGET .

7 and 8 are diagrams showing the relationship between the coil current I _L and the output voltage V _O , respectively. FIG. 7 shows the behavior when the input voltage V _IN is 6 [V], and FIG. 8 shows the behavior when the input voltage V _IN is 13.2 [V]. The solid line in both figures shows the behavior in the case of performing variable control of the reference voltage V _REF, the dashed line in both figures shows the behavior of the case without the variable control of the reference voltage VREF.

In each of FIGS. 7 and 8, as can be seen from the comparison solid and dashed lines, in the case of performing variable control of the reference voltage V _REF, without depending on load variation (variation of the coil current I _L), the output voltage It can be seen that V _O is maintained substantially at the target voltage V _TARGET (in the example of FIGS. 7 and 8, in the vicinity of 0.8 [V]). Further, as can be seen from a comparison between FIGS. 7 and 8, when the variable control of the reference voltage V _REF is performed, the output voltage V _{O is} almost the same regardless of the input fluctuation (the fluctuation of the input voltage V _IN ). It can be seen that the target voltage V _TARGET is maintained (around 0.8 [V] in the examples of FIGS. 7 and 8).

In the above-described embodiment, the switching regulator having the bootstrap DC-DC converter has been described. However, as a matter of course, the present invention can also be applied to a switching regulator having a DC-DC converter having another configuration. . Moreover, in the said embodiment, although the Zener diode 5 and the capacitor | condenser 6 are used as a bootstrap means, the structure of this invention is not limited to this. If the ON period T _ON is not affected, the comparator 10 may have hysteresis characteristics.

  In addition to the above embodiment, the configuration of the present invention can be variously modified without departing from the gist of the invention.

For example, in the above embodiment, a configuration in which the reference voltage control circuit 14 is formed by using the amplifier AMP2 that amplifies the difference between the output voltage V _O and the target voltage V _TARGET to generate the reference voltage V _REF is taken as an example. Although described, the configuration of the present invention is not limited to this. The output voltage V _O is monitored, and the reference voltage V _REF is varied so that the voltage level matches the desired target voltage V _TARGET. Any configuration may be adopted as long as it can be controlled.

  The present invention is a technique useful for achieving both high speed and stable output of a switching regulator.

These are figures which show the basic composition of the switching regulator which concerns on this invention. These are figures which show the example of 1 structure of the control signal generation circuit which the switching regulator of FIG. 1 comprises. These are time charts of voltages or currents of the respective parts of the switching regulator shown in FIG. 1 and the control signal generation circuit shown in FIG. _These are timing charts showing how the _ON period T _ON of the output transistor 3 varies substantially due to load variation. These are figures which show the characteristic structure of the switching regulator which concerns on this invention. FIG. 4 is a waveform diagram showing a relationship among an output voltage V _O , a reference voltage V _REF , a target voltage V _TARGET , and a ripple voltage ΔV generated in the output voltage V _O. Is a diagram showing the relationship between the coil current I _L and the output voltage V _O (input voltage V _IN is low). Is a diagram showing the relationship between the coil current I _L and the output voltage V _O (input voltage V _IN is high).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Control signal generation circuit 2 Driver logic circuit 3, 4 N channel type MOS field effect transistor 5 Zener diode 6 Capacitor 7 Coil 8 Output capacitor 10 Comparator 11 Reference voltage source 12 Flip-flop 13 Pulse control circuit 14 Reference voltage control circuit R1- R5 resistance Q1, Q2 pnp type bipolar transistor Q3 npn type bipolar transistor Q4 N channel type MOS field effect transistor AMP1 high speed amplifier AMP2 amplifier COM1 comparator

Claims (4)

A comparator that compares the output voltage of the switching regulator with a reference voltage;
A flip-flop set by the output of the comparator;
A pulse control circuit that resets the flip-flop when a predetermined on-period elapses after the flip-flop is set;
A reference voltage control circuit that monitors the output voltage and variably controls the reference voltage so that the voltage level matches a desired target voltage;
Comprising
A switching regulator control signal generation circuit that outputs an output pulse of the flip-flop as a control signal of a switching element.   2. The switching regulator control signal generation according to claim 1, wherein the reference voltage control circuit includes an amplifier that amplifies a difference between the output voltage and the target voltage to generate the reference voltage. circuit.   The amplifier operates to lower the reference voltage when the output voltage is higher than the target voltage, and conversely operates to increase the reference voltage when the output voltage is lower than the target voltage. The switching regulator control signal generation circuit according to claim 2, wherein: A DC-DC converter, a control signal generation circuit that generates a control signal according to an output voltage of the DC-DC converter, a driver circuit that drives a switching element in the DC-DC converter based on the control signal, In a switching regulator with
A switching regulator, wherein the control signal generating circuit is the switching regulator control signal generating circuit according to claim 1.

Images