JP2012194276A - Gradation voltage generating circuit and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately prevent deterioration in driving speed even when the same gradation is intensively displayed.SOLUTION: A voltage follower circuit group (2) includes two operational amplifiers (2_1_L to 2_64_L and 2_1_R to 2_64_R) provided for one of reference voltages (γref1 to γref64) generated from a ladder resistor (1). Selection circuits (3_1 to 3_M) in a gradation voltage selection circuit (3) are divided for each of the two operational amplifiers (2_1_L to 2_64_L and 2_1_R to 2_64_R) for one of gradation voltages (γref1 to γref64).

Description

  The present invention relates to a gradation voltage generating circuit and a display device using the same.

  2. Description of the Related Art In recent years, active matrix type liquid crystal panels using TFTs (Thin Film Transistors), which are becoming smaller and higher in definition, are required to display images with abundant colors and high image quality due to multi-gradation. In order to satisfy such a requirement, the gradation voltage is corrected according to the gamma characteristic, and a signal line (also referred to as a source line or a data line) of the liquid crystal panel is driven by the corrected gradation voltage. The correction of the gradation voltage is generally performed by a gradation voltage generation circuit including a ladder resistor configured by connecting a plurality of resistors in series.

  FIG. 14 is a diagram showing a configuration of a conventional gradation voltage generation circuit (reference power supply circuit) disclosed in Patent Document 1. In FIG. 14 includes a resistor string (ladder resistor) in which a plurality of resistors R1A to R3A are connected in series, a constant current source IG connected to one end of the resistor string, and the resistor string. And a plurality of operational amplifiers OP1A to OP4A that respectively generate reference voltages V1A to V4A in response to potentials at connection points of the resistors of the resistor string. Yes.

  For the upper bit group of the image data DATA, a voltage corresponding to the upper bit group is selected from a plurality of types of reference voltages. For the lower bit group of the image data DATA, a staircase voltage is added to a plurality of types of reference voltages, and a voltage corresponding to the lower bit group is selected from each voltage value, and the selected voltage is applied to the data line. The distribution capacity is maintained.

JP-A-6-95623

  The configuration of Patent Document 1 has the following problems. First, when the gradation voltage of the lower bit is charged to the pixel capacitance of the liquid crystal panel, it is necessary to switch the gradation voltage of the lower bit in time series after the gradation voltage of the upper bit is determined. There is a problem that the speed deteriorates. Second, since one of the plurality of gradation voltages output from the plurality of operational amplifiers provided for each gradation voltage is selected and supplied to the liquid crystal panel, When one gradation voltage is continuously selected in a concentrated manner, all signal lines of the liquid crystal panel are driven by one operational amplifier. As a result, the deterioration of the driving speed becomes more remarkable. Third, it is necessary to adjust the timing in consideration of the operation of the entire liquid crystal display device (liquid crystal panel, scanning line driving circuit), and this cannot necessarily be a realistic system. Fourthly, since the gradation voltage for the lower bits depends on the voltage of the staircase voltage generation source constituted by the transistors, there is a drawback that the accuracy varies due to a change in temperature or the like.

  An object of the present invention is to solve the above-described problems, and is a gradation capable of appropriately eliminating the deterioration of the driving speed even when the gradation being displayed is concentrated on one. A voltage generation circuit and a display device using the voltage generation circuit are provided.

  In order to solve the above-described problem, a gradation voltage generation circuit according to one aspect of the present invention provides a gradation of image data by dividing a voltage between a high potential side power source and a low potential side power source. A ladder resistor configured by connecting a plurality of resistors in series so as to generate a plurality of reference voltages corresponding to the reference voltage, and a predetermined number of voltage follower circuits of two or more input reference voltages each having the gradation Voltage follower circuit units that output voltage as voltage follower circuit groups provided for each of the plurality of reference voltages, and the predetermined number of selection circuit groups respectively corresponding to the predetermined number of voltage follower circuits of the voltage follower circuit unit And the predetermined number of selection circuit groups each include the voltage follower circuit unit. Each of the selection circuits receives the gradation voltage output from the voltage follower circuit corresponding to the selection circuit group to which the selection circuit group belongs, and receives the image data. Thus, one gradation voltage corresponding to the gradation of the image data is selected from the gradation voltages corresponding to the plurality of reference voltages and output.

  In the gradation voltage generation circuit, the voltage follower circuit may be configured by an operational amplifier in which an output terminal is connected to an inverting input terminal and the reference voltage is input to a non-inverting input terminal.

  According to this configuration, the voltage follower circuit group is configured such that two or more predetermined number of voltage follower circuit units are provided for each reference voltage generated by the ladder resistor. The gradation voltage generation circuit includes a predetermined number of selection circuit groups corresponding to a predetermined number of voltage follower circuits, and the predetermined selection circuit group includes a selection circuit corresponding to a voltage follower circuit unit. For this reason, even when a certain gradation is selected in a concentrated manner during display on the display panel, the load is distributed and driven by a predetermined number of voltage follower circuit units and a predetermined number of selection circuit groups. It will be possible to eliminate the speed degradation.

  In the gradation voltage generation circuit, a correction reference selection circuit for selecting the reference voltage input to the voltage follower circuit to be corrected, and a correction for selecting the gradation voltage output from the voltage follower circuit to be corrected A target selection circuit; a comparator that compares the reference voltage selected in the correction reference voltage circuit with the gradation voltage selected in the correction target selection circuit; and a voltage to be corrected based on an output of the comparator A correction control circuit that outputs a correction signal to the follower circuit, and the plurality of voltage follower circuits included in the voltage follower circuit group correct the offset voltage based on the correction signal output from the correction control circuit. It is good also as comprised.

  According to this configuration, when two or more predetermined number of voltage follower circuits are provided for one reference voltage, the offset voltage is corrected to be equal among the predetermined number of voltage follower circuits. become. As a result, display unevenness of the display panel due to the difference in offset voltage among a predetermined number of voltage follower circuits can be eliminated.

  In the gradation voltage generation circuit, the plurality of voltage follower circuits included in the voltage follower circuit group may be configured to have an offset cancel function.

  According to this configuration, when two or more predetermined number of voltage follower circuits are provided for one reference voltage, the offset voltage of each of the predetermined number of voltage follower circuits is cancelled. As a result, display unevenness of the display panel due to the difference in offset voltage among a predetermined number of voltage follower circuits can be eliminated.

  In the gradation voltage generation circuit, an unused gradation voltage is detected during display on the display panel based on the image data input to the plurality of selection circuits, and the detected unused gradation voltage is output. An unused gradation detection circuit for turning off the voltage follower circuit may be provided.

  According to this configuration, the voltage follower circuit that outputs an unused gradation voltage is forcibly turned off during display on the display panel, so that the power consumption of the gradation voltage generation circuit can be reduced.

  In the gradation voltage generation circuit, based on the image data input to the plurality of selection circuits, among the predetermined number of voltage follower circuits of the voltage follower circuit unit, an unused voltage follower circuit being displayed on the display panel And an unused gradation detection circuit that turns off the detected unused voltage follower circuit.

  According to this configuration, among the two or more predetermined number of voltage follower circuits, the unused voltage follower circuit is forcibly turned off during display on the display panel, so that the power consumption of the gradation voltage generation circuit can be reduced. become.

  In order to solve the above problems, a display device according to another aspect of the present invention includes a plurality of pixels arranged in a matrix and a plurality of pixels connected to the plurality of pixels for each column or row. A display panel comprising: a signal line; and a plurality of scanning lines for selecting, for each row or column, a pixel to which the gradation voltage is to be applied among the plurality of pixels, via the plurality of scanning lines A scanning line driving circuit for selecting the pixel, the gradation voltage generating circuit in which the plurality of output terminals are connected to the plurality of signal lines, and a gradation voltage corresponding to the image data are the plurality of pixels. A timing controller that controls output of the grayscale voltage from the plurality of output terminals by the grayscale voltage generation circuit and selection of the pixel by the scanning line driving circuit so as to be applied to It is.

  According to the present invention, it is possible to provide a gradation voltage generation circuit capable of appropriately eliminating the deterioration in driving speed even when gradations being displayed are concentrated on one, and a display device using the gradation voltage generation circuit. be able to.

FIG. 1 is a circuit diagram showing a configuration example of a display device according to Embodiment 1 of the present invention. FIG. 2 is a diagram schematically showing the configuration of each pixel shown in FIG. FIG. 3 is a graph showing the relationship between image data and gradation voltage. FIG. 4 is a block diagram showing a configuration example of the gradation voltage generating circuit according to the first embodiment of the present invention. FIG. 5 is a diagram showing a configuration example of a selection circuit included in the gradation voltage selection circuit shown in FIG. FIG. 6 is a physical layout image diagram of the gradation voltage generating circuit shown in FIG. FIG. 7 is a block diagram showing another configuration example of the gradation voltage generating circuit according to Embodiment 1 of the present invention. FIG. 8 is a circuit diagram showing a configuration example of an operational amplifier with an offset voltage correction function shown in FIG. FIG. 9 is a diagram for explaining a method of correcting the offset voltage by the correction control circuit shown in FIG. FIG. 10 is a block diagram showing another configuration example of the gradation voltage generating circuit according to Embodiment 1 of the present invention. FIG. 11 is a circuit diagram showing a configuration example of an operational amplifier with an offset cancel function shown in FIG. FIG. 12 is a block diagram showing a configuration example of the gradation voltage generating circuit according to Embodiment 2 of the present invention. FIG. 13 is a circuit diagram showing a configuration example of the operational amplifier shown in FIG. FIG. 14 is a diagram showing a configuration of a conventional gradation voltage generation circuit (reference power supply circuit).

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the following description, the same or corresponding elements are denoted by the same reference symbols throughout the drawings, and redundant description thereof is omitted.

(Embodiment 1)
[Display device]
FIG. 1 is a diagram showing a configuration example of a display device according to Embodiment 1 of the present invention. Note that, through all the following embodiments, a liquid crystal display device will be described as an example of a display device according to the present invention, but an active matrix type in which a gradation voltage according to image data is corrected according to a gamma characteristic Any display device may be used. FIG. 2 is a diagram schematically showing the configuration of each pixel shown in FIG. FIG. 3 is a graph showing the relationship between image data and gradation voltage.

  The liquid crystal display device of FIG. 1 includes a liquid crystal panel 100, a backlight 110, a scanning line driving circuit 10, a signal line driving circuit 20, and a timing controller 30. Scanning lines are supplied so that display light is supplied from the backlight 110 to the liquid crystal panel 100 and the display light is transmitted at a transmittance according to image data DATA (gradation data, display data) commanded from the outside. By driving the drive circuit 10 and the signal line drive circuit 20, an image corresponding to the image data DATA is displayed on the liquid crystal panel 100.

  The liquid crystal panel 100 has a structure in which a liquid crystal layer 103 is sandwiched between a counter substrate 101 and an array substrate 102. A deflection plate 105 is disposed on the surface of the array substrate 102 and the counter substrate 101 opposite to the liquid crystal layer 103, and a light distribution film (not shown) is disposed on the surface of the array substrate 102 and the counter substrate 101 on the liquid crystal layer 103 side. Is arranged.

  On the inner surface of the array substrate 102, N × M pixels PIX_ij (i = 1) arranged in a matrix (here, N rows × M columns, where N and M are natural numbers, and so on). N, j = 1 to M), N signal lines Y_i (i = 1 to N) connected to the pixel PIX_ij for each column or row, and a pixel to which the gradation voltage is to be applied among the pixels PIX_ij M scanning lines G_j (j = 1 to M) are selected for selecting each row or column. The scanning line G_j is driven by the scanning line driving circuit 10, and the signal line Y_i is driven by the signal line driving circuit 20.

  In the pixel PIX_ij, a thin film transistor (TFT) W and a pixel electrode PIX are formed at the intersection of the scanning line G_j and the signal line Y_i. The thin film transistor W has a gate connected to one scanning line G_j, a source connected to one signal line Y_i, and a drain connected to the pixel electrode PIX.

  The counter substrate 101 includes a color filter (not shown) disposed on the glass substrate and a common electrode VCOM disposed on the color filter so as to face the pixel electrode PIX of the array substrate 102. A liquid crystal capacitor C (including parasitic capacitance) is formed between the common electrode VCOM and the pixel electrode PIX facing the common electrode VCOM. The transmittance of the pixel PIX_ij is a difference voltage between the gradation voltage (pixel voltage) supplied to the pixel electrode PIX of the array substrate 102 and the common voltage supplied to the common electrode VCOM of the counter substrate 101 in the liquid crystal layer 103. It is controlled according to the applied driving voltage. The common electrode VCOM is connected to a power source for applying a common voltage via a common line (not shown) formed on the counter substrate 101.

  The signal line drive circuit 20 includes a gradation voltage generation circuit 40 and an output circuit 50. The gradation voltage generation circuit 40 generates a plurality of gradation voltages based on a power supply voltage supplied from a power supply circuit (not shown). For example, when the image data DATA per pixel is 6 bits, 64 (= 2 to the sixth power) types of gradation voltages γ1 to γ64 are generated (see FIG. 3). Further, the gradation voltage generation circuit 40 selects one of the plurality of gradation voltages based on the plurality of bits of image data DATA and outputs the selected signal line Y_i to the output circuit 50. The output circuit 50 buffers the grayscale voltage supplied from the grayscale voltage generation circuit 40 for each signal line Y_i, and outputs it to each signal line Y_i. Thereby, each of the plurality of signal lines Y_i is driven.

  The timing controller 30 outputs the grayscale voltage outputs γ1 to γ64 from the grayscale voltage generation circuit 40 and the pixels from the scanning line driving circuit 10 so that the grayscale voltages γ1 to γ64 corresponding to the image data DATA are applied to the pixels PIX_ij. Controls selection of PIX_ij. Specifically, the control signal CTG for sequentially selecting the scanning lines G_1 to G_N every one vertical scanning period (1V) and one line of pixels included in the image data DATA every one horizontal scanning period (1H). A control signal CTY for assigning analog image data DATA for PIX_ij to each of the signal lines Y_1 to Y_M is generated.

  The control signal CTG includes a vertical start signal, which is a pulse generated every one vertical scanning period (1V), and a vertical clock signal, which is a pulse generated for the number of scanning lines G_j in one vertical scanning period (1V). Including. The control signal CTG is supplied from the timing controller 30 to the scanning line driving circuit 10. The control signal CTY includes a horizontal start signal STH which is a pulse generated every horizontal scanning period (1H), a horizontal clock signal CKH which is a pulse generated by the number of signal lines in each horizontal scanning period, and pixels for one line. In order to drive the signal line Y_i corresponding to the image data DATA for PIX_ij, a strobe signal STB which is a pulse generated with a predetermined time delay from the start signal STH every horizontal scanning period (1H), and every horizontal scanning period (1H) and a polarity signal POL for setting the polarity of the pixel voltage with respect to the common voltage VCOM every vertical scanning period (1V). The control signal CTY is supplied from the timing controller 30 to the signal line driving circuit 20 together with the image data DATA. The image data DATA includes gradation data for correcting gradation characteristics (gamma characteristics) of the liquid crystal panel 100.

[Grayscale voltage generator]
FIG. 4 is a block diagram showing a configuration example of the gradation voltage generation circuit according to the first embodiment of the present invention.

  The gradation voltage generation circuit 40 shown in FIG. 4 includes a ladder resistor 1, a voltage follower circuit group 2, and a gradation voltage selection circuit 3. In the example shown in the figure, the image data DATA has 6 bits, and the gradation level has voltage levels corresponding to 64 types of gradations, which is the sixth power of 2.

  The ladder resistor 1 includes 65 resistors R1 to R65 between a high-potential-side power supply VDD and a low-potential-side power supply VSS generated based on a power supply voltage supplied from a power supply circuit (not shown). It is configured to be connected in series. The ladder resistor 1 divides the potential difference between the high-potential-side power supply VDD and the low-potential-side power supply VSS by the resistors R1 to R65, so that the reference voltages γref1 to γref64 are taken out from the connection points of the resistors R1 to R65. . The reference voltage γref1 is the maximum reference voltage, and the reference voltage γref64 is the minimum reference voltage.

  The voltage follower circuit group 2 is provided with a voltage follower circuit unit including two operational amplifiers 2_k_L and 2_k_R (k = 1 to 64) for each of the reference voltages γref1 to γref64 generated by the ladder resistor 1. It is configured. One operational amplifier 2_k_L of the voltage follower circuit unit drives one output terminal group OUT1 to OUT (M / 2). The other operational amplifier 2_k_R of the voltage follower circuit unit drives the other output terminal group OUT (M / 2 + 1) to OUTM.

  Each of the operational amplifiers 2_k_L and 2_k_R is configured to function as a so-called voltage follower circuit. That is, the operational amplifiers 2_k_L and 2_k_R receive the reference voltages γref1 to γref64 from the ladder resistor 1 and perform impedance conversion while maintaining the voltage so that they can be driven without loss even if the input impedance of the external load is low. It is configured to output γ1 to γ64. Note that the two voltage follower circuits of the voltage follower circuit unit may be configured by a transistor amplifier circuit such as a source follower in addition to the operational amplifier.

  The gradation voltage selection circuit 3 is configured such that one selection circuit (3_1 to 3_M) is provided for each of the output terminals OUT1 to OUTM corresponding to the number of signal lines Y_i. The selection circuits 3_1 to 3_M are configured to select only one voltage to be applied to the pixels PIX_ij connected to the output terminals OUT1 to OUTM from the gradation voltages γ1 to γ64. Specifically, the selection circuits 3_1 to 3_M receive the gradation voltages γ1 to γ64 from the voltage follower circuit group 2 and the 6-bit image data DATA from the timing controller 30, and the 6-bit image data DATA. Is selected and output from the gradation voltages γ1 to γ64 based on the decoded result.

  The selection circuits 3_1 to 3_M included in the gradation voltage selection circuit 3 include one selection circuit group 3_1 to 3_ (M) to which one gradation voltage γLk output from one operational amplifier 2_k_L in the voltage follower circuit unit is input. / 2) and the other selection circuit groups 3_ (M / 2 + 1) to 3M to which the other gradation voltage γRk output from the other operational amplifier 2_k_R is input.

  FIG. 5 is a diagram showing a configuration example of one selection circuit 3_1 included in the gradation voltage selection circuit 3 shown in FIG. The other selection circuits 3_2 to 3_M have the same configuration.

  The selection circuit 3_1 is configured by arranging a switch formed of a P-type transistor or an N-type transistor so as to realize a so-called tournament-type selection algorithm. Here, the tournament method selection algorithm is to repeatedly select two adjacent gradation voltages from among 64 gradation voltages based on the bit value of the image data DATA. Thus, it means an algorithm in which one gradation voltage is finally selected. “L: ON” in FIG. 5 represents a P-type transistor that is turned on when the corresponding bit of the image data DATA is Low (= 0) and is turned off when the corresponding bit is High (= 1). Yes. “H: ON” in FIG. 5 represents an N-type transistor that is turned on when the corresponding bit of the image data DATA is High (= 1) and turned off when the corresponding bit is Low (= 0). Yes. For example, when the 6-bit image data DATA is “111111”, all the switches are turned on in the path from 64 input terminals γ1 to γ64 to one output terminal OUT1. There is only a path from γ64 to the output terminal OUT1. In this case, the selection circuit 3_1 selects the gradation voltage γ64 input to the input terminal 64 and outputs it from the output terminal OUT1.

  Next, an outline of the operation of the gradation voltage generating circuit shown in FIG. 4 will be described. For example, assume that a load capacitance of 50 pF is connected to each of the output terminals OUT1 to OUTM. In this case, if each pixel connected to each of the output terminals OUT1 to OUTM selects the same gradation voltage, a single operational amplifier drives a load capacitance of 50 pF × M, and the convergence time of the operational amplifier output is prolonged. There is a risk. Therefore, as described above, by preparing two operational amplifiers 2_k_L and 2_k_R (k = 1 to 64) for each of the reference voltages γrefk (k = 1 to 64), a load driven by one operational amplifier. The capacitance will be halved from 50 pF × M to 50 pF × (M / 2). Thereby, it is possible to improve the lengthening of the convergence time of the operational amplifier output.

  FIG. 6 is a physical layout image diagram of the grayscale voltage generation circuit shown in FIG. As shown in FIG. 6, the signal line driving circuit 20 of the liquid crystal display device is arranged so that the arrangement direction of the output terminals OUT <b> 1 to OUTM is the longitudinal direction of the signal line driving circuit 20. For this reason, as the distance from the operational amplifiers 2_k_L, 2_k_R to the output terminals OUT1 to OUTM increases, not only the load capacity increases, but also the area increases due to wiring. That is, it is preferable that the distances from the operational amplifiers 2_k_L and 2_k_R to the output terminals OUT1 to OUTM be as short as possible. Therefore, as described above, when two operational amplifiers 2_k_L and 2_k_R are provided for each of the reference voltages γrefk, as shown in FIG. 6, one of the output terminal groups OUT1 to OUT (M / 2) is in the vicinity. By arranging the operational amplifier 2_k_L and arranging the other operational amplifier 2_k_R in the vicinity of the other output terminal groups OUT (M / 2 + 1) to OUTM, the distance from the operational amplifiers 2_k_L, 2_k_R to the output terminals OUT1 to OUTM is substantially reduced. Can be shortened.

[Correction of offset voltage due to operational amplifier load distribution]
As described above, when one grayscale voltage is driven by two operational amplifiers, a difference in offset voltage between the two operational amplifiers appears as a difference in grayscale voltage, which may cause display unevenness. Therefore, an offset voltage correction function is added to each operational amplifier to take measures to reduce the operational amplifier offset itself.

  FIG. 7 shows another configuration example of the grayscale voltage generation circuit according to the first embodiment of the present invention, that is, a configuration in which an offset correction function is added to the voltage follower circuit group 2 of the grayscale voltage generation circuit shown in FIG. It is the block diagram which showed the example. FIG. 8 is a circuit diagram showing a configuration example of the operational amplifier with the offset voltage correction function shown in FIG.

  First, the structure of the operational amplifier 2_1_L_C with an offset voltage correction function illustrated in FIG. 8 is described. Note that an operational amplifier 2_1_L_C illustrated in FIG. 8 represents one of the operational amplifiers 2_k_L_C illustrated in FIG. 7, and each of the operational amplifiers 2_k_R_C illustrated in FIG. 7 has the same configuration.

  A correction signal line 71 that connects between the output terminal of the correction control circuit 7 and a predetermined input terminal of the operational amplifiers 2_k_L_C and 2_k_R_C is a signal line that transfers digital data of a plurality of bits. Here, 3 bits are used as an example. The correction voltage line 72 connecting the output terminal of the correction control circuit 7 and the predetermined input terminals of the operational amplifiers 2_k_L_C and 2_k_R_C is a voltage line that transmits two or more analog signals having different voltage values. It is. If the correction signal line 71 is 3 bits, the number of correction voltage lines 72 is 8 which is the cube of 2.

  The operational amplifier 2_1_L_C includes a storage circuit 8, a correction voltage selection circuit 9, a correction current supply unit 2U, a differential amplification unit 2S, and an output unit 2O.

  The storage circuit 8 is configured to take in 3-bit digital data transferred from the correction control circuit 7 via the correction signal line 71 and store it.

  The correction voltage selection circuit 9 selects one of eight analog voltages transmitted from the correction control circuit 7 via the correction voltage line 72 according to the digital data stored in the storage circuit 8, Based on the selected analog voltage, the correction differential input voltages P and N are applied to the gates of the correction transistors M21 and M22 of the correction current supply unit 2U.

  The correction current supply unit 2U supplies the correction currents I1 and I2 to each of the two current paths in the differential amplification unit 2S based on the correction differential input voltages P and N supplied from the correction voltage selection circuit 9. It is configured as follows. Specifically, the correction current supply unit 2U supplies the correction current I1 corresponding to the voltage value of the correction differential input voltage N to the drain of the differential transistor M1 of the differential amplification unit 2S, and The correction current I2 corresponding to the voltage value of the correction differential input voltage P is supplied to the drain of the differential transistor M2 of the differential amplifier 2S. Here, “supplying current” means including both “discharge current” and “suck current”.

  In the above configuration, the offset voltage of the operational amplifier 2_1_L_C can be canceled by adjusting the difference between the corrected differential input voltages P and N. Specifically, when the gradation voltage γL1 is larger than the reference voltage γref1 by ΔV, the corrected differential input voltage P may be set to a voltage value smaller than the corrected differential input voltage N by ΔV. Similarly, when the gradation voltage γL1 is smaller than the reference voltage γref1 by ΔV, the corrected differential input voltage P may be set to a voltage value larger than the corrected differential input voltage N by ΔV. The voltage values of the corrected differential input voltages P and N may be arbitrary values as long as they are within a voltage range in which the correction transistors M21 and M22 can operate (for example, greater than or equal to the transistor threshold voltage). In this way, the operational amplifier 2_1_L_C outputs the output voltage (grayscale voltage γL1) according to the analog voltage of the correction voltage line 72 selected based on the digital data of the correction signal line 71 set so that the offset voltage is minimized. ) Can be corrected.

  Next, the configuration of the gradation voltage generating circuit shown in FIG. 7 will be described.

  The gradation voltage generation circuit shown in FIG. 7 is obtained by adding a correction reference selection circuit 4, a correction target selection circuit 5, a comparator 6, and a correction control circuit 7 to the configuration shown in FIG. Furthermore, the operational amplifiers 2_k_L_C and 2_k_R_C included in the voltage follower circuit group 2C are configured to have a function of correcting the offset voltage as shown in FIG.

  The correction reference selection circuit 4 is configured to select a reference voltage γrefk that is an input voltage of the operational amplifiers 2_k_L_C and 2_k_R_C, and supply the reference voltage γrefk to one input terminal of the comparator 6 via the correction reference line 41. Yes.

  The correction target selection circuit 5 selects the gradation voltages γLk and γRk output from the operational amplifiers 2_k_L_C and 2_k_R_C, and supplies the gradation voltages γLk and γRk to the other input terminal of the comparator 6 via the correction target line 51. It is configured to supply.

  The comparator 6 compares the reference voltage γrefk supplied via the correction reference line 41 with the gradation voltages γLk and γRk supplied via the correction target line 51, and the gradation voltages γLk and γRk are compared with the reference voltage. If it is higher than γrefk, a high level signal is output to the correction control circuit 7 via the comparator output line 61, and if the gradation voltages γLk and γRk are lower than the reference voltage γrefk, the low level is output via the comparator output line 61. Is output to the correction control circuit 7.

  The correction control circuit 7 transfers digital data for correction via the correction signal line 71 to each of the operational amplifiers 2_k_L_C and 2_k_R_C based on the signal supplied from the comparator 6 via the comparator output line 61 and performs correction. The correction analog voltage is transmitted via the voltage line 72.

  Next, the offset voltage correcting operation of the gradation voltage generating circuit shown in FIG. 7 will be described with reference to FIG. FIG. 9 is a diagram for explaining a correction method of the offset voltage by the correction control circuit shown in FIG.

  The correction control circuit 7 controls the correction reference selection circuit 4 and the correction target selection circuit 5 through the first control line 73 and the second control line 74 in order to correct the offset voltage of the operational amplifier 2_1_L_C as follows. To do.

  First, the correction control circuit 7 sets the digital data to be transferred via the correction signal line 71 to 3′h0 (“0” in hexadecimal notation with a 3-bit width). As shown in FIG. 9, the operational amplifier 2_1_L_C outputs the voltage A as the gradation voltage γL1. At this time, the voltage input from the correction target selection circuit 5 to the comparator 6 via the correction target line 51 is the voltage A.

  Next, the comparator 6 compares the reference voltage γref1 supplied from the correction reference selection circuit 4 with the voltage A supplied from the correction target selection circuit 5. Here, since the voltage A is lower than the reference voltage γref1, the comparator 6 outputs a low level signal to the correction control circuit 7 via the comparator output line 61.

  Next, since the signal supplied from the comparator 6 via the comparator output line 61 is at the low level, the correction control circuit 7 outputs the digital data transferred via the correction signal line 71 to 3′h1 (with a 3-bit width). Increment to "1") in hexadecimal notation. Then, as illustrated in FIG. 9, the operational amplifier 2_1_L_C outputs the voltage B as the gradation voltage γL1. At this time, the voltage input from the correction target selection circuit 5 to the comparator 6 via the correction target line 51 is the voltage B.

  Next, the comparator 6 compares the reference voltage γref1 supplied from the correction reference selection circuit 4 with the voltage B supplied from the correction target selection circuit 5. Here, since the voltage B is lower than the reference voltage γref1, the comparator 6 outputs a low level signal to the correction control circuit 7 via the comparator output line 61.

  Next, since the signal supplied from the comparator 6 via the comparator output line 61 is at the low level, the correction control circuit 7 outputs the digital data transferred via the correction signal line 71 to 3′h2 (with a 3-bit width). Increment to "2") in hexadecimal notation. Then, as illustrated in FIG. 9, the operational amplifier 2_1_L_C outputs the voltage C as the gradation voltage γL1. At this time, the voltage input from the correction target selection circuit 5 to the comparator 6 via the correction target line 51 is the voltage C.

  Next, the comparator 6 compares the reference voltage γref1 supplied from the correction reference selection circuit 4 with the voltage C supplied from the correction target selection circuit 5. Here, since the voltage C is higher than the reference voltage γref1, the comparator 6 outputs a high level signal to the correction control circuit 7 via the comparator output line 61.

  Next, since the signal supplied from the comparator 6 via the comparator output line 61 is at a high level, the correction control circuit 7 performs control so that the storage circuit 8 of the operational amplifier 2_1_L_C continues to hold 3′h2 of the digital data. To do.

  In this way, correction is performed so that the offset voltage of the operational amplifier 2_1_L_C becomes small. The offset voltage is similarly corrected for all other operational amplifiers. As a result, the difference between the offset voltages of the two operational amplifiers provided for one gradation voltage for load distribution is canceled, and as a result, the occurrence of display unevenness is suppressed.

[Adoption of operational amplifier with offset cancel function]
10 shows another configuration of the gradation voltage generating circuit according to the first embodiment of the present invention, that is, the operational amplifiers 2_k_L_C and 2_k_R_C (k = 1 to M) added with the offset voltage correction function shown in FIG. A configuration example is shown in which the operational amplifiers 2_k_L_D and 2_k_R_D (k = 1 to M) with a cancel function are replaced, and the correction control circuit 7, the correction reference selection circuit 4, the correction target selection circuit 5, and the comparator 6 shown in FIG. 7 are omitted. It is a block diagram. FIG. 11 is a circuit diagram illustrating a configuration example of the operational amplifiers 2_k_L_D and 2_k_R_D with an offset cancel function illustrated in FIG. As described above, even when the operational amplifiers 2_k_L_D and 2_k_R_D with the offset cancel function are employed, the same effect as that obtained when the operational amplifiers 2_k_L_C and 2_k_R_C to which the offset voltage correction function is added is obtained.

[Modification]
The voltage follower circuit group 2 includes a plurality of reference voltages γref <b> 1 generated by the ladder resistor 1, and voltage follower circuit units, each of which outputs the reference voltage as a gradation voltage by a predetermined number of two or more voltage follower circuits. What is necessary is just to prepare for every (gamma) ref64. That is, the voltage follower circuit unit is not limited to a configuration including two voltage follower circuits, and may be configured to include three or more voltage follower circuits.

  The gradation voltage selection circuit 3 may include a predetermined number of selection circuit groups respectively corresponding to the predetermined number of voltage follower circuits of the voltage follower circuit unit. That is, the gradation voltage selection circuit 3 may include a predetermined number of selection circuit groups in correspondence with a predetermined number of voltage follower circuits included in the voltage follower circuit unit.

(Embodiment 2)
FIG. 12 is a block diagram showing a configuration example of the gradation voltage generating circuit according to the second embodiment of the present invention. The gradation voltage generation circuit shown in FIG. 12 is obtained by adding an unused gradation detection circuit 11 to the gradation voltage generation circuit shown in FIG. In the present embodiment, paying attention to the fact that a quiescent current continues to flow even in an operational amplifier that has no gradation display and is in a drive stop state, the unused gradation detection circuit 11 is displayed when the liquid crystal panel 100 is displayed. Detects an unused gradation and forcibly turns off an operational amplifier corresponding to the detected unused gradation. As a result, the power consumption of the gradation voltage generating circuit can be reduced.

  Specifically, the unused gradation detection circuit 11 receives the image data 1 to M of each output terminal OUT1 to OUTM as a 6-bit digital signal in time series via the image data bus [5: 0]. Is configured to do. In addition, the unused gradation detection circuit 11 decodes the content of the 6-bit digital signal received in time series, and corresponds to a certain gradation that has never been selected when the liquid crystal panel 100 is displayed. High-level amplifier off signals are output to the operational amplifiers 2_k_L and 2_k_R (k = 1 to M). In order to detect a gray scale that has never been selected during display, for example, a single flip-flop (hereinafter referred to as FF) is provided for every gray scale, and the FF has a corresponding gray scale level. Is selected even once, a high level flag (amplifier off signal) is held.

  The operational amplifiers 2_k_L and 2_k_R are configured to stop driving when a high-level amplifier off signal is input from the unused gradation detection circuit 11. FIG. 12 is a circuit diagram illustrating a configuration example of the operational amplifiers 2_k_L and 2_k_R. As shown in FIG. 12, the operational amplifiers 2_k_L and 2_k_R include P-type transistors P1 and P2 that form a current mirror, and N-type transistors N1 and N2 provided on the current discharge side of the current mirror as differential amplifiers. And an N-type transistor N3 connected in common with the N-type transistors N1 and N2. Further, the operational amplifiers 2_k_L and 2_k_R include a P-type transistor P3 and an N-type transistor N4 connected in series as their output units.

  When two or more operational amplifiers are provided for one reference voltage using the newly provided unused gradation detection circuit 11 as in the first embodiment, the unused one of the two or more operational amplifiers is not used. It is also possible to detect the used operational amplifier and forcibly turn off the unused operational amplifier. Thereby, the power consumption of the gradation voltage generating circuit can be further reduced.

  From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

  The gradation voltage circuit and the display device using the same according to the present invention are particularly useful for a liquid crystal display device used in an electronic device such as a notebook personal computer that is required to be compact and have high performance.

DESCRIPTION OF SYMBOLS 10 ... Scanning line drive circuit 20 ... Signal line drive circuit 30 ... Timing controller 40 ... Gradation voltage generation circuit 50 ... Output circuit 100 ... Liquid crystal panel 101 ... Counter substrate 102 ... Array substrate 103 ... Liquid crystal layer 105 ... Deflection plate 110 ... Back Lights OUT1 to OUTM: Output terminals OUT1 to OUT (M / 2): One output terminal group OUT (M / 2) to OUT (M / 2 + 1): The other output terminal group Y_1 to Y_N: Signal lines G_1 to G_N Scanning line 12_D1 ... gradation voltage generator 1 ... ladder resistors R1 to R65 ... frequency dividing resistors γref1 to γref64 ... reference voltages 2, 2B, 2C ... voltage follower circuit group 3 ... gradation voltage selection circuits γL1 to γL64 ... Gradation voltages γR1 to γR64 ... the other gradation voltages 3_1 to 3_M ... selection circuits 3_1 to 3_ (M / 2) ... one selection circuit group 3_ (M / 2 + 1) to 3M ... the other selection circuit group 3_D1 ... switch circuit 2_1_L to 2_64_L ... one operational amplifier 2_1_L_C to 2_64_L_C of the voltage follower circuit unit ... the operational amplifier 2_1_L_D to 2_64_L_D with the offset voltage correction function added Operational amplifier 2_1_R to 2_64_R with the other operational amplifier 2_1_R_C to 2_64_R_C with operational amplifier 2_1_R_D to 2_64_R_D with the offset voltage correction function ... Operational amplifier 2U with offset canceling function ... Correction unit 2O ... Output unit 2S ... Differential amplification Unit 4 ... Correction reference selection circuit 41 ... Correction reference line 5 ... Correction target selection circuit 51 ... Correction target line 6 ... Comparator 61 ... Comparator Over data output lines 7 correction control circuit 71 ... correction signal line 72 ... correction voltage line 73 ... control line 74 ... control line 8 ... storage circuit 9 ... correction voltage selection circuit 11 ... Unused tone detector

Claims (7)

A ladder resistor configured by connecting a plurality of resistors in series so as to generate a plurality of reference voltages corresponding to the gradation of image data by dividing each voltage between a high potential side power source and a low potential side power source. When,
A voltage follower circuit group including, for each of the plurality of reference voltages, a voltage follower circuit unit that outputs, as the gradation voltage, a predetermined number of two or more voltage follower circuits that input the reference voltage;
A gradation voltage selection circuit comprising the predetermined number of selection circuit groups respectively corresponding to the predetermined number of voltage follower circuits of the voltage follower circuit unit;
Each of the predetermined number of selection circuit groups includes a selection circuit corresponding to the voltage follower circuit unit;
Each selection circuit receives the gradation voltage output from the voltage follower circuit corresponding to the selection circuit group to which the selection circuit belongs, and also receives the image data to correspond to the gradation of the image data. A gradation voltage generation circuit configured to select and output one gradation voltage from among gradation voltages corresponding to the plurality of reference voltages.   The gradation voltage generation circuit according to claim 1, wherein the voltage follower circuit includes an operational amplifier in which an output terminal is connected to an inverting input terminal and the reference voltage is input to a non-inverting input terminal. A correction reference selection circuit that selects the reference voltage input to the voltage follower circuit to be corrected;
A correction target selection circuit for selecting the gradation voltage output from the voltage follower circuit to be corrected;
A comparator that compares the reference voltage selected in the correction reference voltage circuit with the gradation voltage selected in the correction target selection circuit;
A correction control circuit that outputs a correction signal to the voltage follower circuit to be corrected based on the output of the comparator,
The gradation according to claim 1, wherein the plurality of voltage follower circuits included in the voltage follower circuit group is configured to correct an offset voltage based on the correction signal output from the correction control circuit. Voltage generation circuit.   The gradation voltage generation circuit according to claim 1, wherein the plurality of voltage follower circuits included in the voltage follower circuit group are configured to have an offset cancel function.   Based on the image data input to the plurality of selection circuits, an unused gradation voltage is detected during display on the display panel, and the voltage follower circuit that outputs the detected unused gradation voltage is turned off. The grayscale voltage generation circuit according to claim 1, further comprising an unused grayscale detection circuit.   Based on the image data input to the plurality of selection circuits, an unused voltage follower circuit is detected during display on the display panel among the predetermined number of voltage follower circuits of the voltage follower circuit unit. The gradation voltage generation circuit according to claim 1, further comprising an unused gradation detection circuit that turns off the used voltage follower circuit. A plurality of pixels arranged in a matrix, a plurality of signal lines connected to the plurality of pixels for each column or row, and a pixel to which the gradation voltage is applied among the plurality of pixels are arranged in rows or columns. A display panel comprising a plurality of scanning lines for selecting each;
A scanning line driving circuit for selecting the pixel through the plurality of scanning lines;
The gradation voltage generation circuit according to claim 1, wherein the plurality of output terminals are respectively connected to the plurality of signal lines.
The gradation voltage output from the plurality of output terminals by the gradation voltage generation circuit and the pixel by the scanning line driving circuit so that the gradation voltage corresponding to the image data is applied to the plurality of pixels. And a timing controller for controlling selection of the display device.

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