JP2012191671A - Output buffer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output buffer circuit that suppresses increases in the area, volume and number of components of output buffers and improves drive capability.SOLUTION: In an output buffer circuit 1 having a first input path 4a for transmitting a first drive signal LIN, a second input path 4b for transmitting a second drive signal RIN, a first output buffer 6a corresponding to the first input path 4a, and a second output buffer 6b corresponding to the second input path 4b, input path switching means 8 electrically connects the first input path 4a to the first output buffer 6a and second output buffer 6b in a monaural mode out of stereo and monaural modes, and output path switching means 10 electrically connects the first output buffer 6a and second output buffer 6b to a first load 2a corresponding to the first input path 4a and first output buffer 6a.

Description

  The present invention relates to an output buffer circuit that performs multi-channel signal processing using a C-MOS digital integrated circuit.

In general, an output buffer circuit, particularly an output buffer circuit that performs multi-channel signal processing using a C-MOS digital integrated circuit (hereinafter referred to as “C-MOSIC”), depends on the application and load. In some cases, it is necessary to increase the drive capacity. The “drive ability” is an ability to drive a load such as a speaker.
As a method of increasing the drive capability of the output buffer circuit, for example, there is a method of reducing the output impedance of the output buffer circuit by increasing the area, volume, and number of parts of the output buffer provided in the output buffer circuit. In this case, the output voltage of the output buffer circuit increases in accordance with the reduction of the output impedance, so that the maximum output current of the output buffer circuit increases.

Also, a method has been proposed for dealing with a case where the output load characteristic changes depending on the application, as described in Patent Documents 1 and 2, for example, with a single output buffer circuit.
In these methods, the configuration of the output buffer circuit is configured to include a plurality of output buffers that can be selected and added by a control signal in addition to the normally used output buffer. Then, as necessary, a plurality of output buffers are selected and added as needed by a control signal in addition to the output buffers normally used. As a result, the drive capability of the output buffer circuit is varied.
JP-A-5-226948 Japanese Patent Laid-Open No. 5-268050

By the way, in an output buffer circuit, particularly an output buffer circuit used for reproduction of an audio signal, there is a demand for increasing the maximum output power as much as possible according to the output state of the audio signal. In addition to this, there is also a demand to reduce the mounting area of the output buffer in order to reduce the board area and reduce the board cost.
Therefore, there is a trade-off relationship between the increase in drive capability and the area / volume / number of parts of the output buffer. In particular, when the load required for the output buffer circuit is large, the area occupied by the output buffer is larger than that of other circuit elements arranged on the substrate. It appears more prominently. This is because when the area of the output buffer is increased in response to a request to increase the drive capability, it is necessary to increase the area of the output buffer in accordance with an increase in the load required for the output buffer circuit.
The present invention has been made paying attention to the above-described problems, and is capable of suppressing an increase in the area, volume, and number of parts of the output buffer and improving the drive capability of the output buffer circuit. It is an object to provide a circuit.

In order to solve the above-described problems, the invention described in claim 1 is a plurality of input paths that respectively transmit a plurality of drive signals, and a plurality of input paths that correspond to the input paths. An output buffer circuit comprising: an output buffer;
Each of the plurality of output buffers includes a control unit that is electrically connected to the input path, and an output unit that has a one-to-one correspondence with the control unit and that is electrically connected to the control unit. ,
A plurality of output units including a first input path connection mode for electrically connecting the control unit and the output unit included in the same output buffer, and one of the control units and the output unit corresponding to the control unit And an input path switching unit for switching between the second input path connection mode and the second input path connection mode.

  According to the present invention, by electrically connecting one of the control units and a plurality of output units including the output unit corresponding to the control unit, one type of drive signal transmitted by one of the control units Can be amplified at the output section.

  According to the present invention, since it becomes possible to amplify the drive signal using an output buffer that does not receive the corresponding drive signal input, an increase in the area, volume, and number of parts of the output buffer is suppressed, and output is also achieved. It becomes possible to improve the drive capability of the buffer circuit.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
First, a first embodiment of the present invention will be described with reference to the drawings.
(Constitution)
First, the configuration of the present embodiment will be described with reference to FIGS. 1 and 2.
1 and 2 are diagrams showing the configuration of the output buffer circuit 1 of the present embodiment.
As shown in FIG. 1 and FIG. 2, the output buffer circuit 1 is a stereo speaker reproduction circuit, and responds to an input signal from an input device (such as a microphone) outside the figure by BTL (Balanced Transformer-Less) connection. Thus, the first load 2a and the second load 2b are driven. In the present embodiment, a case will be described in which the first load 2a and the second load 2b are speakers. Also, a case will be described in which the first load 2a is an Lch (left channel) speaker and the second load 2b is an Rch (right channel) speaker among the first load 2a and the second load 2b.

  Moreover, in the following description, the case where both the first load 2a and the second load 2b are driven is described as “stereo mode”, and only the first load 2a among the first load 2a and the second load 2b is described. The case of driving will be described as “monaural mode”. 1 is a diagram illustrating a state of the output buffer circuit 1 in the stereo mode, and FIG. 2 is a diagram illustrating a state of the output buffer circuit 1 in the monaural mode.

Here, advantages of the BTL connection will be described.
In general, the maximum amplitude of a signal is limited by the power supply voltage of the output buffer circuit 1. However, when audio is output from the first load 2a and the second load 2b by the BTL connection, the first load 2a and the second load 2b are driven by driving the first load 2a and the second load 2b with a plus / minus balanced signal. There is an advantage that it is possible to obtain a maximum amplitude of about twice at the end of 2b. Further, the common-mode noise riding on the balanced signal on the path to the ends of the first load 2a and the second load 2b does not affect the differential signals at the ends of the first load 2a and the second load 2b. There is also an advantage.

Hereinafter, the description returns to the configuration of the output buffer circuit 1.
The output buffer circuit 1 includes four systems of input paths 4a to 4d, four output buffers 6a to 6d, input path switching means 8, and output path switching means 10.
Each of the four input paths 4a to 4d transmits a drive signal input from an input device. In the drawing and the following description, the input path 4a is “first input path 4a”, the input path 4b is “second input path 4b”, the input path 4c is “third input path 4c”, and the input The route 4d will be described as “fourth input route 4d”.

  The first input path 4a transmits a first drive signal (described as “LIN + signal” in the drawing) for driving the first load 2a, and the second input path 4b drives the second load 2b. A second drive signal (denoted as “RIN + signal” in the figure) is transmitted. The third input path 4c transmits a third drive signal (denoted as “LIN-signal” in the drawing) having a phase opposite to that of the first drive signal, and the fourth input path 4d is a second drive signal. And a fourth drive signal (denoted as “RIN-signal” in the figure) having the opposite phase to the above.

  The four output buffers 6a to 6d are provided in one-to-one correspondence with the four input paths 4a to 4d, respectively, amplify the input drive signal, and output from the four external output terminals 12a to 12d. Output. In the drawings and in the following description, the output buffer 6a is “first output buffer 6a”, the output buffer 6b is “second output buffer 6b”, the output buffer 6c is “third output buffer 6c”, and output. The buffer 6d will be described as “fourth output buffer 6d”.

The first output buffer 6a corresponds to the first input path 4a, and the second output buffer 6b corresponds to the second input path 4b. The third output buffer 6c corresponds to the third input path 4c, and the fourth output buffer 6d corresponds to the fourth input path 4d.
The four external output terminals 12a to 12d are provided in one-to-one correspondence with the four output buffers 6a to 6d, respectively. In the drawings and the following description, the external output terminal 12a is referred to as "first external output terminal 12a", the external output terminal 12b is referred to as "second external output terminal 12b", the external output terminal 12c is referred to as "third external output". The “output terminal 12c” and the external output terminal 12d will be described as “fourth external output terminal 12d”.

The first external output terminal 12a corresponds to the first output buffer 6a, and the second external output terminal 12b corresponds to the second output buffer 6b. The third external output terminal 12c corresponds to the third output buffer 6c, and the fourth external output terminal 12d corresponds to the fourth output buffer 6d.
The first external output terminal 12a is electrically connected to the positive (+) pole side of the first load 2a, and the third external output terminal 12c is connected to the negative (−) pole side of the first load 2a. Electrically connected.

On the other hand, the second external output terminal 12b is electrically connected to the positive electrode side of the first load 2a or the positive electrode side of the second load 2b via a first output path switching means 10a described later. The fourth external output terminal 12d is electrically connected to the negative electrode side of the first load 2a or the negative electrode side of the second load 2b via a second output path switching means 10b described later.
Here, the first load 2a corresponds to the first input path 4a and the first output buffer 6a, and the third input path 4c and the third output buffer 6c. The second load 2b corresponds to the second input path 4b and the second output buffer 6b, and the fourth input path 4d and the fourth output buffer 6d.

The input path switching unit 8 includes a first input path switching unit 8a and a second input path switching unit 8b. The first input path switching unit 8a and the second input path switching unit 8b are formed by switching elements, for example.
The first input path switching unit 8a is electrically connected to the first input path 4a and the second input path 4b and the second output buffer 6b in response to a switching control signal input from a mode switching unit (not shown). Is switched to the first input path connection mode or the second input path connection mode.

  In addition, said mode switching part is provided with the switch of a switch type, for example, according to the operation state of this switch, to the 1st input path switching means 8a, a 1st input path connection mode or a 2nd input path connection mode A switching control signal for switching is output. The switch operating state refers to the switching state of the stereo mode or monaural mode described above. When the switch operation state is the stereo mode, the mode switching unit switches the first input path switching unit 8a to the first input path connection mode (hereinafter referred to as “first switching control signal”). Is written). In addition, when the switch operation state is the monaural mode, the mode switching unit switches the first input path switching unit 8a to the second input path connection mode (hereinafter referred to as “second switching control signal”). Is written). Note that the configuration of the mode switching unit is not limited to a configuration that receives a signal input from the outside and switches to the first input path connection mode or the second input path connection mode. It is good also as a structure which switches to 1st input path | route connection mode or 2nd input path | route connection mode by manual operation, such as a formula.

Specifically, in the first input path connection mode, the second input path 4b and the second output buffer 6b are electrically connected, and in the second input path connection mode, the first input path 4a and the second output buffer 6b are connected. Are electrically connected.
Similarly to the first input path switching unit 8a, the second input path switching unit 8b responds to the switching control signal input from the mode switching unit to the third input path 4c, the fourth input path 4d, and the fourth output buffer 6d. Is switched to the first input path connection mode or the second input path connection mode.
Specifically, in the first input path connection mode, the fourth input path 4d and the fourth output buffer 6d are electrically connected, and in the second input path connection mode, the third input path 4c and the fourth output buffer 6d are connected. Are electrically connected.

As described above, the input path switching unit 8 electrically connects one of the input paths 4 and the output buffer 6 corresponding to the input path 4 in the first input path connection mode. In the second input path connection mode, one of the input paths 4 and a plurality of output buffers 6 including the output buffer 6 corresponding to the input path 4 are electrically connected.
The output path switching unit 10 includes a first output path switching unit 10a and a second output path switching unit 10b. Similar to the first input path switching means 8a and the second input path switching means 8b, the first output path switching means 10a and the second output path switching means 10b are formed by switching elements, for example.

The first output path switching unit 10a switches the electrical connection state between the second output buffer 6b and the first load 2a and the second load 2b according to the state of the first input path switching unit 8a. As a means for detecting the state of the first input path switching means 8a, for example, similarly to the first input path switching means 8a, the switching control signal input from the mode switching section is received, and the received switching control signal is received. Accordingly, the state of the first input path switching means 8a is detected.
Specifically, when the first input path switching unit 8a is in the first input path connection mode, the second output buffer 6b and the second load 2b are electrically connected, and the first input path switching unit 8a is In the two-input path connection mode, the second output buffer 6b and the first load 2a are electrically connected.

The second output path switching unit 10b switches the electrical connection state between the fourth output buffer 6d and the first load 2a and the second load 2b according to the state of the second input path switching unit 8b. The means for detecting the state of the second input path switching means 8b is, for example, the second input path switching means in accordance with the switching control signal input from the mode switching section, as in the first output path switching means 10a. The state of 8b is detected.
Specifically, when the second input path switching unit 8b is in the first input path connection mode, the fourth output buffer 6d and the second load 2b are electrically connected, and the second input path switching unit 8b In the two-input path connection mode, the fourth output buffer 6d and the first load 2a are electrically connected.

  As described above, the output path switching unit 10 electrically connects the output buffer 6 and the load 2 corresponding to the output buffer 6 when the input path switching unit 8 is in the first input path connection mode. . In addition, when the input path switching unit 8 is in the second input path connection mode, the double-row connection input path (in this embodiment, the first input path 4a) that is one of the input paths 4 in the second input path connection mode. And the third input path 4c) are electrically connected to the plurality of output buffers 6 and the load 2 corresponding to the double-row connection input path.

(Operation)
Next, the operation of the output buffer circuit 1 having the above configuration will be described with reference to FIGS.
First, the operation of the output buffer circuit 1 common to the stereo mode and the monaural mode will be described with reference to FIG.
In the stereo mode and the monaural mode, the first drive signal transmitted by the first input path 4a is input to the first output buffer 6a, and the third drive signal transmitted by the third input path 4c is input to the third output buffer 6c. To enter.

The first output buffer 6a amplifies the input first drive signal, and the third output buffer 6c amplifies the input third drive signal.
Next, the first drive signal amplified by the first output buffer 6a is output to the positive side of the first load 2a via the first external output terminal 12a, and the third drive signal amplified by the third output buffer 6c. Is output to the negative side of the first load 2a via the third external output terminal 12c.
As described above, in both the stereo mode and the monaural mode, the first drive signal and the third drive signal are amplified by the first output buffer 6a and the third output buffer 6c, respectively, and balanced output to the first load 2a.

Next, the operation of the output buffer circuit 1 in the stereo mode will be described with reference to FIG.
In the stereo mode, the mode switching unit outputs the first switching control signal to the first input path switching unit 8a, the second input path switching unit 8b, the first output path switching unit 10a, and the second output path switching unit 10b. .
Upon receiving the first switching control signal, the first input path switching unit 8a electrically connects the second input path 4b and the second output buffer 6b. As a result, the second drive signal transmitted by the second input path 4b is input to the second output buffer 6b. The second output buffer 6b amplifies the input second drive signal.

The second input path switching means 8b that has received the input of the first switching control signal electrically connects the fourth input path 4d and the fourth output buffer 6d. As a result, the fourth drive signal transmitted by the fourth input path 4d is input to the fourth output buffer 6d. The fourth output buffer 6d amplifies the input fourth drive signal.
On the other hand, the first output path switching means 10a receiving the input of the first switching control signal electrically connects the second output buffer 6b and the second load 2b. As a result, the second drive signal amplified by the second output buffer 6b is output to the positive electrode side of the second load 2b via the second external output terminal 12b.
Further, the second output path switching means 10b that has received the input of the first switching control signal electrically connects the fourth output buffer 6d and the second load 2b. As a result, the fourth drive signal amplified by the fourth output buffer 6d is output to the negative electrode side of the second load 2b via the fourth external output terminal 12d.

As described above, in the stereo mode, the amplified first drive signal and third drive signal are balanced and output to the first load 2a, and the second drive signal and the fourth drive signal are respectively output to the second output buffer 6b and the fourth output signal. Amplified by the output buffer 6d and balanced output to the second load 2b.
Therefore, in the stereo mode, the first drive signal and the third drive signal amplified by one output buffer 6 are balanced with respect to the first load 2a, and one output buffer 6 is amplified with respect to the second load 2b. The second drive signal and the fourth drive signal are output in a balanced manner.

Next, the operation of the output buffer circuit 1 in the monaural mode will be described with reference to FIG.
In the monaural mode, the mode switching unit outputs a second switching control signal to the first input path switching unit 8a, the second input path switching unit 8b, the first output path switching unit 10a, and the second output path switching unit 10b. .
Upon receiving the second switching control signal, the first input path switching means 8a electrically connects the first input path 4a and the second output buffer 6b. As a result, the first drive signal transmitted by the first input path 4a is input to the second output buffer 6b. The second output buffer 6b amplifies the input first drive signal.

The second input path switching means 8b that has received the input of the second switching control signal electrically connects the third input path 4c and the fourth output buffer 6d. As a result, the third drive signal transmitted by the third input path 4c is input to the fourth output buffer 6d. The fourth output buffer 6d amplifies the input third drive signal.
On the other hand, the first output path switching means 10a that has received the input of the second switching control signal electrically connects the second output buffer 6b and the first load 2a. Thus, the first drive signal amplified by the second output buffer 6b is output to the positive electrode side of the first load 2a via the second external output terminal 12b.

The second output path switching means 10b that has received the input of the second switching control signal electrically connects the fourth output buffer 6d and the first load 2a. As a result, the third drive signal amplified by the fourth output buffer 6d is output to the negative side of the first load 2a via the fourth external output terminal 12d.
As described above, in the monaural mode, the amplified first drive signal and third drive signal are balanced and output to the first load 2a. In addition, the first drive signal and the third drive signal are amplified by the second output buffer 6b and the fourth output buffer 6d, respectively, and balanced output to the first load 2a.

Therefore, in the monaural mode, in addition to the first drive signal and the third drive signal amplified by the first output buffer 6a and the third output buffer 6c for the first load 2a, the second output buffer 6b and the fourth output buffer 6d. The first drive signal and the third drive signal amplified by are balanced and output. That is, the first drive signal and the third drive signal are each amplified by the two output buffers 6 and output to the first load 2a.
As a result, in the monaural mode, the first load 2a, that is, the output of the audio reproduced by the Lch is compared with the stereo mode, the first drive signal amplified by the second output buffer 6b, and the fourth output buffer 6d. It increases according to the amplified third drive signal.

(Effects of the first embodiment)
Therefore, in the output buffer circuit 1 of the present embodiment, in the monaural mode, the first input path switching unit 8a electrically connects the first input path 4a, the first output buffer 6a, and the second output buffer 6b. In addition to this, the second input path switching means 8b electrically connects the third input path 4c with the third output buffer 6c and the fourth output buffer 6d.

For this reason, the first drive signal transmitted by the first input path 4a can be amplified by the first output buffer 6a and the second output buffer 6b. In addition, the third drive signal transmitted by the third input path 4c can be amplified by the third output buffer 6c and the fourth output buffer 6d.
Thus, in the monaural mode, the first drive signal can be amplified using the second output buffer 6b that does not receive the input of the corresponding second drive signal. In addition, the third drive signal can be amplified using the fourth output buffer 6d that does not receive the corresponding fourth drive signal.

As a result, an increase in the area, volume, and number of parts of the output buffer 6 can be suppressed, and the drive capability of the output buffer circuit 1 can be improved.
In the output buffer circuit 1 of the present embodiment, in the monaural mode, the first output path switching unit 10a electrically connects the first output buffer 6a and the second output buffer 6b to the positive side of the first load 2a. Let In addition, the second output path switching unit 10b electrically connects the third output buffer 6c and the fourth output buffer 6d to the negative electrode side of the first load 2a.

Therefore, in addition to the first drive signal amplified by the first output buffer 6a and the second output buffer 6b, the first load 2a is generated by the third drive signal amplified by the third output buffer 6c and the fourth output buffer 6d. Can be driven.
As a result, the output of the audio reproduced by the first load 2a is compared with the stereo mode, according to the first drive signal amplified by the second output buffer 6b and the third drive signal amplified by the fourth output buffer 6d. Can be increased.

Further, in the output buffer circuit 1 of the present embodiment, in the monaural mode, the third drive signal having the opposite phase to the first drive signal is amplified by the third output buffer 6c and the fourth output buffer 6d, and the first load 2a To enter.
As a result, since the first drive signal and the third drive signal amplified together can be output in parallel to the first load 2a, the advantages of BTL connection can be efficiently exhibited. Become.

(Application examples)
In the output buffer circuit 1 of the present embodiment, the configuration of the output buffer circuit 1 is a circuit that connects the input device and the first load 2a and the second load 2b, that is, the input device and the two loads 2. However, the present invention is not limited to this. That is, the configuration of the output buffer circuit 1 may be a configuration in which an input device and three or more loads 2 are connected. Similarly, the configuration of the output buffer circuit 1 may be a configuration including five or more input paths 4 and five or more output buffers 6 provided in one-to-one correspondence with these input paths 4. In this case, the input path switching means 8 includes one of the input paths 4 and a plurality of output buffers 6 including the output buffer 6 corresponding to the input path 4 in the second input path connection mode equivalent to the above-described monaural mode. Are electrically connected. The output path switching means 10 includes a plurality of output buffers 6 that are electrically connected to one of the input paths 4 by the input path switching means 8 when the input path switching means 8 is in the second input path connection mode. The load 2 corresponding to one of the input paths 4 is electrically connected.

  In the output buffer circuit 1 of the present embodiment, the first output path switching unit 10a is connected to the second output buffer 6b via the second external output terminal 12b. However, the present invention is not limited to this. That is, the first output path switching means 10a is connected to the second output buffer 6b without going through the second external output terminal 12b, and is arranged between the second external output terminal 12b and the second output buffer 6b. Also good. Similarly, the second output path switching means 10b is connected to the fourth output buffer 6d without going through the fourth external output terminal 12d, and is arranged between the fourth external output terminal 12d and the fourth output buffer 6d. May be.

  Further, in the output buffer circuit 1 of the present embodiment, the positive side of the first load 2a or the positive side of the second load 2b is electrically connected to the second external output terminal 12b via the first output path switching means 10a. Although connected, it is not limited to this. That is, the positive electrode side of the first load 2a may be electrically connected to the second external output terminal 12b without using the first output path switching means 10a. In this case, in the monaural mode, the degree of decrease in the first drive signal amplified by the second output buffer 6b can be suppressed according to the internal resistance of the first output path switching unit 10a, and the positive electrode of the first load 2a It is possible to increase the first drive signal output to the side. Similarly, the negative electrode side of the first load 2a may be electrically connected to the fourth external output terminal 12d without using the second output path switching means 10b.

  Further, in the output buffer circuit 1 of the present embodiment, the first input path switching means 8a is disposed between the first input path 4a and the second input path 4b and the second output buffer 6b to switch the second input path. The means 8b is arranged between the third input path 4c and the fourth input path 4d and the fourth output buffer 6d. In other words, the input path switching unit 8 is arranged only on the second load 2b side (Rch side), but the present invention is not limited to this, and the input path switching unit 8 is arranged on the first load 2a side (Lch side). You may arrange only. In this case, in the monaural mode, the second drive signal is amplified by the first output buffer 6a, and the fourth drive signal is amplified by the third output buffer 6c. Further, the input path switching means 8 may be arranged on the first load 2a side and the second load 2b side.

  In the output buffer circuit 1 of the present embodiment, the first output path switching unit 10a is arranged between the second output buffer 6b and the first load 2a and the second load 2b, and the second output path switching unit 10b. Is arranged between the fourth output buffer 6d and the first load 2a and the second load 2b. In other words, the output path switching means 10 is arranged only on the second load 2b side (Rch side), but the present invention is not limited to this, and the output path switching means 10 is arranged on the first load 2a side (Lch side). You may arrange only. In this case, in the monaural mode, the second load 2b, that is, the output of the sound reproduced by the Rch is compared with the stereo mode, and the second drive signal amplified by the first output buffer 6a and the third output buffer 6c It increases according to the amplified fourth drive signal. Further, the output path switching means 10 may be arranged on the first load 2a side and the second load 2b side.

In the output buffer circuit 1 of the present embodiment, the first load 2a and the second load 2b are speakers. However, the present invention is not limited to this, and the first load 2a and the second load 2b are, for example, headphones. An audio output device other than a speaker may be used.
Further, in the output buffer circuit 1 of the present embodiment, the configuration of the input path switching unit 8 includes the first input path switching unit 8a and the second input path switching unit 8b, but is not limited thereto. is not. That is, for example, the configuration of the input path switching unit 8 may be configured by a single switching element. The same applies to the configuration of the output path switching means 10.

(Second embodiment)
Next, a second embodiment of the present invention will be described with reference to the drawings.
(Constitution)
First, the configuration of the present embodiment will be described with reference to FIGS. 3 and 4. Detailed description of the same configuration as that of the first embodiment described above will be omitted.
3 and 4 are diagrams showing the configuration of the output buffer circuit 1 of the present embodiment. FIG. 3 is a diagram illustrating the state of the output buffer circuit 1 in the stereo mode, and FIG. 4 is a diagram illustrating the state of the output buffer circuit 1 in the monaural mode.
As shown in FIGS. 3 and 4, the output buffer circuit 1 of the present embodiment includes two systems of input paths 4a and 4b, two output buffers 6a and 6b, input path switching means 8, and output paths. And switching means 10.

The two systems of input paths 4a and 4b each transmit a drive signal input from an input device. In the drawings and the following description, the input path 4a is described as “first input path 4a”, and the input path 4b is described as “second input path 4b”.
The first input path 4a transmits a first drive signal (described as “LIN signal” in the figure) for driving the first load 2a, and the second input path 4b drives the second load 2b. A second drive signal (denoted as “RIN signal” in the figure) is transmitted.

  The two output buffers 6a and 6b are provided in one-to-one correspondence with the two systems of input paths 4a and 4b, respectively, amplify the input drive signal, and output from the two external output terminals 12a and 12b. Output. In the drawings and the following description, the output buffer 6a is described as “first output buffer 6a”, and the output buffer 6b is described as “second output buffer 6b”.

The first output buffer 6a corresponds to the first input path 4a, and the second output buffer 6b corresponds to the second input path 4b.
The two external output terminals 12a and 12b are provided in one-to-one correspondence with the two output buffers 6a and 6b, respectively. In the drawings and the following description, the external output terminal 12a is described as “first external output terminal 12a”, and the external output terminal 12b is described as “second external output terminal 12b”.

The first external output terminal 12a corresponds to the first output buffer 6a and is electrically connected to the first load 2a. The second external output terminal 12 b corresponds to the second output buffer 6 b and is electrically connected to the first load 2 a or the second load 2 b via the output path switching means 10.
Here, the first load 2a corresponds to the first input path 4a and the first output buffer 6a. The second load 2b corresponds to the second input path 4b and the second output buffer 6b.

The input path switching unit 8 determines the electrical connection state between the first input path 4a and the second input path 4b and the second output buffer 6b in accordance with a switching control signal input from a mode switching unit (not shown). Switch to the first input path connection mode or the second input path connection mode.
Specifically, in the first input path connection mode, the second input path 4b and the second output buffer 6b are electrically connected, and in the second input path connection mode, the first input path 4a and the second output buffer 6b are connected. Are electrically connected.

The output path switching unit 10 switches the electrical connection state between the second output buffer 6b, the first load 2a, and the second load 2b according to the state of the input path switching unit 8.
Specifically, when the input path switching means 8 is in the first input path connection mode, the second output buffer 6b and the second load 2b are electrically connected, and the input path switching means 8 is connected to the second input path. In the mode, the second output buffer 6b and the first load 2a are electrically connected.
Other configurations are the same as those of the first embodiment described above.

(Operation)
Next, the operation of the output buffer circuit 1 having the above configuration will be described with reference to FIGS. In the following description, differences from the above-described first embodiment will be mainly described.
First, the operation of the output buffer circuit 1 common to the stereo mode and the monaural mode will be described with reference to FIG.
In the stereo mode and the monaural mode, the first drive signal transmitted by the first input path 4a is input to the first output buffer 6a, and the input first drive signal is amplified by the first output buffer 6a.
Then, the first drive signal amplified by the first output buffer 6a is output to the first load 2a via the first external output terminal 12a.
As described above, in the stereo mode and the monaural mode, the first drive signal is amplified by the first output buffer 6a and output to the first load 2a.

Next, the operation of the output buffer circuit 1 in the stereo mode will be described with reference to FIG.
In the stereo mode, the mode switching unit outputs the first switching control signal to the input path switching unit 8 and the output path switching unit 10.
Upon receiving the first switching control signal, the input path switching means 8 electrically connects the second input path 4b and the second output buffer 6b. As a result, the second drive signal transmitted by the second input path 4b is input to the second output buffer 6b. The second output buffer 6b amplifies the input second drive signal.

On the other hand, the output path switching means 10 that has received the input of the first switching control signal electrically connects the second output buffer 6b and the second load 2b. As a result, the second drive signal amplified by the second output buffer 6b is output to the second load 2b via the second external output terminal 12b.
As described above, in the stereo mode, the amplified first drive signal is output to the first load 2a, and the second drive signal is amplified by the second output buffer 6b and output to the second load 2b.
Therefore, in the stereo mode, the first output buffer 6a, that is, the first drive signal amplified by one output buffer 6 is output to the first load 2a. Further, the second output signal amplified by the second output buffer 6b, that is, one output buffer 6, is output to the second load 2b.

Next, the operation of the output buffer circuit 1 in the monaural mode will be described with reference to FIG.
In the monaural mode, the mode switching unit outputs a second switching control signal to the input path switching unit 8 and the output path switching unit 10.
Upon receiving the second switching control signal, the input path switching unit 8 electrically connects the first input path 4a and the second output buffer 6b. As a result, the first drive signal transmitted by the first input path 4a is input to the second output buffer 6b. The second output buffer 6b amplifies the input first drive signal.

On the other hand, the output path switching means 10 that has received the input of the second switching control signal electrically connects the second output buffer 6b and the first load 2a. As a result, the first drive signal amplified by the second output buffer 6b is output to the first load 2a via the second external output terminal 12b.
As described above, in the monaural mode, the amplified first drive signal is output to the first load 2a. In addition, the first drive signal is amplified by the second output buffer 6b and output to the first load 2a.

Accordingly, in the monaural mode, the first drive signal amplified by the second output buffer 6b is output to the first load 2a in addition to the first drive signal amplified by the first output buffer 6a. That is, the first drive signal is amplified by the two output buffers 6 and output to the first load 2a.
As a result, in the monaural mode, the output of the sound reproduced by the first load 2a, that is, the Lch, is increased according to the first drive signal amplified by the second output buffer 6b, as compared with the stereo mode.
Other operations are the same as those in the first embodiment described above.

(Effect of the second embodiment)
Therefore, in the output buffer circuit 1 of the present embodiment, in the monaural mode, the input path switching unit 8 electrically connects the first input path 4a, the first output buffer 6a, and the second output buffer 6b.
Therefore, the first drive signal transmitted through the first input path 4a can be amplified by the first output buffer 6a and the second output buffer 6b, and the corresponding second drive signal is received in the monaural mode. The first drive signal can be amplified using the second output buffer 6b that is not present.
As a result, an increase in the area, volume, and number of parts of the output buffer 6 can be suppressed, and the drive capability of the output buffer circuit 1 can be improved.

In the output buffer circuit 1 of the present embodiment, in the monaural mode, the output path switching unit 10 electrically connects the first output buffer 6a, the second output buffer 6b, and the first load 2a.
For this reason, in addition to the first drive signal amplified by the first output buffer 6a, the first load 2a can be driven by the first drive signal amplified by the second output buffer 6b.
As a result, the output of the sound reproduced by the first load 2a can be increased according to the first drive signal amplified by the second output buffer 6b as compared with the stereo mode.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to the drawings.
(Constitution)
First, the configuration of the present embodiment will be described with reference to FIGS. 5 and 6. Detailed description of the same configuration as that of the first embodiment described above will be omitted.
5 and 6 are diagrams showing the configuration of the output buffer circuit 1 of the present embodiment. 5 is a diagram illustrating a state of the output buffer circuit 1 in the stereo mode, and FIG. 6 is a diagram illustrating a state of the output buffer circuit 1 in the monaural mode.
As shown in FIGS. 5 and 6, the output buffer circuit 1 of this embodiment includes two systems of input paths 4a and 4b, two output buffers 6a and 6b, input path switching means 8, and an output path. And switching means 10.

  The two systems of input paths 4a and 4b transmit drive signals input from input devices via the input terminals 14a and 14b, respectively. In the drawings and the following description, the input path 4a is described as “first input path 4a”, and the input path 4b is described as “second input path 4b”. Similarly, in the drawings and the following description, the input terminal 14a will be described as “first input terminal 14a” and the input terminal 14b will be described as “second input terminal 14b”.

The first input path 4a transmits a first drive signal (described as “LIN signal” in the figure) for driving the first load 2a, and the second input path 4b drives the second load 2b. A second drive signal (denoted as “RIN signal” in the figure) is transmitted.
The two output buffers 6a and 6b are provided in one-to-one correspondence with the two systems of input paths 4a and 4b, respectively, amplify the input drive signal, and output from the two external output terminals 12a and 12b. Output. In the drawings and the following description, the output buffer 6a is described as “first output buffer 6a”, and the output buffer 6b is described as “second output buffer 6b”.

The first output buffer 6a corresponds to the first input path 4a, and includes a first control unit 16a and a first output unit 18a that has a one-to-one correspondence with the first control unit 16a.
The first control unit 16a is, for example, a non-inverting amplifier including an N channel type transistor and a P channel type transistor. Moreover, the 1st control part 16a is electrically connected with the 1st input path | route 4a via the 1st input resistance 20a. Accordingly, the first control unit 16a receives the first reference drive signal LNIN generated by the first drive signal passing through the first input resistor 20a and the first reference voltage signal LPIN.

  The first output unit 18a is formed by including a first P-channel transistor 22a and a first N-channel transistor 24a, and is electrically connected to the first controller 16a. The output side of the first output unit 18a is connected to the input side of the first control unit 16a via the first feedback resistor 26a, specifically between the first control unit 16a and the first input resistance 20a. Electrically connected.

The first P-channel transistor 22a receives the first N-side control signal VN_L from the first controller 16a, and the first N-channel transistor 24a receives the first P-side control signal from the first controller 16a. Receives input of VP_L.
The second output buffer 6b corresponds to the second input path 4b, and includes a second control unit 16b and a second output unit 18b that has a one-to-one correspondence with the second control unit 16b.

  Similar to the first control unit 16a, the second control unit 16b is, for example, a non-inverting amplifier including an N-channel transistor and a P-channel transistor. Moreover, the 2nd control part 16b is electrically connected with the 2nd input path | route 4b via the 2nd input resistance 20b. As a result, the second control unit 16b receives the second reference drive signal RNIN and the second reference voltage signal RPIN generated when the second drive signal passes through the second input resistor 20b.

  The second output unit 18b is formed by including a second P-channel transistor 22b and a second N-channel transistor 24b, and is electrically connected to the second control unit 16b via the input path switching means 8. is doing. The output side of the second output unit 18b is connected to the input side of the second control unit 16b, specifically, the second control unit 16b and the second input via the second feedback resistor 26b and the feedback path switching means 28. It is electrically connected to the resistor 20b.

Here, the first load 2a corresponds to the first input path 4a and the first output buffer 6a. The second load 2b corresponds to the second input path 4b and the second output buffer 6b.
The input path switching unit 8 includes a first input path switching unit 8a and a second input path switching unit 8b. The first input path switching unit 8a and the second input path switching unit 8b are formed by switching elements, for example.

The first input path switching unit 8a is connected to the first control unit 16a, the second control unit 16b, and the second output unit 18b in response to a switching control signal input from a mode switching unit (not shown). Is switched to the first input path connection mode or the second input path connection mode.
Specifically, in the first input path connection mode, the second control unit 16b and the second P-channel transistor 22b are electrically connected. In the second input path connection mode, the first control unit 16a and the second P-channel transistor 22b are electrically connected. The channel type transistor 22b is electrically connected.

Similar to the first input path switching unit 8a, the second input path switching unit 8b responds to the switching control signal input from the mode switching unit, and includes the first control unit 16a, the second control unit 16b, and the second output unit 18b. Is switched to the first input path connection mode or the second input path connection mode.
Specifically, in the first input path connection mode, the second control unit 16b and the second N-channel transistor 24b are electrically connected. In the second input path connection mode, the first control unit 16a and the second N-channel transistor 24b are electrically connected. The channel type transistor 24b is electrically connected.

As described above, in the second input path connection mode, the second P-channel transistor 22b receives the input of the second N-side control signal VN_R from the second controller 16b, and the second N-channel transistor 24b A second P-side control signal VP_R is received from the control unit 16b.
Therefore, the input path switching unit 8 electrically connects the control unit 16 and the output unit 18 included in the same output buffer 6 in the first input path connection mode. In the second input path connection mode, one of the control units 16 and a plurality of output units 18 including the output unit 18 corresponding to the control unit 16 are electrically connected.

The return path switching means 28 is formed by a switching element, for example, like the first input path switching means 8a and the second input path switching means 8b.
The feedback path switching unit 28 switches the electrical connection state between the output side of the second output unit 18b and the input side of the second control unit 16b according to the state of the input path switching unit 8.
Specifically, when the input path switching unit 8 is in the first input path connection mode, the output side of the second output unit 18b and the input side of the second control unit 16b are electrically connected. On the other hand, when the input path switching unit 8 is in the second input path connection mode, the electrical connection between the output side of the second output unit 18b and the input side of the second control unit 16b is cut off.

  As described above, the feedback path switching unit 28 electrically connects the second output unit 18b and the second control unit 16b when the input path switching unit 8 is in the first input path connection mode. In addition, when the input path switching unit 8 is in the second input path connection mode, the electrical connection between the second output unit 18b and the second control unit 16b is cut off, and the second output unit 18b is controlled in the second control mode. It is electrically disconnected from the portion 16b.

The two external output terminals 12a and 12b are provided in one-to-one correspondence with the first output unit 18a and the second output unit 18b, respectively. In the drawings and the following description, the external output terminal 12a is described as “first external output terminal 12a”, and the external output terminal 12b is described as “second external output terminal 12b”.
The first external output terminal 12a corresponds to the first output unit 18a and is electrically connected to the first load 2a. The second external output terminal 12 b corresponds to the second output unit 18 b and is electrically connected to the first load 2 a or the second load 2 b via the output path switching means 10.

The output path switching unit 10 switches the electrical connection state between the second output unit 18b, the first load 2a, and the second load 2b according to the state of the input path switching unit 8.
Specifically, when the input path switching unit 8 is in the first input path connection mode, the second output unit 18b and the second load 2b are electrically connected, and the input path switching unit 8 is connected to the second input path. In the mode, the second output unit 18b and the first load 2a are electrically connected.

As described above, the output path switching unit 10 electrically connects the output unit 18 and the load 2 corresponding to the output buffer 6 including the output unit 18 when the input path switching unit 8 is in the first input path connection mode. Connect to. In addition, when the input path switching unit 8 is in the second input path connection mode, a double-row connection control unit (in the present embodiment, the first control unit 16a) that is one of the control units 16 in the second input path connection mode. ) And the load 2 corresponding to the output buffer 6 including the double-row connection control unit are electrically connected.
Other configurations are the same as those of the first embodiment described above.

(Operation)
Next, the operation of the output buffer circuit 1 having the above configuration will be described with reference to FIGS. In the following description, differences from the above-described first embodiment will be mainly described.
First, the operation of the output buffer circuit 1 common to the stereo mode and the monaural mode will be described with reference to FIG.
In the stereo mode and the monaural mode, the first N-side control signal VN_L and the first P-side control signal VP_L are input from the first control unit 16a to the first output unit 18a and input by the first output unit 18a. The first N-side control signal VN_L and the first P-side control signal VP_L are amplified.

The first N-side control signal VN_L and the first P-side control signal VP_L amplified by the first output unit 18a are output to the first load 2a via the first external output terminal 12a.
As described above, in both the stereo mode and the monaural mode, the first N-side control signal VN_L and the first P-side control signal VP_L are amplified by the first output unit 18a and output to the first load 2a.

Next, the operation of the output buffer circuit 1 in the stereo mode will be described with reference to FIG.
In the stereo mode, the mode switching unit outputs a first switching control signal to the first input path switching unit 8a, the second input path switching unit 8b, the feedback path switching unit 28, and the output path switching unit 10.
Upon receiving the first switching control signal, the first input path switching unit 8a electrically connects the second control unit 16b and the second P-channel transistor 22b.
The second input path switching means 8b that has received the input of the first switching control signal electrically connects the second control unit 16b and the second N-channel transistor 24b.

  On the other hand, the feedback path switching means 28 that has received the input of the first switching control signal electrically connects the output side of the second output unit 18b and the input side of the second control unit 16b. Thus, the second N-side control signal VN_R and the second P-side control signal VP_R output from the second control unit 16b are input to the second P-channel transistor 22b and the second N-channel transistor 24b, respectively. The second P-channel transistor 22b amplifies the input second N-side control signal VN_R, and the second N-channel transistor 24b amplifies the input second P-side control signal VP_R.

Further, the output path switching means 10 that has received the input of the first switching control signal electrically connects the second output unit 18b and the second load 2b. As a result, the second N-side control signal VN_R and the second P-side control signal VP_R amplified by the second output unit 18 are output to the second load 2b via the second external output terminal 12b.
As described above, in the stereo mode, the amplified first N-side control signal VN_L and the first P-side control signal VP_L are output to the first load 2a, and the second N-side control signal VN_R and the second P-side control signal VP_R are output. Amplified by the second output unit 18b and output to the second load 2b.
Accordingly, in the stereo mode, the first output unit 18a, that is, the first output unit 18 outputs the first N-side control signal VN_L and the first P-side control signal VP_L to the first load 2a. Further, the second output unit 18b, that is, the second output unit 18 outputs the second N-side control signal VN_R and the second P-side control signal VP_R that are amplified by the second load 2b.

Next, the operation of the output buffer circuit 1 in the monaural mode will be described with reference to FIG.
In the monaural mode, the mode switching unit outputs a second switching control signal to the first input path switching unit 8a, the second input path switching unit 8b, the feedback path switching unit 28, and the output path switching unit 10.
Upon receiving the second switching control signal, the first input path switching unit 8a electrically connects the first control unit 16a and the second P-channel transistor 22b.
In addition, the second input path switching unit 8b that has received the input of the second switching control signal electrically connects the first control unit 16a and the second N-channel transistor 24b.

  On the other hand, the feedback path switching means 28 that has received the input of the second switching control signal cuts off the electrical connection between the output side of the second output unit 18b and the input side of the second control unit 16b. Thus, the first N-side control signal VN_L and the first P-side control signal VP_L output from the first control unit 16a are input to the second P-channel transistor 22b and the second N-channel transistor 24b, respectively. The second P-channel transistor 22b amplifies the input first N-side control signal VN_L, and the second N-channel transistor 24b amplifies the input first P-side control signal VP_L.

Further, the output path switching means 10 that has received the input of the second switching control signal electrically connects the second output unit 18b and the first load 2a. As a result, the first N-side control signal VN_L and the first P-side control signal VP_L amplified by the second output unit 18b are output to the first load 2a via the second external output terminal 12b.
As described above, in the monaural mode, the first N-side control signal VN_L and the first P-side control signal VP_L amplified by the first output unit 18a are output to the first load 2a. In addition, the first N-side control signal VN_L and the first P-side control signal VP_L are amplified by the second output unit 18b and output to the first load 2a.

Therefore, in the monaural mode, in addition to the first N-side control signal VN_L and the first P-side control signal VP_L amplified by the first output unit 18a, the first N 2 amplified by the second output unit 18b with respect to the first load 2a. Side control signal VN_L and first P side control signal VP_L are output. That is, the first N-side control signal VN_L and the first P-side control signal VP_L are amplified by the two output units 18 and output to the first load 2a.
Thereby, in the monaural mode, the first load 2a, that is, the output of the audio reproduced by the Lch is compared with the stereo mode, and the first N side control signal VN_L and the first P side amplified by the second output unit 18b It increases according to the control signal VP_L.
Other processes are the same as those in the first embodiment described above.

(Effect of the third embodiment)
Therefore, in the output buffer circuit 1 of the present embodiment, in the monaural mode, the input path switching unit 8 electrically connects the first control unit 16a, the first output unit 18a, and the second output unit 18b. Further, the feedback path switching means 28 cuts off the electrical connection between the output side of the second output unit 18b and the input side of the second control unit 16b.
For this reason, it becomes possible to amplify the 1st N side control signal VN_L and the 1st P side control signal VP_L which the 1st control part 16a outputs by the 1st output part 18a and the 2nd output part 18b. Thus, in the monaural mode, the first N-side control signal VN_L and the first P-side control signal VP_L are amplified using the second output unit 18b that does not receive the control signal input from the corresponding second output unit 18b. Is possible.

As a result, it is possible to suppress an increase in the area / volume / number of parts of the output unit 18 and to suppress an increase in the area / volume / number of parts of the output buffer 6 and to improve the drive capability of the output buffer circuit 1. It becomes.
Further, in the output buffer circuit 1 of the present embodiment, in the monaural mode, the output path switching unit 10 electrically connects the first output unit 18a, the second output unit 18b, and the first load 2a.

Therefore, in addition to the first N-side control signal VN_L and the first P-side control signal VP_L amplified by the first output unit 18a, the first N-side control signal VN_L and the first P-side amplified by the second output unit 18b. The first load 2a can be driven by the side control signal VP_L.
As a result, the output of the sound reproduced by the first load 2a is increased in accordance with the first N-side control signal VN_L and the first P-side control signal VP_L amplified by the second output unit 18b, compared with the stereo mode. It becomes possible.

Further, when a common first drive signal is input to each of the first output buffer 6a and the second output buffer 6b, the output of each output unit 18 is electrically output by an offset voltage generated due to variation in performance of each control unit. When the connection is made, a current flows between the outputs of the output unit 18 due to a potential difference generated between the output of the output unit 18a and the output of the output unit 18b, and the current consumption increases.
However, in the output buffer circuit 1 of the present embodiment, only the first output unit 18a and the second output unit 18b, that is, the output unit 18 among the first output buffer 6a and the second output buffer 6b are shared, The one N-side control signal VN_L and the first P-side control signal VP_L are amplified.

  As a result, the first control unit 16a and the second output buffer 6b share the control unit 16 as compared with the case where the common first drive signal is input to the first output buffer 6a and the second output buffer 6b, respectively. While suppressing the occurrence of an output potential difference generated between the output of the output unit 18a and the output of the output unit 18b due to the offset voltage of the control unit 16b, and the increase in current consumption due to the current flowing between the outputs, the maximum load at the first load 2a The output power can be increased.

It is a figure which shows the state of the output buffer circuit 1 of 1st embodiment of this invention in a stereo mode. It is a figure which shows the state of the output buffer circuit 1 of 1st embodiment of this invention in monaural mode. It is a figure which shows the state of the output buffer circuit 1 of 2nd embodiment of this invention in a stereo mode. It is a figure which shows the state of the output buffer circuit 1 of 2nd embodiment of this invention in monaural mode. It is a figure which shows the state of the output buffer circuit 1 of 3rd embodiment of this invention in a stereo mode. It is a figure which shows the state of the output buffer circuit 1 of 3rd embodiment of this invention in monaural mode.

DESCRIPTION OF SYMBOLS 1 Output buffer circuit 2 Load 4 Input path 6 Output buffer 8 Input path switching means 10 Output path switching means 12 External output terminal 14 Input terminal 16 Control part 18 Output part 20 Input resistance 22 P channel type transistor 24 N channel type transistor 26 Feedback Resistor 28 Return path switching means

Claims (1)

An output buffer circuit comprising a plurality of input paths that respectively transmit a plurality of drive signals, and a plurality of output buffers provided in one-to-one correspondence with the input paths,
Each of the plurality of output buffers includes a control unit that is electrically connected to the input path, and an output unit that has a one-to-one correspondence with the control unit and that is electrically connected to the control unit. ,
A plurality of output units including a first input path connection mode for electrically connecting the control unit and the output unit included in the same output buffer, and one of the control units and the output unit corresponding to the control unit An output buffer circuit comprising input path switching means for switching between and a second input path connection mode for electrically connecting the two.

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