JPH05226948A - Multiple output amplifier - Google Patents

Abstract

PURPOSE:To realize plural amplifier circuits comprising a constant current source, an input stage, and a level shift stage in common and comprising output stages used though changeover and-whose drive capability differs from each other. CONSTITUTION:The amplifier circuits whose drive capability differs from each other are formed by employing a constant current source comprising a transistor(TR) P1 and a resistor R, an amplifier input stage comprising TRs P2, P4, P5, N6, N7 and a level shift stage comprising TRs P3, P8 in common and changing over only output stages 1, 2 with switching signals phi, phi'. The circuit configuration of the plural amplifier circuits is simplified in comparison with the care providing the constant current source, the amplifier input stage and the level shift stage and the chip area is not increased especially in the case of the semiconductor integrated circuit processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-output amplifier in which an output stage is switched by a switching signal and a different drive capacity can be selected depending on a transistor size of the output stage.

[0002]

2. Description of the Related Art Conventionally, in order to create a multi-output amplifier having a plurality of output stages having different drive capabilities, it has been necessary to separately prepare a plurality of amplifier circuits. In the case of forming such a multi-output amplifier on a semiconductor integrated circuit, if the number of amplifier circuits to be created increases, the chip area increases proportionally, leading to a decrease in yield and a cost increase. Was there. In addition, there is a problem that the number of input terminals and output terminals increases proportionally, and the wiring becomes complicated.

[0003]

As described above, the conventional multi-output amplifier has a problem that the chip area increases because the amplifier circuits having the same circuit configuration are individually formed. However, when the amplifier circuit is composed of a constant current source, an input stage, a level shift stage, and an output stage, it is considered that an amplifier circuit having different drive capabilities can be provided by switching only the output stage.

The present invention has been made on the basis of such knowledge, and its object is to provide a plurality of output stages in an amplifier circuit including a constant current source, an input stage, a level shift stage and an output stage. On the other hand, it is an object of the present invention to provide a multi-output amplifier that can realize an amplifier circuit having different drive capabilities by sharing a constant current source, an input stage, and a level shift stage and switching only the output stage.

[0005]

In order to solve the above-mentioned problems, the multi-output amplifier of the present invention constitutes a constant current source by a series circuit of a resistor R and a first transistor P1 as shown in FIG. The second and third transistors P2 and P that form a current mirror with the first transistor P1.
A third transistor P4 to which the first input signal S1 is applied and a fifth transistor P2 to which the second input signal S2 is applied.
And a sixth transistor N6 in which a current flowing through the second transistor P2 and the sixth transistor N6 is made to form a current mirror with the sixth transistor N6. The seventh transistor N7, which is supplied with a flowing current, and the eighth transistor P8, which is controlled by the potential of the connection point between the fifth transistor P5 and the seventh transistor N7, and is supplied with a current flowing through the third transistor P3. And a ninth transistor P9 controlled by the potential at the connection point between the third transistor P3 and the eighth transistor P8, and a ninth transistor P9 connected in series, and controlled by the input potential of the eighth transistor P8. And the input of the eighth transistor P8 controlled by the switching signal φ. Position through the phase compensation capacitor C1 the ninth
And the eleventh transistor N11 which transmits to the output terminal V1 which is a connection point between the transistor P9 and the tenth transistor N10.
It is characterized in that a plurality of output stages 1 composed of 9, N10, N11 and the phase compensation capacitance C1 are provided.

[0006]

In the multi-output amplifier of the present invention, the constant current source composed of the transistor P1 and the resistor R, the transistor P2,
An amplifier input stage made up of P4, P5, N6 and N7 and a level shift stage made up of transistors P3 and P8 are made common, and by switching between output stages 1 and 2, an amplifier circuit having different drive capabilities is constructed. Therefore, for a plurality of amplifier circuits, the circuit configuration is simplified as compared with the case where a constant current source, an amplifier input stage, and a level shift stage are individually created. The area is not increased.

[0007]

1 is a circuit diagram of a first embodiment of the present invention.
The circuit configuration will be described below. Power supply voltage Vdd
In the line of, PMOS transistors P1, P2, P3
Source is connected. PMOS transistor P
The gates of 1, P2 and P3 are PMOS transistors P1
Connected to the drain of. PMOS transistor P
The drain of 1 is grounded via a resistor R. PM
The drain of the OS transistor P2 is connected to the sources of the PMOS transistors P4 and P5. Input signals S1 and S2 are applied to the gates of the PMOS transistors P4 and P5, respectively. PMOS transistor P
The drains of P4 and P5 are connected to the drains of NMOS transistors N6 and N7, respectively. The gates of the NMOS transistors N6 and N7 are connected to the drain of the NMOS transistor N6. The sources of the NMOS transistors N6 and N7 are grounded. The drains of the PMOS transistor P5 and the NMOS transistor N7 are connected to the gate of the PMOS transistor P8. The source of the PMOS transistor P8 is connected to the drain of the PMOS transistor P3,
The drain of the transistor P8 is grounded. PMO
The drain of the S transistor P3 and the source of the PMOS transistor P8 are connected to the gate of the PMOS transistor P9. The source of the PMOS transistor P9 is connected to the line of the power supply voltage Vdd. The drain of the PMOS transistor P9 is connected to the NMOS transistor N
The drain 10 is connected to the output terminal V1. The source of the NMOS transistor N10 is grounded. The gate of the NMOS transistor N10 is PMOS
It is connected to the gate of the transistor P8. PMOS
The source of the NMOS transistor N11 is connected to the gate of the transistor P8. The drain of the NMOS transistor N11 is connected to the output terminal V1 via the phase compensation capacitance C1. NMOS transistor N1
The switching signal φ is input to the gate of 1. PMO
S transistor P9 and NMOS transistors N10, N
11 and the phase compensation capacitor C1 form a first output stage 1. A second output stage 2 having a circuit configuration similar to that of the first output stage 1 is provided, and the PMOS transistor P12, NMOS transistors N13 and N14, and phase compensation capacitance C2 of the second output stage 2 are the same as those of the first output stage 1. It corresponds to the transistor P9, the NMOS transistors N10 and N11, and the phase compensation capacitance C1, respectively.

The operation of this embodiment will be described below.
First, the PMOS transistors P1, P2 and P3 form a current mirror, and the same current that flows to the PMOS transistor P1 via the resistor R flows to the PMOS transistors P2 and P3. PMOS transistor P4
P5 constitutes an amplifier input stage for differentially amplifying the input signals S1 and S2, and the NMOS transistors N6 and N7 constitute its load resistance. PMOS transistor P
3 and P8 form a level shift stage. PMOS
The transistor P9 and the NMOS transistor N10 are CM
An output stage including an OS circuit is configured. Also, NMO
The S-transistor N11 operates as an output stage switching switch that also serves as a zero-point adjusting resistor, and has a role of disconnecting the phase compensation capacitance C1 when not conducting.

In the present embodiment, the switching signal φ of the first output stage 1 and the switching signal φ'of the second output stage 2 are in opposite phase, and when the first output stage 1 is effective, , The second output stage 2
Is invalid, and conversely, when the second output stage 2 is valid, the first output stage 1 is invalid. Note that the phase compensation capacitors C1 and C2 are NMO respectively when not used.
Since they are separated by the S transistors N11 and N14, the output stage 1 and the output stage 2 do not influence each other.

FIG. 2 is a circuit diagram of the second embodiment of the present invention. In this embodiment, in addition to the first output stage 1 and the second output stage 2, a third output stage is further added.
The first output stage 1 is selected by the first switching signal φ1
A voltage signal obtained by differentially amplifying the input signals S1 and S2 is obtained from the output terminal V1. The second output stage 2 is selected by the second switching signal φ2, and the voltage signal obtained by differentially amplifying the input signals S1 and S2 is obtained from the output terminal V2. Similarly,
The third output stage 3 is selected by the third switching signal φ3,
A voltage signal obtained by differentially amplifying the input signals S1 and S2 is obtained from the output terminal V3. The output stages 1, 2 and 3 have different drive capabilities, and the output stage having the required drive capability is appropriately selected and used. The number of output stages may be further increased to four or more.

FIG. 3 is a circuit diagram of a third embodiment of the present invention. The circuit configuration of this embodiment is similar to that of FIG.
The arrangements of the OS transistor and the NMOS transistor are all reversed. The operation is similar to that of the embodiment shown in FIG.

[0012]

According to the multi-output amplifier of the present invention,
As described above, in the amplifier circuit including the constant current source, the input stage, the level shift stage, and the output stage, the constant current source, the input stage, and the level shift stage are common to a plurality of output stages, and only the output stage is switched by the switching signal. Since the switch circuits are configured to be switched, there is an effect that amplifier circuits having different drive capabilities can be easily realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 R Resistance of constant current source P1, ..., P14 PMOS transistor N1, ..., N14 NMOS transistor C1, ..., C3 Phase compensation capacitance

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masanori Hayashi 1048, Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Works, Ltd.

Claims (1)

[Claims] 1. A constant current source is formed by a series circuit of a resistor and a first transistor, and a second and a third transistor that form a current mirror with the first transistor are provided, and a first input signal is applied. A fourth transistor, a fifth transistor to which the second input signal is applied, a sixth transistor to which a current flowing through the second transistor is passed through the fourth transistor, and a sixth transistor And a current mirror, which controls the current flowing through the third transistor by being controlled by the potential of the seventh transistor to which the current flowing through the fifth transistor is conducted and the connection point between the fifth transistor and the seventh transistor. An eighth transistor which is energized, a ninth transistor which is controlled by a potential at a connection point between the third transistor and the eighth transistor, A tenth transistor connected in series with the ninth transistor and controlled by the input potential of the eighth transistor; and a ninth transistor controlled by the switching signal to shift the input potential of the eighth transistor through the phase compensation capacitor. And an eleventh transistor for transmitting to an output terminal composed of a connection point of the tenth transistor, and a plurality of output stages composed of the ninth to eleventh transistors and the phase compensation capacitance. ..