JP2012186939A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter device with low harmonic distortion, high efficiency, and low cost.SOLUTION: An inverter device has a first control unit 30 supplying a PWM signal to a bridge circuit 10 including four switches that are bridge-connected. The first control unit 30 includes a first inverter command signal generator 31, a second inverter command signal generator 32, a ripple current generator 33, an inverter command signal selector 34, and a gate signal generator 35. The first control unit 30 performs a closed loop control in a mode 1 (MOD1) and a mode 6 (MOD6), and performs an open-loop control in a mode 2 (MOD2) to a mode 5 (MOD5) based on an inverter command signal i.

Description

  The present invention relates to an inverter device such as a grid-connected inverter device which is a power conditioner for photovoltaic power generation.

  Conventionally, there are Patent Documents 1 to 3 and Non-Patent Documents as technologies related to the grid interconnection inverter device.

  Patent Document 1 discloses an inverter that detects a peak value of a system voltage and controls a DC voltage value obtained by adding a voltage drop of a switching device and a voltage drop of an output inductor to the peak value of an AC voltage as a target DC link voltage command. An apparatus is described.

  In Patent Document 2, in order to improve the distortion characteristic of the output signal, the tan-off delay characteristic of the insulated gate bipolar transistor (IGBT) is stored in a memory, and the inverter is designed to minimize the dead time according to the temperature change. An apparatus is described.

  In Patent Document 3, three PWM modulation patterns are provided for a pulse width modulation (hereinafter referred to as “PWM”) inverter of bipolar modulation, and a non-linear operation of the inverter is detected using a switching function. An inverter device is described in which the adverse effects of dead time are eliminated by switching.

  Non-Patent Document 1 includes a dedicated zero-current detection circuit and a high-speed arithmetic circuit for a programmable ic device (FPGA) to accurately detect the polarity of the output current and achieve control that eliminates dead time. Inverter is described.

JP 2010-213365 A JP 2010-142074 A JP 2010-268584 A

Yong-Kai Lin; Yen-Shin Lai;, "Dead-time elimination method and current polarity detection circuit for three-phase PWM-controlled inverter," ECCE 2009. IEEE, vol., No., Pp.83-90, 20 -24 Sept. 2009.

  However, the conventional inverter devices described in Patent Documents 1 to 3 and Non-Patent Document 1 have the following problems (a) to (d).

  (A) In the inverter device described in Patent Document 1, in order to reduce the size of the device, when a high switching frequency is employed, the utilization rate of the DC link voltage is reduced due to the influence of the dead time. Therefore, it is necessary to employ a higher DC link voltage than the ideal switch condition.

  (B) In the inverter device described in Patent Document 2, it is necessary to add a circuit for measuring an actual tan-off time or to add a temperature sensor in order to cope with variations in IGBT characteristics. .

  (C) In the inverter device described in Patent Document 3, when unipolar modulation is used, the operating characteristics of the inverter greatly change due to changes in the output power factor and output power. The output characteristics cannot be obtained.

  (D) The motor drive inverter described in Non-Patent Document 1 is considered effective in the case of a motor drive having a high load impedance. However, in the case of a grid-connected inverter, since the impedance between the inverter and the commercial system is very low, the harmonic distortion at light load increases.

  An object of the present invention is to solve the above problems and to provide an inverter device with low harmonic distortion, high efficiency, and low cost.

  The inverter device according to the first aspect of the present invention includes the bridge circuit 10, the filter circuit 20, and the first control unit 30.

The bridge circuit 10 includes a plurality of switches connected in a bridge, and converts an input first DC signal V _dc into a first AC signal (V _inv , i _inv ) based on the PWM signal V _g. It is. The filter circuit 20 is a circuit that filters the first AC signal (V _inv , i _inv ) and outputs a second AC signal (V _ac , i _o ).

The first control unit 30, based on the inverter command signal i _ref, the bridge circuit 10, and outputs the PWM signal _{V g.} The first control unit 30, depending on the value of the inverter command signal i _ref, the said plurality of switches and said plurality of switches on / off control, the values of the inverter command signal i _ref is, the threshold value When (i _r / 2) is exceeded, the bridge circuit 10 is closed-loop controlled, and when the value of the inverter command signal i _ref is less than or equal to a threshold value ( _ir / 2), the bridge circuit 10 is opened. Loop control.

For example, when the value of the inverter command signal i _ref is positive, the first control unit 30 turns off one of the switches and performs on / off control on the other switch, and the inverter command signal When the value of i _ref is negative, the other switch is turned off and the one switch is turned on / off. When the value of the inverter command signal i _ref exceeds the threshold ( _ir / 2), the bridge circuit 10 is controlled based on the inverter command signal i _ref and the first AC signal i _inv. When the closed loop control is performed and the value of the inverter command signal i _ref is equal to or less than the threshold value (i _r / 2), the bridge circuit 10 is set to the open loop control based on the inverter command signal i _ref .

  The inverter device of the second invention further controls the level of the output voltage of the converter so as to add a stability margin to the peak value of the converter and the second AC signal to the inverter device of the first invention. And are added.

  According to the inverter device of the present invention, the harmonic distortion can be significantly improved including the small current output region. Further, it is possible to eliminate the need to insert a dead time in the PWM modulation gate signal, and to reduce the DC link voltage. As described above, an inverter device can be realized with low harmonic distortion, high efficiency, and low cost.

  According to the inverter device of the second invention, the DC link voltage can always be minimized regardless of the change in the AC voltage by performing the control with the stability margin added to the peak value of the AC voltage. High efficiency can be achieved.

FIG. 1 is a block diagram showing a configuration of an inverter device according to Embodiment 1 of the present invention. FIG. 2 is a diagram showing a PWM signal waveform (1) and an output waveform (2) of the comparative example. FIG. 3 is a functional block diagram of the main part of the inverter device of FIG. FIG. 4 is a diagram showing a waveform of the PWM signal of the first control unit of MOD1 in FIG. FIG. 5 is a diagram showing a waveform of the PWM signal of the first control unit of MOD2 in FIG. FIG. 6 is a waveform diagram showing the relationship between the first inverter command signal and the PWM signal in FIG. FIG. 7 is a block diagram in which the first control unit in FIG. 3 is mathematically modeled. FIG. 8 is an output waveform when only PI control is used as a comparative example in FIG. 3, and is a waveform diagram showing a case of rated output (1) and a case of 20% rated output (2). FIG. 9 is a waveform diagram showing waveforms of the output current and the PWM signal at the rated output, and is a waveform diagram showing the case of control in the comparative example (1) and the case of control in FIG. 3 (2). FIG. 10 is a waveform diagram of the output current and the PWM signal at the time of 10% rated output, and shows the case of control in the comparative example (1) and the case of control in FIG. 3 (2). FIG. 11 is a characteristic comparison diagram showing a comparison of total harmonic distortion between the control of FIG. 3 and the control of the comparative example. FIG. 12 is a waveform diagram showing an output waveform (1) at the rated output and an output waveform (2) at the 20% rated output. FIG. 13 is a characteristic comparison diagram showing the improvement of the total harmonic distortion by the verification experiment of FIGS. 1 and 3. FIG. 14 is a waveform diagram showing the inductor current waveform at the time of 3 kW output, and shows the case of the control of the comparative example (1) and the case of reducing the DC link voltage by the control of FIGS. 1 and 3 (2). It is. FIG. 15 is a characteristic comparison diagram showing improvement of the ripple current characteristic with respect to the output current of FIGS. FIG. 16 is a characteristic comparison diagram showing efficiency improvement with respect to the rated load factor (output current / rated current) of Example 1. FIG. 17 is a characteristic diagram showing efficiency characteristics when the DC link voltage of FIGS. 1 and 3 is changed. FIG. 18 is a block diagram showing the configuration of the inverter device according to the second embodiment of the present invention. FIG. 19 is a block diagram showing a configuration of an inverter device according to Embodiment 3 of the present invention.

  Modes for carrying out the present invention will become apparent from the following description of the preferred embodiments when read in light of the accompanying drawings. However, the drawings are only for explanation and do not limit the scope of the present invention.

(Configuration of Example 1)
FIG. 1 is a block diagram illustrating a configuration of an inverter device according to Embodiment 1 of the present invention.

This inverter device is, for example, a grid-connected inverter device, and includes a DC power source (for example, photovoltaic power generation (PV)) 1 that outputs a DC voltage V _PV . A DC / DC converter (hereinafter referred to as “DC / DC converter”) 2 is connected to the DC power source 1. The DC / DC converter 2 is a circuit that converts the level of the output signal (V _PV ) of the DC power supply 1 in accordance with a circuit connected to a subsequent stage. A bridge circuit is connected to the output side via an electrolytic capacitor 3. 10 is connected.

The bridge circuit 10 is a circuit that inputs a first DC signal (for example, DC voltage) V _dc and outputs a first AC signal (for example, AC power, (i _inv , V _inv )). The bridge circuit 10 includes first, second, third, and fourth switches (for example, NPN transistors) 11 to 14 that are bridge-connected, and a filter circuit 20 is connected to the output side. PWM signals V _{gl +} , V _gl− V _{g2 +} , and V _g2− are input to the bases of the first to fourth NPN transistors 11 to 14, respectively. Further, regenerative diodes 11a to 14a are connected in the opposite direction between the collectors and emitters of the NPN transistors 11 to 14, respectively.

The filter circuit 20 (for example, composed of a coil 21 and a capacitor 22, reduces the ripple component of the AC power (i _inv , V _inv ) and reduces the second AC signal (for example, AC power (i _o , V _ac )). ), And an AC system 50 is connected to the output side of the AC system 50. The AC system 50 includes an AC power supply 50 and is connected to an inverter device through a distribution line etc. 51 53 and 53 show the inductance of the distribution line, and 52 and 54 show the resistance impedance of the distribution line, between the inductor 21 and the capacitor 22 of the filter circuit 20 and the input of the current detector 23. The current detector. 23, the second alternating current i _o and phase detects a different first alternating current i _inv, and supplies the detection signal to the first control unit 30. second alternating current i When why different phases in the first alternating current i _inv is because a current flows through the capacitor 22. The filter circuit 20 AC system 50 connecting point, the voltage detector for detecting a second alternating voltage V _ac A device 24 is connected to supply the detection signal to the first control unit 30.

Based on the first inverter command signal i _ref , the first control unit 30 _applies PWM signals V _{gl +} , V _{g2 +} , V _g2− , V _gl− to the bases of the NPN transistors 11 to 14 in the bridge circuit 10. Each is output. Here, the first inverter command signal i _ref is a signal for determining the first AC signal i _inv output from the DC / AC inverter 10, and is given from the outside, for example. The first control unit 30 includes first and second inverter command signal generation units 31 and 32, a ripple current calculation unit 33, an inverter command signal selection unit 34, and a gate signal generation unit 35. .

The first inverter command signal generator 31 generates a first inverter command signal i _ref , a first AC signal (for example, AC current) i _inv, and a second AC signal (for example, AC voltage) V _ac . Based on this, it has a function of generating two types of inverter modulation signals corresponding to the two types of modes (1, 6) and supplying them to the inverter command signal selector 34. The second inverter signal generation unit 32 generates four types of inverter modulation signals corresponding to the four types of modes (2, 3, 4, 5) based on the first inverter command signal i _ref , and generates an inverter command signal. It has a function of supplying to the selector 34. Ripple current computing unit 33, the second AC signal (e.g., an AC voltage) based on V _ac and the first DC voltage V _dc, calculates the ripple current i _r, a function of supplying the inverter command signal selector 34 Have.

The inverter command signal selection unit 34 includes a first inverter command signal generation unit 31 and a second inverter signal generation unit based on the first inverter command signal i _ref , the ripple current i _r , and the second AC voltage V _ac. The function of selecting one second inverter command signal V _ref from the six types of inverter modulation signals corresponding to the six types of modes 1 to 6 supplied from 32 and supplying this signal to the gate signal generation unit 35 have. Further, the gate signal generation unit 35 applies the PWM signal V _g (=) to each gate input of the NPN transistors 11 to 14 in the bridge circuit 10 based on the inverter command modulation V _ref selected by the inverter command signal selection unit 34. V _{gl +} , V _{g2 +} , V _g2− , V _gl− ).

(Operation of comparative example)
FIGS. 2A and 2B are diagrams for explaining the operation of the comparative example. FIG. 2A shows an inverter modulation signal m _ref (=) normalized by the DC link voltage V _dc. (V _ref / V _dc ) control timing, (b) to (e) are PWM signal V _g (= V _{gl +} , V _{g2 +} , V _g2− , V _gl− ) control timing, and (f) is the first control timing. The waveform of the alternating voltage, (g) is a time chart showing the waveform of the first alternating current, and (a) to (d) of FIG. 2 (2) are diagrams showing the output waveforms during the control.

Among the NPN transistors 11 to 14 constituting the bridge circuit 10, the NPN transistors 11 and 12 and the NPN transistors 13 and 14 are connected in series when viewed from the input side of the bridge circuit 10. When the NPN transistor 11 and the NPN transistor 12 connected in series or the NPN transistor 13 and the NPN transistor 14 are simultaneously turned on, the load of the power supply is short-circuited (hereinafter referred to as “arm short-circuit”). There is a risk of destruction. Therefore, in FIG. 2A, for example, the _dead time T _{d is set} so that the PWM signals V _{gl +} and V _g1− input to the respective bases of the NPN transistor 11 and the NPN transistor 12 connected in series are not _brought into conduction. Has been inserted. Similarly, for the PWM signals V _{g2 +} and V _g2− , a dead time _Td is inserted in order to prevent an arm short circuit.

2 (2) shows a second waveform of the AC voltage _{V ac} and the second alternating current _{i o} in the case of the control of FIG. 2 (1). The influence of the dead time T _d, the second alternating current i _o, harmonic distortion is observed.

(Operation of Example 1)
The operation of the inverter device according to the first embodiment will be described below with reference to FIGS.

  FIG. 3 is a functional block diagram modeling the main part of the inverter device of FIG.

The first inverter command signal generation unit 31 includes a subtractor 31a, a PI control unit 31b, and an adder 31c. In cooperation with the subtractor 31a, the PI control unit 31b, and the adder 31c, the output of the PI control unit 31b so that the difference between the first inverter command signal i _ref and the first alternating current i _inv decreases. _{Is controlled} to generate the inverter modulation signal V _ref . The second inverter command signal generation unit 32 includes a mode (hereinafter referred to as “MOD”) MOD2 function block 32a, MOD3 function block 32b, MOD4 function block 32c, and MOD5 function block 32d. The inverter command selection unit 34 includes switches 34a to 34f. The gate signal generation unit 35 includes a division unit 35a (1 / V _dc ) 35a, a PWM control unit 35b, and a drive circuit unit 35c. The bridge circuit 10 is connected to the filter circuit 20.

In the first embodiment, the control transitions between six MOD1, MOD2, MOD3, MOD4, MOD5 and MOD6, and each of MOD1 to MOD6 is defined by the following conditions.
MOD1: i _r / 2 <i _ref
MOD2: 0 ≦ i _ref ≦ i _r / 2 and 0 ≦ V _ac
MOD3: 0 ≦ i _ref ≦ i _r / 2 and V _ac <0
MOD4: −i _r / 2 ≦ i _ref <0 and V _ac <0
MOD5: −i _r / 2 ≦ i _ref <0 and 0 ≦ V _ac
MOD6: i _ref <−i _r / 2

_{Here, i ref} is the magnitude of the first inverter command signal, _{i r} is the ripple _current, the _{V ac} is the magnitude of the second AC voltage.

In the case of MOD1 and MOD6, the output signal of the first inverter command signal generation unit 31 is selected by the inverter command signal selection unit 34 as the inverter modulation signal _Vref . Based on the inverter modulation signal V _ref , the gate signal generation unit 35 uses the division unit (1 / V _dc ) 35a, the PWM control unit 35b, and the drive circuit unit 35c to generate the PWM signals V _g (= V _{gl +} , V _{g2 +} , V _g2− , V _gl− ) are output.

  4A to 4G are time charts showing the control timing of the first control unit 30 in the case of MOD1 in FIG.

4A shows the inverter modulation signal m _ref (= V _ref , / V _dc ) normalized by the DC link voltage V _dc , FIG. 4B shows the PWM signal V _{gl +} , and _FIG . _4C shows the PWM signal V _g1- (D) shows the waveform of the PWM signal V _{g2 +} , (e) shows the waveform of the PWM signal V _g2- , (f) shows the first AC voltage V _inv , and (g) shows the waveform of the first AC current i _inv , respectively. . In the case of MOD6, since the operation is the same as that in the case of MOD1, the time chart for MOD6 is omitted.

In the case of MOD1 and MOD6, the first AC current i _inv detected by the current detector 23 is supplied to the first inverter command signal generation unit 31, and the closed loop control is performed. The first inverter command signal generation unit 31 outputs the inverter modulation signal V _ref so that the difference between the first inverter command signal i _ref and the first alternating current i _inv decreases.

In the case of MODs 2, 3, 4, and 5, the output signal of the second inverter command signal generation unit 32 is selected as the inverter modulation signal V _ref by the inverter command signal selection unit 34. The gate signal generation unit 35 outputs a PWM signal V _g (= V _{gl +} , V _{g2 +} , V _g2− , V _gl− ) based on the inverter modulation signal V _ref .

  (A)-(g) of FIG. 5 is a time chart which shows the control timing of the 1st control part 30 in the case of MOD2.

5A shows the inverter modulation signal m _ref (= V _ref / V _dc ) normalized by the DC link voltage V _dc , FIG. 5B shows the PWM signal V _{gl +} , and _FIG . _5C shows the PWM signal V _g1− , ( d) shows the waveform of the PWM signal V _{g2 +} , (e) shows the PWM signal V _g2- , (f) shows the waveform of the first AC voltage V _inv , and (g) shows the waveform of the first AC current i _inv , respectively. In the case of MOD3 to 5, since the operation is the same as that in the case of MOD2, the time chart for MOD3 to 5 is omitted.

In the case of MOD2 to MOD5, the second inverter command signal generation unit 32 generates the inverter modulation signal V _ref only by the first inverter command signal i _ref , so that the open loop control is performed.

6, ₊ first inverter command signal _{i ref} and the PWM signal _V gl in Fig. 1, V g2 _{+, V G2-,} and is a waveform diagram showing a relationship between _{V GL-.}

When the first inverter command signal i _ref is positive, the NPN transistors 12 and 13 are turned off, and the NPN transistors 11 and 14 are on / off controlled. When the first inverter command signal i _ref is negative, the NPN transistors 11 and 14 are turned off, and the NPN transistors 12 and 13 are on / off controlled. Since there is no fear of the NPN transistor 11 and the NPN transistor 12 and the NPN transistor 13 and the NPN transistor 14 being simultaneously turned on, no dead time is inserted.

  FIG. 7 is a block diagram in which the first control unit 30 in FIG. 3 is mathematically modeled based on the results of FIGS.

The figure is a mathematical model for representing the relationship between the inverter command signal V _ref and the first alternating current i _inv . It is a mathematical model when the inverter command signal i _ref is the average value of the first alternating current i _inv / i _inv . The MOD1 block 31-1, the MOD2 block 32a, the MOD3 block 32b, the MOD4 block 32c, the MOD5 block 32d, and the MOD6 block 31-2 correspond to MOD1 to MOD6, respectively, and the first alternating current i _inv of the following equation Is output.
MOD1: i _inv = (1 / (s · L _f )) · (V _ref −V _ac ) + _ir / 2
MOD2: i _inv = (V _ref / V _ac ) ² · (i _r / 2)
MOD3: i _inv = ((V _ref + V _dc ) / (V _ac + V _dc )) ² · (i _r / 2)
MOD4: i _inv = − (V _ref / V _ac ) ² · (i _r / 2)
MOD5: i _inv = − ((V _ref −V _dc ) / (V _ac −V _dc )) ² · (i _r / 2)
_{MOD6: i inv = (1 /} (s · L f)) · (V ref -V ac) -i r / 2

Here, s is a Laplace operator, i _inv is the magnitude of the first alternating current, L _f is the value of the inductance of the filter circuit 20, V _ref is the magnitude of the inverter modulation signal, and V _ac is the second alternating current. the size of, i _r denotes the magnitude of the ripple current in the inductor, respectively.

  The inverter command signal selection unit 33 is represented by switches 34a to 34f.

(Simulation result of Example 1)
A simulation result of the inverter device according to the first embodiment of the present invention will be described below with reference to FIGS.

  FIG. 8 is a waveform diagram showing an output waveform at the time of control according to the first embodiment by conventional general PI control.

  8 (1) and 8 (2) are output waveforms when only PI control is used as a comparative example in FIG. 3, and shows a case of rated output and a case of 20% rated output.

(A) to (d) in FIG. 8 (1) show the case of rated output, and (a) to (d) of FIG. 8 (2) show the case of 20% rated output. 8 (1) and (2), (a) is the second AC voltage V _ac , (b) is the second AC current i _o , (c) is the PWM number V _{gl +} , and (d) is the PWM. Signal _Vg1- .

Focusing on the second alternating current i _o , the output waveform of the 20% rated output has higher harmonic distortion than the second alternating current i _o at the rated output.

FIGS. 9A and 9B are waveform diagrams showing waveforms of the output current i _o and the PWM signal V _g at the rated output.

(A) to (e) of FIG. 9 (1) show the case of the control of the comparative example, and (a) to (e) of FIG. 9 (2) show the case of the control of the first embodiment. 9 (1) and 9 (2), (a) is the second AC current i _o , (b) is the PWM signal V _{gl +} , (c) is the PWM signal V _g1− , and (d) is the PWM signal V _{g2 +.} , And (e) show the waveform of the PWM signal V _g2- , respectively.

  The total harmonic distortion (THD) in the control of the comparative example is 3.0%, whereas the total harmonic distortion in the control of the first embodiment is 0.5%. The total harmonic distortion (THD) in the case of the control of the first embodiment is greatly improved as compared with the total harmonic distortion (THD) in the case of the control of the comparative example.

FIGS. 10A and 10B are waveform diagrams showing waveforms of the output current i _o and the PWM signal V _g at the 10% rated output.

(A) to (e) of FIG. 10 (1) show the case of the control of the comparative example, and (a) to (e) of FIG. 10 (2) show the case of the control of the first embodiment. 10 (1) and 10 (2), (a) is the second alternating current i _o , (b) is the PWM signal V _{gl +} , (c) is the PWM signal V _g1− , and (d) is the PWM signal V _{g2 +.} , And (e) show the waveform of the PWM signal V _g2- , respectively.

  The total harmonic distortion (THD) in the control of the comparative example is 11.5%, whereas the total harmonic distortion (THD) in the control of the first embodiment is 3.9%. The total harmonic distortion (THD) in the case of the control of the first embodiment is greatly improved as compared with the total harmonic distortion (THD) in the case of the control of the comparative example.

  FIG. 11 is a characteristic comparison diagram showing a comparison of total harmonic distortion by the control of FIG. 3 and the control of the comparative example.

  In the range of 5% to 100% of the output rating, the total harmonic distortion (THD) in the case of the control of the first embodiment is greatly improved compared to the total harmonic distortion in the case of the control of the comparative example. .

(Results of demonstration experiment of Example 1)
The result of the verification experiment performed on the inverter device of FIGS. 1 and 3 will be described below with reference to FIGS.

FIGS. 12A and 12B are waveform diagrams showing waveforms of the second AC signal (V _ac , i _o ) and the PWM signal showing the results of the demonstration experiment.

(A) to (d) in FIG. 12 (1) show waveforms at the rated output, and (a) to (d) in FIG. 12 (2) show waveforms at the 20% rated output. 12 (1) and 12 (2), (a) is a second AC voltage V _ac , (b) is a second AC current i _o , (c) is a PWM signal V _{gl +} , and (d) is a PWM signal. The waveform of V _g1− is shown as shifted.

  FIG. 13 is a characteristic comparison diagram showing a characteristic comparison of total harmonic distortion (THD) by the demonstration experiment of FIGS. 1 and 3.

  The total harmonic distortion (THD) in the case of the control of the first embodiment is greatly improved as compared with the total harmonic distortion (THD) in the case of the control of the comparative example.

FIG. 14 is a waveform diagram showing an inductor current waveform at the time of 3 kW output.
FIG. 14 (1) shows the case of the control of the comparative example, FIG. 14 (2) shows the case of the control of the embodiment 1, (a) shows the inductor current waveform, and (b) shows the output current waveform.

It can be observed that the ripple component of the inductor current is smaller in the case of the control of the first embodiment than in the case of the control of the comparative example. Inductor current current by subtracting the output current (b) from (a) is a ripple current i _r of the inductor.

Figure 15 is a characteristic comparison diagram showing a characteristic comparison of the ripple current i _r of the inductor to the rated load factor (output current / rated current).

15, (a) shows the case of control of Comparative Example, (b) each of the characteristics of the ripple current i _r of the inductor with respect to the rated load factor in the case of the control of the first embodiment (the output current / rated current) Show.

Ripple current i _r inductor when the control of the first embodiment, compared with the ripple current i _r inductor when the control of the comparative example, is improved by about 20%.

  FIG. 16 is a characteristic comparison diagram showing a characteristic comparison of efficiency with respect to the rated load factor (output current / rated current).

  In FIG. 16, (a) shows the efficiency in the case of the control of the first embodiment, and (b) shows the efficiency in the case of the control of the comparative example.

  The efficiency in the case of the control of the first embodiment is improved as compared with the efficiency in the case of the control of the comparative example. In particular, it is greatly improved in the small current output region.

FIG. 17 is a characteristic diagram showing efficiency characteristics when the first DC voltage V _dc that is the input current of FIG. 1 is changed.

  From this characteristic diagram, it can be confirmed that the conversion efficiency can be improved when the DC link voltage is reduced. In the case of the first embodiment, since the same output is performed, the DC link voltage can be reduced, so that the conversion efficiency of the apparatus can be improved.

(Effect of Example 1)
According to the first embodiment, in order to prevent the arm short circuit, since it is not necessary to provide a dead time, total harmonic distortion, the ripple current i _r, compared with the control in the comparative example, it is possible to greatly improve . In particular, the rated output, if the output current i _o is small, total harmonic distortion, and the effect of improving the ripple current i _r is remarkable. Furthermore, since the DC link voltage can be minimized, the efficiency can be improved and the DC link capacitor 3 can be miniaturized.

(Modification of Example 1)
The bridge circuit 10 of FIG. 1 may be configured by a unipolar transistor such as a PNP transistor or a MOS transistor instead of the NPN transistors 11 to 14. Further, not only a full-bridge inverter device but also a half-bridge inverter (two switches) and a three-phase full-bridge inverter device (six switches) are possible. Thereby, substantially the same operation and effect as the first embodiment can be achieved.

(Configuration and operation of embodiment 2)
FIG. 18 is a block diagram showing the configuration of the inverter device according to the second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

In the inverter device according to the second embodiment, a first control unit 30A having a different configuration from that of the first control unit 30 according to the first embodiment is provided. In the first control unit 30A of the second embodiment, a DC link voltage command generation unit 36 and a DC link voltage control unit 37 are added to the first control unit 30 of the first embodiment. The DC link voltage command generation unit 36 receives the detection signal V _ac of the voltage detector 24 and generates a first DC voltage command signal V _{dcref in} which a safety margin is added to the peak value of the second AC voltage Vac. , And has a function of outputting to the DC link voltage control unit 37. The DC link voltage control unit 37 _adjusts the first inverter command signal i _ref so that the DC link voltage V _dc matches the first DC voltage command signal V _dcref, and the second inverter command signal i _{refA is adjusted.} It has a function to output. The second inverter command signal i _refA is _supplied to the first inverter command signal generation unit 31 and the second inverter command signal generation unit 32, and the inverter modulation signal V _ref is selected by the inverter command signal selection unit 34. The Other configurations are the same as those of the first embodiment.

(Effect of Example 2)
According to the second embodiment, the DC link voltage can always be minimized regardless of the change in the AC voltage by performing the control with the stability margin added to the peak value of the AC voltage, so that the efficiency of the inverter can be increased. Can be planned.

(Configuration of Example 3)
FIG. 19 is a block diagram showing the configuration of the inverter device according to the third embodiment of the present invention. Elements common to those in FIG. 1 illustrating the first embodiment are denoted by common reference numerals.

  In the inverter device of this embodiment, the DC link voltage command generation unit 36 and the DC link voltage control unit 37 in FIG. 18 are removed, and the second control unit 40 having substantially the same function is replaced with the first control. It is provided outside the portion 30.

The second control unit 40 generates a second DC signal command value V _{DC / DC in} which a safety margin is added to the peak value of the second AC voltage (V _ac ), and the output voltage of the DC / DC converter 2. It has a function to control the level.

  According to this embodiment, the same operations and effects as those of Embodiment 2 can be achieved.

1 DC power supply (for example, solar PV)
2 DC / DC converter 3 Electrolytic capacitor 10 Bridge circuit 11-14 First to fourth switch 20 Filter circuit 21 Current detector 22 Voltage detector 30, 30A First control unit 31 First inverter control signal generation unit 32 Second inverter control signal generation unit 33 Ripple current calculation unit 34 Inverter command signal selection unit 35 Gate signal generation unit 36 DC link voltage command generation unit 37 DC link voltage control unit 15, 31a Subtractor 40 Second control unit 50 AC system

Claims (6)

A plurality of switches are bridge-connected, and based on the pulse width modulation signal, a bridge circuit that converts the input first DC signal into a first AC signal;
A filter circuit for filtering the first AC signal and outputting a second AC signal;
A first control unit for controlling the on / off of the plurality of switches based on a first inverter command signal and outputting the pulse width modulation signal by the bridge circuit;
With
The first controller is
According to the value of the first inverter command signal, on / off control of the plurality of switches,
When the value of the first inverter command signal exceeds a threshold value, the bridge circuit is closed-loop controlled,
When the value of the first inverter command signal is equal to or less than the threshold, the bridge circuit is subjected to open loop control. The first controller is
When the value of the first inverter command signal is positive, one of the switches is turned off and the other switch is turned on / off. When the value of the first inverter command signal is negative , The other switch is turned off, and the one switch is turned on / off,
When the value of the first inverter command signal exceeds the threshold value, the bridge circuit is closed-loop controlled based on the first inverter command signal and the first AC signal,
2. The inverter device according to claim 1, wherein when the value of the first inverter command signal is equal to or less than the threshold value, the bridge circuit is set to open loop control based on the first inverter command signal. .   The inverter device according to claim 1, wherein the threshold value is a half value of a switching ripple current generated from the second AC signal and the first DC signal. When the first inverter command signal exceeds the threshold value, the bridge circuit is controlled based on the closed loop control,
When the first inverter command signal is less than the threshold value, the pulse width modulation signal is set according to a plurality of cases determined by the positive / negative of the first inverter command signal and the positive / negative of the second AC signal. The inverter device according to claim 1, wherein the inverter device is generated. The inverter device according to any one of claims 1 to 4,
A converter that converts the level of a second DC signal output from the DC voltage source and outputs the first DC signal;
The first control unit generates a first DC voltage command signal obtained by adding a stability margin to the peak value of the second AC signal, and the first DC signal and the DC voltage command signal coincide with each other. And generating a second inverter command signal obtained by adjusting the first inverter command signal, and performing control based on the second inverter command signal instead of the first inverter command signal. Inverter device. The inverter device according to any one of claims 1 to 4,
A converter that converts a level of a second DC signal output from a DC voltage source and outputs the first DC signal;
The first control unit generates a second DC signal command value obtained by adding a stability margin to the peak value of the second AC signal, and an input level of the first DC signal that is an output of the converter A second control unit for controlling
An inverter device comprising:

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