JP2012174950A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a semiconductor structure called SOI, which is less likely to be restricted in circuit design to set a lower surface of a semiconductor substrate of the semiconductor structure to ground potential.SOLUTION: A semiconductor device comprises a multilayer printed board 12 and a semiconductor structure 31 called SOI mounted in a recess 15 provided on the side of a lower surface of the multilayer printed board 12 in a face-up manner. Further, the semiconductor structure 31 is mounted on a printed wiring board 1 by connection of a center part of a lower surface of a semiconductor substrate 33 with ground wiring 3 of the printed wiring board 1 via a conductive adhesive layer 43 arranged below the lower surface of the semiconductor substrate 33. In this case, it is almost unnecessary to regard a routing line for ground. Accordingly, it becomes possible to cause the semiconductor device to be less likely to be restricted in circuit design to set the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 to ground potential.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Some conventional semiconductor devices have a semiconductor structure called a CSP (chip size package) fixed on a base plate larger in size than the semiconductor structure (see, for example, Patent Document 1). In this case, an insulating layer is provided on the base plate around the semiconductor structure. An upper insulating film is provided on the semiconductor structure and the insulating layer. On the upper insulating film, an upper layer wiring is provided connected to the external connection electrode of the semiconductor structure. An upper overcoat film is provided on the upper surface of the upper insulating film excluding the land of the upper wiring. Solder bumps are provided on the lands of the upper layer wiring.

  In this case, the semiconductor structure is called SOI (Silicon on Insulator), and includes an insulating film provided on the semiconductor substrate and an integrated circuit portion formed by forming a thin film transistor on the insulating film. Yes. In this semiconductor structure, in order to stabilize the potential of the semiconductor substrate due to the characteristics of the integrated circuit portion, it is necessary to set the back surface (surface opposite to the circuit formation surface) of the semiconductor substrate to the ground potential.

  Therefore, in the conventional semiconductor device, a ground layer is provided on the upper surface of the base plate. A semiconductor structure is provided on the upper surface of the ground layer via an insulating adhesive layer. The ground layer is connected to the upper layer wiring for ground via a vertical conduction member provided in the insulating layer. The lower surface of the semiconductor substrate of the semiconductor structure is connected to the upper surface of the ground layer via connection electrodes provided on the insulating adhesive layer. Thereby, the lower surface (back surface) of the semiconductor substrate is set to the ground potential.

JP 2007-35989 A

  However, in the above-described conventional semiconductor device, the lower surface of the semiconductor substrate of the semiconductor structure includes the connection electrodes provided on the insulating adhesive layer, the ground layer provided on the upper surface of the base plate, and the vertical conduction member provided on the insulating layer. Since the ground wiring is connected to the upper layer wiring for the ground, the ground wiring is routed from the lower surface side of the semiconductor structure to the upper surface side of the semiconductor structure, and the circuit design is restricted. There is a problem.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can be made less susceptible to restrictions on circuit design for setting a semiconductor substrate of a semiconductor structure to a ground potential.

According to a first aspect of the present invention, there is provided a semiconductor device including a circuit board provided with a ground wiring and a wiring other than the ground wiring, a multilayer substrate having a concave portion on one surface, and an SOI substrate accommodated in the concave portion. A wiring provided on the one surface of the multilayer substrate other than the concave portion is connected to the wiring on the circuit board through a first bonding member, and the SOI substrate is It is connected to the ground wiring of the circuit board through a second bonding member.
According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a circuit board provided with a ground wiring and a wiring other than the ground wiring; a multilayer substrate having a recess on one surface; Preparing a semiconductor structure having an SOI substrate, and connecting a wiring provided other than the recess on the one surface of the multilayer substrate to the wiring of the circuit board via a first bonding member, In addition, the SOI substrate is connected to the ground wiring of the circuit board through a second bonding member.

  According to this invention, since the SOI substrate of the semiconductor structure is connected to the ground wiring of the circuit board via the second bonding member, the SOI substrate of the semiconductor structure is set to the ground potential. There is almost no need to consider the ground lead line, and therefore it is possible to make it difficult to be restricted by the circuit design for setting the SOI substrate of the semiconductor structure to the ground potential.

1 is a cross-sectional view of a semiconductor device as an embodiment of the present invention. Sectional drawing of what was initially prepared in an example of the manufacturing method of the semiconductor device shown in FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. Sectional drawing of the process following FIG. FIG. 9 is a cross-sectional view of the process following FIG. 8.

  FIG. 1 is a sectional view of a semiconductor device as an embodiment of the present invention. In brief, in this semiconductor device, a semiconductor device body 11 including a multilayer printed wiring board (multilayer board) 12 and a semiconductor structure 31 is provided on a printed wiring board (circuit board) 1, and the multilayer printed wiring board 12. Two chip components (electronic components) 51 are provided above, and a shield cover 61 is provided on the multilayer printed wiring board 12 so as to cover the two chip components 51.

  First, the printed wiring board 1 will be described. The printed wiring board 1 includes a planar rectangular insulating substrate 2 made of a glass cloth base epoxy resin or the like. A ground wiring 3 made of copper or the like and other wiring 4 are provided on the upper surface of the insulating substrate 2. In this case, the land of the wiring 4 is arranged around the land of the ground wiring 3 in FIG. An overcoat film 5 made of a solder resist or the like is provided on the upper surface of the insulating substrate 2 excluding the land of the ground wiring 3 and the land of the wiring 4, and the land of the ground wiring 3 and the land of the wiring 4 are provided on the overcoat film 5. The first opening 6 and the second opening 7 are exposed.

  Next, the semiconductor device body 11 will be described. The semiconductor device body 11 includes a planar rectangular printed wiring board (multilayer substrate) 12. The multilayer printed wiring board 12 has a structure in which a plurality of, for example, six insulating substrates 13 and one more wiring 14 are alternately stacked. In this case, the insulating substrate 13 is made of a glass cloth base epoxy resin or the like. The wiring 14 is made of copper or the like. Here, the uppermost layer wiring is composed of the uppermost layer ground wiring 14a and the other uppermost layer wiring 14b. The outermost part of the uppermost ground wiring 14a has a rectangular frame shape.

  A flat rectangular recess 15 is provided at the center of the lower surface side of the multilayer printed wiring board 12. In this case, since the recesses 15 are provided in the lower four insulating substrates 13, the wiring 14 located in the recess 15 on the lower surface of the fifth insulating substrate 13 from the bottom is exposed. An overcoat film 16 made of a solder resist or the like is provided on the lower surface of the fifth insulating substrate 13 including the exposed wiring 14 from the bottom. An opening 17 is provided in the overcoat film 16 in a portion corresponding to the land of the exposed wiring 14.

  In the multilayer printed wiring board 12, an upper overcoat film 18 made of a solder resist or the like is provided on the upper surface of the uppermost insulating substrate 13 including the uppermost ground wiring 14a and the uppermost wiring 14b. A third opening 19 and a fourth opening 20 are provided in the upper overcoat film 18 in the outermost portion of the uppermost ground wiring 14a and the portion corresponding to the land of the uppermost wiring 14b.

  In a portion other than the recess 15 of the multilayer printed wiring board 12, a lower overcoat film 21 made of a solder resist or the like is provided on the lower surface of the lowermost insulating substrate 13 including the lowermost wiring 14. An opening 22 is provided in the lower overcoat film 21 in a portion corresponding to the land of the lowermost wiring 14. Here, the lower overcoat film 21 in the portion corresponding to the recess 15 is provided with an opening that substantially constitutes the lower portion of the recess 15. That is, the recess 15 is substantially provided in the lower four insulating substrates 13 and the lower overcoat film 21.

  A semiconductor structure 31 is disposed under the overcoat film 16 in the recess 15. The semiconductor structure 31 is generally called a CSP and includes an SOI substrate 32. The SOI substrate 32 is a substrate having a structure in which silicon oxide or the like is inserted between a silicon substrate and a surface silicon layer. Since the parasitic capacitance of the transistor can be reduced, the operation speed is improved and the power consumption is reduced.

  Specifically, the SOI substrate 32 is provided with an insulating film 34 made of silicon oxide or the like on the upper surface of a planar rectangular semiconductor substrate 33 made of silicon, and made of silicon like the semiconductor substrate 33 on the upper surface of the insulating film 34. A semiconductor layer 65 is provided, and an integrated circuit portion 35 formed by forming a thin film transistor on the upper surface of the semiconductor layer 65 is provided. The semiconductor layer 65 and the integrated circuit portion 35 may be separate or integrated.

  A plurality of connection pads 36 made of aluminum-based metal or the like are provided on the periphery of the upper surface of the integrated circuit portion 35 so as to be connected to the integrated circuit portion 35. Although not shown in detail, an insulating film 37 composed of two layers of a passivation film and a resin protective film is provided on the upper surface of the integrated circuit part 35 excluding the central part of the connection pad 36. A plurality of wirings 38 made of copper or the like are provided on the upper surface of the insulating film 37. One end of the wiring 38 is connected to the connection pad 36 through an opening provided in the insulating film 37, and the other end is a land.

  A columnar external connection electrode 39 made of copper is provided on the upper surface of the land of the wiring 38. On the upper surface of the insulating film 37 including the wiring 38, a sealing film 40 made of an epoxy resin containing silica filler or the like is provided around the external connection electrode 39. A solder bump (third bonding member) 41 is provided on the upper surface of the external connection electrode 39.

  Then, the solder bump 41 is bonded to the land of the wiring 14 exposed through the opening 17 of the overcoat film 16, so that the semiconductor structure 31 has a face under the overcoat film 16 in the recess 15. It is mounted by the up method. In this state, the lower surface of the semiconductor structure 31 is located above the lower surface of the lower overcoat film 21.

  The semiconductor device main body 11 includes a solder layer (first layer) in which the land of the lowermost wiring 14 of the multilayer printed wiring board 12 is provided in and above the second opening 7 of the overcoat film 5 of the printed wiring board 1. Conductive adhesive layer (second bonding member) which is bonded to the land of the wiring 4 via the first bonding member 42 and the central portion of the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 is disposed thereunder. It is mounted on the printed wiring board 1 by being bonded to the land of the ground wiring 3 exposed through the first opening 6 of the overcoat film 5 of the printed wiring board 1 through 43.

  The conductive adhesive layer 43 is formed by dispersing conductive particles made of silver, copper, carbon or the like in a binder made of a thermosetting resin such as an epoxy resin. In this state, the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 is connected to the ground wiring 3 of the printed wiring board 1 through the conductive adhesive layer 43 so that the ground potential is reached. Yes.

  Next, the chip component 51 will be described. The chip component 51 includes a capacitor, a resistor, and the like. Then, the chip component 51 has its electrodes 52 and 53 in the upper layer wiring 14b of the multilayer printed wiring board 12 through the solder layer 54 provided in and above the fourth opening 20 of the upper overcoat film 18. It is mounted on the upper overcoat film 18 by being connected to this land.

  Next, the shield cover 61 will be described. The shield cover 61 is made of a metal such as aluminum, and is formed by providing a flange portion 63 at the lower end portion of a headed rectangular tube-shaped cover body 62. The shield cover 61 has the lower surface of the flange portion 63 connected to the outermost layer of the uppermost ground wiring 14a via the solder layer 64 provided in and above the third opening 19 of the upper overcoat film 18. As a result, the upper overcoat film 18 is provided. In this state, the two chip components 51 are covered with the shield cover 61 and are electromagnetically cut off from the outside.

  As described above, in this semiconductor device, by connecting the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 to the ground wiring 3 of the printed wiring board 1 through the conductive adhesive layer 43 disposed thereunder, Since the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 is set to the ground potential, there is almost no need to consider the ground lead line. Therefore, the lower surface of the semiconductor substrate 33 of the semiconductor structure 31 is set to the ground potential. Therefore, it is possible to make the circuit design difficult to be restricted.

  Next, an example of a method for manufacturing a semiconductor device will be described. First, the printed wiring board 1, the multilayer printed wiring board 12, the semiconductor component 31, the two chip components 51, and the shield cover 61 are prepared. In this case, a concave portion 15 is provided in the center portion on the lower surface side of the multilayer printed wiring board 12. The semiconductor structure 31 includes solder bumps 41.

  Next, as shown in FIG. 2, in the state where the multilayer printed wiring board 12 is turned upside down so that the concave portion 15 is on the upper side, the solder bump 41 is turned upside down in the concave portion 15 of the multilayer printed wiring board 12. The semiconductor structure 31 in the state of the lower side is simply positioned and aligned. Next, as shown in FIG. 3, when reflow is performed, the solder bumps 41 of the semiconductor structure 31 are joined to the exposed wirings 14 through the openings 17 of the overcoat film 16, so that a multilayer printed wiring is obtained. A semiconductor structure 31 is mounted on the overcoat film 16 in the recess 15 of the plate 12 by a face-down method.

  Next, when the multilayer printed wiring board 12 is turned upside down, as shown in FIG. 4, the recess 15 is on the lower side, and the semiconductor structure 31 is mounted in the recess 15 in a face-up manner. Next, as shown in FIG. 5, a screen printing method or dispenser using a cream solder printer (screen printer) is used in and above the third and fourth openings 19 and 20 of the upper overcoat film 18. As a result, the solder paste 54a and 64a are applied by adding flux to the solder powder to obtain an appropriate viscosity. Next, as shown in FIG. 6, the chip component 51 is simply positioned and placed on the cream solder 54a. Next, the shield cover 61 is positioned and simply placed on the cream solder 64a.

  Next, as shown in FIG. 7, when reflow is performed, both electrodes 52 and 53 of the chip component 51 are joined to the land of the uppermost wiring 14b of the multilayer printed wiring board 12 via the solder layer 54, and The lower surface of the flange portion 63 of the shield cover 61 is joined to the uppermost ground wiring 14 a of the multilayer printed wiring board 12 via the solder layer 64, so that the chip component 51 and the shield cover 61 are formed on the multilayer printed wiring board 12. Installed.

  Next, as shown in FIG. 8, cream solder 42 a is applied by using a screen printing method or a dispenser in and above the second opening 7 of the upper overcoat film 5 of the upper layer 5 of the printed wiring board 1. Next, a conductive adhesive 43a containing an uncured thermosetting resin is applied by using a dispenser in and above the first opening 6 of the upper overcoat film 5 of the printed wiring board 1. .

  Next, as shown in FIG. 9, the semiconductor device main body 11 in the state shown in FIG. 7 is simply positioned and placed on the cream solder 42a and the conductive adhesive 43a. Next, as shown in FIG. 1, when reflow is performed, the lowermost layer wiring 14 of the multilayer printed wiring board 12 is bonded to the land of the wiring 4 of the printed wiring board 1 through the solder layer 42, and is conductive. The thermosetting resin in the adhesive 43 a is cured, and the lower surface of the semiconductor structure 31 is bonded to the land of the ground wiring 3 of the printed wiring board 1 through the conductive adhesive layer 43, whereby the printed wiring board 1. The semiconductor device body 11 is mounted on the top. In this case, a dedicated process for curing the thermosetting resin in the conductive adhesive is not required. Thus, the semiconductor device shown in FIG. 1 is obtained.

  Instead of the solder layer 42, a solder bump is provided in advance under the land of the lowermost layer wiring 14 of the multilayer printed wiring board 12, and the lowermost layer wiring 14 of the multilayer printed wiring board 12 is interposed via the solder bump. May be joined to the land of the wiring 4 of the printed wiring board 1.

  The embodiment of the present invention has been described above. However, the present invention is not limited to this, and includes the invention described in the claims and the equivalent scope thereof. Hereinafter, the invention described in the scope of claims of the present application will be appended.

(Appendix)
The invention according to claim 1 is a circuit board provided with ground wiring and wiring other than the ground wiring,
A multilayer substrate having a recess on one side;
A semiconductor structure housed in the recess and having an SOI substrate;
Comprising
Wiring provided other than the concave portion on the one surface of the multilayer board is connected to the wiring of the circuit board via a first bonding member,
The SOI substrate is a semiconductor device characterized in that the SOI substrate is connected to the ground wiring of the circuit board through a second bonding member.

The invention according to claim 2 is the semiconductor device according to claim 1, wherein the SOI substrate includes a semiconductor substrate, an insulating film, and an integrated circuit portion.
A wiring provided at a position corresponding to the concave portion on the one surface of the multilayer substrate and a wiring provided in the semiconductor structure are electrically connected via a third bonding member,
The semiconductor device is characterized in that the first joining member is solder, the second joining member is a conductive adhesive, and the third joining member is a solder bump.

  According to a third aspect of the present invention, in the second aspect of the present invention, the semiconductor structure includes an external connection electrode provided on the integrated circuit portion, and a seal provided around the external connection electrode. In the recess of the multilayer substrate, the solder bump is provided on the stop film and the external connection electrode, and the solder bump is connected to the wiring exposed in the recess of the multilayer substrate. The semiconductor device is mounted in a face-up manner.

  The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the lower surface of the semiconductor structure is located above the lower surface of the multilayer substrate. It is a semiconductor device.

  According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, an electronic component is connected to the uppermost layer wiring of the multilayer board via a solder layer. A semiconductor device is provided.

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, a shield cover is provided on the multilayer substrate so as to cover the electronic component, and a lower end portion of the shield cover is an outermost portion of the multilayer substrate. A semiconductor device is characterized in that it is connected to an upper ground wiring via a solder layer.

The invention according to claim 7 is a circuit board provided with a ground wiring and wiring other than the ground wiring,
A multilayer substrate having a recess on one side;
A semiconductor structure housed in the recess and having an SOI substrate;
Prepare
Wirings other than the recesses on the one surface of the multilayer substrate are connected to the wirings of the circuit board via a first bonding member, and the SOI substrate is bonded to a second bonding member. And connecting to the ground wiring of the circuit board through the semiconductor device manufacturing method.

The invention according to claim 8 is the invention according to claim 7, wherein the SOI substrate includes a semiconductor substrate, an insulating film, and an integrated circuit portion,
Electrically connecting a wiring provided at a position corresponding to the concave portion on the one surface of the multilayer substrate and a wiring provided in the semiconductor structure via a third bonding member;
Wirings other than the recesses on the one surface of the multilayer substrate are connected to the wirings of the circuit board via a first bonding member, and the SOI substrate is bonded to a second bonding member. The step of connecting to the ground wiring of the circuit board through the step of applying the first bonding member on the land of the wiring of the circuit board and the second of the land on the land of the ground wiring of the circuit board. A method of manufacturing a semiconductor device comprising a step of applying a joining member and performing reflow.

  The invention according to claim 9 is the invention according to claim 8, wherein the first joining member is solder, the second joining member is either a conductive adhesive or solder, 3 is a method for manufacturing a semiconductor device, wherein the bonding member 3 is a solder bump.

  According to a tenth aspect of the present invention, in the ninth aspect of the invention, the semiconductor structure includes an external connection electrode provided on the integrated circuit portion, and a seal provided around the external connection electrode. The solder bump provided on the stop film and the external connection electrode is provided, and the solder bump is connected to the wiring exposed in the recess of the multilayer substrate. A semiconductor device manufacturing method comprising mounting the semiconductor structure.

1 Printed wiring board (circuit board)
2 Insulating substrate 3 Ground wiring 4 Wiring 5 Overcoat film 11 Semiconductor device body 12 Multilayer printed wiring board (multilayer substrate)
13 Insulating substrate 14 Wiring 14a Ground wiring 14b Wiring 15 Recess 16 Overcoat film 18 Upper layer overcoat film 21 Lower layer overcoat film 31 Semiconductor structure 32 SOI substrate 33 Semiconductor substrate 34 Insulating film 35 Integrated circuit part 36 Connection pad 37 Insulating film 38 Wiring 39 External connection electrode 40 Sealing film 41 Solder bump (third bonding member)
42 Solder layer (first bonding member)
43 Conductive adhesive layer (second bonding member)
51 Chip Component 54 Solder Layer 61 Shield Cover 64 Solder Layer 65 Semiconductor Layer

Claims (10)

A circuit board provided with ground wiring and wiring other than the ground wiring;
A multilayer substrate having a recess on one side;
A semiconductor structure housed in the recess and having an SOI substrate;
Comprising
Wiring provided other than the concave portion on the one surface of the multilayer board is connected to the wiring of the circuit board via a first bonding member,
The semiconductor device, wherein the SOI substrate is connected to the ground wiring of the circuit board through a second bonding member. In the invention according to claim 1, the SOI substrate includes a semiconductor substrate, an insulating film, and an integrated circuit portion,
A wiring provided at a position corresponding to the concave portion on the one surface of the multilayer substrate and a wiring provided in the semiconductor structure are electrically connected via a third bonding member,
The semiconductor device according to claim 1, wherein the first joining member is solder, the second joining member is a conductive adhesive, and the third joining member is a solder bump.   3. The semiconductor device according to claim 2, wherein the semiconductor structure includes an external connection electrode provided on the integrated circuit portion, a sealing film provided around the external connection electrode, and the external connection electrode. The solder bumps are mounted on the multi-layer substrate in a face-up manner by being connected to wiring exposed in the recesses of the multilayer substrate. A semiconductor device.   4. The semiconductor device according to claim 1, wherein the lower surface of the semiconductor structure is located above the lower surface of the multilayer substrate. 5.   5. The invention according to claim 1, wherein an electronic component is provided on the multilayer substrate by being connected to the uppermost wiring of the multilayer substrate via a solder layer. Semiconductor device.   6. The invention according to claim 5, wherein a shield cover is provided on the multilayer substrate so as to cover the electronic component, and a lower end portion of the shield cover is connected to an uppermost ground wiring of the multilayer substrate via a solder layer. A semiconductor device characterized by being connected. A circuit board provided with ground wiring and wiring other than the ground wiring;
A multilayer substrate having a recess on one side;
A semiconductor structure housed in the recess and having an SOI substrate;
Prepare
Wirings other than the recesses on the one surface of the multilayer substrate are connected to the wirings of the circuit board via a first bonding member, and the SOI substrate is bonded to a second bonding member. And connecting to the ground wiring of the circuit board through the semiconductor device. In the invention according to claim 7, the SOI substrate includes a semiconductor substrate, an insulating film, and an integrated circuit portion,
Electrically connecting a wiring provided at a position corresponding to the concave portion on the one surface of the multilayer substrate and a wiring provided in the semiconductor structure via a third bonding member;
Wirings other than the recesses on the one surface of the multilayer substrate are connected to the wirings of the circuit board via a first bonding member, and the SOI substrate is bonded to a second bonding member. The step of connecting to the ground wiring of the circuit board through the step of applying the first bonding member on the land of the wiring of the circuit board and the second of the land on the land of the ground wiring of the circuit board. A method for manufacturing a semiconductor device, comprising: applying a joining member and performing reflow.   The invention according to claim 8, wherein the first joining member is solder, the second joining member is either a conductive adhesive or solder, and the third joining member is a solder bump. A method for manufacturing a semiconductor device.   10. The semiconductor device according to claim 9, wherein the semiconductor structure includes an external connection electrode provided on the integrated circuit portion, a sealing film provided around the external connection electrode, and the external connection electrode. Mounting the semiconductor structure in the concave portion of the multilayer substrate by connecting the solder bump to the wiring exposed in the concave portion of the multilayer substrate. A method of manufacturing a semiconductor device.

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