JP2012174949A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high breakdown voltage semiconductor device which can be manufactured by a simple method and in which variation is eliminated in the source-drain breakdown voltage or the on resistance.SOLUTION: A plurality of trenches 11, an N type pillar region 2 formed by diffusing N type impurities contained in a dielectric layer 12 filling the trench 11 into a P type epitaxial layer, and a P type pillar region 3 by the P type epitaxial layer remaining between the diffusion regions are provided on the P type epitaxial layer laminated on a high concentration N type semiconductor substrate 1.

Description

  The present invention relates to a semiconductor device having a so-called super junction structure and a method for manufacturing the same.

  In semiconductor devices in which MOS field effect transistors are formed, attempts have been made to improve breakdown voltage. FIG. 4 is a cross-sectional view of a conventional super junction type semiconductor device in which a MOSFET is formed. Stripes such that a semiconductor layer including an N-type pillar layer 102 and a P-type P-type pillar layer 103 alternately and repeatedly appears in a direction parallel to the semiconductor substrate 101 on an N ++ type semiconductor substrate 101 to be a drain layer. The so-called super junction structure is formed.

  A P-type base region 104 is selectively formed on the surface, and an N-type source region 105 is formed on the surface of each base region 104. A gate electrode 107 is formed on the source region 105 and the base region 104 adjacent to each other from the base region 104 and the source region 105 via the N-type pillar layer 102 via a gate oxide film 106. An interlayer insulating film 108 is formed so as to open the source region 105, and a source electrode 109 connected to the source region 105 is formed. On the other hand, a drain electrode 110 connected to the semiconductor substrate 101 is formed on the back surface.

  FIG. 5 is a sectional view showing the manufacturing process. An N-type semiconductor layer 111 is epitaxially grown to a thickness of 20 μm or more on an N ++ type semiconductor substrate 101 serving as a drain layer, and a plurality of N-type pillar layers 102 are formed in a region where the N-type pillar layer 102 is to be formed. A trench groove 112 is formed. The trench grooves 112 have a depth (about 20 μm) that reaches the vicinity of the interface between the N-type semiconductor layer 111 and the semiconductor substrate 101 and have inner walls that are substantially perpendicular to the surface of the semiconductor substrate 101 and are parallel to each other at equal intervals. Form (FIG. 5a).

  Next, a P-type semiconductor layer 113 is formed by an epitaxial growth technique so as to fill the trench groove 112, and the trench groove 112 is filled with the P-type semiconductor layer 113 (FIG. 5b).

  The N-type pillar layer 102 and the P-type pillar layer 103 are formed by polishing the surface of the P-type semiconductor layer 113 by a CMP (Chemical Mechanical Polish) method (FIG. 5C).

  A P-type base layer 104 in which a MOSFET channel is formed is formed on the surface of the P-type pillar layer 103 (FIG. 5d).

  After forming the gate oxide film 106, a polysilicon film is grown and patterned by the CVD method, thereby forming the gate electrode 107 (FIG. 5e) and further forming the source region 105 made of an N-type semiconductor region (FIG. 5e). FIG. 5f).

  After forming the interlayer insulating film 108, a contact hole 114 is formed (FIG. 5g). After that, the source electrode 109 connected to the source region 105 and the drain electrode 110 connected to the semiconductor substrate 101 are formed, whereby the semiconductor device illustrated in FIG. 4 can be completed.

  In the semiconductor device thus formed, an external load is connected to one of the source electrode 109 and the drain electrode 110, and a voltage is applied by a power source provided between the source electrode 109 and the drain electrode 110 and the load. Used in. The voltage applied here is applied so that a reverse bias is applied to the PN junction formed by the P-type pillar layer 103 and the N-type pillar layer 102. When the gate electrode 107 is set to an appropriate potential in this state, the MOSFET is turned on, and a current can flow between the source electrode 109 and the drain electrode 110. This is because, by applying an appropriate voltage to the gate electrode 107, a reverse bias divided by the load and the on-resistance of the MOSFET is applied to the PN junction, and the spread of the depletion layer generated at this time is slight. This is because a carrier path exists in the type pillar layer 102. This is because a channel is formed at the interface between the base region 104 and the gate oxide film 106 between the N-type pillar layer 102 and the source region 105.

  On the other hand, when the potential of the gate electrode 107 is set to a potential at which no channel is formed, the MOSFET is turned off, and no current flows through the MOSFET. Therefore, the gate electrode 107 is formed by the N-type pillar layer 102 and the P-type pillar layer 103. The power supply voltage is directly applied to the PN junction as a reverse bias. Therefore, a depletion layer spreads from the interface between the N-type pillar layer 102 and the P-type pillar layer 103 to the N-type pillar layer 102 and the P-type pillar layer 103, and local electric field concentration is eliminated. Since the pillar layer 103 is completely depleted, a high breakdown voltage can be maintained. This type of super junction type semiconductor device is described in Patent Document 1 (FIG. 15), for example.

JP 2004-214511 A

  In the semiconductor device formed by the above manufacturing method, it is necessary to form a deep trench groove of about 20 μm and epitaxially grow a P-type semiconductor layer in the trench groove. Therefore, there is a demand for an epitaxial growth technique with good filling properties without voids in trench grooves having a high aspect ratio (3 to 4 or more). In addition, the large-area PN junction formed by the P-type pillar layer 103 and the N-type pillar layer 102 formed in the trench groove needs to have zero crystal defects.

In order to form an epitaxial layer that satisfies these conditions, a growth sequence that repeats epitaxial growth under reduced pressure using SiH ₂ Cl ₂ gas and etching with HCl gas is generally employed. However, in order to fill a trench groove having an aspect ratio of 3 or more at a depth of about 20 μm, it is necessary to perform epitaxial growth of 10 μm or more, and the low-pressure epitaxial growth method employing the above growth sequence and having a slow growth rate has a very high production efficiency. There was a problem of being bad.

  In addition, since the N-type pillar layer 102 and the P-type pillar layer 103 are formed by the CMP (Chemical Mechanical Polish) method after the epitaxial growth, variations in the respective thicknesses occur due to variations in the polishing thickness. As a result, there is a problem that variations occur in the breakdown voltage (BVDSS) and on-resistance (Rdson) between the source and drain of the semiconductor device.

  An object of the present invention is to provide a semiconductor device having a high withstand voltage which can solve the above problems and can be manufactured by a simple method and has no source-drain breakdown voltage and on-resistance variation.

  In order to solve the above-described problems, the present invention according to claim 1 includes a first conductivity type semiconductor substrate, a second conductivity type epitaxial layer stacked on the semiconductor substrate, and the surface of the epitaxial layer. A trench groove extending in a depth direction from the semiconductor substrate to the semiconductor substrate; a dielectric layer filled in the trench groove; and a first conductivity type impurity contained in the dielectric layer diffused into the epitaxial layer. A first pillar region of a first conductivity type formed so as to reach the semiconductor substrate, a second pillar region composed of the epitaxial layer between the trench groove and the first pillar region, and the second pillar region A base region of a second conductivity type formed on the surface so as to connect to the first pillar region, a source region of a first conductivity type formed on the surface of the base region, and the first pillar region A gate electrode disposed on a surface of the base region between the source region and a gate oxide film; a source electrode connected to the source region; and a drain electrode connected to the semiconductor substrate; The first pillar region and the second pillar region are formed alternately and in parallel on the semiconductor substrate.

  The invention according to claim 2 includes a step of forming a second conductivity type epitaxial layer on a first conductivity type semiconductor substrate, and a step of forming a second conductivity type semiconductor region on the surface of the epitaxial layer. A step of forming a trench groove in a stripe shape from the surface of the semiconductor region of the second conductivity type into the epitaxial layer; a step of filling a dielectric layer containing an impurity of the first conductivity type in the trench groove; Then, the first conductivity type impurity is diffused from the dielectric layer into the epitaxial layer by performing a heat treatment, and the first conductivity type first pillar region composed of a diffusion region, and the first pillar region A step of forming a second conductivity type second pillar region comprising the epitaxial layer remaining between, a step of forming a gate oxide film, and a step of forming a gate electrode on the gate oxide film; Forming a source region of a first conductivity type in the semiconductor region so that the base region is directly under the gate electrode; a source electrode connected to the source region; and a drain electrode connected to the semiconductor substrate. And a step of forming.

  In the present invention, a dielectric (for example, PSG; phosphorus-doped silica glass) layer doped with N-type impurities at a high concentration is buried in a deep trench formed in a P-type epitaxial layer, and the dielectric Impurities are diffused directly and uniformly from the body layer into the epitaxial layer to form an N-type pillar layer. Therefore, it is not necessary to perform high-quality epitaxial growth in the deep trench groove as in the prior art, and it is not necessary to planarize the epitaxial layer by the CMP method, which is a very simple manufacturing method. Since the crystallinity of the interface between the P-type pillar layer and the N-type pillar layer is not deteriorated, there is an advantage that a stable breakdown voltage (BVDSS) and on-resistance (Rdson) can be obtained.

It is sectional drawing of the semiconductor device of the Example of this invention. It is a figure explaining the manufacturing process of the semiconductor device of the Example of this invention. It is sectional drawing of the semiconductor device of another Example of this invention. It is sectional drawing of this kind of conventional semiconductor device. It is a figure explaining the manufacturing process of this kind of conventional semiconductor device.

  In the semiconductor device of the present invention, instead of growing an epitaxial layer in a deep trench groove, a dielectric layer containing an impurity is filled in the trench groove, and the impurity is diffused from the dielectric layer, whereby an N-type pillar layer is formed. And a P-type pillar layer. Examples of the present invention will be described in detail below.

  FIG. 1 is a sectional view of a semiconductor device according to the present invention. In the figure, 1 is a high-concentration N-type (N ++ type) semiconductor substrate that becomes a drain layer, 2 is an N-type pillar layer, 3 is a P-type pillar layer made of a P-type epitaxial layer, and 4 is a P-type pillar layer. Base region, 5 is an N-type source region, 6 is a gate oxide film, 7 is a gate electrode, 8 is an interlayer insulating film, 9 is a source electrode, 10 is a drain electrode, 11 is a trench groove, 12 is in the trench groove 11 It is a filled dielectric layer. The semiconductor device having such a structure is formed as follows.

  First, a P-type epitaxial layer 13 is formed on a semiconductor substrate 1 made of a high-concentration N-type silicon semiconductor substrate and serving as a drain layer, and a P-type base region 4 is formed on the surface of the epitaxial layer 13. A silicon oxide film 14 is formed on the entire surface by a CVD (Chemical Vapor Deposition) method and patterned so as to open a trench trench formation scheduled region. Then, using the silicon oxide film 14 as an etching mask, the trench groove 11 is formed. The trench groove 11 penetrates the base region 4 formed on the surface, and has an inner wall surface substantially perpendicular to the surface of the semiconductor substrate 1 at a depth (about 20 μm) reaching the vicinity of the interface between the epitaxial layer 13 and the semiconductor substrate 1. And are formed in stripes parallel to each other at equal intervals (FIG. 2a).

  Next, a dielectric layer 12 (PSG film) containing a desired concentration of phosphorus (P) as an N-type impurity is grown under reduced pressure conditions. As a result, the trench groove 11 is uniformly filled with the dielectric layer 12 (FIG. 2b). Here, in order to uniformly embed the dielectric layer 12 in the trench groove 11, when a PSG film is used as the dielectric layer, it may be about 1.2 to 2.0 times the trench opening width or more.

  Next, the dielectric layer 12 covering the surface is etched back or polished by a CMP method so that the surface of the dielectric layer 12 that extends over the trench groove 11 is at the same position as or slightly below the surface of the base region 4. The etch back time or the CMP polishing amount is adjusted so as to be (FIG. 2c).

  Thereafter, by performing heat treatment, impurities (phosphorus) contained in the dielectric layer 12 are diffused into the epitaxial layer 13 and the base region 4 to form the N-type pillar layer 2. Here, the diffusion of impurities (phosphorus) into the epitaxial layer 13 is performed uniformly and can be performed with good controllability. Therefore, by adjusting the diffusion depth, epitaxial thickness, and trench groove depth, the N-type pillars The bottom of the layer 2 reaches the semiconductor substrate 1. As a result, a P-type pillar layer 3 made of an epitaxial layer is formed (FIG. 2d).

  Thereafter, as in the conventional example, a gate oxide film 6 is formed on the entire surface, and then a polysilicon film to be the gate electrode 7 is formed (FIG. 2e).

  After the polysilicon film is patterned to form the gate electrode 7, the source region 5 is formed in a self-aligning manner using the gate electrode 7 as a part of the mask (FIG. 2f).

  After the interlayer insulating film 8 is grown, contact holes 15 that open the source region 5 and the base region 4 are formed (FIG. 2g). Thereafter, the source electrode 9 and the drain electrode 10 are formed to complete the semiconductor device shown in FIG.

  The semiconductor device of the present invention formed as described above is formed by thermally diffusing impurities from the dielectric layer 12 embedded in the trench groove into the P-type epitaxial layer 13, thereby forming the N-type pillar layer 2 and the impurities. P-type pillar layer 3 composed of a P-type epitaxial layer that remains without being diffused is arranged in parallel in a stripe shape on the semiconductor substrate, and the bottom of N-type pillar layer 2 is connected to semiconductor substrate 1. Is formed.

  With such a structure, when a positive voltage is applied to the gate electrode 7, a channel is formed on the surface of the base layer 4 below the gate electrode 7, the MOSFET is turned on, and the drain electrode 11 A current flows to the source electrode 10 using the semiconductor substrate 1, the N-type pillar layer 2, and the channel region and the source region 5 formed in the base region 4 as current paths.

  On the other hand, when a voltage that does not form a channel is applied to the gate electrode 7, the MOSFET is turned off, and the power supply voltage is directly applied to the N-type pillar layer 2 and the P-type pillar layer 3. The N-type pillar layer and the P-type pillar layer are completely depleted by optimizing the concentration of the N-type pillar layer and the P-type epitaxial layer by making the impurity concentration and diffusion conditions of the buried dielectric layer appropriate. It becomes possible to maintain the withstand voltage higher than the power supply voltage.

  When the source region 5 is formed, the trench groove side source region formed on the surface of the epitaxial layer at the same time may not be formed as shown in FIG.

  In addition, this invention is not limited to the said Example. For example, instead of diffusing the N-type impurity into the P-type epitaxial layer to form the N-type pillar layer 2, the P-type pillar layer 3 is formed by diffusing the P-type impurity into the N-type epitaxial layer. Is also possible.

As described above, in the semiconductor device formed according to the present invention, the concentration and thickness of the N-type pillar layer 2 and the P-type pillar layer 3 are determined by the impurity concentration in the dielectric layer embedded in the trench groove and the dielectric layer. Since it is determined by controlling the diffusion length of the impurity to be diffused, the controllability is very good, and variations in the breakdown voltage and on-resistance between the source and drain are reduced. On the other hand, in a conventional semiconductor device formed by embedding an epitaxial layer, the upper limit of the impurity concentration of the epitaxial layer is about 1.0 × 10 ¹⁷ cm ⁻³ because of its controllability. It was necessary to increase the width of the pillar layer formed by the layers. As a result, the cell pitch is increased, and there is a limit in reducing the on-resistance per unit area. In contrast, in the semiconductor device formed according to the present invention, by increasing the concentration of each pillar layer and conversely reducing the thickness, the cell pitch can be reduced while maintaining the same breakdown voltage. The on-resistance can be reduced.

1: Semiconductor substrate, 2: N-type pillar layer, 3: P-type pillar layer, 4: Base region, 5: Source region, 6: Gate oxide film, 7: Gate electrode, 8: Interlayer insulating film, 9: Source electrode 10: Drain electrode, 11: Trench groove, 12: Dielectric layer

Claims (2)

A first conductivity type semiconductor substrate;
An epitaxial layer of a second conductivity type laminated on the semiconductor substrate;
A trench groove extending in a depth direction from the surface of the epitaxial layer toward the semiconductor substrate;
A dielectric layer filled in the trench groove;
A first conductivity type first pillar region formed so that the first conductivity type impurity contained in the dielectric layer diffuses into the epitaxial layer and reaches the semiconductor substrate;
A second pillar region comprising the epitaxial layer between the trench groove and the first pillar region;
A base region of a second conductivity type formed on the surface of the second pillar region so as to be connected to the first pillar region;
A first conductivity type source region formed on the surface of the base region;
A gate electrode disposed on the surface of the base region between the first pillar region and the source region via a gate oxide film, a source electrode connected to the source region, and a drain electrode connected to the semiconductor substrate And
The semiconductor device, wherein the first pillar region and the second pillar region are alternately arranged in parallel on the semiconductor substrate. Forming a second conductivity type epitaxial layer on the first conductivity type semiconductor substrate;
Forming a second conductivity type semiconductor region on the surface of the epitaxial layer;
Forming trench grooves in stripes from the surface of the semiconductor region of the second conductivity type into the epitaxial layer;
Filling the trench groove with a dielectric layer containing a first conductivity type impurity;
By performing a heat treatment, the first conductivity type impurities are diffused from the dielectric layer into the epitaxial layer, and the first conductivity type first pillar region formed of a diffusion region is interposed between the first pillar regions. Forming a second conductivity type second pillar region comprising the epitaxial layer remaining in
Forming a gate oxide film;
Forming a gate electrode on the gate oxide film;
Forming a first conductivity type source region in the semiconductor region such that the base region is directly under the gate electrode;
Forming a source electrode connected to the source region and a drain electrode connected to the semiconductor substrate.

Images