JP2012168851A - Emulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an emulator capable of also simulating hardware operating time.SOLUTION: An emulator for simulating a hardware structure of a device to be simulated when being executed on an information processor includes a virtual hardware part for simulating a structure part included in the hardware structure. The virtual hardware part comprises: a drive part for driving an actual hardware part within the information processor associated with the virtual hardware part; and a response part that is executed on the information processor for simulating a response result shown to input by the structure part simulated by the virtual hardware part after driving of the actual hardware part by the drive part.

Description

  The present disclosure relates to an emulator.

  With the recent acceleration of technological progress, there is a demand for shortening the development period especially for information processing related devices. As a result, the number of manufacturing methods that develop and manufacture all parts by themselves only decreases. On the other hand, the number of manufacturing methods that collect and develop parts and software that are separately developed and manufactured by multiple companies increases. ing. In the case of a large-scale apparatus, software is often developed and manufactured by dividing it into fine software parts, so debugging after drawing up the software parts is important. However, many software cannot be debugged unless they are executed on the hardware of the apparatus, and it has been difficult to shorten the time required for debugging.

  As a method for shortening the debugging time, it is conceivable to prepare a large number of prototype devices and perform debugging at the same time. However, since there are many prototype devices, there is a possibility that the cost may be increased. In addition, if the hardware is modified (revised), a large number of prototype devices are also recreated, which increases the number of man-hours and may not shorten the development period.

  Therefore, a method of simulating hardware operation of the entire apparatus or a part of the apparatus with software has been adopted. Such software that simulates the operation of hardware is generally called an emulator. Using the emulator or the like to try the hardware operation under a specific condition is generally called simulation.

  By using the emulator as a prototype device and executing the software to be installed in the device on the emulator, the operation when installed in the actual device can be simulated. The software can be debugged by referring to the simulation result.

  With respect to such a simulation, an efficient simulation has been proposed. In this proposal, actual hardware corresponding to the memory, hard disk device, and input / output device of the simulation target computer system is prepared and connected to the simulation execution computer system. For the CPU and the like of the computer system to be simulated, a model is built in a memory in the simulation execution computer system. In the simulation of the computer system to be simulated, a model constructed with prepared actual hardware and memory is used.

JP-A-6-187191

  However, according to the above method for preparing actual hardware, it is considered that there is a risk of cost increase under the same circumstances as the method for preparing a prototype device.

  On the other hand, it is naturally impossible for hardware simulated by an emulator to reproduce all operations performed by actual hardware. Therefore, in general, a hardware element is prepared as a function that defines a correspondence between an input and an output in response to the input. However, with such hardware elements prepared as functions, it is difficult to simulate the passage of operating time that occurs during actual hardware operation. In particular, in actual hardware, the operation time is not a fixed delay, but varies due to differences in operation conditions. Therefore, it is desired to simulate the operation time including such variations.

  In view of the above circumstances, it is an object of the present disclosure to provide an emulator that can also simulate the operation time of hardware.

  An emulator that achieves the above object simulates the hardware structure of an apparatus different from the information processing apparatus by being executed on the information processing apparatus. This emulator has a virtual hardware part that simulates the structural part included in the hardware structure. And this virtual hardware part is provided with the response part and the drive part.

  The said drive part drives the hardware part in the said information processing apparatus matched with the said virtual hardware part.

  The response unit is executed on the information processing apparatus after driving the actual hardware part by the drive unit in order to simulate a response result that the structure part simulated by the virtual hardware part shows with respect to the input. Is.

  According to the present disclosure, it is possible to simulate the operation time of hardware by using an emulator.

It is a figure which shows specific 1st Embodiment of an emulator. It is a structural diagram showing the information processing apparatus which performs the emulator of 2nd Embodiment. It is a structural diagram showing the storage apparatus equivalent to an example of the simulation object apparatus which an emulator simulates. It is a figure showing the emulator which simulates the storage apparatus shown in FIG. It is a figure which shows the main-body part (virtual NAS) expand | deployed on the memory of information processing apparatus. It is a figure which shows the structure of virtual HDC. It is a figure which shows the structure of a virtual LAN board. It is a flowchart showing the starting process of virtual NAS. It is a figure which shows an example of a correspondence table. It is a figure which shows an example of a priority table. It is a figure showing the process sequence in access to virtual HDD. 4 is a flowchart showing a read processing procedure in access processing to a virtual HDD. 4 is a flowchart showing a write process procedure in an access process to a virtual HDD. It is a figure showing the process sequence in access to a virtual LAN board. It is a figure which shows the process sequence of access to the virtual hard disk apparatus in the modification provided with two or more virtual hard disk apparatuses.

  Specific embodiments of the emulator described above will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a specific first embodiment of an emulator.

  The emulator 10 illustrated in FIG. 1 virtually executes the hardware structure of the simulation target device by being executed on the information processing device 20 having the actual hardware portion 21. The execution of the emulator 10 on the information processing apparatus 20 is specifically that the emulator 10 is developed on the memory of the information processing apparatus 20 and processed by the CPU or the like.

  The emulator 10 includes a virtual hardware portion 11 that simulates a structural portion included in the hardware structure of the simulation target device. The virtual hardware portion 11 includes a response unit 12 and a drive unit 13.

  The response unit 12 is executed on the information processing apparatus 20. The structural part simulated by the virtual hardware part 11 simulates the response result to the input. By simulating the response unit 12 as described above, an operation result in an internal operation or an external response operation in the simulation target apparatus is simulated. However, what is simulated by the response unit 12 is a result, and the process is not simulated.

  The drive unit 13 is provided in at least one virtual hardware part 11, but is not necessarily provided in all virtual hardware parts 11. The virtual hardware portion 11 including the drive unit 13 is associated with an actual hardware portion 21 included in the information processing apparatus 20. The drive unit 13 drives the hardware part 21 associated with the virtual hardware part 11 prior to the execution of the response part 12 when the response part 12 in the virtual hardware part 11 is executed. . In other words, the response unit 12 is executed after driving the hardware part 21 by the drive unit 13. As a result of such driving by the driving unit 13, the operation time in the simulation target apparatus is simulated.

  In other words, according to the emulator 10 shown in FIG. 1, the operation of the simulation target device is simulated including the operation time of the hardware, so that the accuracy of the emulator 10 is high. Moreover, the actual hardware portion used by the emulator 10 for simulating the hardware operating time is the hardware portion 21 of the information processing apparatus 20 that executes the emulator 10. Therefore, it is not necessary to prepare extra hardware for simulating hardware operation time.

  Next, a more specific second embodiment will be described.

  FIG. 2 is a structural diagram illustrating an information processing apparatus that executes the emulator according to the second embodiment.

  The information processing apparatus 100 shown in FIG. 2 includes a CPU 110, a north bridge 120, a memory 130, a south bridge 140, a hard disk device 150, and a UART (Universal Asynchronous Receiver / Transmitter) 160 as actual hardware elements.

  The CPU 110, the north bridge 120, and the south bridge 140 are connected to each other via an original bus 170. On the other hand, the UART 160 is connected to the south bridge 140 via the PCI bus 180.

  Since the north bridge 120 has a built-in function as a memory controller, the memory 130 is directly connected to the north bridge 120 without a bus.

  Further, since the south bridge 140 has a function as a hard disk controller (HDC), the hard disk device 150 is directly connected to the south bridge 140 without a bus. In the following description, the south bridge 140 may be referred to as HDC 140.

  When the information processing apparatus 100 operates as a host for executing the emulator, the emulator is expanded on the memory 130 and executed by the CPU 110. This emulator is stored in the hard disk device 150 before being deployed on the memory 130.

  The UART 160 is a device that performs mutual conversion between parallel data and serial data.

  FIG. 3 is a structural diagram showing a storage apparatus corresponding to an example of a simulation target apparatus simulated by an emulator.

  The storage device 200 shown here is a type of storage device called NAS (network attached storage). This NAS is connected to the network and used as a file server from the network.

  The storage apparatus 200 includes a CPU 210, a memory controller 220, a memory 230, a hard disk controller 240, a hard disk apparatus 250, and a LAN board 260 as simulation target hardware elements. The CPU 210, the memory controller 220, the hard disk controller 240, and the LAN board 260 are connected to each other via the PCI bus 270. On the other hand, the memory 230 is directly connected to the memory controller 220 without a bus. The hard disk device 250 is directly connected to the hard disk controller 240 without a bus.

  The CPU 210 controls the operation of each unit in the storage device 200.

  The memory 230 includes RAM and ROM. A program executed by the CPU 210 is expanded in the memory 230. The memory controller 220 controls data input / output with respect to the memory 230.

  The LAN board 260 connects the storage apparatus 200 to a network.

  The hard disk device 250 stores data sent from the network. The hard disk controller 240 controls data input / output with respect to the hard disk device 250.

  FIG. 4 is a diagram illustrating an emulator that simulates the storage apparatus illustrated in FIG.

  An emulator 300 shown in FIG. 4 is an emulator according to the second embodiment. The emulator 300 includes a main body unit 320 and an activation unit 310.

  The main unit 320 virtually expands on the memory 130 of the information processing apparatus 100 illustrated in FIG. 2 to virtually simulate the hardware structure of the storage apparatus 200 illustrated in FIG. 3. On the other hand, the activation unit 310 activates the main body unit 320 by expanding it on the memory 130. In the following description, the main body 320 expanded on the memory 130 may be referred to as a virtual NAS 320.

  The activation unit 310 includes a virtual hardware development unit 311, a real hardware confirmation unit 312, and a priority table 313. The activation unit 310 will be described later. First, the main body unit 320 developed on the memory 130 will be described.

  FIG. 5 is a diagram showing a main body (virtual NAS) developed on the memory of the information processing apparatus.

  As shown in FIG. 5, the virtual NAS 320 is expanded on a part of the memory 130 of the information processing apparatus 100. The virtual NAS 320 deployed on the memory 130 has a virtual structure similar to the hardware structure of the storage apparatus 200 shown in FIG. In other words, the virtual NAS 320 includes a virtual CPU 321, a virtual memory controller 322, and a virtual memory 323 as virtual hardware elements. The virtual NAS 320 further includes a virtual hard disk controller (virtual HDC) 324, a virtual hard disk device 325, and a virtual LAN board 326 as virtual hardware elements.

  These virtual hardware elements 321 to 326 simulate the simulation target hardware elements 210 to 260 included in the storage apparatus 200 illustrated in FIG. 3.

  The virtual NAS 320 is also provided with a correspondence table 327. This correspondence table 327 shows correspondence between virtual hardware elements 321 to 326 provided in the virtual NAS 320 and actual hardware elements included in the information processing apparatus 100. The correspondence table 327 is constructed when the virtual NAS 320 is expanded on the memory 130, and detailed description will be made later together with the explanation of the activation unit 310 shown in FIG. 4.

  In the following description, for convenience of explanation, a virtual hardware element, a simulation target hardware element, and a real hardware element may be abbreviated as virtual hardware, target hardware, and real hardware, respectively. .

  Here, the structure of the virtual hardware element will be described by taking the virtual HDC 324 and the virtual LAN board 326 as examples.

  FIG. 6 is a diagram illustrating the structure of the virtual HDC. FIG. 7 shows the structure of the virtual LAN board.

  The virtual HDC 324 includes an actual hardware operation instruction unit 410 and a virtual hardware operation execution unit 420. The virtual LAN board 326 also includes an actual hardware operation instruction unit 430 and a virtual hardware operation execution unit 440.

  The target hardware simulated by virtual hardware is generally one that receives an input such as data or a command and returns a response. The virtual hardware operation execution unit 420 of the virtual HDC 324 is a kind of function or routine program that represents the correspondence between the input and the response result in the HDC 240 to be simulated. A response in the simulation target HDC 240 is simulated by the CPU 110 of the information processing apparatus 100 executing such a virtual hardware operation execution unit 420 and obtaining a response result. Similarly, the virtual hardware operation execution unit 440 of the virtual LAN board 326 represents the correspondence relationship between the input and the response result on the simulation target LAN board 260. The virtual hardware operation execution unit 440 is executed by the CPU 110 of the information processing apparatus 100 to obtain a response result, thereby simulating a response in the LAN board 260 to be simulated. Thus, each virtual hardware simulates the response of the target hardware, so that an emulator configured with such virtual hardware can simulate the internal operation of the simulation target device and the response to the outside.

  By the way, the acquisition of the response result by the virtual hardware operation execution units 420 and 440 as functions or routine programs does not take the operation time for the simulation target HDC 240 or the LAN board 260 to operate as hardware. However, in order for the virtual NAS 320 shown in FIG. 5 to be highly accurate as an emulator, it is desirable that simulation including the operation time of hardware is realized. In particular, in actual hardware, fluctuations occur in the operation time depending on the operation state of the apparatus, and it is desirable to simulate such fluctuations.

  Therefore, in the virtual HDC 324 and the virtual LAN board 326, the actual hardware operation instruction units 410 and 430 instruct the information processing apparatus 100 to operate the actual hardware included in the information processing apparatus 100. The correspondence between the virtual hardware and the real hardware at this time follows the correspondence table described above. By such an instruction from the actual hardware operation instruction units 410 and 430, the virtual HDC 324 and the virtual LAN board 326 realize the simulation including the hardware operation time. Since the simulated operation time can be expected to fluctuate according to the operation status of the information processing apparatus 100, simulation of the operation time desirable for an emulator is realized. Note that such an actual hardware operation instruction unit is not necessary for all virtual hardware. For example, for the virtual CPU 321, the virtual memory controller 322, and the virtual memory 323, the operation time of the target hardware may be considered to be approximately the same as the time that the above-described virtual hardware operation execution unit is executed by the CPU 110 of the information processing apparatus 100. Therefore, the virtual hardware operation execution unit can be simulated with sufficiently high accuracy only by being executed by the CPU 110 of the information processing apparatus 100. Therefore, the actual hardware operation instruction unit is provided only in the type of virtual hardware that requires simulation of the operation time by the actual hardware operation instruction unit.

  Hereinafter, activation of the virtual NAS by the activation unit 310 of the emulator 300 illustrated in FIG. 4 will be described.

  FIG. 8 is a flowchart showing the virtual NAS activation process. Hereinafter, in describing the activation process represented by this flowchart, FIG. 3 is also referred to as appropriate.

  When the activation process of the main body (virtual NAS) 320 by the activation unit 310 of the emulator 300 illustrated in FIG. 4 is started, first, the virtual hardware of the virtual NAS is placed on the memory 130 of the information processing apparatus 100 by the virtual hardware expansion unit 311. Expanded (step S101). At this time, the virtual hardware development unit 311 registers each virtual hardware developed on the memory 130 in the correspondence table 327 described above.

  FIG. 9 is a diagram illustrating an example of the correspondence table.

  As illustrated in FIG. 9, the correspondence table 327 is a table in which virtual hardware 450 and real hardware 460 are associated with each other and registered. In step S101 of FIG. 8, only the virtual hardware 450 side in the correspondence table 327 is registered, and the actual hardware 460 side is blank. In the example of the correspondence table 327 in FIG. 9, “CPU” is registered in the first row, “HDC” in the second row, and “LAN” in the third row. Since the hard disk controller operates when operating the hard disk device, the correspondence table 327 does not distinguish them.

  When the virtual hardware is registered in this manner in step S101 of FIG. 8, in the next step S102, the real hardware confirmation unit 312 selects one of the registered virtual hardware. In step S <b> 103, the real hardware confirmation unit 312 acquires the priority table 313 of the selected virtual hardware from the hard disk device 150. This priority table 313 represents the priority order of real hardware to be associated with virtual hardware. The priority table 313 is incorporated in the activation unit 310 from the beginning corresponding to the virtual hardware of the main unit (virtual NAS) 320.

  FIG. 10 is a diagram illustrating an example of a priority table.

  A priority table 313 illustrated in FIG. 10 is an example of a priority table 313 associated with a LAN board. In the priority table 313, “LAN”, “UART”, and “USB” are sequentially described as hardware types. This means that the hardware of the type described above in the priority table 313 has a higher priority. In the example of the priority table 313 shown in FIG. 10, the operation content is similar to the LAN board for the types of hardware described above. However, the order in which the operation contents are similar is not necessarily the priority order, and even if the contents are different, the order in which the operation times are close may be set as the priority order.

  The priority table 313 as shown in FIG. 10 is prepared only for virtual hardware of the type that requires simulation of the operation time by the above-described actual hardware operation instruction unit among the virtual hardware. For this reason, when the real hardware confirmation part 312 cannot acquire the priority table 313 in step S103 of FIG. 8, subsequent step S104 and step S105 are abbreviate | omitted and it progresses to step S106. On the other hand, when the real hardware confirmation unit 312 acquires the priority table 313 in step S103, the real hardware confirmation unit 312 confirms the existence of the real hardware with respect to the information processing apparatus 100 in the order of the priority table 313 in step S104. . As described above, the information processing apparatus 100 is an apparatus that operates as a host that executes an emulator. As a specific method for confirming the presence of actual hardware, a function originally provided in the information processing apparatus 100 is used as a mechanism for the BIOS or the like to confirm the apparatus configuration in the information processing apparatus 100. Note that the details of this mechanism are not directly related to the gist of the present disclosure and will not be described further.

  When the presence of real hardware is confirmed in step S104, the real hardware confirmation unit 312 registers the real hardware in the correspondence table 327 in association with the virtual hardware corresponding to the priority table 313 (step S105).

  An information processing apparatus whose existence of real hardware is confirmed is an apparatus for executing an emulator (virtual NAS in the present embodiment), and is generally a target apparatus (NAS in the present embodiment) to be simulated by the virtual NAS. Another type of device. In addition, when creating an emulator, the hardware structure of an information processing apparatus that executes the emulator is often unknown. For this reason, the application form provided with the following corresponding | compatible parts is suitable. The corresponding unit searches for a hardware part existing in the information processing apparatus. Then, the correspondence unit associates the hardware part obtained by the search with the virtual hardware part of the emulator, for example, with a priority order and other correspondence rules described later. According to such an application mode, even if the hardware structure of the information processing apparatus that executes the emulator is unknown, the actual hardware portion can be associated with the virtual hardware portion. The actual hardware confirmation unit 312 illustrated in FIG. 4 corresponds to an example of the corresponding unit.

Further, the hardware structure of the information processing apparatus that executes the emulator does not always include the same type of real hardware as the type of virtual hardware. For this reason, the following application forms are more suitable. In this more preferred application mode, the correspondence unit is given a priority of the hardware part to be associated with the virtual hardware part, and the hardware part obtained by the search is assigned the virtual part according to the priority. Correspond to the hardware part.
By associating in accordance with the priority order as described above, the virtual hardware part is associated with the actual hardware part suitable for the simulation of the operation time even if they are not of the same type. The priority table 313 shown in FIG. 10 corresponds to an example of the priority order in this more preferable application form. Moreover, the real hardware confirmation part 312 shown in FIG. 4 is corresponded also to an example of the corresponding | compatible part in this more suitable application form.

  The correspondence table 327 shown in FIG. 9 shows an example of registered actual hardware 460.

  Since the above priority table is not prepared for the “CPU” registered in the first level on the virtual hardware 450 side in the correspondence table 327, the first level on the actual hardware 460 side is blank. .

  Regarding “HDC (HDD)” registered in the second row on the virtual hardware 450 side of the correspondence table 327, since the same type of hardware actually exists in the information processing apparatus 100 shown in FIG. “HDC (HDD)” is registered in the second row on the hardware 460 side.

  Regarding “LAN” registered in the third row on the virtual hardware 450 side of the correspondence table 327, the same type of hardware does not exist in the information processing apparatus 100 illustrated in FIG. 5, but the priority table 313 illustrated in FIG. The second “UART” described in FIG. For this reason, “UART” is registered in the third row on the actual hardware 460 side.

  When the real hardware is confirmed and registered in steps S102 to S105 in FIG. 8 as described above, the process proceeds to step S106, and whether or not the real hardware has been confirmed and registered for all virtual hardware in the virtual NAS. It is confirmed. If finished, the startup process is finished, and if not finished, the process returns to the above-described step S102, one next virtual hardware is selected, and confirmation and registration of the actual hardware are repeated.

  As a result of the activation process described above, the virtual NAS 320 is expanded and activated on the memory 130 of the information processing apparatus (ie, host) 100 as shown in FIG. Hereinafter, the processing procedure in the specific operation of the virtual NAS 320 deployed in this way will be described by taking the access to the virtual HDD 325 and the access to the virtual LAN board 326 as examples.

  FIG. 11 is a diagram illustrating a processing procedure in accessing a virtual HDD. FIG. 12 is a flowchart showing the read processing procedure in the access processing to the virtual HDD. Hereinafter, the read process represented by the flowchart of FIG. 12 will be described with reference to FIG. The read process represented by the flowchart of FIG. 12 is an example of the read process for starting up the OS stored in the virtual HDD.

  This read processing is started when the CPU 110 of the information processing apparatus 100 accesses the virtual CPU 321 included in the virtual NAS 320 in the memory 130 via the north bridge 120 (processing procedure 1 and processing procedure 2 indicated by arrows in FIG. 11). ).

  When this read process is started, the virtual CPU 321 of the virtual NAS 320 issues a read command to the virtual HDC 324 in step S201 of FIG. 12 (process procedure 3 of FIG. 11). This read command is a command for reading the OS from the virtual hard disk device 325. That is, this read command instructs the virtual HDC 324 to read data (OS) stored in sectors 0 to n on the virtual hard disk device 325. The operation of the virtual hardware such as the processing procedure 3 in FIG. 11 is strictly speaking a processing operation by the CPU 110 or the memory 130 of the information processing apparatus 100. However, since the description is only complicated, the following will be described. The operation of the virtual hardware will be described.

  The virtual HDC 324 of the virtual NAS 320 recognizes that the read command has been issued (processing procedure 4 in FIG. 11). In step S202 of FIG. 12, the virtual HDC 324 instructs the information processing apparatus 100 to access the actual hardware in the information processing apparatus 100 in order to simulate the hardware operation time. This access to the actual hardware is an access corresponding to the reading designated by the read command. At this time, the virtual HDC 324 refers to the correspondence table 327 to confirm that the real hardware corresponding to itself is the HDC 140 (processing procedure 4 ′ in FIG. 11). Then, the information processing apparatus (ie, host) 100 is instructed to access the confirmed HDC 140 and the process is entrusted.

  On the information processing apparatus 100 side, the CPU 110 causes the hard disk device 150 to read data stored in sectors 0 to n via the hard disk controller 140 (processing procedure 5 and processing procedure 6 in FIG. 11, FIG. 12). Step S203). As a result, data from sector 0 to sector n is read from the hard disk device 150 to the CPU 110 (processing procedure 7 in FIG. 11). However, since the data read in this way is unused data, it is discarded by the CPU 110 in accordance with a prior instruction from the virtual HDC 324. Then, the CPU 110 waits for completion of the reading process and returns the process to the virtual HDC 324. It should be noted that this read process may be executed simultaneously with other processes on the host in the same manner that the processes of a plurality of application software may be executed simultaneously on a general personal computer. For this reason, in the processing time required for this reading process, fluctuations according to the operation status of the host occur.

  Thereafter, in step S204 of FIG. 12, the virtual HDC 324 accesses the virtual hard disk device 325 and reads data (OS) from sector 0 to sector n. Further, in step S205 in FIG. 12, the virtual HDC 324 notifies the virtual CPU 321 of the completion of processing (processing procedure 8 in FIG. 11). Finally, the virtual CPU 321 returns the process to the CPU 110 of the information processing apparatus 100.

  With such a processing procedure, the virtual NAS 320 simulates the read processing operation for the hard disk including the access time. In addition, as described above, since the fluctuation of the access time that occurs in the actual hard disk device 150 included in the information processing apparatus 100 is reflected, the simulated read processing operation is real and the simulation accuracy is high.

  Next, write processing among the access processing to the virtual HDD will be described below.

  FIG. 13 is a flowchart showing the procedure of the write process in the access process to the virtual HDD. Hereinafter, the write process represented by the flowchart of FIG. 13 will be described with reference to FIG.

  This write processing is also started when the CPU 110 of the information processing apparatus 100 accesses the virtual CPU 321 included in the virtual NAS 320 in the memory 130 via the north bridge 120 (processing procedure 1 and processing procedure 2 indicated by arrows in FIG. 11). ).

  When this write processing is started, the virtual CPU 321 of the virtual NAS 320 issues a write command to the virtual HDC 324 in step S301 of FIG. 13 (processing procedure 3 of FIG. 11). This write command is a command for writing data to the virtual hard disk device 325. In other words, this write command instructs the virtual HDC 324 to write data from sector n to sector m on the virtual hard disk device 325.

  The virtual HDC 324 of the virtual NAS 320 recognizes that the write command has been issued (processing procedure 4 in FIG. 11). In step S302 in FIG. 12, the virtual HDC 324 instructs the information processing apparatus 100 to access the actual hardware in the information processing apparatus 100 in order to simulate the hardware operation time. This access to the actual hardware is an access corresponding to the writing instructed by the write command. Also at this time, the virtual HDC 324 refers to the correspondence table 327 to confirm that the real hardware corresponding to itself is the HDC 140 (processing procedure 4 ′ in FIG. 11). Then, the information processing apparatus 100 is instructed to access the confirmed HDC 140 and the process is entrusted.

  On the information processing device (ie, host) 100 side, the CPU 110 causes the hard disk device 150 to write data from sector n to sector m via the hard disk controller 140 (processing procedure 5 and processing procedure 6 in FIG. Step S303 in FIG. 13). However, based on a prior instruction from the virtual HDC 324, writing to the sector area from sector n to sector m is not performed, but seeking to that sector area is performed. Then, after the seek, the data from sector n to sector m is written into the sector area not used by the information processing apparatus 100. As such an unused sector area, for example, “/ tmp” can be considered. If the unused sector area is small compared to sectors n to m, the unused sector area is repeatedly used to write data from sector n to sector m. It is. Since the operation time required for seeking is much longer than the operation time required for writing data, the data writing itself can be omitted. When the completion of data writing is notified from the hard disk device 150 to the CPU 110 via the hard disk controller 140 (processing procedure 7 in FIG. 11), the CPU 110 returns the process to the virtual HDC 324.

  Thereafter, in step S304 of FIG. 13, the virtual HDC 324 accesses the virtual hard disk device 325 and writes data from sector n to sector m. Further, in step S305 in FIG. 13, the virtual HDC 324 notifies the virtual CPU 321 of the completion of processing (processing procedure 8 in FIG. 11). Finally, the virtual CPU 321 returns the process to the CPU 110 of the information processing apparatus 100.

  With this processing procedure, the virtual NAS 320 simulates the write processing operation for the hard disk including the access time. Similarly to the simulation of the read processing operation, the fluctuation of the access time that occurs in the actual hard disk device 150 included in the information processing apparatus 100 is reflected, so the simulated write processing operation is also real and the simulation accuracy is high. .

  Next, a processing procedure for accessing the virtual LAN board 326 will be described.

  FIG. 14 is a diagram illustrating a processing procedure in accessing the virtual LAN board.

  Access to the virtual LAN board 326 is also started when the CPU 110 of the information processing apparatus 100 accesses the virtual CPU 321 included in the virtual NAS 320 in the memory 130 via the north bridge 120 (processing procedure 1 indicated by an arrow in FIG. 14). And processing procedure 2).

  The virtual CPU 321 of the virtual NAS 320 issues a command for instructing communication processing to the virtual LAN board 326 (processing procedure 3 in FIG. 14).

  The virtual LAN board 326 of the virtual NAS 320 recognizes that the communication processing command has been issued. The virtual LAN board 326 instructs the information processing apparatus 100 to access the actual hardware in the information processing apparatus 100 in order to simulate the operating time of the hardware. At this time, the virtual LAN board 326 confirms that the actual hardware corresponding to itself is the UART 160 by referring to the correspondence table 327 (processing procedure 3 ′ in FIG. 14). Then, the access to the confirmed UART 160 is instructed to the information processing apparatus (that is, the host) 100 and the processing is entrusted. The access to the UART 160 is an access corresponding to the communication processing instruction.

  On the information processing apparatus 100 side to which the processing is entrusted, the CPU 110 accesses the UART 160 via the south bridge 140 and issues a command corresponding to the communication processing instruction to the UART 160 (processing procedure 4 and processing procedure in FIG. 14). 5). When processing of such a command is completed, the UART 160 sends a notification of completion to the CPU 110 (processing procedure 6 in FIG. 14). Then, the CPU 110 returns the process to the virtual LAN board 326.

  Thereafter, the virtual LAN board 326 executes a response process to the communication process command. Then, the virtual LAN board 326 notifies the virtual CPU 321 of the completion of processing (processing procedure 7 in FIG. 14). Finally, the virtual CPU 321 returns the process to the CPU 110 of the information processing apparatus 100.

  With such a processing procedure, in the virtual NAS 320, an access operation to the LAN board is simulated including the processing time in the LAN board. In addition, as described above, the fluctuation of the processing time that occurs in the actual UART 160 of the information processing apparatus 100 is reflected, so that the simulated access operation is real and the simulation accuracy is high.

  This is the end of the description of the second embodiment.

  In the second embodiment described above, one virtual hard disk device is provided, but a modified example in which a plurality (two by way of example) of virtual hard disk devices are provided will be described below. However, this modified example is the same as that of the second embodiment except that a plurality of virtual hard disk devices are provided, and therefore, different points will be described below and redundant description will be omitted.

  FIG. 15 is a diagram illustrating a processing procedure of access to a virtual hard disk device in a modification in which a plurality of virtual hard disk devices are provided.

  As shown in FIG. 15, in this modification, the virtual NAS 470 includes a plurality of virtual hard disk devices 471 and 472, and the information processing apparatus 101 that is a host also includes a plurality of hard disk devices 151 and 152. Therefore, in the correspondence table 327 in this modification, the actual hard disk devices 151 and 152 are individually associated with the virtual hard disk devices 471 and 472, respectively.

  Access to the virtual hard disk device is started when the CPU 110 of the information processing device 101 accesses the virtual CPU 321 of the virtual NAS 320 in the memory 130 via the north bridge 120 (processing procedure 1 and arrow indicated by arrows in FIG. 15). Processing procedure 2). Then, the virtual CPU 321 of the virtual NAS 320 issues an access (read or write) command to the virtual HDC 324 (processing procedure 3 in FIG. 15). It is assumed that this command instructs access to the first virtual hard disk device 471 among the plurality of virtual hard disk devices 471 and 472.

  The virtual HDC 324 of the virtual NAS 320 recognizes that the command has been issued (processing procedure 4 in FIG. 15). The virtual HDC 324 confirms from the correspondence table 327 that the actual hardware associated with the first virtual hard disk device 471 is the first hard disk device 151 in order to simulate the operating time of the hardware (FIG. 15). Procedure 4 ′). Then, the virtual HDC 324 instructs the information processing apparatus 101 to access the first hard disk device 151 and entrusts the processing.

  On the information processing apparatus (ie, host) 101 side, the CPU 110 issues a command instructing access to the first hard disk device 151 to the hard disk controller 140 (processing procedure 5 in FIG. 15). The HDC 140 that has received the command executes access to the first hard disk device 151.

  In this modification, while the first virtual hard disk device 471 and the first hard disk device 151 are being accessed, the second virtual hard disk device 472 and the second hard disk device 152 are further multitasked. Access is possible.

  Access to the second virtual hard disk device 472 by multitasking is also started when the CPU 110 of the information processing device 101 accesses the virtual CPU 321 of the virtual NAS 320 in the memory 130 via the north bridge 120 (the processing of FIG. 15). Procedure 7 and processing procedure 8).

  Similar to the process of accessing the first virtual hard disk device 471, issuance of an access command (processing procedure 9 in FIG. 15), recognition of command issuance (processing procedure 10 in FIG. 15), and actuality in the correspondence table 327. Hardware confirmation (processing procedure 10 'in FIG. 15) is performed.

  Subsequently, an instruction to access the information processing apparatus 101 to the second hard disk device 152, a command issuance by the CPU 110 (processing procedure 11 in FIG. 15), and an access to the second hard disk device 152 (processing procedure 12 in FIG. 15) are performed. Is called.

  Here, which of the access to the first hard disk device 151 and the access to the second hard disk device 152 is completed first differs depending on the operation status. Here, the description will be continued on the assumption that the “overtaking” in which the access to the second hard disk device 152 is completed first occurs.

  When the completion of access is notified from the second hard disk device 152 to the CPU 110 via the HDC 140 (processing procedure 13 in FIG. 15), the CPU 110 causes the virtual HDC 324 to access the second virtual hard disk device 472. When the access is completed, the virtual HDC 324 notifies the virtual CPU 321 of the completion of processing (processing procedure 14 and processing procedure 15 in FIG. 15). Further, the virtual CPU 321 notifies the CPU 110 of the information processing apparatus 100 of the completion of processing (processing procedure 16 and processing procedure 17 in FIG. 15).

  On the other hand, when the completion of access is notified from the first hard disk device 151 to the CPU 110 after the second hard disk device 152 (processing procedure 18 in FIG. 15), the CPU 110 notifies the virtual HDC 324 to the first virtual hard disk device 471. Have access performed. When the access is completed, the virtual HDC 324 notifies the virtual CPU 321 of the completion of processing (processing procedure 19 and processing procedure 20 in FIG. 15). Further, the virtual CPU 321 notifies the CPU 110 of the information processing apparatus 100 of the completion of processing (processing procedure 21 and processing procedure 22 in FIG. 15).

  In this way, the “overtaking” process can be simulated by the virtual hardware instructing the driving of the real hardware.

DESCRIPTION OF SYMBOLS 10 Emulator 21 Real hardware part 20 Information processing apparatus 11 Virtual hardware part 12 Response part 13 Drive part 100,101 Information processing apparatus (host)
110 CPU
120 North Bridge 130 Memory 140 South Bridge (Hard Disk Controller)
150, 151, 152 Hard disk device 160 UART
170 Original bus 180 PCI bus 200 Storage device 210 CPU
220 Memory Controller 230 Memory 240 Hard Disk Controller 250 Hard Disk Device 260 LAN Board 300 Emulator 310 Start Unit 320, 470 Main Unit (Virtual NAS)
311 Virtual Hardware Expansion Unit 312 Real Hardware Confirmation Unit 313 Priority Table 321 Virtual CPU
322 Virtual memory controller 323 Virtual memory 324 Virtual hard disk controller 325, 471, 472 Virtual hard disk device 326 Virtual LAN board 327 Correspondence table 410, 430 Real hardware operation instruction unit 420, 440 Virtual hardware operation execution unit

Claims (3)

An emulator that simulates the hardware structure of a simulation target device by being executed on an information processing device,
A virtual hardware part that simulates a structural part included in the hardware structure, the virtual hardware part comprising:
A drive unit for driving an actual hardware part in the information processing apparatus associated with the virtual hardware part;
A response unit that is executed on the information processing apparatus after driving the actual hardware part by the drive unit in order to simulate the response result that the virtual hardware part simulates with respect to the input;
An emulator characterized by comprising:   The emulator according to claim 1, further comprising: a corresponding unit that searches for a hardware part existing in the information processing apparatus and associates the hardware part obtained by the search with the virtual hardware part. .   The correspondence unit associates the hardware part obtained by the search with the virtual hardware part according to the priority order based on the priority order of the hardware part to be associated with the virtual hardware part. The emulator according to claim 2.

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