JP2012165305A - Image processing device and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce scale of a circuit with high utilization efficiency of circuits such as line memories and delay elements.SOLUTION: A first stage filter 11 performs a filter calculation over a plurality of lines of image data, and a second stage filter 12 performs a filter calculation over a plurality of lines of image data on the subsequent stage of the filter 11. The setting circuit 50 assigns a part of a plurality of line memories 52 to the first stage filter 11, and another part of the plurality of line memories 52 to the second stage filter 12 in accordance with the number of lines of the filter calculation L1 of the first stage filter 11 and the number of lines of the filter calculation L2 of the second stage filter 12.

Description

  The present invention relates to an image processing apparatus and an image forming apparatus.

  In an image forming apparatus such as a printer or a multifunction peripheral, filter processing may be performed on image data.

  When a plurality of filters for performing a filter operation over a plurality of lines are provided, a number of line memories that are one less than the number of lines to be subjected to the filter operation are required for each filter (see, for example, Patent Document 1).

JP 2007-6133 A

  When the image processing apparatus has a plurality of stages of filters connected in a column, a line memory whose number is one less than the number of lines to be subjected to filter operation is required for each filter. Therefore, when the number of lines to be subjected to the filter operation is variable, a line memory that is one less than the maximum value of the number of lines for the filter operation is required for each filter. Further, when performing a filter operation on a plurality of columns, a number of delay elements that is one less than the maximum value of the number of columns in the filter operation is required for each line.

  For example, when the number of lines in the front stage filter is variable by any number from 1 to 8, and the number of lines in the rear stage filter is variable by any number from 1 to 8, the number of lines in the front stage is 7 Line memory is provided, and seven line memories are provided for the subsequent filter.

  Further, for example, when the number of columns of the front-stage filter is variable by any number from 1 to 8, and the number of columns of the rear-stage filter is variable by any number from 1 to 8, Seven delay elements connected in cascade for each line are provided, and seven delay elements connected in cascade for each line are provided for the subsequent filter.

  However, when performing a filter operation with a small number of lines, the number of unused line memories increases, and the utilization efficiency of circuits such as line memories decreases.

  SUMMARY An advantage of some aspects of the invention is that it provides an image processing apparatus and an image forming apparatus capable of reducing the circuit scale by increasing the use efficiency of a circuit such as a line memory. To do.

  In order to solve the above problems, the present invention is configured as follows.

  An image processing apparatus according to the present invention includes a pre-stage filter that performs a filter operation over a plurality of lines of image data, a post-stage filter that performs a filter operation over a plurality of lines of image data at a subsequent stage of the pre-stage filter, a plurality of line memories, Depending on the number of lines of the filter operation of the pre-stage filter and the number of lines of the filter operation of the post-stage filter, one or more line memories that are a part of the plurality of line memories are allocated to the pre-stage filter, and a plurality of lines A setting circuit that allocates one or more line memories, which are another part of the line memories.

  Thereby, since the sizes of the front-stage filter and the rear-stage filter can be arbitrarily set, it is possible to increase the use efficiency of the circuit, and to reduce the circuit scale of the image processing apparatus.

  In addition to the image processing apparatus described above, the image processing apparatus according to the present invention may be configured as follows. In this case, the setting circuit allocates (L1-1) line memories to the front-stage filter according to the number of lines L1 of the filter operation of the front-stage filter and the number of lines L2 of the filter operation of the rear-stage filter. L2-1) Allocate line memory.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus further includes an input selector that selects an input of the line memory from one of the output of the previous line memory and the input of the image data and the output of the previous filter. Then, the setting circuit controls the input selector to cascade the line memories assigned to the preceding filter, cascades the line memories assigned to the succeeding filter, and sets the line memory assigned to the preceding filter to the head of the line memory assigned to the preceding filter. Connect the image data input, and connect the output of the pre-filter to the head of the line memory assigned to the post-filter.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus further includes a delay circuit that is provided in the subsequent stage of the line memory and in which a predetermined number of delay elements are connected in cascade. Then, the setting circuit selects one or a plurality of delay elements in the delay circuit for the line memory assigned to the pre-filter, inputs the selected delay element and / or output to the pre-filter, and assigns it to the post-filter. One or a plurality of delay elements in the delay circuit for the selected line memory are selected, and the input and / or output of the selected delay element is input to the subsequent filter.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus further includes an output selector that selects the input of the delay circuit from the output of the line memory and at least one of the front-stage filter and the rear-stage filter.

  As a result, this delay circuit can be used for delaying the output of the pre-stage filter and the post-stage filter, and a delay circuit for acquiring a plurality of columns of pixel values can be connected to an external circuit (for example, another filter unit connected in parallel, which will be described later). Etc.) can be used for synchronization.

  The image processing apparatus according to the present invention may be as follows in addition to any of the image processing apparatuses described above. In this case, the image processing apparatus includes a plurality of filter units connected in parallel. Each of the plurality of filter units includes a front-stage filter, a rear-stage filter, a line memory, and a setting circuit.

  An image forming apparatus according to the present invention includes any of the image processing apparatuses described above.

  According to the present invention, in the image processing apparatus, the circuit utilization efficiency can be increased and the circuit scale can be reduced.

FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of the filter unit in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus according to an embodiment of the present invention. This image processing apparatus is built in, for example, an image forming apparatus such as a printer or a multifunction peripheral, and used for filtering image data to be printed.

  The image processing apparatus shown in FIG. 1 has three filter units 1 to 3 connected in parallel.

  Image data is sequentially input to the filter units 1 to 3 along the main scanning direction for each line. Then, the sum of the outputs of the filter units 1 to 3 is calculated by the adder 4 and output through the final stage filter 5.

  The filter unit 1 includes a front-stage filter 11, a rear-stage filter 12, and a delay circuit 13. The delay circuit 13 is a delay circuit for synchronizing the outputs of the filter units 1 to 3 connected in parallel.

  FIG. 2 is a block diagram illustrating a configuration example of the filter unit 1 in FIG.

  The filter unit 1 includes filters 11 and 12, line circuits 41 to 48, a selection circuit 49, and a setting circuit 50.

  The filter 11 is a pre-filter and is an arithmetic circuit that performs a filter operation on the pixel values of the L1 line and the M1 column. The filter 12 is a post-stage filter, and is an arithmetic circuit that performs a filter operation on the pixel values of the L2 line and the M2 column. For example, the filters 11 and 12 are opening and closing filters that perform expansion and contraction.

  The line circuit 41 has a delay circuit composed of delay elements 54 connected in cascade, and an image data input is connected to the leading delay element 54 of the line circuit 41. A flip-flop or the like is used for the delay element 54.

  Each of the line circuits 42 to 48 includes a delay circuit including an input selector 51, a line memory 52, an output selector 53, and delay elements 54 connected in cascade. This delay circuit is used to input pixel values of a plurality of columns to the filters 11 and 12, but also functions as the above-described delay circuit 13 as necessary.

  The input selector 51 of the line circuit 42 inputs one of image data input, the output of the filter 11 and the output of the filter 12 to the line memory 52 according to the value of the control signal. The input selector 51 of the line circuits 43 to 48 outputs any one of the output of the line memory 52, the output of the filter 11 and the output of the filter 12 to the line memory 52 according to the value of the control signal. input.

  The line memory 52 has a size corresponding to one line of image data, and the image data is sequentially input pixel by pixel along the main scanning direction, and the image is displayed pixel by pixel in the first-in first-out (FIFO) order. Output data.

  The output selector 53 inputs one of the output of the line memory 52, the output of the filter 11 and the output of the filter 12 to the head delay element 54 in accordance with the value of the control signal.

  This delay circuit has the same number of delay elements 54 as the number of line memories 52 (here, seven).

  The selection circuit 49 selects the input and / or output of one or more delay elements 54 in the line circuits 41 to 48 according to the control signal, and inputs the selected input and / or output to the filter 11 and the filter 12. To do.

  The setting circuit 50 inputs a control signal that is a value corresponding to a command such as a predetermined register value to the input selector 51, the output selector 53, and the selection circuit 49 of the line circuits 42 to 48.

  The setting circuit 50 assigns one or a plurality of line memories 52 to the filter 11 according to the number L1 of filter operations of the filter 11 in the front stage and the number of lines L2 of filter operation of the filter 12 in the rear stage. One or a plurality of line memories 52 are allocated.

  In this embodiment, (L1-1) line memories 52 are allocated to the filter 11, and (L2-1) line memories 52 are allocated to the filter 12. When the total number of line memories 52 is N, L1 and L2 can be arbitrarily set so that (L1-1) + (L2-1) ≦ N.

  Further, the setting circuit 50 controls the input selector 51 to (a) cascade-connect the line memories 52 assigned to the preceding filter 11 and (b) cascade the line memories 52 assigned to the succeeding filter 12 to each other. (C) Connect the image data input to the head of the line memory 52 assigned to the filter 11 in the previous stage, and (d) Connect the image data input to the head of the line memory 52 assigned to the filter 12 in the subsequent stage. Connect the output of.

  Further, the setting circuit 50 controls the selection circuit 49 to select (a) one or a plurality of delay elements 54 in the delay circuit for the line memory 52 assigned to the filter 11 in the previous stage, and the selected delay element 54. Are input to the filter 11 at the preceding stage, and (b) one or more delay elements 54 in the delay circuit for the line memory 52 assigned to the filter 12 at the subsequent stage are selected, and the selected delay element 54 is selected. The input and / or output is input to the subsequent filter 12.

  The filters 21 and 22 and the delay circuit 23 of the filter unit 2 are configured in the same manner as the filter unit 1. The same applies to the filters 31 and 32 and the delay circuit 33 of the filter unit 3. However, the number of line circuits similar to the line circuits 42 to 48 in the filter units 2 and 3 is not limited to 7, but may be other numbers. The delay circuit has the same number of delay elements 54 as the number of line circuits similar to the line circuits 42 to 48 (that is, the number of line circuits having the line memory 52).

  Next, the operation of the image processing apparatus will be described.

  As an initial setting, in each of the filter units 1 to 3, the setting circuit 50 controls the input selector 51, the output selector 53, and the selection circuit 49 of the line circuits 42 to 48 according to a command supplied as a register value or the like. Thereby, a desired filter calculation is executed by each of the filter units 1 to 3.

  For example, when the first-stage filter 11 performs a filter operation on a 3 × 3 (3 columns, 3 lines) pixel region, and the subsequent filter 12 performs a filter operation on a 4 × 3 (4 columns, 3 lines) pixel region. The setting circuit 50 controls the input selector 51, the output selector 53, and the selection circuit 49 of the line circuits 42 to 48 as follows. The setting circuit 50 causes the input filter 51 of the line circuit 42 to select the image data input, causes the input filter 51 of the line circuit 43 to select the output of the line memory 52 of the line circuit 42, and sets the line filter 42 to the output filter 53 of the line circuit 42. The output of the memory 52 is selected, the output filter 53 of the line circuit 43 is selected, and the output of the line memory 52 is selected. As an input to the filter 11, the selection circuit 49 has the first stage delay element 54 of the line circuits 41 to 43. The input and output and the output of the delay element 54 in the second stage are selected (see the part 61 in FIG. 2). The setting circuit 50 causes the input filter 51 of the line circuit 45 to select the output of the filter 11, causes the input filter 51 of the line circuit 46 to select the output of the line memory 52 of the line circuit 45, and outputs the output filter of the line circuit 44. 53 selects the output of the filter 11, causes the output filter 53 of the line circuits 45 and 46 to select the output of the line memory 52, and inputs the input to the filter 12 to the selection circuit 49 from the second stage of the line circuits 44 to 46. The output of the delay element 54 up to the fifth stage is selected (see the part 62 in FIG. 2). Further, the setting circuit 50 causes the input filter 51 of the line circuit 48 to select the output of the filter 12 and selects the output of the last delay element 54 of the line circuit 48 as the output of the filter unit 1. In this case, the delay element 54 of the line circuit 48 functions as the delay circuit 13 for synchronization. The delay amount by the delay circuit 13 is variable by selecting the delay element 54 that is the source of the output of the filter unit 1.

  As described above, according to the above-described embodiment, the front-stage filter 11 performs a filter operation over a plurality of lines of image data, and the rear-stage filter 12 is a filter that straddles a plurality of lines of image data at a subsequent stage of the filter 11. Perform the operation. The setting circuit 50 assigns a part of the line memory 52 to the previous filter 11 according to the number L1 of filter operations of the filter 11 of the preceding stage and the number of lines L2 of filter operation of the subsequent filter 12. Further, another part of the plurality of line memories 52 is assigned to the subsequent filter 12.

Thereby, since the sizes of the front-stage filter 11 and the rear-stage filter 12 can be arbitrarily set, the circuit utilization efficiency can be increased. As a result, the circuit scale of the image processing apparatus can be reduced.
it can.

  The above-described embodiments are preferred examples of the present invention, but the present invention is not limited to these, and various modifications and changes can be made without departing from the scope of the present invention. is there.

  For example, in the above embodiment, the number of filters 11 and 12 is 2, but the number of filters may be 3 or more. In the above embodiment, the total number of line filters 52 is 7, but a plurality of other line filters may be used. Furthermore, in the above embodiment, the number of delay elements 54 in each of the line circuits 41 to 48 is the same as the total number of line filters 52, but may be a different number. Further, in the above embodiment, the setting circuit 50 exists in each of the filter units 1 to 3, but the plurality of filter units 1 to 3 may be controlled independently by one setting circuit 50.

  The present invention is applicable to image processing of an image forming apparatus such as a printer or a multifunction peripheral.

1, 2, 3 Filter section 11 Filter (an example of a pre-filter)
12 Filter (an example of a post filter)
50 Setting Circuit 51 Input Selector 52 Line Memory 53 Output Selector 54 Delay Element

Claims (7)

A pre-stage filter that performs a filter operation across multiple lines of image data;
A post-stage filter that performs a filter operation across a plurality of lines of image data at the post stage of the pre-stage filter,
Multiple line memories,
According to the number of lines of the filter operation of the pre-stage filter and the number of lines of the filter operation of the post-stage filter, one or more line memories that are a part of the plurality of line memories are allocated to the pre-stage filter, A setting circuit that assigns one or more line memories, which are another part of the plurality of line memories, to a post-stage filter;
An image processing apparatus comprising:   The setting circuit stores (L1-1) line memories in the front-stage filter according to the number of lines L1 of the filter operation of the front-stage filter and the number of lines L2 of the filter operation of the rear-stage filter, and the rear-stage filter. 2. The image processing apparatus according to claim 1, wherein (L2-1) line memories are allocated to the filter. An input selector for selecting the input of the line memory from either the output of the previous line memory or the image data input and the output of the previous filter;
The setting circuit controls the input selector to cascade the line memories assigned to the preceding filter, cascades the line memories assigned to the succeeding filter, and assigns the line memory assigned to the preceding filter. Connecting the image data input to the head of the line, and connecting the output of the pre-stage filter to the head of the line memory assigned to the post-stage filter,
The image processing apparatus according to claim 1, wherein: A delay circuit provided at a subsequent stage of the line memory, in which a predetermined number of delay elements are connected in cascade;
The setting circuit selects one or a plurality of the delay elements in the delay circuit for the line memory assigned to the pre-filter, and inputs the input and / or output of the selected delay element to the pre-filter, Selecting one or more of the delay elements in the delay circuit for the line memory assigned to the post-stage filter and causing the input and / or output of the selected delay element to be input to the post-stage filter;
The image processing apparatus according to claim 1, wherein:   The image processing apparatus according to claim 4, further comprising an output selector that selects an input of the delay circuit from an output of the line memory and at least one of the front-stage filter and the rear-stage filter. It has a plurality of filter parts connected in parallel,
Each of the plurality of filter units includes the front-stage filter, the rear-stage filter, the line memory, and the setting circuit.
The image processing apparatus according to claim 1, wherein:   An image forming apparatus comprising the image processing apparatus according to claim 1.

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