JP2012164114A - Non-volatile semiconductor storage device and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate writing of a small amount of data on a non-volatile semiconductor storage device without using a cache function.SOLUTION: A non-volatile semiconductor storage device (1) connectable to a host system (2) includes a non-volatile semiconductor storage unit (11), and a controller (12) that controls the operation of the non-volatile semiconductor storage unit. The controller separately manages a correspondence relationship between a physical address and a logical address by using either the access unit on the host system side or the access unit on the non-volatile storage unit side. Based on the data size in a write command from the host system, the controller determines whether the data should be managed by using the access unit on the host system side or not, and whether the data should be managed by using the access unit on the non-volatile semiconductor storage unit or not, and then writes the data on the corresponding area in the non-volatile storage unit, thereby eliminating the need for saving the data on a buffer memory.

Description

  The present invention relates to a nonvolatile semiconductor memory device and a data processing system including the nonvolatile semiconductor memory device, and to a technique for speeding up small capacity writing in the nonvolatile semiconductor memory device.

  Patent Document 1 describes a technique for rewriting a nonvolatile memory. According to this, when executing the flash memory rewrite process by repeatedly erasing the written data and writing the download data for each sector of the flash memory, a check indicating the checksum of the written data of each sector is performed. The thumb table is stored in the flash memory. Acquires the checksum table of the download data created in the storage capacity unit corresponding to each sector, compares the checksum table corresponding to each sector with the checksum table, and processes the sector determined to match the value The execution of the erasure and writing as targets is omitted, and the checksum table is updated every time the rewriting process is executed.

  Patent Document 2 describes a storage device that can eliminate the need for redundant writing of non-selected data and can optimize the page arrangement to a state that is efficient for rewriting. According to this, a large-capacity main memory composed of a NAND flash memory and a relatively small-capacity auxiliary memory composed of a ferroelectric memory are connected to an external input / output interface circuit via an internal bus BS. . Further, the main memory is highly parallelized inside, and a 32 kB data group is simultaneously accessed as a unit page and transferred to and from the internal bus BS. An address table with pages as management units is constructed in the apparatus.

JP 2007-199985 A JP 2006-236304 A

  An example of a nonvolatile semiconductor memory device is a flash SSD (Solid State Drive). A flash SSD is a storage device that uses a flash memory, which is a semiconductor storage element, is a specification that emulates the functions of a hard disk drive, and has an interface equivalent to that of a hard disk drive. In addition to the flash memory, a dedicated controller and the like are incorporated in the device. A NAND type is used for the flash memory in the flash SSD. The flash SSD is characterized by being capable of high-speed access with a small capacity as compared with a hard disk drive, which is an important index representing the performance of the flash SSD. Small-capacity high-speed access is realized by using a cache function that temporarily stores data in a volatile memory such as a DRAM (dynamic random access memory) that can be accessed at a higher speed than a NAND flash memory. .

  However, since the cache in the NAND flash memory is a volatile memory such as a DRAM, there is a possibility that data in the cache may be lost due to an undesired power shutdown. Therefore, depending on the use of the flash SSD, it is strongly desired to increase the speed of small-capacity writing without using the cache function.

  In the conventional flash SSD, logical addresses are managed for each erase unit and program (write) unit of the NAND flash memory. The unit of the logical address is a sector. The program (write) unit is “page”, and one page is composed of a plurality of sectors. Therefore, when data for one sector is written from the host system to the NAND flash memory in the flash SSD, the page data including the sector is read from the NAND flash memory to the buffer memory. The data of the corresponding sector is updated. After this data update, the data in the buffer memory is written to another address in the NAND flash memory. After the writing is completed, the table for converting the logical address and the physical address is updated.

  However, as described above, when data for one sector is written from the host system to the NAND flash memory in the flash SSD, the page data including the sector needs to be read from the NAND flash memory to the buffer memory. For this reason, writing of a small capacity may be slowed down.

  An object of the present invention is to provide a technique for speeding up small-capacity writing in a nonvolatile semiconductor memory device without using a cache function.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, the nonvolatile semiconductor memory device that can be connected to the host system includes a nonvolatile memory unit and a controller that controls the operation thereof. The controller manages the correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit separately for the access unit on the host system side and the access unit on the nonvolatile storage unit side Then, the management in the access unit on the host system side and the management in the access unit on the nonvolatile storage unit side are determined according to the size of the data related to the write instruction from the host system. Based on the determination result, the controller writes data related to a write instruction from the host system in a corresponding area in the nonvolatile storage unit.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to increase the speed of small capacity writing in the nonvolatile semiconductor memory device without using the cache function.

1 is a block diagram illustrating a configuration example of a data processing system according to the present invention. It is explanatory drawing of the table referred with the flash SSD contained in the data processing system shown by FIG. It is explanatory drawing about the data structure of the flash array in the flash SSD contained in the data processing system shown by FIG. 2 is a flowchart of a write process in a flash SSD included in the data processing system shown in FIG. 5 is a flowchart showing details of a main part in the flowchart of the write process shown in FIG. 4. 5 is a flowchart showing details of a main part in the flowchart of the write process shown in FIG. 4. 5 is a flowchart showing details of a main part in the flowchart of the write process shown in FIG. 4. It is explanatory drawing of the logical-physical conversion table of the area | region managed in a block unit. It is explanatory drawing of the erasable PBA table. It is explanatory drawing of the logical-physical conversion table of the area | region managed in a page unit. It is explanatory drawing of a writable page table. It is explanatory drawing of the logical-physical conversion table of the area | region managed in a sector unit. It is a flowchart in the case of performing garbage collection for every reset process. It is a flowchart in the case of performing garbage collection for every reset process. It is a block diagram of another example of a structure of the data processing system concerning this invention. It is a flowchart of the garbage collection performed with the data processing system shown by FIG. It is a flowchart of the garbage collection performed with the data processing system shown by FIG. It is a flowchart of the garbage collection when the area | region for writing in "the area | region to logically convert in a unit smaller than a block" is insufficient. It is explanatory drawing of the erasure count value table. 18 is a garbage collection flowchart using the erase count value table shown in FIG.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A nonvolatile semiconductor memory device (1) according to a typical embodiment of the present invention is connectable to a host system (2), and includes a nonvolatile memory unit (11) and a controller for controlling its operation. (12). The controller manages the correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit separately for the access unit on the host system side and the access unit on the nonvolatile storage unit side Then, the management in the access unit on the host system side and the management in the access unit on the nonvolatile storage unit side are determined according to the size of the data related to the write instruction from the host system. Based on the determination result, the controller writes data related to a write instruction from the host system in a corresponding area in the nonvolatile storage unit.

  Here, in the data writing in the conventional apparatus, the data saving to the buffer memory is necessary because the correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit side is shown on the host system side. This is because it is not managed in units of access. As a result, for example, when data for one sector is written from the host system, it is necessary to read the data of the page including the sector into the buffer memory and update the data for the corresponding sector in the buffer memory. .

  On the other hand, according to the nonvolatile semiconductor memory device according to the representative embodiment of the present invention, in the access unit on the host system side according to the size of data related to the write instruction from the host system. Management and management in units of access on the nonvolatile storage unit side are determined, and a write destination of the data in the nonvolatile storage unit is determined based on the determination result. As described above, it is not necessary to save data to the buffer memory by determining an appropriate area as a write destination in the nonvolatile storage unit according to the size of the data related to the write instruction from the host system. Therefore, it is possible to increase the speed of small capacity writing from the host system to the nonvolatile semiconductor memory device. In addition, such high-speed writing of small capacity does not use a cache function such as a DRAM, so there is no need to worry that data in the cache is lost due to undesired power interruption.

  [2] In the above [1], when the erase unit of the nonvolatile storage unit is a block, the write unit of the nonvolatile storage unit is a page, and the write unit from the host system is a sector, the controller The correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit side can be managed separately for the block unit, the page unit, and the sector unit.

  [3] In the above [2], the nonvolatile storage unit includes a first area corresponding to the management in the block unit, a second area corresponding to the management in the page unit, and the sector unit. A third region corresponding to management can be formed. At this time, the controller writes the data in the first area when the size of the data related to the write instruction from the host system is larger than the size of the block. The controller writes the data in the second area when the size of the data related to the write instruction from the host system is smaller than the block size and larger than the page size. Further, the controller writes the data in the third area when the size of the data related to the write instruction from the host system is smaller than the block size and smaller than the page size.

  [4] In the above [3], the controller moves the valid data in the block corresponding to the second area or the block corresponding to the third area to another area, thereby moving the second area or the second area. A garbage collection process for increasing the free space in the three areas can be executed.

  [5] In the above [4], the garbage collection process can be executed for each reset process (FIGS. 13A and 13B).

  [6] In the above [4], the garbage collection process can be executed when the bus enabling the exchange of signals with the flash memory is in an idle state (FIGS. 15A and 15B).

  [7] In the above [4], the garbage collection process can be executed when the number of writable pages in the second area or the third area is smaller than a predetermined number (FIG. 16).

  [8] A data processing system (100) according to a representative embodiment of the present invention includes a nonvolatile semiconductor memory device (1) and a host system (2) capable of accessing the nonvolatile semiconductor memory device. . The non-volatile semiconductor memory device includes a non-volatile memory unit (11) and a controller (12) for controlling the operation thereof. The controller manages the correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit separately for the access unit on the host system side and the access unit on the nonvolatile storage unit side In accordance with the size of the data related to the write instruction from the host system, the management in the access unit on the host system side and the management in the access unit on the nonvolatile storage unit side are determined, and based on The data related to the write instruction from the host system is written into the corresponding area in the nonvolatile storage unit.

  According to the data processing system having the above configuration, according to the size of the data related to the write instruction from the host system, the management in the access unit on the host system side and the access unit on the nonvolatile storage unit side Management is determined, and the write destination of the data in the nonvolatile storage unit is determined based on the determination result. As described above, it is not necessary to save data to the buffer memory by determining an appropriate area as a write destination in the nonvolatile storage unit according to the size of the data related to the write instruction from the host system. Therefore, it is possible to increase the speed of small capacity writing from the host system to the nonvolatile semiconductor memory device. In addition, such high-speed writing of small capacity does not use a cache function such as a DRAM, so there is no need to worry that data in the cache is lost due to undesired power interruption.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 shows a data processing system according to the present invention. A data processing system 100 shown in FIG. 1 includes a flash SSD 1 and a host system (simply referred to as “host”) 2 that can access the flash SSD 1.

  The host 2 is not particularly limited, but may be a computer system (mobile PC) that can be carried around or a digital camera. A flash SSD 1 is coupled to the host 2 via a terminal.

  The flash SSD 1 includes a flash memory 11, a controller 12, and an external RAM 13, and can be read / written by the host 2. The flash memory 11, the controller 12, and the external RAM 13 are each formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

  The flash memory 11 is not particularly limited, but is a NAND type, and includes a buffer 111 and a flash array 112. Data writing to the flash array 112 and data reading from the flash array 112 are performed via the buffer 111. For example, as shown in FIG. 3, the write unit (referred to as “page”) for the flash array 112 is 2 kB + 64 B, and the erase unit (referred to as “block”) is 64 pages. The minimum unit of writing from the host 2 (referred to as “sector”) is 512B. The sector, page, and block sizes can be set arbitrarily. The flash memory 11 and the controller 12 are coupled via a bus BS.

  The controller 12 interprets the command given from the host 2 and controls the operation of the flash memory 11. The controller 12 is not particularly limited, but includes a ROM (Read Only Memory) 121, a RAM (Random Access Memory) 122, a CPU (Central Processing Unit) 123, an ECC (Error Detection and Correction) circuit 124, and a flash interface 125. , Page buffer 126, buffer interface 127, and host interface 128. The ROM 121 stores a program executed by the CPU 123. The CPU 123 controls the operation of each unit by executing a program in the ROM 121. The RAM 122 is used as a work area when the CPU 123 executes a program. The ECC circuit 124 detects and corrects a code error (error) that has occurred in the data read from the flash memory 1. The flash interface 125 mediates information exchange between the CPU 123, the ECC circuit 124, the buffer interface 127, and the flash memory 11. The page buffer 126 has a storage capacity corresponding to the writing unit of the flash memory 11. The buffer interface 127 mediates exchange of information between the flash buffer 125, the host interface 128, the external RAM 13, and the page buffer 126. The host interface 128 mediates exchange of information between the CPU 123, the buffer interface 127, and the host 2.

  The external RAM 13 is an SDRAM that operates in synchronization with a clock signal having a fixed period. The host 2 is not particularly limited, but is a computer system. Data to be written from the host 2 is temporarily stored in the external RAM 13 or the page buffer 126 and written to the flash array 112 via the buffer 111 of the flash memory 11. Here, each block of the flash array 112 can be written with data after being erased. When the host 2 reads data from the flash memory 11, the data is stored in the external RAM 13 or the page buffer 126 from the flash array 112 via the buffer 111 and then output to the host 2.

  Various tables are referred to in the arithmetic processing by the CPU 123. As the above-mentioned various tables, for example, as shown in FIG. 2, an area logical-physical conversion table TB1, an erasable PBA table TB2, an area logical-physical conversion table TB3 managed in page units, and a writable page A table TB4 and a logical-physical conversion table TB5 for areas managed in units of sectors can be listed.

  FIG. 8 shows a configuration example of the logical-physical conversion table TB1 for the area managed in units of blocks.

  The logical-physical conversion table TB1 of the area managed in units of blocks makes it possible to grasp the correspondence between the logical address and the physical address of the area managed in units of blocks, and the size thereof is 2048 bytes. A plurality of entries (Entry-0 to Entry-1023) are formed in the logical-physical conversion table. Entry-0 to Entry-1023 are physical information and are areas on the table for managing one block. One Entry is 16 bits (= 2B). As each Entry is enlarged, a PBA storage area (11 bits) and a flash array chip (Chip) number storage area (5 bits) are formed. PBA is indicated by 0-7FFh, and the chip number is indicated by 0-1Fh. LBA which is logical information is assigned to the vertical axis of the logical-physical conversion table. LBAs are assigned in ascending order corresponding to the Entry subscript (0 to 1023). For example, Entry-0 is assigned a size of one entry from LBA = 0, and Entry-1 is assigned a size of 1 Entry from the address next to Entry-0. For example, when the host 2 writes LBA0 data to the flash memory 11, the logical-physical conversion table is updated by rewriting the contents of Entry-0.

  FIG. 9 shows a configuration example of the erasable PBA table TB2.

  The erasable PBA table TB2 is a table that makes it possible to grasp which physical address of which chip has a block in which data relating to a logical address is not stored, and its size is 2048 bytes (bytes). A plurality of entries (Entry-0 to Entry-1023) are formed in the erasable PBA table TB2. Entry-0 to Entry-1023 are physical information and are areas on the table for managing one block. One Entry is 16 bits (= 2B). As each Entry is enlarged, a PBA storage area (11 bits) and a flash array chip (Chip) number storage area (5 bits) are formed. PBA is indicated by 0-7FFh, and the chip number is indicated by 0-1Fh. The erasable PBA table TB2 is a table for ascertaining which physical address of which chip has a block in which no data related to the logical address is stored. Since logical information is unnecessary, an LBA is assigned. Not.

  FIG. 10 shows a configuration example of the logical-physical conversion table TB3 for the area managed in units of pages.

  The logical / physical conversion table TB3 of the area managed in units of pages makes it possible to grasp the correspondence between the logical address and the physical address of the area managed in units of pages, and the size thereof is 2048 bytes. A plurality of entries (Entry-0 to Entry-168) are formed in the logical-physical conversion table TB3 of the area managed in units of pages. Entry-0 to Entry-168 are areas on the table for managing one page. One Entry is 70 bits. As each of the entries is enlarged, an LBA storage area (48 bits), a PBA storage area (11 bits), a page number storage area (6 bits) indicating a page address, and a flash array chip. A (Chip) number storage area (5 bits) is formed. PBA is indicated by 0-7FFF FFFF FFFFh, PBA is indicated by 0-7FFh, page number is indicated by 0-3Fh, and chip number is indicated by 0-1FFh.

  FIG. 11 shows a configuration example of the writable page table TB4.

  The writable page table TB4 is a table that enables grasping of writable pages, and its size is 2048 bytes. A plurality of entries (Entry-0 to Entry-681) are formed in the writable page table TB4. Entry-0 to Entry-681 are areas on the table for managing one page. One Entry is 22 bits. Each Entry has a PBA storage area (11 bits), a page (Page) storage area (6 bits) indicating a page address, and a flash array chip (Chip) number. A storage area (5 bits) is formed. PBA is indicated by 0-7FFh, page number is indicated by 0-3Fh, and chip number is indicated by 0-1FFh.

  FIG. 12 shows a configuration example of the logical-physical conversion table TB5 for the area managed in units of sectors.

  The logical-physical conversion table TB5 of the area managed in units of sectors makes it possible to grasp the correspondence between logical addresses and physical addresses in the areas managed in units of sectors, and the size thereof is 2048 bytes. A plurality of entries (Entry-0 to Entry-168) are formed in the logical-physical conversion table TB5 of the area managed in units of sectors. Entry-0 to Entry-168 are areas on the table for managing one sector. One Entry is 72 bits. Each Entry has an LBA storage area (48 bits), a PBA storage area (11 bits), a page (Page) number storage area (6 bits), a flash, as shown in an enlarged view of one of them. An array chip number (Chip) number storage area (5 bits) and a sector number (2 bits) are formed. The LBA is indicated by 0 to FFFF FFFF FFFFh, the PBA is indicated by 0 to 7FFh, the page number is indicated by 0 to 3Fh, the chip number is indicated by 0 to 1FFh, and the number of sectors is indicated by 0 to 3h.

  Area logical-physical conversion table TB1 managed in block units, erasable PBA table TB2, area logical-physical conversion table TB3 managed in page units, writable page table TB4, area logical-physical conversion table managed in sector units TB5 is stored in the flash array 112 and is loaded into the page buffer 126 or the external RAM 13 in the initialization process of the flash SSD1. The table reference and update of the table information by the CPU 123 are performed on the table loaded in the page buffer 126 or the external RAM 13. When the table information is updated, the table in the flash array 112 is updated accordingly.

  FIG. 4 shows the flow of write processing in the flash SSD 1.

  A write command is issued from the host 2 to the flash SSD 1 (S301). The CPU 123 in the flash SSD 1 analyzes the write command, obtains a write destination LBA (Logical Block Address) and the number of write sectors (S302), and sets the number of write sectors as “the number of sectors specified by the host”. (S303). Here, “LBA” means a logical block address on the host side. The write data is temporarily stored in the page buffer 126 via the host interface 128 and the buffer interface 127. Then, the CPU 123 determines whether or not the number of write sectors is larger than the block size (S304). In this determination, if it is determined that the number of write sectors is larger than the block size (Yes), the process for writing the write data relating to the write destination LBA acquired in step S302 to the area managed by the block Is executed by the CPU 123 (S306). If it is determined in step S304 that the number of write sectors is smaller than the block size (No), the CPU 123 determines whether the write size is larger than the page size (S305). In this determination, when it is determined that the write size is larger than the page size (Yes), the CPU 123 executes a process for writing the write destination LBA acquired in step S302 in the area managed by the block. (S307). If it is determined in step S305 that the write size is smaller than the page size (No), a process for writing the write destination LBA acquired in step S302 into the area managed in units of sectors is performed. This is executed by the CPU 123 (S308). Note that the processes in steps S306, S307, and S308 will be described in detail later.

  After each of the above steps S306, S307, and S308, the number of sectors actually written is subtracted from the number of write sectors, and it is determined whether or not the number of write sectors is greater than 0 (S310). In this determination, if it is determined that the number of write sectors is greater than 0 (Yes), since the writing is still possible, the process returns to the determination in step S304. If it is determined in step S310 that the number of write sectors is not greater than 0 (No), writing is impossible, and the processing according to this flowchart ends.

  FIG. 5 shows details of the write process (process for writing the write data relating to the write destination LBA to the area managed in block units) in step S306 in FIG.

  In the process for writing the write data relating to the write destination LBA to the area managed in block units, the CPU 123 first refers to an erasable PBA (Physical Block Address) table to obtain the address of the erasable block. (S401), the erasable block corresponding to the address is erased. The CPU 123 writes the host transfer data stored in the page buffer 126 to the block erased in step 402 (S403). Thereafter, the CPU 123 updates the logical-physical conversion table TB1 and the erasable PBA table TB2 of the area managed in block units (S404). Here, the logical-physical conversion table TB1 of the area managed in units of blocks enables conversion between logical addresses and physical addresses in the areas managed in units of blocks, and is formed in the page buffer 126 or the external RAM 13.

  FIG. 6 shows details of the processing in step S307 in FIG. 4 (processing for writing the write data relating to the write destination LBA to the area managed in block units).

  In the process for writing the write data relating to the write destination LBA to the area managed in block units, the CPU 123 first acquires the address of the writable page with reference to the writable page table TB4 (S501). The writable page table TB4 is formed in the page buffer 126 or the external RAM 13. Then, the CPU 123 determines whether there is a writable page (S502). If it is determined that there is a writable page (Yes), the host transfer data temporarily stored in the page buffer 126 is written to the flash array 112 (S506). If it is determined in step S502 that there is no writable page (No), the CPU 123 refers to the erasable PBA table TB2 and acquires the address of the erasable block (S503). Is erased (S504), and then a writable page is obtained from the erased block (S505). Then, the host transfer data is written to the acquired landing-possible page (S506). The CPU 123 determines whether or not erasure has been executed (S507). In this determination, if it is determined that erasure is not executed (No), the logical-physical conversion table of “area managed in units of pages” and the writable page table TB4 are updated (S508). If it is determined in step S507 that erasure has been executed (Yes), the logical-physical conversion table, the writable page table TB4, and the erasable PBA table TB2 in “area managed in units of pages” are updated. (S509).

  FIG. 7 shows details of the processing in step S308 in FIG. 4 (processing for writing the write data relating to the write destination LBA to the area managed in units of sectors).

  In the process for writing the write data related to the write destination LBA to the area managed in units of sectors, first, the CPU 123 refers to the writable page table TB4 to obtain the address of the writable page (S601). Then, the CPU 123 determines whether there is a writable page (S602). If it is determined that there is a writable page (Yes), the host transfer data temporarily stored in the page buffer 126 is written to the flash array 112 (S606). When determining in step S602 that there is no writable page (No), the CPU 123 refers to the erasable PBA table TB2 to acquire the address of the erasable block (S603), and Is erased (S604), and then a writable page is obtained from the erased block (S605). Then, the host transfer data is written to the acquired landing-possible page (S606). The CPU 123 determines whether or not erasure has been executed (S607). In this determination, if it is determined that erasure is not executed (No), the logical-physical conversion table of “area managed in sector units” and the writable page table TB4 are updated (S608). If it is determined in step S607 that erasing has been executed (Yes), the logical / physical conversion table, the writable page table TB4, and the erasable PBA table TB2 of “area managed in sector units” are updated. (S609).

  Next, garbage collection will be described.

  The “area for logical-physical conversion in units smaller than the block” may be limited to an area that is smaller than the entire capacity of the flash SSD 1, and therefore, if writing is performed continuously from the host 2, there may be no free pages. . For this reason, the controller 12 executes garbage collection for creating an empty page in the “area for logical-physical conversion in units smaller than the block”. Garbage collection can be executed (1) every time the flash SSD 1 is reset.

  First, a case where garbage collection is executed for each reset process of the flash SSD 1 will be described.

  FIGS. 13A and 13B show a flowchart in a case where garbage collection is executed for each reset process. In FIG. 13A and FIG. 13B, “CON1” indicates that the processing is continuous.

  When the flash SSD 1 is turned on or a reset signal is asserted, a predetermined reset process is started (S1301). That is, the CPU 123 executes a predetermined reset program. During the reset process in the flash SSD 1, the host 2 is busy. Before the busy state is canceled, the CPU 123 performs the following processing.

  First, the CPU 123 checks the number of empty pages in the “region to be logically converted in units smaller than the block” (S1302). This confirmation is performed by referring to the logical / physical conversion table TB3 of the area managed in units of pages and the logical / physical conversion table TB5 of the area managed in units of sectors. Then, it is determined whether or not the number of empty pages in the “region for logical-physical conversion in units smaller than the block” is equal to or less than a specified value (S1303). In this determination, if it is determined that the number of free pages in the “area for logical-physical conversion in units smaller than the block” is equal to or less than the predetermined value (Yes), garbage collection is necessary, so the erasable PBA table TB2 Is referred to, erasable PBA is acquired (S1304), and the acquired erasable PBA is erased (S1305). Next, a block having the number of empty pages equal to or less than a predetermined value in the block of “region to be logically converted in units smaller than the block” is selected (S1306), and the processing page number is set to “0”. Here, “processing page number” means an internal variable. Then, it is determined whether or not the time required for the garbage collection process exceeds a specified time (S1308). Here, the “specified time” means a time allowed for the reset process, for example. The garbage collection process needs to be completed within the time allowed for this reset process. If it is determined that the time required for the garbage collection process does not exceed the specified time (No), it is determined whether the number of processed pages is less than the maximum number of pages in the block (S1309). That is, it is determined whether or not the page number to be processed has reached the maximum number of pages in the block erased in step S1305. In this determination, if it is determined that the number of processed pages is less than the maximum number of pages in the block (Yes), it is determined whether there is valid data on the page (S1310). In this determination, if it is determined that there is valid data on the page (Yes), the valid data is read to the page buffer 126 (S1312). Then, it is determined whether or not the data read to the page buffer 126 is equal to or larger than the page size (S1313). In this determination, if it is determined that the data read to the page buffer 126 is equal to or larger than the page size (Yes), the data read to the page buffer 126 is stored in the PBA erased in step S1305. It is written (S1314). Thereafter, after the process page number is incremented (S1311), the process returns to the determination in step S1308 to perform the garbage collection process for the next process page number.

  In the determination in step S1303, if it is determined that the number of empty pages in the “region to be logically converted in units smaller than the block” is not less than the predetermined value (No), “logically convert in units smaller than the block”. There are enough free pages in the area, and garbage collection is not required. In this case, it is determined whether or not data remains on the page buffer 126 (S1315). In this determination, if it is determined that data remains on the page buffer 126 (Yes) (Yes), the data is written to the PBA erased in step S1305 (S1316). Thereafter, it is determined whether or not the data has been moved by garbage collection (S1317). In this determination, if it is determined that the data has been moved by garbage collection (Yes), the logical-physical conversion table of “area to logically convert in units smaller than blocks”, that is, the area to be managed in page units The logical / physical conversion table TB3 and the logical / physical conversion table TB5 of the area managed in units of sectors, the logical / physical conversion table TBTB1 of the area managed in units of blocks, the erasable PBA table TB2, and the writable page table TB4 are updated (S1318). After that, the reset busy is canceled, and the end of the reset process is notified to the host 2 (S1319).

  If it is determined in step S1308 that the time required for the garbage collection process exceeds the specified time (Yes), the garbage collection process should not be performed. Similarly to the case where it is determined that the number of empty pages in the “area to be logically converted in units” is not less than or equal to the predetermined value (No), the process proceeds to the determination of whether data remains on the page buffer 126 (S1315). ).

  If it is determined in step S1310 that there is no valid data on the page (No), the processing page number is incremented (S1311) and then returned to the determination in step S1308. The garbage collection process for the process page number is performed. If it is determined in step S1313 that the data on the page buffer is not equal to or larger than the page size (No), the processing page number is incremented without writing the data in step S1314 ( In step S1311, the process returns to the determination in step S1308 to perform the garbage collection process for the next process page number. If it is determined in step S1309 that the number of processed pages is not less than the maximum number of pages in the block (No), the garbage collection processing for all the processed page numbers is completed. The process returns to the confirmation process in S1302.

  When a read command is issued from the host 2, the controller 12 refers to the logical / physical conversion table TB 1, TB 3, or TB 5, and data related to the read command is read from the flash memory 11 and sent to the host 2. Communicated.

  According to this embodiment, the following effects can be obtained.

  According to the conventional system, the logical address is managed for each flash memory erase unit or program (write) unit. Therefore, when writing data for one sector from the host system to the flash memory in the flash SSD. The data of the page including the sector is read from the flash memory to the buffer memory, and then the data of the corresponding sector in the buffer memory is updated. After the data update, the data in the buffer memory is changed to another address in the flash memory. Written in. Thus, when data for one sector is written from the host system to the flash memory in the flash SSD, data other than the sector to be written by the host system must be read from the flash memory. This hinders the speeding up of small capacity writing.

  On the other hand, in the flash SSD 1 shown in FIG. 1, the write destination of the data in the nonvolatile storage unit is determined according to the number of write sectors. For example, when one sector of data is written to the flash memory 11, data is written to an area managed in units of sectors. As in the case of data writing in the conventional system, the buffer memory is written. Since it is not necessary to save data to the memory, it is possible to increase the speed of small-capacity writing.

  In addition, by performing the garbage collection process for each reset process, if there is valid data in the block, it is all moved to another area, and the block is made writable again by erasing. Thereby, the writable free space can be increased.

<< Embodiment 2 >>
FIG. 14 shows another configuration example of the flash SSD 1 as an example of the nonvolatile semiconductor memory device according to the present invention.

  The flash SSD 1 shown in FIG. 14 is greatly different from that shown in FIG. 1 in that a plurality of flash memories 11A, 11B, 11C, and 11D are provided. Each of the flash memories 11A, 11B, 11C, and 11D is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The flash interface 125 in the controller 12 and the flash memories 11A, 11B, 11C, and 11D are coupled to each other by dedicated buses BS1, BS2, BS3, and BS4, respectively. The controller 12 controls the operation of the flash memories 11A, 11B, 11C, and 11D via the buses BS1, BS2, BS3, and BS4. The basic contents of the operation control for the flash memories 11A, 11B, 11C, and 11D are the same as those of the flash SSD 1 shown in FIG.

  In the configuration shown in FIG. 14, the buses BS1, BS2, BS3, BS4 are not always used. For example, when data is written to the flash memories 11A to 11C, but data is not written to the flash memory 11D, the bus BS4 is in an idle state (empty state). It is possible. Therefore, when there is an idle bus, garbage collection processing for the corresponding flash memories 11A, 11B, 11C, and 11D can be executed using the bus.

  FIGS. 15A and 15B show a flowchart in the case of executing the garbage collection process using the idle bus. In FIGS. 15A and 15B, “CON2” indicates that the processing is continuous. This garbage collection process is performed by the CPU 123.

  After the command is received from the host 2, the LBA to be written and the number of sectors are acquired (S1401, S1402), and it is determined whether or not there is an idle bus (S1403). The write destination is determined by the information (LBA to be written and the number of sectors) acquired in step S1402. When the write destination is determined, the bus to be used at that time is determined, so that it is possible to determine whether or not there is an idle bus. If it is determined that there is no idle bus (No), garbage collection is not executed. If it is determined that there is an empty bus, it is checked whether or not there is a block whose number of empty pages is equal to or less than a predetermined value in the flash memory corresponding to the bus with reference to the writable page table TB4. (S1404, S1405). If it is determined in step S1405 that there is a block whose number of empty pages is equal to or less than the predetermined value (Yes), the erasable PBA is acquired with reference to the erasable PBA table TB2, and the corresponding data is erased. (S1406, 1407).

  Before moving the data by garbage collection, it is confirmed whether or not the processing of the command given from the host 2 has been completed (S1410). If it is determined that the command processing has been completed (Yes), garbage collection is not performed. If it is determined that the processing of the command given from the host 2 has not ended (No), garbage collection is executed (S1411 to S1416). The garbage collection processing in steps S1411 to S1416 corresponds to the processing in steps S1309 to S1314 in FIG. 13A. That is, referring to the logical-physical conversion table (TB3, TB5) of the area to be logically converted in units smaller than the block, it is confirmed whether there is valid data in the selected block (S1412), and there is valid data The data is read into the page buffer. It is checked whether or not data larger than the page size has been read into the page buffer (S1415), and when data larger than the page size is read, the data is written (S1416). If it is less than the page size, the garbage collection is continued without writing.

  When the garbage collection end condition is reached, it is checked whether or not unwritten data remains on the page buffer 126 (S1417), and writing of the read data is executed only when the data remains. (S1418). Thereafter, it is determined whether or not the data has been moved during the garbage collection (S1419). When the data is moved, the logical-physical conversion table (TB3, TB5) of the area to be logically converted in units smaller than the block. ), The logical-physical conversion table TB1 and the erasable PBA table TB2 of the area managed in block units are updated to change the correspondence relationship of logical-physical conversion (S1420).

  By using the bus in the idle state in this way, the garbage collection process can be executed without hindering the read / write operation of the flash memory.

<< Embodiment 3 >>
In the configuration shown in FIG. 1 or FIG. 14, when “the area for logical-physical conversion in units smaller than the block” is less than the entire capacity of the flash SSD 1, or in the “area for logical-physical conversion in units smaller than the block” Garbage collection can be executed even when there is not enough space.

  FIG. 16 shows a garbage collection flowchart in the case where there is a shortage of an area for writing in “an area for logical-physical conversion in units smaller than a block”.

  After the write command is received from the host (S1501), it is determined whether or not there is a writable page to be written in the “area to be logically converted in units smaller than the block” (S1502). In this determination, when it is determined that a writable page exists (Yes), writing to the writable page is executed (S1510), and the logical area of “region to be logically converted in units smaller than the block” The conversion table (TB3, TB5) and the writable page table TB4 are updated (S1511), and the processing according to this flowchart ends. If it is determined in step S1502 that there is no writable page (No), it is determined whether or not the erasable PBA is equal to or less than a specified value (S1503). In this determination, if it is determined that it is not less than the specified value (No), the erasable page is erased (S1504), the erased area is made a writable page, and the process proceeds to the write process in step S1510. The If it is determined in step S1503 that the erasable PBA is equal to or less than the specified value (Yes), the logical-physical conversion table (TB3, TB5) of “region for logical-physical conversion in units smaller than the block” is stored. With reference to the block, the block having the smallest valid data is selected (S1505). Valid data of the selected block is read to the page buffer 126 (S1506), the erasable PBA is erased (S1507), and valid data on the page buffer 126 is written to the erased block (S1508). Then, the logical-physical conversion table (TB3, TB5), the writable page table TB4, and the erasable PBA table (TB4) of “area for logical-physical conversion in units smaller than the block” are updated (S1509). As a result, the block having the smallest valid data can be made an erasable PBA, and an area storing invalid data that cannot be written can be made free. After the process of step S1509, the process proceeds to the write process of step S1510. As described above, according to the processing shown in FIG. 16, the “area to be logically converted in units smaller than the block” is smaller than the total capacity of the flash SSD 1 or the “area to logically convert in units smaller than the block”. Garbage collection can be executed even when the area for writing is insufficient.

<< Embodiment 4 >>
A memory element of a flash memory is deteriorated by electrons penetrating an oxide film serving as an insulator on the principle of operation, so that the number of erasures is limited. Therefore, in order to extend the product life of the flash SSD 1, it is desirable to equalize the number of erases for each block. In order to equalize the erase count for each block, it is preferable to have a table for managing the erase count as shown in FIG. 17 in addition to the erasable PBA table TB2. The erase count value table shown in FIG. 17 counts the erase count for each entry (Entry-0 to Entry-1023) shown in FIG.

  FIG. 18 shows the flow of processing using the erase count value table shown in FIG.

  First, referring to the erase count value table shown in FIG. 17, the PBA having the smallest erase count is acquired as the garbage collection execution PBA (S1701), and the garbage collection is executed in the logical-physical conversion tables (TB1, TB3, TB5). By confirming that the PBA is not registered, it is determined whether or not valid data exists in the garbage collection execution PBA (S1702). In this determination, if it is determined that there is no valid data in the garbage collection execution PBA (No), garbage collection is executed using the garbage collection execution PBA (S1706). The specific processing contents of the garbage collection are as described with reference to FIGS. 13A and 13B and FIGS. 15A and 15B. Then, the erase count of the erased PBA in the erase count value table is incremented (S1707).

  If it is determined in step S1702 that there is valid data in the garbage collection execution PBA (Yes), the erasable PBA having the maximum number of deletions is deleted (S1703) and stored in the garbage collection execution PBA. The valid data that has been deleted is moved to the PBA erased in step S1703 (S1704). The logical-physical conversion tables TB1, TB3, TB5, the erasable PBA table TB2, and the writable page table TB5 are updated, whereby the garbage collection execution PBA is changed to the erasable PBA (S1705).

  Since the processing shown in FIG. 18 is periodically performed, even for a block in which data writing by a command from the host 2 is extremely small, data is periodically moved by the processing in step S1704, and the erasable PBA table TB2 or Therefore, all blocks in the flash memory are periodically erased because they are described in the writable page table TB5. As a result, the number of times of erasing for each block can be leveled, so that the product life of the flash SSD 1 can be extended.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

1 Flash SSD
2 Host 11, 11A to 11D Flash memory 12 Controller 13 External RAM
111 Buffer 112 Flash array 121 ROM
122 RAM
123 CPU
124 ECC
125 Flash interface 126 Page buffer 127 Buffer interface 128 Host interface BS, BS1 to BS4 bus

Claims (8)

A non-volatile semiconductor storage device connectable to a host system,
A nonvolatile storage unit and a controller for controlling the operation thereof,
The controller manages the correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit separately for the access unit on the host system side and the access unit on the nonvolatile storage unit side In accordance with the size of the data related to the write instruction from the host system, the management in the access unit on the host system side and the management in the access unit on the nonvolatile storage unit side are determined, and based on A nonvolatile semiconductor memory device, wherein data related to a write instruction from the host system is written into a corresponding area in the nonvolatile memory unit.   When the erase unit of the non-volatile storage unit is a block, the write unit of the non-volatile storage unit is a page, and the write unit from the host system is a sector, the controller has a logical address on the host system side and the The nonvolatile semiconductor memory device according to claim 1, wherein the correspondence relationship with the physical address on the nonvolatile memory unit side is managed separately for the block unit, the page unit, and the sector unit. The nonvolatile storage unit includes a first area corresponding to the management in the block unit, a second area corresponding to the management in the page unit, and a third area corresponding to the management in the sector unit. ,
The controller writes the data in the first area when the size of the data related to the write instruction from the host system is larger than the size of the block, and the size of the data related to the write instruction from the host system is When the size is smaller than the block size and larger than the page size, the data is written to the second area, the size of the data related to the write instruction from the host system is smaller than the block size, and 3. The nonvolatile semiconductor memory device according to claim 2, wherein when the size is smaller than a page size, the data is written in the third area.   The controller moves the valid data in the block corresponding to the second area or the block corresponding to the third area to another area, thereby increasing the garbage in the second area or the third area. The nonvolatile semiconductor memory device according to claim 3, wherein the collection process is executed.   The nonvolatile semiconductor memory device according to claim 4, wherein the controller executes the garbage collection process every reset process.   The nonvolatile semiconductor memory device according to claim 4, wherein the controller executes the garbage collection process when a bus that enables signal exchange with the flash memory is in an idle state.   5. The nonvolatile semiconductor memory device according to claim 4, wherein the controller executes the garbage collection process when the number of writable pages in the second area or the third area is smaller than a predetermined number. A data processing system comprising a nonvolatile semiconductor memory device and a host system accessible to the nonvolatile semiconductor memory device,
The non-volatile semiconductor storage device includes a non-volatile storage unit and a controller that controls the operation thereof,
The controller manages the correspondence between the logical address on the host system side and the physical address on the nonvolatile storage unit separately for the access unit on the host system side and the access unit on the nonvolatile storage unit side In accordance with the size of the data related to the write instruction from the host system, the management in the access unit on the host system side and the management in the access unit on the nonvolatile storage unit side are determined, and based on A data processing system, wherein data related to a write instruction from the host system is written into a corresponding area in the nonvolatile storage unit.

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