JP2012161132A - Overcurrent relay - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an overcurrent relay that can implement fast recovery even in the case where a DC component flows at the occurrence of a system accident.SOLUTION: An overcurrent relay includes: an overcurrent determination section 40 for outputting a first recovery signal to recover a CB 2 from an open state to a closed state according to an effective value Irms and a determination value Is; a current recovery determination section 50 for removing a DC component included in a current I, performing phase shifting of shifting the phase of a current I0 in which the DC component is removed to generate phase-shifted currents I1-I3, and outputting a second recovery signal to recover the CB 2 from the open state to the closed state according to the phase-unshifted current I0 and the phase-shifted currents I1-I3; and a recovery control section 60 for stopping an overcurrent element operation signal when either the first recovery signal or the second recovery signal is input.

Description

  The present invention relates to a protection relay applied for protecting a power system (system), and more particularly to an overcurrent relay (relay) that protects a system based on a current detected in the system.

  The conventional relay compares the CT secondary current from the current transformer (CT) installed in the system with the set value set inside the relay, and when this current is larger than the set value, By detecting an accident and outputting an operation, a circuit breaker (CB: Circuit Breaker) disposed in the system is driven to eliminate the system accident. Further, the relay is configured to turn off (return) the operation output when the current becomes smaller than the set value.

  The CB is opened when an operation command (CB open command) is received from the relay that has detected a system fault, and this disconnects the system and eliminates the fault current flowing through the CB. However, when the CB is not operating due to the CB failure despite receiving the CB release command (CBF: Circuit Breaker Failure), the accident current continues to flow. A relay used for the purpose of detecting such a CBF, for example, takes in a CB release command output from another external relay and uses the CB release command as a starting condition for a set fixed time (CBF detection time). If the current continues to flow, the CB is detected to be inactive. When it is detected that the CB is not operating, a CB release command is output to all CBs surrounding the CB on the system where the CB is disposed. In this way, systematic accidents are eliminated.

  Here, when the system fault is removed, it is necessary to return the relay at high speed from the viewpoint of protection coordination. To explain this, for example, when the return time of the relay that is performing current detection is slow even though the system fault is removed and the current flowing through the system becomes zero, the above-described setting of the CBF detection time is performed. Cannot be shortened. That is, when the CB is not operating, the output of the CB release command to all the CBs surrounding the CB on the system where the CB is disposed is delayed, and the removal of the system fault is delayed. Therefore, if the relay can be returned at high speed when the accident is recovered, the CBF detection time can be shortened, and the system fault can be removed more quickly. Thus, the relay applied for CB malfunction prevention needs to return at high speed at the time of system fault recovery from the relationship of protection coordination.

  For example, a peak value detection method exists as a conventional method for realizing a high-speed return of the relay. In this method, the input peak value is sampled every 30 electrical degrees, and the six sampled values are compared with a predetermined settling value. However, since this peak value detection method uses six consecutive sample values, there is a drawback that when the AC input changes, the response is delayed due to the influence of the sample values before the change. Specifically, in order to detect a peak value every 180 degrees, the input current needs to be correctly alternating, but the grid current is affected by reactance and capacitance existing in the grid. When a system fault occurs, it may be affected by DC components and harmonic distortion. In order to avoid such an influence, a filter circuit for removing a direct current component and removing a harmonic component is required. However, this filter circuit slows down the transient transition of the current, and delays in operation detection and return detection.

  As means for solving such a problem, the prior art disclosed in Patent Document 1 below samples an electric quantity at a predetermined time interval, obtains an absolute value of the sampled output signal, and compares it with a predetermined settling value. First, absolute values of a plurality of sample values within a time interval of 90 electrical degrees are respectively obtained, and a value obtained by multiplying the set value by sin 45 ° = 1 / √2 is compared as a new set value. And two means. Then, after the system fault is detected by the first means, the operation is continuously determined by switching to the second means. In the second comparison means, for example, in the case of 30 ° sampling, four sample values are obtained. Is compared with the settling value, and when the sample value is smaller than the settling value, the recovery judgment is made at the time of recovery from the accident, thereby achieving a high-speed return.

Japanese Patent Laid-Open No. 3-45116 (Section 1 “Problems to be Solved by the Invention”, Section 2 “Means for Solving the Problems”, Section 2 “Operation”)

  However, the conventional technique represented by the above-mentioned Patent Document 1 increases the recovery time from a large current to some extent by giving a difference between the operation value and the return value (in the example of Patent Document 1, the speed is increased by 60 degrees). However, when returning from a large current, the effect of the delay caused by the filter circuit described above is large, so high speed recovery cannot be expected. Furthermore, as another problem, when CT is saturated with a large current, a DC component due to energy release from CT excitation reactance may flow to the CT secondary side even after CB is opened. Since the time until the value becomes less than the set value becomes longer, the return is further delayed.

  The present invention has been made in view of the above, and an object of the present invention is to obtain an overcurrent relay capable of realizing a high-speed recovery even in a case where a DC component flows when a system fault occurs.

  In order to solve the above-described problems and achieve the object, the present invention provides an overcurrent relay that operates a circuit breaker provided in a power system based on a current detected in the power system to protect the power system. A first overcurrent determination unit that outputs a first return signal for returning the output of the overcurrent relay based on an effective value of the current and a predetermined determination value; and included in the current The first current is generated after the phase shift process is performed to remove the DC component to be generated and the phase of the first current data from which the DC component has been removed is changed to generate the second current data after the phase shift process. A second overcurrent determination unit that outputs a second return signal for returning the output of the overcurrent relay based on the data and the second current data; and the first return signal and the second return Overcurrent element movement when any of the signals is input Characterized by comprising a return control unit for stopping the signal.

  According to this invention, after removing the direct current component included in the current detected from the system and generating the current after the phase shift process by performing the phase shift process to change the phase of the current from which the direct current component has been removed, Since it was made to return based on the current before the phase shift process and the current after the phase shift process, the effect that a high-speed return can be realized even in a case where a DC component flows when a system fault occurs. Play.

FIG. 1 is a configuration diagram of an overcurrent relay according to the first embodiment of the present invention. FIG. 2 is a diagram for explaining the operating principle of the overcurrent relay shown in FIG. FIG. 3 is a configuration diagram of the overcurrent relay according to the second embodiment of the present invention. FIG. 4 is a configuration diagram of an overcurrent relay according to the third embodiment of the present invention.

  Embodiments of an overcurrent relay according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram of an overcurrent relay (relay) 4 according to the first exemplary embodiment of the present invention. FIG. 1 schematically shows a power transmission line 1 of a system to be protected by the relay 4, a CB 2 disposed in the power transmission line 1, and a CT 3 disposed in the power transmission line 1. The current I flowing through the transmission line 1 is converted into a CT secondary current by CT3 and input to the relay 4.

  The relay 4 mainly includes an input converter 5, an analog filter circuit 6, an analog-digital converter 7, a CBF detection relay 8, a digital input (DI) circuit 23, and a first digital output relay. A (DO: Digital Output) circuit 16 and a second digital output relay circuit 26 are provided.

  The input converter 5 converts the CB secondary current from CT 3 into an appropriate voltage signal that can be used in the relay 4. The analog filter circuit 6 removes harmonic components, and the analog-to-digital converter 7 performs analog-to-digital conversion of the current I from which the harmonic components have been removed by the analog filter circuit 6 at a constant sampling period.

  The CBF detection relay 8 mainly includes an overcurrent determination unit 40 (first overcurrent determination unit), a current return determination unit (second overcurrent determination unit) 50, a return control unit 60, and a logical product. An (AND) circuit 24 and a fourth operation timer (T4) circuit 25 are provided.

  Hereinafter, the configuration of the CBF detection relay 8 will be described. First, the overcurrent determination unit 40, the return control unit 60, the first digital output relay circuit 16, the digital input circuit 23, the AND circuit 24, the fourth operation timer circuit 25, and the second digital output shown in FIG. The (DO) relay circuit 26 will be described.

  The overcurrent determination unit 40 mainly includes a first digital filter circuit 9-1, an effective value calculation circuit 10, a comparison circuit 11, a first operation timer (T1) circuit 12, and an inverted signal-added first circuit. 2 operation timer (T2) circuit 15. The return control unit 60 includes a logical sum (OR) circuit 22 and a flip-flop circuit 13 as main components.

  The first digital filter circuit 9-1 removes a distorted wave component of the current I converted into digital data by the analog-digital converter 7 and extracts a fundamental wave AC component of the current I. The effective value arithmetic circuit 10 measures the effective value Irms using the digital data from the first digital filter circuit 9-1. The comparison circuit 11 compares the effective value Irms from the effective value calculation circuit 10 with a predetermined determination value Is. The comparison circuit 11 outputs the output “1” to the first operation timer circuit 12 when the effective value Irms is equal to or greater than the determination value Is, and outputs the output “0” when the effective value Irms is less than the determination value Is. It outputs to the 2nd operation | movement timer circuit 15 with an inversion signal. When the output from the comparison circuit 11 is “1”, the first operation timer circuit 12 performs a plurality of operation verifications until a preset operation verification timer value elapses. The operation signal is output. When the output from the comparison circuit 11 is “0”, the second operation timer circuit 15 with an inversion signal performs a plurality of return verifications until a preset return verification timer value elapses. The first return signal “1” of the overcurrent element is output.

  The OR circuit 22 is either a first return signal from the second operation timer circuit 15 with an inversion signal or a second return signal from a third operation timer (T3) circuit with an inversion signal to be described later. Is output. When the operation result “1” from the first operation timer circuit 12 is input to the set S side, the flip-flop circuit 13 sets the overcurrent element operation signal output to “1” to the first digital output relay circuit 16. To do. Further, when the first return signal “1” from the second operation timer circuit 15 with the inverted signal is input to the reset R side via the OR circuit 22, the flip-flop circuit 13 receives the overcurrent element operation signal. Output “1” is reset to “0”. The first digital output relay circuit 16 outputs the output from the flip-flop circuit 13 to the outside as an overcurrent element operation signal.

  For example, the same signal as the CB2 opening command from another relay (not shown) is input to the digital input circuit 23. The AND circuit 24 takes in the output from the digital input circuit 23 and the output from the flip-flop circuit 13 and outputs “1” when both are “1”. When the output “1” from the logical product circuit 24 continues for a predetermined time (CBF detection time) or longer, the fourth operation timer circuit 25 detects that the CB2 is not operating and outputs a CBF detection signal. Output. That is, when an effective value Irms equal to or greater than the determination value Is continues for a predetermined time even when a CB release command is output from another relay, the system fault is not eliminated because CB2 is inoperative. It can be said. In such a case, a CBF detection signal is output. The CBF detection time is set in consideration of the time from when the CB opening command is output by another relay until the arc at the time of CB opening is extinguished and the current I becomes zero. The second digital output relay circuit 26 outputs a CB release command when receiving the CBF detection signal from the fourth operation timer circuit 25. This CB release command is output to all the circuit breakers surrounding CB2 on the power transmission line 1, and such an operation eliminates a system fault even when CB2 is in an inoperative state.

  The configuration described above is an example of a CBF detection circuit similar to that of the prior art. The relay 4 according to the present embodiment ensures the determination accuracy of the operation value (operation signal) and the return value (first return signal) by the effective value calculation by this circuit, and can be quickly returned by the current return determination unit 50. It is configured as follows.

  Next, the configuration of the current recovery determination unit 50 will be described. The current recovery determination unit 50 includes a second digital filter circuit 9-2, a phase shift processing unit 18, a zero cross determination unit 19, a logical sum (OR) circuit 20, and an inversion that is an operation timer with an inversion function. And a third operation timer circuit 21 with a signal.

  In addition, the phase shift processing unit 18 includes, as an example, three independent phase shift circuits (a first phase shift circuit 18-1, a second phase shift circuit 18-2, and a third phase shift circuit 18- 3), and the zero cross determination unit 19 includes, as an example, four independent zero cross determination circuits (first zero cross determination circuit 19-1, second zero cross determination circuit 19-2, third The zero-cross determination circuit 19-3 and the fourth zero-cross determination circuit 19-4).

  The second digital filter circuit 9-2 is useful for removing the DC component of the CT secondary current after the release of CB2 that occurs when CT3 is magnetically saturated by a large current. This will be described with reference to FIG.

  The first phase shift circuit 18-1 performs a phase shift process of the phase of the current I0 that is the first current data output from the second digital filter circuit 9-2 (a process that advances or delays the phase by a predetermined amount). ) And output as current I1 which is second current data. Similarly, the second phase shift circuit 18-2 outputs the current after the phase shift process of the current I0 as the current I2 which is the second current data, and the third phase shift circuit 18-3 The current after the phase shift processing of I0 is output as the current I3 which is the second current data.

  The first zero cross determination circuit 19-1 determines whether or not the current I0 from the second digital filter circuit 9-2 has crossed zero. When the zero cross point is detected, a zero cross signal is detected. Is output. Similarly, the second zero cross determination circuit 19-2 detects the zero cross point of the current I1, the third zero cross determination circuit 19-3 detects the zero cross point of the current I2, and the fourth The zero cross determination circuit 19-4 detects the zero cross point of the current I3.

  The OR circuit 20 calculates a logical sum of the zero cross point signals from the zero cross determination unit 19. The third operation timer circuit 21 with the inversion signal inverts the result of the logical sum from the OR circuit 20, and when the signal is “1” after the inversion, the preset operation verification timer value elapses. Until this time, the return check of the signal of the OR circuit 22 is performed a plurality of times, and a second return signal for returning the operation signal of the overcurrent element is output. The second return signal is output to the OR circuit 22.

  Hereinafter, the operation of the current recovery determination unit 50 will be described. The output of the analog-digital converter 7 is input to the second digital filter circuit 9-2, and the current I0 from the second digital filter circuit 9-2 is transferred to the first zero cross determination circuit 19-1. Each is input to the phase processing unit 18.

  The phase shift processing unit 18 performs phase shift processing for changing the phase of the current I0 from which the DC component has been removed, and generates the currents I0 to I3 after the phase shift processing. The zero cross determination unit 19 determines the zero cross points of the waveforms of the currents I0 to I3 and inputs the results to the OR circuit 20, respectively. When all the determination results from the zero cross determination unit 19 are “0”, the output of the OR circuit 20 is “0”, and the inverted signal “1” is taken into the third operation timer circuit 21 with an inverted signal. It is. In the third operation timer circuit 21 with the inverted signal, the return verification of the circuit 21 input signal is performed a plurality of times, and the second return signal “1” is reset via the OR circuit 22 to the flip-flop circuit 13. Input to the R side. When the second return signal “1” is input to the flip-flop circuit 13, the outputs to the first digital output relay circuit 16 and the AND circuit 24 are reset.

  Next, the operation of the current return determination unit 50 will be described in detail with reference to FIG.

  FIG. 2 is a diagram for explaining the operation principle of the overcurrent relay 4 shown in FIG. In FIG. 2, a broken line based on the waveform of the current I (t) shown in (1) of FIG. 2 (a current obtained by plotting the current I as current data from the analog-digital converter 7) is 90 in the vertical direction. Described in ° intervals. The waveform of the section indicated by “A” in (1) is, for example, a current waveform from when a CB release command is output by another relay (not shown) until CB2 is opened, and is indicated by “B”. The waveform of the section is a waveform of current after CB2 is released.

  A current I0 (t) shown in (2) of FIG. 2 is a waveform of the current I0 output from the second digital filter circuit 9-2. For example, the current I0 (t) shown in FIG. It is the waveform of the electric current after taking the difference. This current I0 (t) is obtained by the equation (1). In the equation (1), I (t) and I (t−30 °) are digital data after analog-digital conversion by the analog-to-digital converter 7, and the former indicates current data and the latter indicates 30 ° before. Data is shown.

  The direct current component included in the alternating current is removed by the calculation of equation (1). To explain this, I (t) and I (t−30 °) shown in equation (1) can be expressed as equations (2) and (3), respectively. Although I (t) and I (t−30 °) include a DC component Idc and harmonics, these DC components Idc are canceled by performing the calculation of equation (1).

  A current I1 (t) indicated by a broken line in (3) of FIG. 2 is a waveform of the current I1 delayed in phase by 90 ° in the first phase shift circuit 18-1. This current I1 (t) is obtained by the equation (4).

  A current I2 (t) indicated by an alternate long and short dash line in (4) of FIG. 2 is a waveform of the current I2 delayed in phase by 45 ° in the second phase shift circuit 18-2. This current I2 (t) is obtained by the equation (5).

  Further, a current I3 (t) indicated by a two-dot chain line in (4) of FIG. 2 is a waveform of the current I3 advanced by 45 ° in the third phase shift circuit 18-3. This current I3 (t) is obtained by the equation (6).

  In Equations (4) to (6), I0 (t) represents the current current, and I0 (t-30 °) represents the current 30 ° before. Moreover, by setting the coefficient in (), the amplitude values of the currents I1 (t) to I3 (t) shown in the expressions (4) to (6) are changed to the currents input to the CBF detection relay 8. It can be matched with the amplitude value. In this way, using the current data I0 (t) and the 30 ° previous data I0 (t-30), a phase shift process of 45 ° delay, 45 ° advance, and 90 ° advance is performed. Note that, in the relay 4 according to the first embodiment, the phase shift processing of ± 45 ° and 90 ° is performed as an example, but is not limited to this, and other angles (for example, ± 30 °, ± 60 °, 90 °).

  When these four currents are arranged on the same time axis, the waveforms of these currents are as shown in (5) of FIG. (5) in FIG. 2 is an enlargement of (4) in FIG. 2. As is clear from the waveform of each current, when the input is an alternating current, a zero-crossing point appears every 45 °.

  In the zero cross determination part 19, the determination shown by Formula (7) or (8) is performed. α is a zero cross determination threshold.

  In (t) shown in the above equations (7) and (8) is the current I0 input to the first zero cross determination circuit 19-1 and the current input to the second zero cross determination circuit 19-2. I1 represents the current I2 input to the third zero cross determination circuit 19-3, or the current I3 input to the fourth zero cross determination circuit 19-4.

  Also, the zero cross determination threshold value α shown in the above equations (7) and (8) is set to avoid an uncertain zero cross determination near the current zero, and is a sufficiently small value with respect to the overcurrent set value *. To do.

  The relationship between the zero cross determination threshold value α and the third operation timer circuit 21 will be described. In the enlarged view of (5) in FIG. 2, broken lines indicating the calculation cycle are shown at intervals of 30 °. In the same figure, a zero cross determination threshold value α is shown. When the alternating current continues when the instantaneous values of the currents I0 to I3 are compared with the zero cross determination threshold value α (−α) by the above formulas (7) and (8), the first to fourth zeros are obtained. Zero cross determination is established in any of the cross determination circuits 19-1 to 19-4. In other words, if the AC input is not continued, neither the waveform of the current I0 before the phase shift process nor the waveform of the currents I1 to I3 after the phase shift process will cross zero. In the section “B” shown in FIG. 2 (4), the state where none of the waveforms of the currents I0 to I3 crosses zero is shown.

  The logical sum circuit 20 performs a logical sum of the zero cross point signals from the first to fourth zero cross determination circuits 19-1 to 19-4, and the third operation timer circuit 21 with an inverted signal The result of the logical sum from the logical sum circuit 20 is inverted, and the return verification is performed by the inverted signal. When the inverted signal is “1”, this signal indicates that the AC input is a small current that does not zero cross compared with the zero cross determination threshold value α, and the signal is the third operation timer circuit 21 with the inverted signal. When the operation collating timer value is continued until the third operation timer circuit 21 with the inversion signal is established, the small current is determined. That is, a small current is determined by the third operation timer circuit 21 with an inverted signal, using the signals from the third operation timer circuit 21 with an inverted signal and the OR circuit 20 as a trigger. The output of the third operation timer circuit 21 with the inversion signal is input to the reset R side of the flip-flop circuit 13 via the OR circuit 22, thereby restoring the output of the first digital output relay circuit 16. To do. The third operation timer circuit 21 with the inversion signal is normally set to the number of verifications once or twice at intervals of 30 °.

  In the relay 4 according to the first embodiment, the effective value Irms is used in current detection based on the determination value Is. However, the effective value calculation is an integral calculation in a sense, and a filter effect that reduces the influence of harmonics and the like. There are advantages that can be expected. By strengthening the filter circuit in the previous stage, the same effect can be obtained even if the determination based on the instantaneous value (that is, the peak value) is performed.

  As described above, the current return determination unit 50 according to the first embodiment includes the second digital filter circuit 9-2 that generates the current I0 (first current data) by removing the DC component included in the current I. The phase shift processing of the current I0 to generate a plurality of currents I1 to I3 having different phases as the second current data, and whether or not the current I0 and each of the currents I1 to I3 cross zero And a zero-cross determining unit 19 that outputs a second return signal when the current I0 and each of the currents I1 to I3 does not zero-cross.

  The current recovery determination unit 50 according to the first embodiment includes three phase shift circuits and four zero cross determination circuits. However, the number of phase shift circuits and zero cross determination circuits is the same. However, the present invention is not limited to this. For example, the configuration includes only the first zero cross determination circuit 19-1, the first phase shift circuit 18-1, and the second zero cross determination circuit 19-2. However, since the zero cross determination using the current before the phase shift process and the current after the phase shift process is performed, a high-speed recovery in less than one cycle is possible.

  As described above, the relay 4 according to the first embodiment is configured to restore the overcurrent relay output based on the effective value Irms of the current I captured from the CT 3 and the preset determination value Is. The overcurrent determination unit 40 (first overcurrent determination unit) that outputs a return signal and the phase of the current I0 (first current data) from which the DC component included in the current I is removed and the DC component is removed After generating the currents I1 to I3 (second current data) after the phase shift process by performing the phase shift process to be changed, the current I0 (first current data) before the phase shift process and the current after the phase shift process Based on I1 to I3 (second current data), a current return determination unit 50 (second overcurrent determination unit) that outputs a second return signal for returning the output of the overcurrent relay, and a first return Overpower when either the signal or the second return signal is input A restoration control section 60 stops the operation signal of the element. Thus comprises, able to detect a current zero speed, it is possible to speed up the return time. Although the conventional technology is configured to speed up the recovery time from a large current to some extent by the function of determining the operation value and the recovery value compared to the set value (determination value Is), the harmonic component Due to the filter circuit for removing the current, since the transient change of the current becomes slow when returning from a large current, the time until the effective value becomes less than the set value is delayed, and it is difficult to recover quickly. . Further, when CT3 is saturated, the recovery is further delayed by the CT secondary current, that is, the DC component. Since the relay 4 according to the present embodiment includes the overcurrent determination unit 40 and the current return determination unit 50, it ensures the determination accuracy of the operation value and the return value by effective value calculation, and the DC component is generated when a system fault occurs. Even in a flowing case, it is possible to return quickly in less than one cycle. In particular, it is possible to shorten the determination time of the second return signal by using a plurality of currents having different phases. As a result, it is possible to achieve both settling value accuracy and fast recovery.

Embodiment 2. FIG.
FIG. 3 is a configuration diagram of the overcurrent relay 4 according to the second embodiment of the present invention. In the first embodiment, the zero cross determination unit 19 is used to perform the fast return determination. However, in the second embodiment, the absolute value determination unit 30 is used instead of the zero cross determination unit 19 and the phase shift is performed. The second return signal is output by looking at the magnitude (effective value, peak value) of the current after processing. Hereinafter, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted, and only different parts will be described here.

  The CBF detection relay 8 according to the second embodiment mainly includes an overcurrent determination unit (first overcurrent determination unit) 40, a current return determination unit (second overcurrent determination unit) 51, and a return control. The unit 60, the logical product circuit 24, and the fourth operation timer circuit 25 are configured. The current recovery determination unit 51 includes a second digital filter circuit 9-2, a phase shift processing unit 18, an absolute value determination unit 30, an OR circuit 20, and a third operation timer circuit 21. It is configured. Further, the absolute value determination unit 30 includes, as an example, four independent absolute value determination circuits (first absolute value determination circuit 30-1, second absolute value determination circuit 30-2, and third absolute value determination). Circuit 30-3 and fourth absolute value determination circuit 30-4).

  The first absolute value determination circuit 30-1 calculates an absolute value of the current I0 and compares the absolute value with a predetermined determination value α ′. The second absolute value determination circuit 30-2 calculates the absolute value of the current I1 and compares the absolute value with a predetermined determination value α ′. The third absolute value determination circuit 30-3 calculates an absolute value of the current I2, and compares the absolute value with a predetermined determination value α ′. The fourth absolute value determination circuit 30-4 calculates an absolute value of the current I3 and compares the absolute value with a predetermined determination value α ′. The logical sum circuit 20 takes a logical sum of the absolute value determination results from the absolute value determination unit 30. The third operation timer circuit 21 with the inversion signal inverts the result of the logical sum from the OR circuit 20, and when the signal after the inversion is “1”, the preset operation verification timer value has elapsed. In the meantime, a second return signal “1” is output by performing a plurality of return verifications. Then, the second return signal “1” of the third operation timer circuit 21 with an inverted signal is output to the OR circuit 22.

  Hereinafter, the operation of the current recovery determination unit 51 will be described. The output of the analog-digital converter 7 is input to the second digital filter circuit 9-2, and the current I0 from the second digital filter circuit 9-2 is phase-shifted with the first absolute value determination circuit 30-1. Each is input to the processing unit 18.

  The phase shift processing unit 18 performs phase shift processing for changing the phase of the current I0 from which the DC component has been removed, and generates the currents I0 to I3 after the phase shift processing. The absolute value determination unit 30 determines the absolute values of the waveforms of the currents I0 to I3 and inputs the results to the OR circuit 20, respectively. When all the determination results from the absolute value determination unit 30 are “0”, the output of the OR circuit 20 is “0”, and the inverted signal “1” is taken into the third operation timer circuit 21 with an inverted signal. It is. In the third operation timer circuit 21 with the inverted signal, the return check is performed a plurality of times, and the second return signal “1” is input to the reset R side of the flip-flop circuit 13 via the OR circuit 22. The When the second return signal “1” is input to the flip-flop circuit 13, the outputs to the first digital output relay circuit 16 and the AND circuit 24 are reset.

  Next, the operation of the current recovery determination unit 51 will be described using the waveform shown in FIG. As shown in (5) of FIG. 2, any of the current I0 (t), the current I1 (t), the current I2 (t), and the current I3 (t) has a peak value every 45 °. The absolute value determination unit 30 calculates the absolute values | I0 (t) |, | I1 (t) |, | I2 (t) |, and | I3 (t) | As shown in FIG. 4, the output when these absolute values exceed the predetermined determination value α ′ is taken into the OR circuit 22 and the third operation timer circuit 21 with an inverted signal. When the state in which the absolute value is equal to or smaller than the predetermined determination value α ′ continues while being set by the operation timer circuit 21 with the inversion signal, the second return signal is output. That is, it is determined that the accident current has returned to zero. The predetermined determination value α ′ is set to avoid an uncertain absolute value determination with respect to the zero current input, and is set to a sufficiently small value with respect to the predetermined settling value *.

  As described above, the current recovery determination unit 51 according to the second embodiment includes the second digital filter circuit 9-2 that generates the current I0 (first current data) by removing the DC component included in the current I. The phase shift processing of the current I0 to generate a plurality of currents I1 to I3 having different phases as the second current data, the absolute value of the current I0, and the absolute values of the currents I1 to I3, Are determined, and it is determined whether or not these absolute values are equal to or smaller than a predetermined determination value α ′, and when these absolute values are both equal to or smaller than the predetermined determination value α ′, a second return signal is output. And an absolute value determination unit 30. In the section “B” shown in FIG. 2 (4), the state when the absolute values of the waveforms of the currents I0 to I3 are equal to or less than the determination value α ′ (not shown) is shown.

  The current recovery determination unit 51 according to the second embodiment is configured to include three phase shift circuits and four absolute value determination circuits. However, the number of phase shift circuits and absolute value determination circuits is as follows. The present invention is not limited to this. For example, even when only the first absolute value determination circuit 30-1, the first phase shift circuit 18-1, and the second absolute value determination circuit 30-2 are configured. Since the absolute value determination using the current before the phase shift process and the current after the phase shift process is performed, a high-speed recovery in less than one cycle is possible.

  As described above, the relay 4 according to the second embodiment is configured to restore the overcurrent relay output based on the effective value Irms of the current I captured from the CT 3 and the preset determination value Is. The overcurrent determination unit 40 (first overcurrent determination unit) that outputs a return signal and the phase of the current I0 (first current data) from which the DC component included in the current I is removed and the DC component is removed After generating the currents I1 to I3 (second current data) after the phase shift process by performing the phase shift process to be changed, the current I0 (first current data) before the phase shift process and the current after the phase shift process Based on I1 to I3 (second current data), a current return determination unit 51 (second overcurrent determination unit) that outputs a second return signal for returning the output of the overcurrent relay, and a first return Overpower when either the signal or the second return signal is input Since the return control unit 60 for stopping the operation signal of the element is provided, both the settling value accuracy and the high-speed return can be achieved in the same manner as the relay 4 according to the first embodiment. It is possible to simplify the return determination than the relay 4.

Embodiment 3 FIG.
In the first and second embodiments, the DC component removal and the phase shift processing are executed using the second digital filter circuit 9-2 and the phase shift processing unit 18, but the third embodiment is applied. The relay 4 includes a phase shift processing unit 14 instead of the second digital filter circuit 9-2 and the phase shift processing unit 18, and the phase shift processing unit 14 performs the removal of the DC component and the phase shift processing. It is configured. Hereinafter, the same reference numerals are given to the same parts as those in the first embodiment, and the description thereof is omitted, and only different parts will be described here.

  FIG. 4 is a configuration diagram of the overcurrent relay 4 according to the third embodiment of the present invention. The CBF detection relay 8 according to the third embodiment mainly includes an overcurrent determination unit (first overcurrent determination unit) 40, a current return determination unit (second overcurrent determination unit) 52, and a return control. The unit 60, the logical product circuit 24, and the fourth operation timer circuit 25 are configured. The current recovery determination unit 52 includes the phase shift processing unit 14, the zero cross determination unit 19, the OR circuit 20, and the third operation timer circuit 21 with an inverted signal. As an example, the phase shift processing unit 14 includes four independent digital filter circuits (second digital filter circuit 9-2, third digital filter circuit 9-3, fourth digital filter circuit 9-4, and It comprises a fifth digital filter circuit 9-5).

  The second digital filter circuit 9-2 removes the DC component included in the current I from the analog-to-digital converter 7 and changes the phase of the current from which the DC component is removed to a different value by a predetermined difference process. The phase shift process is performed to generate a current I0 that is current data. Similarly, the third digital filter circuit 9-3 performs a phase shift process of the current from which the DC component included in the current I is removed, and generates a current I1 that is current data. The fourth digital filter circuit 9-4 performs a phase shift process on the current from which the DC component included in the current I is removed, and generates a current I2 that is current data. The fifth digital filter circuit 9-5 performs a phase shift process on the current from which the DC component included in the current I is removed, and generates a current I3 that is current data. The first zero cross determination circuit 19-1 determines whether or not the current I0 from the second digital filter circuit 9-2 has crossed zero, and outputs a zero cross signal when a zero cross point is detected. . Similarly, the second zero cross determination circuit 19-2 detects the zero cross point of the current I1, the third zero cross determination circuit 19-3 detects the zero cross point of the current I2, and the fourth The zero cross determination circuit 19-4 detects the zero cross point of the current I3.

  The operation will be described below. The output of the analog-digital converter 7 is input to the phase shift processing unit 14, and the currents I <b> 0 to I <b> 3 subjected to the difference processing and the phase shift processing are input to the zero cross determination unit 19. The zero cross determination unit 19 determines the zero cross points of the waveforms of the currents I0 to I3 and inputs the results to the OR circuit 20, respectively. When all the determination results from the zero cross determination unit 19 are “0”, the output of the OR circuit 20 is “0”, and the inverted signal “1” is taken into the third operation timer circuit 21 with an inverted signal. It is. In the third operation timer circuit 21 with the inverted signal, the return check is performed a plurality of times, and the second return signal “1” is input to the reset R side of the flip-flop circuit 13 via the OR circuit 22. The When the second return signal “1” is input to the flip-flop circuit 13, the outputs to the first digital output relay circuit 16 and the AND circuit 24 are reset.

  Next, calculation processing in the phase shift processing unit 14 will be described. The second digital filter circuit 9-2 outputs a current I0 (t) by the calculation shown in the equation (10).

  The third digital filter circuit 9-3 outputs a current I1 (t) by the calculation shown in the equation (11).

  The fourth digital filter circuit 9-4 outputs a current I2 (t) by the calculation shown in the equation (12).

  The fifth digital filter circuit 9-5 outputs a current I3 (t) by the calculation shown in the equation (13).

  In this way, it is possible to obtain the same effect as that of the first embodiment by difference processing that is simpler than the calculation of the phase shift processing according to the first and second embodiments. Note that, by setting the constants k0 to k2 as described above, the amplitude values of the differential currents I0 (t) to I3 (t) output from the phase shift processing unit 14 are changed to the currents input to the CBF detection relay 8. Can be made to coincide with the amplitude value. However, it is possible to set constants k0 to k2 = 1 if there is no particular need to match the magnitudes of amplitude values as in the zero cross determination.

By performing the above difference processing, a DC component generated when the current returns to zero can be removed, and each current I1 (t) to I3 (t) as shown in (5) of FIG. Has the following phase relationship with respect to the current I0 (t).
I1 (t) is 45 ° behind the phase of I0 (t).
I2 (t) is a 45 ° advance phase with respect to I0 (t).
I3 (t) is a phase delayed by 90 ° with respect to I0 (t).

  In the above description, since the past current that takes a difference from the current current is used up to 120 ° before, an electrical angle of 60 ° is compared with the method of the first embodiment (using current up to 60 ° before the current time). However, in the case of the zero cross determination, k0 to k2 = 1 can be set, so that there is an advantage that the calculation is simplified.

  In the zero cross determination unit 19, the zero cross determination is performed using I0 to I3 as in the first embodiment. Since the arithmetic expression used for this zero cross determination is the same as the expressions (7) and (8) shown in the first embodiment, the description thereof is omitted.

  As described above, the current return determination unit 52 according to the third embodiment performs a phase shift process that removes the DC component included in the current I and changes the phase, and performs a plurality of currents I0 to I3 (a plurality of phases different from each other). Current phase), and whether or not each of the currents I0 to I3 (a plurality of current data) from the phase shift processing unit 14 crosses zero and each of the currents I0 to I3 is determined. And a zero cross determination unit 19 that outputs a second return signal when the zero cross is not performed.

  Although the zero cross determination is performed in the third embodiment, the absolute value determination unit 30 shown in the second embodiment may be used instead of the zero cross determination unit 19. In other words, the current return determination unit 52 removes a DC component included in the current I and performs a phase shift process for changing the phase to generate a plurality of currents I0 to I3 (a plurality of current data) having different phases. The processing unit 14, the phase shift processing unit 14 that generates a plurality of current data, and the absolute value of each current from the phase shift processing unit 14 are obtained, and these absolute values are equal to or less than a predetermined determination value α ′. And an absolute value determination unit 30 that outputs a second return signal when any of these absolute values is equal to or less than the predetermined determination value α ′. In the case of such a configuration, it is necessary to multiply by constants k0 to k2. However, as in the second embodiment, high-speed return determination by peak value detection is possible.

  In the third embodiment, four digital filter circuits and four zero cross determination circuits are used. However, the number of digital filter circuits and zero cross determination circuits is not limited to this. For example, Even when only the second digital filter circuit 9-2, the third digital filter circuit 9-3, the first zero cross detection circuit 19-1, and the second zero cross detection circuit 19-2 are configured. Since the zero cross determination using the current before the phase shift process and the current after the phase shift process is performed, a high-speed recovery in less than one cycle is possible. The same applies to the case where the zero cross determination unit 19 is used. That is, for example, the configuration of only the second digital filter circuit 9-2, the third digital filter circuit 9-3, the first absolute value determination circuit 30-1, and the second absolute value determination circuit 30-2. Even in this case, the absolute value determination using the current before the phase shift process and the current after the phase shift process is performed, and a high-speed recovery in less than one cycle is possible.

  As described above, the relay 4 according to the third embodiment is configured to restore the overcurrent relay output based on the effective value Irms of the current I taken from the CT 3 and the preset determination value Is. An overcurrent determination unit 40 (first overcurrent determination unit) that outputs a return signal, and a plurality of currents I0 to I0 that have different phases by performing a phase shift process that removes a DC component included in the current I and changes the phase. After generating I3 (a plurality of current data), a current return determination unit 52 (second overcurrent determination) that outputs a second return signal for returning the overcurrent relay output based on the currents I0 to I3 having different phases And a command control unit 60 for stopping the operation signal of the overcurrent element when any of the first return signal and the second return signal is input, the phase shift processing unit CT saturation by 14 The effect of a direct current component of removal, and, since it is possible to change the current phase, it is possible to obtain the same effect as executing a plurality of phase shift processing.

  In the description of the first to third embodiments, the case of an overcurrent relay used for CBF detection is described as an example of the application of the present invention. However, it is used for purposes other than CBF detection and detects zero current after CB is opened. It can be applied to an overcurrent relay.

  As described above, the present invention can be applied to an overcurrent relay, and is particularly useful as an invention capable of realizing high-speed recovery even in a case where a DC component flows when a system fault occurs.

1 Transmission line 2 CB
3 CT
4 Overcurrent Relay 5 Input Converter 6 Analog Filter Circuit 7 Analog to Digital Converter 8 CBF Detection Relay 9-1 First Digital Filter Circuit 9-2 Second Digital Filter Circuit 9-3 Third Digital Filter Circuit 9- 4 Fourth Digital Filter Circuit 9-5 Fifth Digital Filter Circuit 10 RMS Value Calculation Circuit 11 Comparison Circuit 12 First Operation Timer Circuit 13 Flip-Flop Circuits 14, 18 Phase Shift Processing Unit
DESCRIPTION OF SYMBOLS 15 2nd operation | movement timer circuit with an inversion signal 16 1st digital output relay circuit 18-1 1st phase shift circuit 18-2 2nd phase shift circuit 18-3 3rd phase shift circuit 19 Zero cross determination part 19-1 1st zero cross determination circuit 19-2 2nd zero cross determination circuit 19-3 3rd zero cross determination circuit 19-4 4th zero cross determination circuit 20 OR circuit 21 3rd with inverted signal Operation timer circuit 22 OR circuit 23 Digital input circuit 24 AND circuit 25 Fourth operation timer circuit 26 Second digital output relay circuit 30 Absolute value determination unit
30-1 1st absolute value determination circuit 30-2 2nd absolute value determination circuit 30-3 3rd absolute value determination circuit 30-4 4th absolute value determination circuit 40 Overcurrent determination part (1st excess value determination circuit) Current judgment part)
50, 51, 52 Current recovery determination unit (second overcurrent determination unit)
60 Return control unit α, -α Zero cross determination threshold I current I0 current (first current data or current data)
I1, I2, I3 Current (second current data or current data)
Irms effective value Is, α ′ judgment value

Claims (6)

An overcurrent relay that protects the power system by operating a circuit breaker provided in the power system based on the current detected in the power system,
A first overcurrent determination unit that outputs a first return signal for returning the output of the overcurrent relay based on an effective value of the current and a predetermined determination value;
After removing the direct current component included in the current and performing phase shift processing to change the phase of the first current data from which the direct current component has been removed to generate second current data after the phase shift processing, A second overcurrent determination unit that outputs a second return signal for returning the output of the overcurrent relay based on the first current data and the second current data;
A return control unit for stopping an operation signal of an overcurrent element when any of the first return signal and the second return signal is input;
An overcurrent relay comprising: The second overcurrent determination unit includes:
A digital filter circuit that removes a direct current component included in the current and generates the first current data;
A phase-shift processing unit that performs the phase-shift process on the first current data and generates a plurality of current data with different phases as the second current data;
It is determined whether the first current data from the digital filter circuit and the second current data from the phase shift processing unit cross each other, and the first current data and the second current data are determined. A zero cross determination unit that outputs the second return signal when none of the current data of
The overcurrent relay according to claim 1, further comprising: The second overcurrent determination unit includes:
A digital filter circuit that removes a direct current component included in the current and generates the first current data;
A phase-shift processing unit that performs the phase-shift process on the first current data and generates a plurality of current data with different phases as the second current data;
The absolute value of the first current data from the digital filter circuit and the absolute value of the second current data from the phase shift processing unit are respectively obtained, and these absolute values are equal to or smaller than a predetermined determination value. An absolute value determination unit that outputs the second return signal when any of these absolute values is less than or equal to the predetermined determination value;
The overcurrent relay according to claim 1, further comprising: An overcurrent relay that protects the power system by operating a circuit breaker provided in the power system based on the current detected in the power system,
A first overcurrent determination unit that outputs a first return signal for returning the output of the overcurrent relay based on an effective value of the current and a predetermined determination value;
A plurality of current data with different phases is generated by removing a DC component contained in the current and changing the phase, and then the output of the overcurrent relay is restored based on the current data with different phases. A second overcurrent determination unit that outputs a second return signal to be output;
A return control unit for stopping an operation signal of an overcurrent element when any of the first return signal and the second return signal is input;
An overcurrent relay comprising: The second overcurrent determination unit includes:
A phase shift processing unit for generating the plurality of current data;
Determining whether or not each of the current data from the phase shift processing unit crosses zero, and outputs the second return signal when none of the current data crosses zero;
The overcurrent relay according to claim 4, further comprising: The second overcurrent determination unit includes:
A phase shift processing unit for generating the plurality of current data;
Each absolute value of each of the current data from the phase shift processing unit is obtained, and it is determined whether or not these absolute values are equal to or less than a predetermined determination value, and any of these absolute values is the predetermined determination value. An absolute value determination unit that outputs the second return signal when:
The overcurrent relay according to claim 4, further comprising:

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