JP2009017738A - Transformer protection relay - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a transformer protection relay for preventing malfunction in current-differential relay, even when it takes longer time when deciding an inrush current than when deciding a current-ratio differential. <P>SOLUTION: A respective-phase locking circuit 3B locks only the decision results of current-ratio differential decision circuits 1A to 1C corresponding to each phase. The locking circuit 3B feeds the output OUTO33 of a respective-phase decision trip signal, based on the decision results in inrush decision circuits 2A to 2C to decide whether or not an inrush curent is generated in each of a first to third phases of a transformer to be protected. A three-phase locking circuit 3A locks all the decision results of the current-ratio differential decision circuits 1A to 1C. The locking circuit 3A feeds the output OUTA21 of a three-phase decision trip signal, based on any of the decision results in the inrush decision circuits 2A to 2C. A trip signal TP is asserted on the basis of the output OUTO33 and the otput OUTA21. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transformer protection relay that outputs a signal for detecting a system fault and tripping a circuit breaker by using a system current of a power system of a transformer as an input, and in particular, by an inrush current of the transformer. The present invention relates to a transformer protection relay that prevents malfunction of a current differential relay.

  In the conventional main transformer protection relay system, a system mainly using a current differential relay is adopted. In the main transformer protection relay system based on this current differential relay, whether or not the fault point is inside the transformer by vector calculation of each terminal current of the transformer to be protected, or outside the transformer There is an advantage that it can be determined with high sensitivity whether there is any. In this system, the operating coil of the current differential relay is energized by the differential current generated in the case of an internal accident, and the circuit breaker is tripped.

  However, an inrush current is generated when the transformer is charged or when the power transmission line linked to the transformer is closed, and the current differential relay may malfunction due to the inrush current.

  As a prior art for improving such a problem, for example, there is a second harmonic suppression method. The second harmonic suppression method pays attention to the fact that the inrush current contains a relatively large amount of the second harmonic component (second harmonic component), and the content ratio of the second harmonic component with respect to the fundamental wave component is determined in advance. The case where it becomes more than a predetermined threshold value is determined as an inrush current, and the current ratio differential relay is locked for a short time using the second harmonic component as a suppression force.

  On the other hand, the resonance frequency with the system inductance component at the time of failure decreases due to the increase in ground capacitance due to the recent increase in voltage, capacity, distance, and cable system of power transmission facilities. Tend. In particular, in ultra-high voltage systems, it is considered that a large amount of low-order harmonic components near the second harmonic are generated in the event of an internal fault in the transformer. In conventional second harmonic suppression methods, the inrush current and the transformer There arises a problem that it is difficult to accurately discriminate from the internal fault current.

  As a conventional technique for improving such a problem, for example, there is Non-Patent Document 1. Non-Patent Document 1 states that inrush current occurs when the transformer's tertiary terminal voltage is large (0.5 PU or more) and the second harmonic component in the differential current is also large (15% or more). A technique relating to a second harmonic suppression method with voltage detection for determining and locking a current differential relay is disclosed.

  Specifically, the voltage at the third terminal of the transformer is greatly reduced at the time of an internal fault of the transformer where the second harmonic component is large, and at the time of charging of the transformer where inrush current is generated. Focusing on the fact that the third terminal voltage of the transformer is large in addition to the large second harmonic component, the third terminal voltage detection means of the transformer is provided in the conventional second harmonic suppression method, and the inrush current and the transformer It is possible to discriminate from the internal fault current of the vessel.

Proceedings of 1998 Annual Conference of the Institute of Electrical Engineers of Japan

  However, the conventional second harmonic suppression method with voltage detection described in Non-Patent Document 1 described above is a countermeasure against distortion waves of the transformer's tertiary terminal voltage when detecting the magnitude of the transformer's tertiary terminal voltage. For example, since the average value of the voltage waveform for one cycle is taken, depending on variations in operation time due to the magnitude and phase of system current / voltage input, sampling timing of current differential relay, calculation timing, etc. The inrush current determination process may take longer than the current ratio differential determination process. In this case, there is a problem that the current ratio differential determination processing result cannot be locked (invalidated) with the inrush current determination processing result, and the current differential relay malfunctions. This problem becomes significant when the current ratio differential determination process is speeded up in order to speed up the operation time of the current differential relay.

  The present invention has been made in view of the above, and is capable of preventing malfunction of the current differential relay even when the inrush current determination process takes more time than the current ratio differential determination process. The purpose is to obtain a device protection relay.

  In order to solve the above-described problems and achieve the object, the present invention is a transformer protection relay for preventing malfunction of a current differential relay due to an inrush current of a transformer, the first phase of the transformer being A first current ratio differential determination circuit for determining whether or not the differential current is equal to or higher than a predetermined threshold level; and the second phase differential current of the transformer is equal to or higher than a predetermined threshold level. A second current ratio differential determination circuit for determining whether or not there is, and a third current ratio for determining whether or not the third-phase differential current of the transformer is greater than or equal to a predetermined threshold level A differential determination circuit, a first inrush determination circuit for determining whether an inrush current is generated in the first phase of the transformer, and whether an inrush current is generated in the second phase of the transformer A second inrush determination circuit for determining whether or not the transformer A third inrush determination circuit that determines whether or not an inrush current has occurred in the third phase, and the first, second, or third inrush determination circuit has determined that an inrush current has occurred. In this case, the determination results of the first, second, and third current ratio differential determination circuits are invalidated, a three-phase determination trip signal is negated, and the first, second, and third inrush determination circuits When all of the above determine that no inrush current has occurred, the determination results of the first, second, and third current ratio differential determination circuits are validated, and the first, second, or second A three-phase lock circuit that asserts the three-phase determination trip signal when the determination result of the current ratio differential determination circuit of 3 indicates that the differential current is greater than or equal to the threshold level; Second or third a When the rush determination circuit determines that the inrush current has occurred, the differential current having the same phase as the first, second, or third inrush determination circuit that has determined that the inrush current has occurred is determined. The determination result of the first, second, or third current ratio differential determination circuit to be performed is invalidated and each phase determination trip signal is negated, and the first, second, or third inrush determination circuit is When it is determined that no rush current is generated, a differential current having the same phase as that of the first, second, or third inrush determination circuit determined that no inrush current is generated is determined. The determination result of the first, second, or third current ratio differential determination circuit is validated, and the determination result of the first, second, or third current ratio differential determination circuit is the differential current Be above threshold level Each phase lock system circuit that asserts each phase determination trip signal when indicating a current difference that asserts a trip signal based on the three-phase determination trip signal and each phase determination trip signal A dynamic relay.

  According to this invention, the determination results of the first to third inrush determination circuits that determine whether or not an inrush current has occurred for each of the first to third phases of the transformer to be protected. Each phase determination trip signal output by each phase lock system circuit that locks only the determination result of the first to third current ratio differential determination circuits corresponding to the phase, and the first to third inrushes A trip signal is generated based on a three-phase determination trip signal output from a three-phase lock circuit that locks the determination results of all the first to third current ratio differential determination circuits based on the determination result of any of the determination circuits. Since the inrush current determination process takes more time than the current ratio differential determination process, the transformer protection relay that can prevent malfunction of the current differential relay is obtained. In There is an effect that that.

  Hereinafter, embodiments of a transformer protection relay according to the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a power system configuration to which a transformer protection relay according to the present invention is applied. In this power system configuration, the protected transformer Tr, the current transformer CT1 that detects the primary terminal system current of the protected transformer Tr, and the current transformer that detects the secondary terminal system current of the protected transformer Tr. CT2, current transformer CT3 for detecting the tertiary terminal system current of the protected transformer Tr, voltage transformer PT3 for detecting the tertiary terminal system voltage of the protected transformer Tr, and current transformers CT1 to CT3 Transformer protection for detecting a system fault of the protected transformer Tr and outputting a trip signal based on each system current of the protected transformer Tr detected by the voltage transformer and the tertiary terminal system voltage detected by the voltage transformer PT3 The circuit breakers CB1 to CB3 are provided that cut off each system of the protected transformer Tr by the relay signal Ry and the trip signal TP output from the transformer protection relay Ry. In FIG. 1, the system breaker CB1 shuts off the primary terminal system of the protected transformer Tr, the system breaker CB2 shuts off the 2:00 terminal system of the protected transformer Tr, and the system breaker CB3 is protected. The tertiary terminal system of the transformer Tr is shut off. Hereinafter, the primary terminal system may be referred to as a first phase, the secondary terminal system may be referred to as a second phase, and the tertiary terminal system may be referred to as a third phase.

  In general, the current differential relay in the transformer protection relay Ry may malfunction due to the inrush current of the protected transformer Tr. Therefore, it is necessary to negate the trip signal TP for controlling the system breakers CB1 to CB3 when an inrush current is generated. That is, when an inrush current is generated, it is necessary to lock (invalidate) the operation of the current differential relay.

  Therefore, the current differential relay used in the transformer protection relay Ry of the first embodiment shown in FIG. 1 uses the second harmonic suppression method with voltage detection, and the first to third terminals of the protected transformer Tr Whether or not inrush current is generated based on the level of the second harmonic component included in the system current (the differential current of the first phase to the third phase) and the voltage level of the tertiary terminal system (third phase). When the inrush current is detected, the trip signal TP1 to CB3 is prevented from erroneous tripping by negating (locking) the trip signal TP.

  FIG. 2 is a diagram showing the function of the current differential relay according to the present invention of the transformer protection relay Ry shown in FIG. In FIG. 2, the current differential relay includes current ratio differential determination circuits 1A to 1C, inrush determination circuits 2A to 2C, a 2-input OR circuit (hereinafter referred to as an OR circuit) O21, and a 3-input OR. Circuits O31 to O33, inverting circuits (hereinafter referred to as NOT circuits) N1 to N4, two-input AND circuits (hereinafter referred to as AND circuits) A21 to A25, and a delay circuit 4, and current ratio differential determination The circuits 1A to 1C, the inrush determination circuits 2A to 2C, the OR circuits O31 and O32, the NOT circuit N1, and the AND circuit A21 constitute a three-phase lock circuit 3A, and the current ratio differential determination circuits 1A to 1C and the inrush Determination circuits 2A to 2C, NOT circuits N2 to N4, AND circuits A22 to A24, and OR circuit O33 constitute each phase lock circuit 3B. The AND circuit A25 realizes the function of each phase determination trip signal lock circuit in the scope of claims.

  The current ratio differential determination circuits 1A to 1C are input with the first to third phase differential currents detected by the current transformers CT1 to CT3, and the input differential current is equal to or higher than a predetermined threshold level. It is determined whether or not. When the current ratio differential determination circuits 1A to 1C determine that the input differential current is equal to or higher than the threshold level, the outputs OUT1A to OUT1C are asserted (here, “H”), and the input differential is determined. When it is determined that the current is smaller than the threshold level, the outputs OUT1A to OUT1C are negated (here, “L”). The current ratio differential determination circuits 1A to 1C output the outputs OUT1A to OUT1C to the OR circuit O31 and the AND circuits A22 to A24.

  The inrush determination circuits 2A to 2C include the differential signal input from the current transformers CT1 to CT3 and the tertiary terminal system voltage (third phase voltage) of the protected transformer Tr input from the voltage transformer PT3. Based on the above, it is determined whether or not an inrush current has occurred in the first to third phases of the protected transformer Tr. The inrush determination circuits 2A to 2C assert the outputs OUT2A to OUT2C (here, “H”) when it is determined that an inrush current has occurred, and when it is determined that no inrush current has occurred. Causes the outputs OUT2A to OUT2C to be negated (here, “L”). The inrush determination circuits 2A to 2C output the outputs OUT2A to OUT2C to the OR circuit O32 and the NOT circuits N2 to N4.

  The inrush determination circuits 2A to 2C have the same internal configuration. With reference to the internal configuration of the inrush determination circuit 2A using the second harmonic suppression method with voltage detection shown in FIG. 3, the internal configuration of the inrush determination circuit will be described. In FIG. 3, the inrush determination circuit 2A includes a second harmonic detection circuit 21, a tertiary voltage detection circuit 22, and a 2-input AND circuit A26.

  The second harmonic detection circuit 21 determines whether or not there is a second harmonic component included in the differential current input from the current transformer CT1 (in this case, the first-phase differential current of the protected transformer Tr). To detect. The second harmonic detection circuit 21 detects the second harmonic component when the level of the second harmonic component included in the input differential current is equal to or higher than a predetermined second harmonic component threshold level. When the output is asserted (in this case, “H”) and the level of the second harmonic component included in the input differential current is smaller than the second harmonic component threshold level, the second harmonic component The output is negated (in this case, “L”).

  The tertiary voltage detection circuit 22 determines whether or not the tertiary terminal system voltage (third phase voltage) of the protected transformer Tr input from the voltage transformer PT3 is equal to or higher than a predetermined threshold voltage. . The tertiary voltage detection circuit 22 asserts the output (in this case, “H”) when the input third-phase voltage is equal to or higher than the threshold voltage, and the input third-phase voltage is the threshold voltage. If it is smaller, the output is negated (in this case, “L”).

  The AND circuit A26 receives the outputs of the second harmonic detection circuit 21 and the tertiary voltage detection circuit 22 as inputs, and outputs the logical sum of these inputs as the output OUT2A of the inrush determination circuit 2A. That is, the inrush determination circuit 2A includes the differential current, which is the third phase current of the protected transformer Tr, including the second harmonic component equal to or higher than the second harmonic component threshold level, and the protected transformer Tr. When the third phase voltage is equal to or higher than the threshold voltage, it is determined that an inrush current is generated in the first phase, and the output OUT2A is asserted (in this case, “H”). Further, the inrush determination circuit 2A determines that the first-phase differential current of the protected transformer Tr does not include the second harmonic component above the second harmonic component threshold level, or the protected transformer Tr When the third phase voltage is smaller than the threshold voltage, it is determined that no inrush current is generated in the first phase, and the output OUT2A is negated (in this case, “L”).

  Returning to FIG. 2, the three-phase lock circuit 3A determines whether or not the differential current of at least one of the first to third phases of the protected transformer Tr is equal to or higher than a threshold level. In the case where no inrush current is generated in any of the three phases of the protected transformer Tr, the determination result of the presence or absence of the differential current is valid, and among the three phases of the protected transformer Tr When an inrush current is generated in at least one phase, the determination result of the presence or absence of the differential current is invalidated (locked).

  Specifically, the outputs of the current ratio differential determination circuits 1A to 1C for determining whether or not the differential current of each phase of the protected transformer Tr detected by the current transformers CT1 to CT3 is equal to or higher than a threshold level. OUT1A to OUT1C are input to the OR circuit O31. The OR circuit O31 inputs the logical sum of the outputs OUT1A to OUT1C of the current ratio differential determination circuits 1A to 1C as an output OUTO31 to the AND circuit A21. That is, the OR circuit O31 asserts the output OUTO31 when the differential current of any one of the first to third phases of the protected transformer Tr is equal to or higher than the threshold level (in this case, “H”). When the differential currents of the first to third phases of the protected transformer Tr are all smaller than the threshold level, the output OUTO31 is negated (in this case, “L”).

  Based on the differential current of each phase of the protected transformer Tr detected by the current transformers CT1 to CT3 and the third phase voltage of the protected transformer Tr detected by the voltage transformer PT3, the inrush in each phase. The outputs OUT2A to OUT2C of the inrush determination circuits 2A to 2C for determining whether or not a current is generated are input to the OR circuit O32.

  The OR circuit O32 takes the logical sum of the outputs OUT2A to OUT2C of the inrush determination circuits 2A to 2C, and inputs this logical sum to the NOT circuit N1 and the delay circuit 4 as an output OUTO31. That is, the OR circuit O32 asserts the output OUTO32 (in this case, “H”) when an inrush current is generated in any phase of the protected transformer Tr, and all three phases of the protected transformer Tr. When no inrush current is generated, the output OUTO32 is negated (in this case, “L”).

  The NOT circuit N1 inverts the output of the OR circuit O32 and inputs it to the AND circuit A21. The AND circuit A21 inputs the logical sum of the output of the NOT circuit N1 and the output OUTO31 of the OR circuit O31 to the OR circuit O21 as an output OUTA21. That is, the AND circuit A21 determines the current ratio differential of each phase of the protected transformer Tr when no inrush current is generated in any of the first to third phases of the protected transformer Tr. If the result of the determination is valid and an inrush current is generated in at least one of the first to third phases of the protected transformer Tr, the current ratio differential determination of each phase of the protected transformer Tr Invalidate the result of. In other words, the AND circuit A21 asserts the output OUTA21 when the differential current of any phase of the protected transformer Tr is equal to or higher than the threshold level and no inrush current is generated in any phase. When the differential current of each phase of the protected transformer Tr is smaller than the threshold level, or when the inrush current is generated in any phase of the protected transformer Tr, the output OUTA21 is negated (in this case Is “L”).

  Each phase lock circuit 3B validates / invalidates the current ratio differential determination result for each phase of the protected transformer Tr depending on whether or not an inrush current is generated in that phase. Specifically, the NOT circuits N2 to N3 include the differential current of each phase of the protected transformer Tr detected by the current transformers CT1 to CT3 and 3 of the protected transformer Tr detected by the voltage transformer PT3. Based on the next terminal system voltage, the outputs OUT2A to OUT2C of the inrush determination circuits 2A to 2C for determining whether or not an inrush current is generated in each phase are inverted and output to the AND circuits A22 to A24.

  The AND circuits A22 to A24 take the logical product of the outputs OUT1A to OUT1C of the current ratio differential determination circuits 1A to 1C and the outputs of the NOT circuits N2 to N4, and output the logical products as outputs OUTA22 to OUTA24 to the OR circuit O33. To do. That is, the AND circuits A22 to A24 validate the outputs of the current ratio differential determination circuits 1A to 1C when no inrush current is generated in the first to third phases of the protected transformer Tr. When an inrush current is generated in the first to third phases of the protection transformer Tr, the outputs of the current ratio differential determination circuits 1A to 1C are invalidated.

  In other words, the AND circuits A22 to A24 output when the outputs OUT2A to OUT2C of the inrush determination circuits 2A to 2C are asserted or when the outputs OUT1A to 1C of the current ratio differential determination circuits 1A to 1C are negated. When OUTA24 is negated (in this case, “L”), the outputs OUT2A to OUT2C of the inrush determination circuits 2A to 2C are negated, and the outputs OUT1A to OUT1C of the current ratio differential determination circuits 1A to 1C are asserted The outputs OUTA22 to OUTA24 are asserted (in this case, “H”).

  The OR circuit O33 takes a logical sum of the outputs OUTA22 to OUTA24 of the AND circuits A22 to A24 and outputs the logical sum as an output OUTO33 to the AND circuit A25. That is, the OR circuit O33 takes the logical sum of the results of valid / invalidate the current ratio differential determination result for each phase of the protected transformer Tr depending on whether or not an inrush current is generated in the phase. In other words, the OR circuit O33 asserts the output OUTO33 when there is a phase in which no inrush current is generated in the phase and the differential current of the phase is equal to or greater than the threshold (in this case, “H ”), And the output OUTO33 is negated (in this case, if an inrush current is generated in the phase, or if no inrush current is generated in the phase and the differential current of the phase is smaller than the threshold value) Is “L”).

  The delay circuit 4 receives an output OUTO32 of the OR circuit O32, that is, a signal indicating whether or not an inrush current is generated in any phase of the protected transformer Tr, and is predetermined after the input is asserted. If the assertion continues for more than the time, the output is asserted (in this case “H”). If the input is negated in a time shorter than the predetermined time after the input is asserted, the input assertion is invalidated. The output is negated (in this case, “L”). Note that the predetermined time is a time necessary to absorb the time variation required for the detection of the inrush current, that is, the processing of the inrush determination circuits 2A to 2C.

  The AND circuit A25 takes the logical product of the output of the delay circuit 4 and the OR circuit O33, and outputs this logical product to the OR circuit O21 as an output OUTA25. That is, the AND circuit A25 asserts the output OUTA25 when the inrush current is generated in any phase of the protected transformer Tr and the differential current of the phase in which no inrush current is generated is equal to or higher than the threshold level. (In this case, “H”), and when no inrush current is generated in any phase of the protected transformer Tr, the output OUTA25 is negated (in this case, “L”).

  The OR circuit O21 takes a logical product of the output OUTA21 of the AND circuit A21 and the output OUTA25 of the AND circuit A25, and outputs the logical product as a trip signal TP to the system breakers CB1 to CB3 to output the system breakers CB1 to CB3. Control and eliminate grid faults. That is, the OR circuit O21 is used when the differential current of any phase of the protected transformer Tr is equal to or higher than the threshold level and no inrush current is generated in any phase, or the protected transformer Tr The trip signal TP is asserted (in this case, “H”) when the inrush current is generated in any of the phases and the differential current of the phase where the inrush current is not generated is equal to or higher than the threshold level. When the differential current of all phases is less than the threshold level, or when the inrush current is occurring in any phase and the differential current of the phase where no inrush current is occurring is less than the threshold level The trip signal TP is negated (in this case, “L”).

  Next, the operation of the current differential relay of the transformer protection relay according to the present invention will be described with reference to the timing charts of FIGS. First, referring to the timing charts of FIGS. 4 to 6, the operation time of the current differential relay is increased in each phase lock circuit 3B, and the tertiary voltage detection circuit 22 of the inrush determination circuit 2A detects the tertiary voltage. The operation when the time is required for the determination of the tertiary voltage will be described by taking an example of the operation when the time is required for the determination.

  FIG. 4 is a timing chart for explaining the operation of each phase lock circuit 3B. In FIG. 4, the protected transformer Tr is turned on at time t0, and the current ratio differential determination circuits 1A to 1C determine whether or not the differential current input from the current transformers CT1 to CT3 is equal to or higher than a threshold level. Start judgment. On the other hand, based on the differential signal input from the current transformers CT1 to CT3 and the tertiary terminal system voltage of the protected transformer Tr input from the voltage transformer PT3, each system of the protected transformer Tr Judgment is made on whether or not an inrush current has occurred.

  At time t1, the inrush determination circuit 2B determines that an inrush current has occurred in the second phase and sets the output OUT2B to “H”. Therefore, in the second phase, the occurrence of the inrush current causes the output OUT1B of the current ratio differential determination circuit 1B to be locked by the output OUT2B, and the output OUTA23 of the AND circuit A23 is fixed to “L” (no unnecessary response). .

  Further, since the inrush determination circuits 2A and 2C have not determined that the inrush current has occurred in the first phase and the third phase, the outputs OUT2A and OUT2C remain “L”. However, since the current ratio differential determination circuits 1A and 1C determine that the first-phase and third-phase differential currents are smaller than the threshold level, the outputs OUT1A and OUT1C become “L”, and the AND circuits A22 and A24. The outputs OUTA22 and OUTA24 also become “L”. Accordingly, the output (output of the OR circuit O33) OUTO33 of each phase lock circuit 3B becomes “L”.

  At time t2, the inrush determination circuit 2C determines that an inrush current has occurred in the third phase and sets the output OUT2C to “H”. Therefore, in the third phase, the occurrence of the inrush current causes the output OUT1C of the current ratio differential determination circuit 1C to be locked by the output OUT2C, and the output OUTA24 of the AND circuit A24 is fixed to “L” (no unnecessary response). .

  On the other hand, the current ratio differential determination circuit 1A determines that the first-phase differential current is equal to or higher than the threshold level, and sets the output OUT1A to “H”. The inrush determination circuit 2A determines that no inrush current is generated in the first phase, and the output OUT2A remains “L”. Therefore, the output OUT1A of the current ratio differential determination circuit 1A is not locked by the output OUT2A of the inrush determination circuit 2A. Accordingly, the output OUTA22 of the AND circuit A22 becomes “H”, and the output OUTO33 of each phase lock circuit 3B becomes “H”.

  At time t3, the inrush determination circuit 2A determines that an inrush current has occurred in the first phase and sets the output OUT2A to “H”. Therefore, in the first phase, the output OUT1A of the current ratio differential determination circuit 1A is locked by the output OUT2A due to the occurrence of the inrush current, and the output OUTA22 of the AND circuit A22 becomes “L”. Therefore, the output OUTO33 of each phase lock circuit 3B becomes “L”.

  As described above, the determination elements of the current ratio differential determination circuits 1A to 1C and the inrush determination circuits 2A to 2C are the magnitude and phase of the system current / voltage input, the sampling timing of the current differential relay, the calculation timing, and the like. Therefore, the operation time varies, and the determination by the tertiary voltage detection circuit 22 takes time. Therefore, as shown in the timing chart shown in FIG. 4, for example, each phase lock circuit 3B delays the output OUT2A (lock signal) of the inrush determination circuit 2A, and the current ratio differential determination circuit 1A The output OUT1A may not be locked and may trip erroneously. That is, in FIG. 4, each phase lock circuit 3B outputs an unnecessary response with the delay of the output of the lock signal (output OUT2A) only for the first phase (“H” of the output OUTA22), and the second and third phases are unnecessary. None (outputs OUTA23 and OUTA24 are “L”), and an unnecessary response (“H”) may be output as each phase determination trip signal (output OUTO33) of each phase lock circuit 3B.

  FIG. 5 is a timing chart for explaining the operation of the three-phase lock circuit 3A. As shown in FIG. 5, in the three-phase lock circuit 3A, the protected transformer Tr is turned on at time t0, and at time t1, the inrush determination circuit 2B detects the occurrence of the second phase inrush current. When the output OUT2B is set to “H”, the OR circuit O32 sets the output OUTO32 to “H”. As a result, the output OUTO31 of the OR circuit O31 that takes the logical sum of the outputs OUT1A to OUT1C of the current ratio differential determination circuits 1A to 1C is locked, and the output of the three-phase lock circuit 3A (the output OUTA21 of the AND circuit A21) is “ L ”, the outputs OUT1A and OUT1B of the current ratio differential determination circuits 1A and 1B become“ H ”at time t2, and the output OUT1C of the current ratio differential determination circuit 1C becomes“ H ”at time t3. The output OUTA21 of the three-phase lock circuit 3A remains fixed at “L”.

  As described above, the determination elements of the current ratio differential determination circuits 1A to 1C and the inrush determination circuits 2A to 2C are the magnitude and phase of the system current / voltage input, the sampling timing of the current differential relay, the calculation timing, and the like. As shown in the timing chart of FIG. 5, the three-phase lock circuit 3 </ b> A includes the inrush determination circuits 2 </ b> A to 2 </ b> C even when the operation time varies and the determination of the tertiary voltage detection circuit 22 takes time. Of these, the outputs OUT1A to 1C of the current ratio differential determination circuits 1A to 1C can be blocked by the determination element that outputs the lock signal first (sets OUT2A to OUT2C to "H"). That is, in FIG. 5, in the three-phase lock circuit 3A, the second-phase inrush determination circuit 2B outputs the lock signal the fastest (the output OUT2B is set to “H”), and the output OUTA21 of the three-phase lock circuit 3A. No unnecessary response ("L") is output as (three-phase determination trip signal).

  6 shows the output OUTO33 of each phase lock circuit 3B and the output OUTA21 of the three phase lock circuit 3A shown in FIGS. 4 and 5, and the output OUTO32 of the OR circuit O32 which is a lock signal of the three phase lock circuit 3A. 4 is a timing chart showing the relationship among the output OUTD of the delay circuit 4, the output OUTA25 of the AND circuit A25, and the trip signal TP that is the output of the OR circuit O21.

  In FIG. 6, as described with reference to the timing chart of FIG. 5, the output OUTA21 of the three-phase lock circuit 3A is fixed to “L”, and the lock signal of the three-phase lock circuit 3A is fixed at time t1. The output OUTO32 is “H”. On the other hand, as described with reference to the timing chart of FIG. 4, the output OUTO33 of each phase lock circuit 3B becomes “H” at time t2 and becomes “L” at time t3.

  The delay circuit 4 receives the output OUTO32 that has become “H” at time t1, and delays this input by the delay time dly, and sets the output OUTD to “H” at time t4. The AND circuit A25 outputs the logical product of the output OUTO33 of each phase lock circuit 3B and the output OUTD of the delay circuit 4 to the OR circuit O21 as an output OUTA25. Therefore, the AND circuit A25 causes the output OUTO33 of each phase lock circuit 3B to be “H” from time t2 to time t3 by the output OUTD of the delay circuit 4, that is, the signal obtained by delaying the lock signal of the three phase lock circuit 3A. To prevent unnecessary response output. As a result, the OR circuit O21 that takes the logical sum of the output OUTA21 of the three-phase lock circuit A and the output OUTD of the delay circuit 4 fixes the trip signal TP, which is an output, to “L” to prevent unnecessary response of the ratio differential relay. It is preventing.

  Next, referring to the timing charts of FIGS. 7 to 9, when an accident occurs in the protected transformer Tr, that is, when the accident transformer is turned on, the first and second phases are the accident phases. A case will be described as an example. FIG. 7 is a timing chart for explaining the operation of each phase lock circuit 3B.

  In FIG. 7, an accident occurs in the protected transformer Tr at time t10, and the current ratio differential determination circuits 1A to 1C determine whether or not the differential current input from the current transformers CT1 to CT3 is equal to or higher than a threshold level. Start the determination. On the other hand, based on the differential signal input from the current transformers CT1 to CT3 and the tertiary terminal system voltage of the protected transformer Tr input from the voltage transformer PT3, each system of the protected transformer Tr Judgment is made on whether or not an inrush current has occurred.

  At time t11, the current ratio differential determination circuits 1A and 1B determine that the first and second phase differential currents are equal to or higher than the threshold level, and set the outputs OUT1A and OUT1B to “H”. The inrush determination circuits 2A and 2B determine that no inrush current is generated in the first and second phases, and leave the outputs OUT2A and OUT2B at “L”. Therefore, the AND circuits A22 and A23 set the outputs OUTA22 and OUTA23 to “H”. That is, in the first and second phases, since no inrush current is generated, no lock signal is generated (outputs OUT2A and OUT2B are “L”), so the outputs of the current ratio differential determination circuits 1A and 1B OUT1A and OUT1B are output without being locked. Therefore, the output of each phase lock circuit 3B (the output of the OR circuit O33) OUTO33 becomes “H”.

  On the other hand, the inrush determination circuit 2A determines that an inrush current has occurred in the third phase and sets the output OUT2C to “H”. Thereby, in the third phase, the output OUT1C of the current ratio differential determination circuit 1C is locked by the output OUT2B due to the occurrence of the inrush current, and the output OUT1C of the current ratio differential determination circuit 1C becomes “H” after time t11. The output OUTA24 of the AND circuit A24 is fixed at “L” even if “” is reached.

  FIG. 8 is a timing chart for explaining the operation of the three-phase lock circuit 3A. As shown in FIG. 8, in the three-phase locking system circuit 3A, when an accident occurs in the protected transformer Tr at time t10, the current ratio differential determination circuits 1A and 1B detect the difference between the first and second phases at time t11. When the dynamic current exceeds the threshold level and the outputs OUT1A and OUT1B become “H”, the OR circuit O31 sets the output OUTO31 to “H”.

  On the other hand, when the inrush determination circuit 2C detects that the inrush current is generated in the third phase and sets the output OUT2C to “H”, the OR circuit O23 sets the output OUTO32 to “H”. As a result, the output OUTO31 of the OR circuit O31 is locked, and the AND circuit A21 fixes the output to “L”. That is, although the current ratio differential determination circuits 1A and 1B detect the first and second phase accidents, the result is not output.

  9 shows the output OUTO33 of each phase lock circuit 3B and the output OUTA21 of the three phase lock circuit 3A shown in FIGS. 7 and 8, and the output OUTO32 of the OR circuit O32 which is a lock signal of the three phase lock circuit 3A. 4 is a timing chart showing the relationship among the output OUTD of the delay circuit 4, the output OUTA25 of the AND circuit A25, and the trip signal TP that is the output of the OR circuit O21.

  In FIG. 9, as described with reference to the timing chart of FIG. 8, the output OUTA21 of the three-phase lock circuit 3A is fixed to “L”, and at time t11, the lock signal of the three-phase lock circuit 3A. The output OUT32A is “H”. On the other hand, as described with reference to the timing chart of FIG. 7, the output OUTO33 of each phase lock circuit 3B becomes “H” at time t11.

  The delay circuit 4 receives the output OUT32A that has become “H” at time t11, delays this input by the delay time dly, and sets the output OUTD to “H” at time t12. The AND circuit A25 outputs the logical product of the output OUTO33 of each phase lock circuit 3B and the output OUTD of the delay circuit 4 to the OR circuit O21 as an output OUTA25. Accordingly, the output OUTO33 of each phase lock circuit 3B is locked by the output OUTD of the delay circuit 4 until time t12. When the output OUTD becomes “H” at time t12, the output OUTO33 of each phase lock circuit 3B is valid. The AND circuit A25 sets the output OUTA25 to “H”. As a result, the OR circuit O21 taking the logical sum of the output OUTA25 and the output OUTA21 can set the trip signal TP, which is an output, to “H” and control the system breakers CB1 to CB3.

  As described above, in the first embodiment, the inrush determination circuits 2A to 2C for determining whether or not the inrush current is generated for each of the first to third phases of the protected transformer Tr. An output OUTO33 which is each phase determination trip signal output from each phase lock circuit 3B that locks only the determination results of the current ratio differential determination circuits 1A to 1C corresponding to the phase based on the determination result, and an inrush determination circuit Based on the output OUTA21 that is a three-phase determination trip signal output by the three-phase lock circuit 3A that locks all the determination results of the current ratio differential determination circuits 1A to 1C based on the determination result of any one of 2A to 2C. Since the trip signal TP is asserted, even if the inrush current determination process takes longer than the current ratio differential determination process, the current differential It is possible to prevent the malfunction of the rate.

  Further, in the first embodiment, each phase trip that locks the output OUTO33 that is each phase trip signal with a signal obtained by delaying the output OUTO32 that is the determination result of any of the inrush determination circuits 2A to 2C by the delay time dly. An AND circuit A25 that is a signal lock circuit is provided, and the trip signal TP is asserted based on the output OUTA25 of the AND circuit A25 and the output OUTA21 that is a three-phase determination trip signal. After preventing the malfunction of the current ratio differential relay based on the determination result of the phase lock circuit 3A, it is possible to switch to the determination result of each phase lock circuit 3B after a certain period of time as a measure against the accident device. As a result, the three-phase lock circuit 3A can prevent the output of the erroneous trip signal of the current differential relay using the phase in which the process for determining whether or not the inrush current has occurred is fast. Even when the speed of the relay is increased, it becomes easy to secure a margin in the time limit coordination of the processing of the current ratio differential determination circuits 1A to 1C and the inrush determination circuits 2A to 2C, and the operation time of the current differential relay is increased. Therefore, even when the current ratio differential determination process is speeded up, malfunction of the current differential relay can be prevented. In addition, each phase lock circuit 3A can easily detect the accident phase when the accident phase and the inrush phase are different when the accident transformer is turned on.

Embodiment 2. FIG.
A second embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the output OUTO33 of each phase lock circuit 3B is delayed by the delay time dly of the output signal OUTO33 of the phase lock circuit 3B by delaying the output signal OUTO32 of the three phase lock circuit 3A by the delay time dly. Although the circuit configuration prevents erroneous tripping, in the second embodiment, it is determined whether or not the assertion has continued for more than the delay time dly after the output OUTO33 of each phase lock circuit 3B is asserted. This prevents erroneous tripping of the output OUTO33 of the phase lock circuit 3B.

  Since the power system configuration to which the transformer protection relay of the second embodiment is applied is the same as the power system configuration of the first embodiment shown in FIG. 1, the description thereof is omitted here.

  FIG. 10 is a configuration diagram showing the function of the current differential relay according to the present invention of the transformer protection relay Ry of the second embodiment. The current differential relay according to the second embodiment shown in FIG. 10 is substantially the same as the current differential relay according to the first embodiment shown in FIG. 2, and the difference is the current difference between the first and second embodiments. The AND circuit A25 is deleted from the dynamic relay, and the output OUTO33 of the OR circuit O33 of each phase lock circuit 3B is input to the input of the delay circuit 4 instead of the output OUTO32 of the OR circuit O32 of the three phase lock circuit 3A. That is, the output OUTD of the delay circuit 4 is input to one input of the OR circuit O21. In addition, the same code | symbol is attached | subjected to the component which has the same function as the current differential relay of Embodiment 1 shown in previous FIG. 2, and the overlapping description is abbreviate | omitted.

  The delay circuit 4 asserts the output OUTD when the assertion is continuously input for a predetermined time or more after the output signal OUTO33 of the OR circuit O33 of each phase lock system circuit 3B, that is, the trip signal from each phase lock system circuit 3B is asserted. When the trip signal by each phase lock system circuit 3B becomes negated in a time shorter than a predetermined time after the trip signal by each phase lock system circuit 3B is asserted, the assertion of the input trip signal is invalidated and output. Is negated. Note that the predetermined time is a time necessary to absorb the time variation required for the detection of the inrush current, that is, the processing of the inrush determination circuits 2A to 2C.

  Next, the operation of the current differential relay according to the second embodiment will be described with reference to FIG. 11 and FIG. The three-phase lock circuit 3A and each phase lock circuit 3B of the current differential relay of the second embodiment are the same as those of the first embodiment. Therefore, the operation of the three-phase locking system circuit 3A and each phase locking system circuit 3B of the current differential relay is the same as the operation described with reference to the timing charts of FIG. 4, FIG. 5, FIG. 7, and FIG. Since there is, explanation is omitted here.

  First, referring to the timing chart of FIG. 11, the operation time of the current differential relay is increased in each phase lock circuit 3B, and the time required for the tertiary voltage detection determination in the tertiary voltage detection circuit 22 of the inrush determination circuit 2A. As an example, the operation when time is required for the tertiary voltage detection determination will be described.

  When each phase lock circuit 3B speeds up the operation time of the current differential relay, and the tertiary voltage detection circuit 22 of the inrush determination circuit 2A takes time for the tertiary voltage detection determination, each phase lock circuit 3B The operation is as described with reference to the timing chart of FIG. 4, and as shown in the timing chart of FIG. 11, the output OUTO33 becomes “H” from time t2 to time t3.

  When the output OUTO33 (its own input) becomes “H” at time t2, the delay circuit 4 monitors the change of the input and determines whether the input “H” continues for the delay time dly or longer. Here, the time from time t2 to time t3 is shorter than the delay time dly of the delay circuit 4 (time from time t2 to time t5). Therefore, the delay circuit 4 invalidates the assertion of the output OUTO33 from time t2 to time t3 and fixes the output OUTD to “L”.

  On the other hand, the three-phase lock circuit 3A operates as described with reference to the timing chart of FIG. 5, and the output OUTA21 is fixed to “L” as shown in the timing chart of FIG. The OR circuit O21 that takes the logical sum of the output OUTA21 and the output OUTD fixes the trip signal TP, which is an output, to “L” to prevent unnecessary response of the ratio differential relay.

  Next, referring to the timing chart of FIG. 12, when an accident occurs in the protected transformer Tr, that is, the operation when the accident transformer is turned on, the case where the first and second phases are the accident phase is an example. Will be described. In this case, each phase lock circuit 3B operates as described with reference to the timing chart of FIG. 7, and as shown in the timing chart of FIG. 12, the output OUTO33 becomes “H” at time t11. Become.

  When the output OUTO33 (own input) becomes “H” at time t11, the delay circuit 4 monitors the change of the input and determines whether the input “H” continues for the delay time dly or longer. Here, the output OUTO33 does not change after it becomes “H” at time t11. Therefore, the delay circuit 4 sets the output OUTD to “H” at time t12 when the delay time dly has elapsed from time t11.

  On the other hand, the three-phase lock circuit 3A operates as described with reference to the timing chart of FIG. 8, and the output OUTA21 is fixed to “L” as shown in the timing chart of FIG. At time t12, the OR circuit O21 that takes the logical sum of the output OUTA21 and the output OUTD can control the system breakers CB1 to CB3 by setting the trip signal TP as an output to “H”.

  As described above, in the second embodiment, the inrush determination circuits 2A to 2C that determine whether or not the inrush current is generated for each of the first phase to the third phase of the protected transformer Tr. An output OUTO33 which is each phase determination trip signal output from each phase lock circuit 3B that locks only the determination results of the current ratio differential determination circuits 1A to 1C corresponding to the phase based on the determination result, and an inrush determination circuit Based on the output OUTA21 that is a three-phase determination trip signal output by the three-phase lock circuit 3A that locks all the determination results of the current ratio differential determination circuits 1A to 1C based on the determination result of any one of 2A to 2C. Since the trip signal TP is asserted, even if the inrush current determination process takes longer than the current ratio differential determination process, the current differential It is possible to prevent the malfunction of the rate.

  In the second embodiment, when the output OUTO33, which is each phase determination trip signal output from each phase lock circuit 3B, continues to be asserted for the delay time dly, the output OUTO33 is delayed by the delay time dly. Since the output signal OUTD is output and the trip signal TP is asserted based on the output OUTD and the output OUTA21 which is the three-phase determination trip signal output from the three-phase lock method circuit 3A, the three-phase lock method circuit Without using the 3A inrush determination condition, when an inrush current is generated, first, after the malfunction of the current ratio differential relay is prevented by the determination result of the three-phase lock circuit 3A, It is possible to switch to the determination result of the lock circuit 3B. As a result, the three-phase lock circuit 3A can prevent the output of the erroneous trip signal of the current differential relay using the phase in which the process for determining whether or not the inrush current has occurred is fast. Even when the speed of the relay is increased, it becomes easy to secure a margin in the time limit coordination of the processing of the current ratio differential determination circuits 1A to 1C and the inrush determination circuits 2A to 2C, and the operation time of the current differential relay is increased. Therefore, even when the current ratio differential determination process is speeded up, malfunction of the current differential relay can be prevented. In addition, the phase-locked circuits 1A to 1C can easily detect the accident phase when the accident phase and the inrush phase are different when the accident transformer is turned on.

Embodiment 3 FIG.
A third embodiment of the present invention will be described with reference to FIG. In the first and second embodiments, the case where the operation time of the current ratio differential determination circuits 1A to 1C is increased in each phase lock circuit 3B has been described. In the third embodiment, a case where the current ratio differential determination circuits 1A to 1C are not accelerated will be described.

  Since the power system configuration to which the transformer protection relay of the third embodiment is applied is the same as the power system configuration of the first embodiment shown in FIG. 1, the description thereof is omitted here.

  FIG. 13 is a configuration diagram showing the function of the current differential relay according to the present invention of the transformer protection relay Ry of the third embodiment. In the current differential relay of the third embodiment shown in FIG. 13, the delay circuit 4 is deleted from the current differential relay of the second embodiment shown in FIG. 10, and the OR circuit of each phase lock circuit 3B. The output OUTO33 of O33 is input to one side of the OR circuit O21. In addition, the same code | symbol is attached | subjected to the component which has the same function as the current differential relay of Embodiment 1 shown in previous FIG. 2, and the overlapping description is abbreviate | omitted.

  The current ratio differential determination circuits 1A to 1C have the same functions as the current ratio differential determination circuits 1A to 1C of the second embodiment, but the circuit configuration has not been increased in speed and inrush. A shift from the processing time of the tertiary voltage detection circuit 22 of the determination circuits 2A to 2C does not occur, or the shift is absorbed by the delay of the circuit element so as not to cause an erroneous trip. Therefore, as described with reference to the timing chart of FIG. 4, there is a large difference in timing when the output OUT1A of the current ratio differential determination circuit 1A and the output OUT2A of the inrush determination circuit 2A become “H”. It does not occur. Therefore, the output OUT1A of the current ratio differential determination circuit 1A can be locked by the output OUT2A of the inrush determination circuit 2A, and the output OUTA22 of the AND circuit A22 is “H” from time t2 to time t3 in FIG. The state which becomes "" does not occur.

  As described above, in the third embodiment, the inrush determination circuits 2A to 2C that determine whether or not the inrush current is generated for each of the first phase to the third phase of the protected transformer Tr. An output OUTO33 which is each phase determination trip signal output from each phase lock circuit 3B that locks only the determination results of the current ratio differential determination circuits 1A to 1C corresponding to the phase based on the determination result, and an inrush determination circuit Based on the output OUTA21 that is a three-phase determination trip signal output by the three-phase lock circuit 3A that locks all the determination results of the current ratio differential determination circuits 1A to 1C based on the determination result of any one of 2A to 2C. Since the trip signal TP is asserted, even if the inrush current determination process takes longer than the current ratio differential determination process, the current differential It is possible to prevent the malfunction of the rate.

  In the first to third embodiments, the inrush determination circuits 2A to 2C are composed of the second harmonic detection circuit 21, the tertiary voltage detection circuit 22, and the AND circuit 26 shown in FIG. Although the second harmonic suppression method with voltage detection is configured, the configuration of the inrush determination circuits 2A to 2C is not limited to this, and any type can be used as long as it can be determined whether or not an inrush current has occurred. It may be a circuit configuration.

  For example, only the second harmonic detection process for determining whether or not the inrush current is generated based on the content ratio of the second harmonic component included in the input differential current (the second harmonic detection shown in FIG. 3). The circuit 21 alone may be configured. In this case, since it is not necessary to perform the tertiary voltage detection processing (the tertiary voltage detection circuit 22 shown in FIG. 3) that takes a long time to determine the third phase voltage due to countermeasures against distortion waves, the determination time for the generation of the inrush current And the operation of the current differential relay can be further speeded up.

  In the first to third embodiments, the current differential relay in the transformer protection relay that protects the protected transformer Tr has been described as an example. However, the present invention is not limited to this. It may be used as a relay that requires processing by determining whether or not it occurs, for example, a distance relay or an overcurrent relay for transformer protection, and is not limited to transformer protection, inrush current flows into the protection section, You may use for the apparatus which needs the countermeasure with respect to this inrush current.

  As described above, the transformer protection relay according to the present invention is useful for a system that needs to prevent malfunction due to inrush current, and in particular, the determination process of inrush current is more than the determination process of current ratio differential. Suitable for time-consuming systems.

It is a figure which shows the electric power grid | system structure to which the transformer protection relay in this invention is applied. It is a figure which shows the function of the current differential relay used for the transformer protection relay shown in FIG. FIG. 3 is a block diagram illustrating a configuration of an inrush determination circuit illustrated in FIG. 2. 3 is a timing chart for explaining the operation of each phase lock circuit of the current differential relay according to the first embodiment. 4 is a timing chart for explaining the operation of the three-phase lock circuit of the current differential relay of the first embodiment. 3 is a timing chart for explaining the operation of the current differential relay of the first embodiment. 3 is a timing chart for explaining the operation of each phase lock circuit of the current differential relay according to the first embodiment. 4 is a timing chart for explaining the operation of the three-phase lock circuit of the current differential relay of the first embodiment. 3 is a timing chart for explaining the operation of the current differential relay of the first embodiment. It is a figure which shows the function of the current differential relay of this Embodiment 2. FIG. It is a timing chart for demonstrating operation | movement of the current differential relay of this Embodiment 2. FIG. It is a timing chart for demonstrating operation | movement of the current differential relay of this Embodiment 2. FIG. It is a figure which shows the function of the current differential relay of this Embodiment 3.

Explanation of symbols

1A, 1B, 1C Current ratio differential determination circuit 2A, 2B, 2C Inrush determination circuit 3A Three-phase lock method circuit 3B Each phase lock method circuit 4 Delay circuit 21 Second harmonic detection circuit 22 Third voltage detection circuit A21, A22, A23, A24, A25, A26 AND circuit CB1, CB2, CB3 System breaker CT1, CT2, CT3 Current transformer N1, N2, N3, N4 NOT circuit O31, O32, O33, O21 OR circuit PT3 Voltage transformer Ry Transformer protection relay Tr Protected transformer

Claims (5)

A transformer protection relay that prevents malfunction of the current differential relay due to the inrush current of the transformer,
A first current ratio differential determination circuit for determining whether or not the first-phase differential current of the transformer is equal to or higher than a predetermined threshold level;
A second current ratio differential determination circuit for determining whether or not the second-phase differential current of the transformer is equal to or higher than a predetermined threshold level;
A third current ratio differential determination circuit for determining whether or not the third-phase differential current of the transformer is equal to or higher than a predetermined threshold level;
A first inrush determination circuit for determining whether an inrush current is generated in the first phase of the transformer;
A second inrush determination circuit for determining whether an inrush current has occurred in the second phase of the transformer;
A third inrush determination circuit for determining whether an inrush current has occurred in the third phase of the transformer;
If the first, second, or third inrush determination circuit determines that an inrush current has occurred, the determination results of the first, second, and third current ratio differential determination circuits are invalidated. If the three-phase determination trip signal is negated and all of the first, second, and third inrush determination circuits determine that no inrush current is generated, the first, second, and The determination result of the third current ratio differential determination circuit is validated, and the determination result of the first, second, or third current ratio differential determination circuit indicates that the differential current is greater than or equal to the threshold level. A three-phase lock circuit that asserts the three-phase determination trip signal when
When the first, second, or third inrush determination circuit determines that an inrush current has occurred, the first, second, or third inrush that has determined that an inrush current has occurred The determination result of the first, second, or third current ratio differential determination circuit that determines the differential current in the same phase as the determination circuit is invalidated, and each phase determination trip signal is negated, and the first, second, When the second or third inrush determination circuit determines that no inrush current has occurred, the first, second, or third inrush determination has determined that no inrush current has occurred. The determination result of the first, second, or third current ratio differential determination circuit that determines the differential current in the same phase as the circuit is valid, and the first, second, or third current ratio difference The judgment result of the motion judgment circuit A phase lock method circuitry for asserting the phase determination trip signal when indicating that but is the threshold level or above,
With
A current differential relay for asserting a trip signal based on the three-phase determination trip signal and each phase determination trip signal;
A transformer protection relay comprising: The current differential relay is
Asserting a trip signal when the three-phase decision trip signal or each phase decision trip signal is asserted;
The transformer protection relay according to claim 1. The current differential relay is
It is monitored whether or not the assertion of each phase determination trip signal is continued, and when the assertion of each phase determination trip signal is continued for a predetermined delay time, the respective phase determination trip signals are delayed. A delay circuit that delays the output of each phase determination trip signal when the assertion of each phase determination trip signal is not continued during the delay time,
Further comprising
Asserting a trip signal when the delay circuit is output or the three-phase decision trip signal is asserted;
The transformer protection relay according to claim 1. The current differential relay is
When the first, second, or third inrush determination circuit determines that an inrush current has occurred, the inrush determination result is monitored, and the inrush determination result is determined for a predetermined delay time. If it continues, the inrush determination result is output after being delayed by the delay time, and if the inrush determination result does not continue for the delay time, the inrush determination result is invalidated and the inrush current is output. A delay circuit that outputs a signal indicating that no occurrence occurred;
When the signal output from the delay circuit indicates that no inrush current has occurred, each phase determination trip signal output from each phase lock circuit is invalidated and the output is negated, and the delay circuit outputs Each phase determination trip signal lock circuit that validates each phase determination trip signal output by each phase lock method circuit and asserts the output when an inrush current signal is generated, and
Further comprising
Asserting a trip signal when the output of each phase determination trip signal lock circuit or the three-phase determination trip signal is asserted;
The transformer protection relay according to claim 1. The first, second, and third inrush determination circuits use a second harmonic suppression circuit with voltage detection;
The transformer protection relay according to any one of claims 1 to 4.

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