JP2012151727A - Analog/digital converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an analog/digital converter that can compensate an error in a short time.SOLUTION: An analog/digital converter includes: a switched capacitor circuit (101) for sampling an analog input voltage; a sign conversion circuit (401) for converting the plus/minus sign of a voltage of the switched capacitor circuit; an amplifier (301) for amplifying an output voltage of the sign conversion circuit; an offset voltage removal circuit (402) for removing an offset voltage of the amplifier from an output voltage of the amplifier; a latch circuit (302) for latching an output voltage of the offset voltage removal circuit; and a control section (103) for compensating an error in the switched capacitor circuit in accordance with an output circuit of the latch circuit in a compensation mode. In an analog/digital conversion mode, the switched capacitor circuit outputs an analog voltage in accordance with the output voltage of the latch circuit.

Description

  The present invention relates to an analog-digital converter.

  A second-order sigma-delta modulator for an analog-digital converter is known (for example, see Patent Document 1).

  Also, an analog-to-digital converter that performs analog-to-digital conversion on the signal amplified by the amplifier circuit, a digital-to-analog converter to perform offset adjustment of the amplifier circuit, and setting of offset adjustment and gain adjustment of the amplifier circuit are performed. An integrated circuit device including a control circuit is known (for example, see Patent Document 2).

  A switching amplifier that involves a switching operation to amplify the input signal; and an averaging circuit that samples the output voltage of the switching amplifier at a plurality of sampling times, generates an average voltage for the output voltage at each sampling time, and outputs the average voltage. An amplifying circuit is known (see, for example, Patent Document 3).

Japanese National Patent Publication No. 10-510405 JP 2009-200807 A JP 2008-219404 A

  An object of the present invention is to provide an analog-digital converter capable of correcting an error in a short time.

  The analog-to-digital converter includes a switched capacitor circuit that samples an analog input voltage, a sign conversion circuit that converts the sign of the voltage of the switched capacitor circuit, an amplifier that amplifies the output voltage of the sign conversion circuit, and the amplifier An offset voltage removing circuit that removes the offset voltage of the amplifier from the output voltage, a latch circuit that latches the output voltage of the offset voltage removing circuit, and, in the correction mode, the switched capacitor circuit according to the output voltage of the latch circuit. And a controller for correcting an error, and the switched capacitor circuit outputs an analog voltage in accordance with an output voltage of the latch circuit in the analog-digital conversion mode.

  The error can be corrected in a short time. Further, the analog-digital conversion accuracy can be improved by removing the offset voltage of the amplifier.

1A and 1B are diagrams illustrating a configuration example of a successive approximation analog-digital converter according to an embodiment. 2A to 2D are diagrams for explaining the correction processing of the capacitance value of the capacitance portion of the analog-digital converter. FIG. 3A is a diagram illustrating a configuration example of an analog-digital converter according to a comparative example, and FIG. 3B is a time chart illustrating an operation example thereof. It is a figure which shows the specific structural example of the analog-digital converter by embodiment. 5A is a circuit diagram illustrating a configuration example of the preamplifier in FIG. 4, and FIG. 5B is a circuit diagram illustrating a configuration example of the latch circuit in FIG. It is a time chart which shows the operation example of the analog-digital converter by embodiment. FIGS. 7A and 7B are diagrams showing comparison of correction times when the sign of the offset voltage and the initial error voltage of the capacitor is different. FIGS. 8A and 8B are diagrams showing comparison of correction times when the sign of the offset voltage and the initial error voltage of the capacitor is the same.

  1A and 1B are diagrams illustrating a configuration example of a successive approximation analog-digital converter according to an embodiment. Hereinafter, the successive approximation analog-digital converter is simply referred to as an analog-digital converter. The analog-digital converter includes a capacitor unit 101, a comparison circuit 102, and a control unit 103. The capacitor unit 101 includes six analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, C, a correction variable capacitor Cv, capacitor switches 111 to 117, and a first switch 110. Each of the six analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, C has one end connected to the input terminal (common node) of the comparison circuit 102, and the other end via the switches 111 to 116. Are connected to the node of the analog input voltage Vin, the node of the high level Vdd, or the node of the low level (0 V). The capacity 16C has a capacity value 16 times that of the capacity C, the capacity 8C has an capacity value 8 times that of the capacity C, and the capacity 4C has a capacity value 4 times that of the capacity C. The capacitance 2C has a capacitance value twice that of the capacitance C. One end of the correction variable capacitor Cv is connected to the input terminal (common node) of the comparison circuit 102, and the other end is connected to the node of the analog input voltage Vin, the node of the high level Vdd, or the low level (0V) via the switch 117. Connected to the node. The first switch 110 is a switch for connecting the input terminal (common node) of the comparison circuit 102 to the node of the first voltage Vc. The first voltage Vc is, for example, 0V. The correction variable capacitor Cv is a capacitor for correcting an error of the six analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, and C. For example, when the error of the six analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, C is zero, the capacitance value of the correction variable capacitor Cv is zero. The control unit 103 controls the switches 110 to 117 in the capacitor unit 101. The comparison circuit 102 compares the voltage at the input terminal with 0 V and outputs a comparison result. The control unit 103 controls the switches 111 to 117 according to the comparison result of the comparison circuit 102.

  Next, a method in which the analog-digital converter performs analog-digital conversion in the analog-digital conversion mode will be described. First, as shown in FIG. 1A, under the control of the control unit 103, the first switch 110 connects the input terminal of the comparison circuit 102 to the node of the first voltage Vc, and six switches 111 to 116 are provided. The other ends of the analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, and C are connected to the node of the analog input voltage Vin, and the switch 117 connects the other end of the correction variable capacitor Cv to the node of the analog input voltage Vin. Connecting. The six analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, C and the correction variable capacitor Cv are charged by the analog input voltage Vin.

  Next, as shown in FIG. 1B, under the control of the control unit 103, the first switch 110 disconnects the input terminal of the comparison circuit 102 from the node of the first voltage Vc, and the switch 111 performs analog-digital conversion. The other end of the capacitor 16C is connected to the node of the high level Vdd, and the switches 112 to 116 have the other ends of the five analog-digital conversion capacitors 8C, 4C, 2C, C, C as nodes of the low level (0V). The switch 117 connects the other end of the correction variable capacitor Cv to a low level (0 V) node. Here, the input voltage of the comparison circuit 102 is Ve. The comparison circuit 102 compares the voltage Ve with 0V. When the voltage Ve is a negative voltage or 0V, the switch 111 is kept connected to the node of the high level Vdd, and when the voltage Ve is a positive voltage, the connection of the switch 111 is switched to the node of the low level (0V). Thereby, the digital bit corresponding to the capacitor 16C is determined.

  Next, under the control of the control unit 103, the switch 112 connects the other end of the analog-digital conversion capacitor 8C to the node of the high level Vdd, and the switches 113 to 116 have four analog-digital conversion capacitors 4C, 2C, C. , C are connected to a low level (0 V) node, and the switch 117 connects the other end of the correction variable capacitor Cv to a low level (0 V) node. The comparison circuit 102 compares the voltage Ve with 0V. When the voltage Ve is a negative voltage or 0 V, the switch 112 is kept connected to the node of the high level Vdd, and when the voltage Ve is a positive voltage, the connection of the switch 112 is switched to the node of the low level (0 V). Thereby, the digital bit corresponding to the capacitor 8C is determined.

  Similarly, by controlling the switches 113 to 116, digital bits corresponding to the analog-digital conversion capacitors 4C, 2C, and C are determined. Here, the switch 117 of the correction variable capacitor Cv performs the same operation as the switch 116.

  Thereafter, the connection state of the switches 111 to 116 at the other ends of the five analog-digital conversion capacitors 16C, 8C, 4C, 2C, C is output as a digital value obtained by converting the analog input voltage Vin into a digital value. . For example, among the switches 111 to 116, a switch connected to a high level Vdd node corresponds to a digital bit of “0”, and a switch connected to a low level (0V) node is a digital of “1”. Corresponds to the bit.

  2A to 2D are diagrams for explaining the correction processing of the capacitance value of the capacitor 101 of the analog-digital converter. The analog-digital converter attempts to reduce the size of the analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, C in order to suppress an increase in area and power. Then, on the other hand, errors due to mismatches in the analog-digital conversion capacitors 16C, 8C, 4C, 2C, C, and C and parasitic capacitances increase, so that the correction capacitor Cv is corrected. For example, the error of the analog-digital conversion capacitor 16C is corrected.

  In the correction mode, the analog-digital converter performs the following correction process. First, the analog-digital converter controls to the connection state of FIG. Under the control of the control unit 103, the first switch 110 connects the input terminal of the comparison circuit 102 to the node of the first voltage Vc, and the switch 111 connects the other end of the capacitor 16C to the low level (0V) node. The switches 112 to 116 connect the other ends of the capacitors 8C, 4C, 2C, C, and C to the node of the high level Vdd, and the switch 117 connects the other end of the correction capacitor Cv to the node of the high level Vdd.

  Next, the analog-digital converter controls the connection state shown in FIG. Under the control of the control unit 103, the first switch 110 disconnects the input terminal of the comparison circuit 102 from the node of the first voltage Vc, and the switch 111 connects the other end of the capacitor 16C to the node of the high level Vdd. 112 to 116 connect the other ends of the capacitors 8C, 4C, 2C, C, and C to the low level (0V) node, and the switch 117 connects the other end of the correction capacitor Cv to the low level (0V) node. . That is, the connection state of the switches 111 to 117 in FIG. 2A and the connection state of the switches 111 to 117 in FIG. 2B are opposite to each other with respect to the low level (0 V) and high level Vdd nodes. Become.

  When the capacitance 16C and the sum of the capacitances 8C, 4C, 2C, C, and C have the same capacitance value, there is no error, so the input voltage Ve of the comparison circuit 102 in FIG. 2B is compared with that in FIG. It becomes the same as the input voltage Vc (0V) of the circuit 102 and becomes 0V. On the other hand, when the capacitor 16C is larger than the sum of the capacitors 8C, 4C, 2C, C, and C, the capacitor 16C includes a positive error, so that the input voltage Ve of the comparison circuit 102 is a positive voltage. Conversely, when the capacitance 16C is smaller than the sum of the capacitances 8C, 4C, 2C, C, C, the capacitance 16C includes a negative error, so the input voltage Ve of the comparison circuit 102 is a negative voltage.

  The comparison circuit 102 compares the input voltage Ve with 0V. The control unit 103 increases the capacitance value of the correction capacitor Cv by a predetermined amount if the input voltage Ve is a positive voltage, and decreases the capacitance value of the correction capacitor Cv by a predetermined amount if the input voltage Ve is a negative voltage. . On the other hand, if the input voltage Ve is approximately 0 V, the control unit 103 maintains the capacitance value of the correction capacitor Cv and ends the correction process.

  Thereafter, in the same manner as described above, the control in FIG. 2A and the control in FIG. 2B are alternately repeated, and when the input voltage Ve in FIG. By this correction processing, the capacitance value of the correction capacitor Cv is controlled, and the error of the capacitor 16C is corrected.

  2C and 2D are diagrams illustrating an image of the above correction processing. The balance of the comparison circuit 102 compares the size of the plate 202 with the capacity 16C including the error with the plate 201 with the capacity 8C, 4C, 2C, C, C and the correction capacity Cv. As shown in FIG. 2C, if the capacity value of the plate 202 having the capacity 16C is larger, the capacity value of the correction capacity Cv is increased. As described above, the capacity value of the correction capacitor Cv is controlled by repeating the process of FIG. 2A and the process of FIG. 2B, and the plates 201 and 202 are controlled as shown in FIG. When the capacitance values are the same, the correction process ends and the capacitance value of the correction capacitor Cv is determined.

  Here, the comparison circuit 102 serving as a balance holds an important key for correction. If there is a discrimination error (offset) in the comparison circuit 102, the capacitance error is mistaken and correction is insufficient. Therefore, the offset of the comparison circuit 102 needs to be sufficiently small.

  FIG. 3A is a diagram illustrating a configuration example of an analog-digital converter according to a comparative example, and FIG. 3B is a time chart illustrating an operation example thereof. The comparison circuit 102 includes a preamplifier 301 and a latch circuit 302. The capacitor 101 outputs a voltage Vem in addition to the voltage Vep. The voltages Vep and Vem are differential signals whose phases are inverted from each other. The differential voltage Ve is expressed as Vep−Vem. The voltage Vei in FIG. 3B is an initial voltage of the voltage Ve. The preamplifier 301 amplifies the voltages Vep and Vem of the differential signal and outputs the voltages V0p and V0m of the differential signal. The latch circuit 302 amplifies and latches the difference between the voltages V0p and V0m of the differential signal in synchronization with the clock signal Φc, and outputs a binary determination value Qo. When the voltage V0p is higher than the voltage V0m, the binary determination value Qo is at a high level, and when the voltage V0p is lower than the voltage V0m, the binary determination value Qo is at a low level. The control unit 103 increases the capacitance value of the correction capacitor Cv when the binary determination value Qo is at a high level. By alternately repeating the processes of FIGS. 2A and 2B, the binary determination value Qo eventually becomes low level, and the correction ends. A period Tc in which the binary determination value Qo is at a high level is a correction time.

  The latch circuit 302 has a role of amplifying a signal at high speed, but has a large offset voltage Vof2 because it is composed of a small-sized element. A preamplifier 301 is provided to reduce the offset voltage Vof2, and the offset voltage Vof2 of the latch circuit 302 can be reduced to 1 / A by the gain A of the preamplifier 301.

  However, although the offset voltage Vof2 of the latch circuit 302 is reduced by the gain A of the preamplifier 301, the offset voltage Vof1 of the preamplifier 301 itself cannot be reduced, so that there is a residual error voltage 311 after correction as shown in FIG. However, a correction error occurs. The residual error voltage 311 is Vof1 + Vof2 / A, and the offset voltage Vof2 is reduced by the gain A of the preamplifier 301, but the offset voltage Vof1 is not reduced. As a result, the residual error voltage 311 increases and the correction error increases.

  Further, as shown in FIG. 3B, the voltage Ve monotonously decreases, so that the correction time Tc becomes longer. In particular, when the voltage Ve is a positive voltage and the offset voltages Vof1 and Vof2 of the comparison circuit 102 are negative voltages, the correction time Tc becomes long. That is, when the sign of the voltage Ve and the offset voltages Vof1 and Vof2 are different, the correction time Tc is particularly long.

  Hereinafter, an embodiment of an analog-digital converter capable of reducing the correction error by reducing the residual error voltage 311 and reducing the correction time Tc will be described.

  FIG. 4 is a diagram illustrating a specific configuration example of the analog-digital converter according to the embodiment, and FIG. 6 is a time chart illustrating an operation example thereof. FIG. 6 shows, in order from the top, signals Φss, Φsc, Φr, voltages Ve, V1, V2, V3, signal Φc, and binary determination value Qo. The analog-digital converter performs storage processing of the offset voltage Vof1 in the period T1, and performs correction processing in the period T2.

  The comparison circuit 102 includes a code conversion circuit 401, a preamplifier 301, an offset voltage removal circuit 402, and a latch circuit 302. The comparison circuit 102 in FIG. 4 is obtained by adding a sign conversion circuit 401 and an offset voltage removal circuit 402 to the comparison circuit 102 in FIG. The capacitor unit 101 outputs a voltage Vep and a voltage Vem. The voltages Vep and Vem are differential signals whose phases are inverted from each other. The voltage Vei in FIG. 6 is an initial voltage of the voltage Ve.

  The sign conversion circuit 401 includes switches 421 to 424, and converts the signs of the voltages Vep and Vem according to the clock signals Φss and Φsc. The clock signals Φss and Φsc are signals that are logically inverted from each other. When the clock signal Φss is at a high level, the switches 421 and 424 are turned on, the switches 422 and 423 are turned off, the voltage Vep is output as the voltage V1p, and the voltage Vem is output as the voltage V1m. That is, the differential signal voltages Vep and Vem are output as the differential signal voltages V1p and V1m as they are. In this case, the differential voltage V1 is represented by V1p−V1m and is the same voltage as the voltage Ve. In FIG. 6, the voltages V1 and Ve are both positive voltages.

  On the other hand, when the clock signal Φsc is at a high level, the switches 421 and 424 are turned off, the switches 422 and 423 are turned on, the voltage Vep is output as the voltage V1m, and the voltage Vem is output as the voltage V1p. That is, the differential signal voltages Vep and Vem are converted into negative signs and output as differential signal voltages V1p and V1m. In this case, the voltage V1 is −1 × Ve. In FIG. 6, the voltage Ve is a positive voltage, and the voltage V1 is a negative voltage.

  The frequency of the clock signals Φss and Φsc of the sign conversion circuit 401 is half the frequency of the clock signal Φc of the latch circuit 302, and the clock signals Φss and Φsc are signals whose phases are inverted from each other. Thereby, + Ve and -Ve appear alternately in the voltage V1. The sign conversion circuit 401 alternately performs conversion to a positive sign and conversion to a negative sign.

  The preamplifier 301 amplifies the differential signal voltages V1p and V1m with a gain A, and outputs the differential signal voltages V2p and V2m. The voltages V2p and V2m include the offset voltage Vof1 of the preamplifier 301. In FIG. 6, the differential voltage V2 is represented by V2p−V2m and is A × V1−Vof1.

  The offset voltage removal circuit 402 includes an average value circuit 403, average value capacitors 411 and 412, and switches 413 to 416, and removes the offset voltage Vof1 of the preamplifier 301 from the differential signal voltages V2p and V2m. Signal voltages V3p and V3m are output. In FIG. 6, the differential voltage V3 is represented by V3p−V3m, and V2 + Vof1 = A × V1. One end of the average value capacitor 411 is connected to the output terminal of the preamplifier 301 or the output terminal of the average value circuit 403 via the switch 413, and the other end is connected to the input terminal of the latch circuit 302. The second switch 415 is a switch for connecting the other end of the average value capacitor 411 to the node of the second voltage Vcm. One end of the average value capacitor 412 is connected to the output terminal of the preamplifier 301 or the output terminal of the average value circuit 403 via the switch 414, and the other end is connected to the input terminal of the latch circuit 302. The second switch 416 is a switch for connecting the other end of the average value capacitor 412 to the node of the second voltage Vcm. The voltage Vcm is, for example, 0V.

  Next, the operation of the offset voltage removal circuit 402 will be described. The signal Φr becomes high level in the offset voltage storage period T1, and then becomes low level. First, processing in the offset voltage storage period T1 will be described. Since the signal Φr is at a high level, the switches 413 and 414 connect the differential output terminal of the average value circuit 403 to the first terminals of the average value capacitors 411 and 412 respectively, and the second switches 415 and 416 The node of the voltage Vcm is connected to the second terminals of the average value capacitors 411 and 412. The voltage at the other end of the average value capacitor 411 is the voltage V3p, and the voltage at the other end of the average value capacitor 412 is the voltage V3m. In FIG. 6, the voltage V3 is 0V.

  The average value circuit 403 is, for example, a low-pass filter, averages the differential signal voltages V2p and V2m in the period T1, and outputs the differential signal average value voltage to the average value capacitors 411 and 412 from the differential output terminal. . That is, the average value circuit 403 includes the output voltages V2p and V2m of the preamplifier 301 when the sign conversion circuit 401 converts to a positive sign, and the output voltages V2p and V2m of the preamplifier 301 when the sign conversion circuit 401 converts to a negative sign. The average value of is output. The average value voltage is {(A × Vei−Vof1) + (− A × Vei−Vof1)} / 2 = −Vof1. The average value capacitors 411 and 412 store an offset voltage of −Vof1.

  As described above, when the signal Φr becomes high level in the offset voltage storage period T1, the average values of the output voltages V2p and V2m of the preamplifier 301 are stored in the average value capacitors 411 and 412, respectively. The voltage Ve, which is a DC component, is frequency-converted by the sign conversion circuit 401 and becomes a frequency component of the clock signals Φss and Φsc, and the DC component of the output voltage V2 of the preamplifier 301 includes only the offset voltage Vof1 of the preamplifier 301. . By passing the voltage V2 through the average value circuit (low-pass filter) 403, the offset voltage Vof1 can be stored in the average value capacitors 411 and 412.

  Next, processing in the correction period T2 will be described. Since the signal Φr is at a low level, the switches 413 and 414 connect the nodes of the voltages V2p and V2m to the first terminals of the average value capacitors 411 and 412 respectively, and the second switches 415 and 416 are turned off. The voltage V3 becomes V2−Vof1 = A × V1. That is, the voltage V3 is a voltage obtained by removing the offset voltage Vof1 from the voltage V2.

  As described above, when the signal Φr becomes low level in the correction period T2, the preamplifier 301 and the latch circuit 302 are coupled by the average value capacitors 411 and 412. Since the average value capacitors 411 and 412 accumulate the offset voltage -Vof1, the offset voltage Vof1 of the preamplifier 301 is removed and transmitted by the input voltages V3p and V3m of the latch circuit 302.

  The latch circuit 302 amplifies and latches the voltages V3p and V3m of the differential signal in synchronization with the rising edge of the clock signal Φc, and outputs a binary determination value Qo. When the voltage V3p is higher than the voltage V3m, the binary determination value Qo is at a high level, and when the voltage V3p is lower than the voltage V3m, the binary determination value Qo is at a low level. The latch circuit 302 has an offset voltage Vof2. For example, in FIG. 6, the offset voltage is −Vof2.

  At the first rising edge of the clock signal Φc, since the voltage V3 is higher than the offset voltage of −Vof2, the binary determination value Qo becomes high level. Then, the control unit 103 increases the capacitance value of the correction capacitor Cv. Thereafter, the processing of FIGS. 2A and 2B is performed.

  Next, at the second rising edge of the clock signal Φc, since the voltage V3 is smaller than the offset voltage of −Vof2, the binary determination value Qo becomes low level. Then, the control unit 103 increases the capacitance value of the correction capacitor Cv. Thereafter, the processing of FIGS. 2A and 2B is performed.

  Next, at the third rising edge of the clock signal Φc, since the voltage V3 is higher than the offset voltage of −Vof2, the binary determination value Qo becomes high level. Then, the control unit 103 increases the capacitance value of the correction capacitor Cv. Thereafter, the processing of FIGS. 2A and 2B is performed.

  Next, at the timing t1 of the fourth rising edge of the clock signal Φc, since the voltage V3 is higher than the offset voltage of −Vof2, the binary determination value Qo becomes high level. Since the binary determination value Qo is continuously at the same level (value) at the third and fourth rising edges, the control unit 103 increases the capacitance value of the correction capacitor Cv, and thereafter, FIG. ) And FIG. 2B are performed, and the correction process is terminated. As described above, when the binary determination value Qo is continuously at the same level twice, the correction process is terminated. Thereby, the correction period T2 ends.

  When the start of operation is instructed, the analog-digital converter first performs the correction process of FIG. 6 in the correction mode, and then performs the analog processing of FIGS. 1A and 1B in the analog-digital conversion mode. Perform digital conversion processing.

  In the above description, the offset voltage Vof2 of the latch circuit 302 is not corrected, but the error voltage Ve of the capacitor unit 101 is multiplied by A by the preamplifier 301. When viewed from the output (= input of the preamplifier 301), it is reduced to Vof2 / A.

  Note that the offset storage period T1 is an example of the length of one cycle of the clock signal Φss, but may be a length that is an integer multiple of 1 or more of the cycle of the clock signal Φss.

  FIG. 5A is a circuit diagram illustrating a configuration example of the preamplifier 301 in FIG. The preamplifier 301 includes field effect transistors 501 to 505, amplifies the voltages V1p and V1m of the input differential signal, and outputs the voltages V2p and V2m of the output differential signal. In the p-channel field effect transistor 501, the source is connected to the power supply potential node, and the gate and drain are connected to the node of the output voltage V2m. In the p-channel field effect transistor 502, the source is connected to the power supply potential node, and the gate and drain are connected to the node of the output voltage V2p. In the n-channel field effect transistor 503, the drain is connected to the node of the output voltage V2m, and the gate is connected to the node of the input voltage V1p. In the n-channel field effect transistor 504, the drain is connected to the node of the output voltage V2p, and the gate is connected to the node of the input voltage V1m. The n-channel field effect transistor 505 has a drain connected to the sources of the n-channel field effect transistors 503 and 504, a gate connected to a bias potential node, and a source connected to a reference potential (ground potential) node.

  FIG. 5B is a circuit diagram illustrating a configuration example of the latch circuit 302 in FIG. The latch circuit 302 includes field effect transistors 511 to 516, latches the voltages V3p and V3m of the input differential signal in synchronization with the rising edge of the clock signal Φc, and outputs the latched binary determination values Qop and Qom. . The binary determination values Qo and Qom are differential signals that are logically inverted from each other. When the voltage V3p is higher than the voltage V3m, the binary determination value Qo is at a high level, and when the voltage V3p is lower than the voltage V3m, the binary determination value Qo is at a low level. In the p-channel field effect transistor 511, the source is connected to the power supply potential node, the gate is connected to the node of the clock signal Φc, and the drain is connected to the node of the binary determination value Qom. In the p-channel field effect transistor 512, the source is connected to the power supply potential node, the gate is connected to the node of the binary determination value Qo, and the drain is connected to the node of the binary determination value Qom. In the n-channel field effect transistor 515, the drain is connected to the node of the binary determination value Qom, the gate is connected to the node of the input voltage V3p, and the source is connected to the reference potential node. In the p-channel field effect transistor 513, the source is connected to the power supply potential node, the gate is connected to the node of the clock signal Φc, and the drain is connected to the node of the binary determination value Qo. In the p-channel field effect transistor 514, the source is connected to the power supply potential node, the gate is connected to the node of the binary determination value Qom, and the drain is connected to the node of the binary determination value Qo. In the n-channel field effect transistor 516, the drain is connected to the node of the binary determination value Qo, the gate is connected to the node of the input voltage V3m, and the source is connected to the reference potential node.

Next, the reason why the correction time of this embodiment is shortened will be described. Since the correction is completed when the output voltage Ve of the capacitor 101 becomes substantially equal to the residual offset voltage Vof after n clocks from the start of the correction, the relationship is expressed by the following equation (1).
Vei−n × ΔV≈Vof (1)

  Here, Vei is an initial value of the output voltage Ve of the capacitor unit 101, ΔV is a change in the output voltage Ve of the capacitor unit 101 every clock by correction, and Vof is an offset voltage of the comparison circuit 102.

In the present embodiment, this is equivalent to the absolute value of the offset voltage Vof. Therefore, when the correction clock number n is obtained from the above equation (1), the following equation (2) is obtained. The offset voltage Vof1 of the operational amplifier 301 is removed by the offset voltage removal circuit 402.
n = {Vei− | Vof2 |} / ΔV (2)

  That is, it can be seen that the correction clock number n is independent of the sign of the offset voltage Vof2.

On the other hand, in the analog-digital converters of FIGS. 3A and 3B, the minimum value n (min) and the maximum value m (max) of the correction clock number n are expressed by Become. However, for simplicity of comparison, it is assumed that the offset voltage Vof1 of the preamplifier 301 is zero. Also, Vei and Vof2 are positive values.
Minimum value: n (min) = {Vei−Vof2} / ΔV
Maximum value: n (max) = {Vei + Vof2} / ΔV

Therefore, the average value n (avg) of the correction clock number n is expressed by the following equation (3).
n (avg) = {n (min) + n (max)} / 2
= Vei / ΔV (3)

  The number of correction clocks n in the expression (2) of this embodiment is smaller than the correction average clock number n (avg) of the analog-digital converters of FIGS. 3 (A) and 3 (B). That is, the average value of the correction time of this embodiment is shorter than the average value of the correction time of the analog-digital converters of FIGS.

  7A and 7B are diagrams showing a comparison of correction times when the sign of the offset voltage Vof2 and the initial error voltage Vei of the capacitor 101 is different. FIG. 7A shows the correction time Tc1 of the analog-digital converter of the present embodiment, and FIG. 7B shows the correction time Tc2 of the analog-digital converter of FIGS. 3A and 3B. 7A, the offset voltage Vof1 is removed by the offset voltage removal circuit 402. In FIG. 7B, it is assumed that the offset voltage Vof1 is 0 for easy comparison. In this case, the corrected residual error voltage 701 in the present embodiment in FIG. 7A is approximately Vof2 / A as the residual error voltage viewed from the output of the capacitor 101. On the other hand, the corrected residual error voltage 702 in FIG. 7B is also approximately Vof2 / 2. The residual error voltage 701 in FIG. 7A and the residual error voltage 702 in FIG. 7B are substantially the same. However, in practice, since the present embodiment removes the offset voltage Vof1 of the preamplifier 301, the residual error is smaller in this embodiment. As described above, the correction times are compared while the residual error voltages 701 and 702 are substantially the same. The correction time Tc1 in FIG. 7A is shorter than the correction time Tc2 in FIG. In particular, the smaller the amount of change ΔV in the output error voltage Ve of the capacitor 101 in correction, the more significant the difference in correction time.

  8A and 8B are diagrams showing a comparison of correction times when the offset voltage Vof2 and the initial error voltage Vei of the capacitor 101 have the same sign. 8A shows the correction time Tc1 of the analog-digital converter of this embodiment, and FIG. 8B shows the correction time Tc2 of the analog-digital converter of FIGS. 3A and 3B. The residual error voltage 801 in FIG. 8A and the residual error voltage 802 in FIG. 8B are similar to the residual error voltage 701 in FIG. 7A and the residual error voltage 702 in FIG. 7B. The correction time Tc1 in FIG. 7A has a relatively small difference from the correction time Tc2 in FIG. However, in this embodiment, considering that the offset voltage Vof1 of the preamplifier 301 is removed, the correction time Tc1 in FIG. 8A is shorter than the correction time Tc2 in FIG.

  The sign of the offset voltage Vof2 has randomness, and even if it is an analog-to-digital converter of the same architecture, there are cases where it is positive and negative depending on the individual. Therefore, when a plurality of analog-digital converters are mounted in one semiconductor chip, the states of FIGS. 7A and 7B and the states of FIGS. 8A and 8B are mixed. . Therefore, there is a great merit that the average value of the correction time Tc1 of the analog-digital converter of the present embodiment is shorter than the average value of the correction time Tc2 of the analog-digital converter of FIGS.

According to this embodiment, the influence of the sign of the offset voltage Vof2 in correction can be reduced, and the average correction time of the capacitance value of the correction variable capacitor Cv can be shortened. Further, the offset voltage Vof1 of the preamplifier 301 can be removed without increasing the element size of the preamplifier 301. This has the merit that the influence on the operation speed is small, and the analog-digital conversion accuracy can be improved.
To do.

  The capacitor 101 is not limited to the above configuration and correction method, and may be a switched capacitor circuit that samples the analog input voltage Vin. The switched capacitor circuit outputs an analog voltage according to the output voltage of the latch circuit 302 in the analog-digital conversion mode. In the correction mode, the control unit 103 corrects the error of the switched capacitor circuit according to the output voltage of the latch circuit 302.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

101 Capacitor 102 Comparison Circuit 103 Control Unit 301 Preamplifier 302 Latch Circuit 401 Code Conversion Circuit 402 Offset Voltage Removal Circuit 403 Average Value Circuit

Claims (6)

A switched capacitor circuit for sampling the analog input voltage;
A sign conversion circuit for converting the sign of the voltage of the switched capacitor circuit;
An amplifier for amplifying the output voltage of the code conversion circuit;
An offset voltage removing circuit for removing the offset voltage of the amplifier from the output voltage of the amplifier;
A latch circuit that latches the output voltage of the offset voltage removal circuit;
In the correction mode, a controller that corrects the error of the switched capacitor circuit according to the output voltage of the latch circuit,
In the analog-digital conversion mode, the switched capacitor circuit outputs an analog voltage according to the output voltage of the latch circuit. The offset voltage removal circuit includes:
An average value circuit that outputs an average value of the output voltage of the amplifier when the sign conversion circuit converts to a positive sign and the output voltage of the amplifier when the sign conversion circuit converts to a negative sign;
One end can be connected to the output terminal of the amplifier or the output terminal of the average value circuit, the other end is connected to the input terminal of the latch circuit, the average value capacitor,
2. The analog-digital converter according to claim 1, further comprising: a second switch for connecting the other end of the average value capacitor to a second voltage node.   3. The analog-digital converter according to claim 1, wherein the sign conversion circuit alternately performs conversion to a positive sign and conversion to a negative sign. The switched capacitor circuit is:
One end of each is connected to a common node, and each other end is connected to an analog input voltage node, a high level node or a low level node, and a plurality of analog-digital conversion capacitors,
One end is connected to the common node, and the other end is connected to the analog input voltage node, the high level node, or the low level node.
A first switch for connecting the common node to a first voltage node;
The sign conversion circuit converts the sign of the voltage of the common node;
4. The analog-digital according to claim 1, wherein in the correction mode, the control unit controls a capacitance value of the variable capacitor for correction according to an output voltage of the latch circuit. 5. converter. In the correction mode,
The first switch connects the common node to the first voltage node, and the other ends of the plurality of analog-digital conversion capacitors are connected to the high level node or the low level node,
Thereafter, the first switch disconnects the common node from the first voltage node, and the other ends of the plurality of analog-digital conversion capacitors are connected to the low-level node or the high-level node contrary to the above. And
5. The analog-digital converter according to claim 4, wherein the control unit controls a capacitance value of the correction variable capacitor according to an output voltage of the latch circuit. In the analog-digital conversion mode,
The first switch connects the common node to the first voltage node, and the other ends of the plurality of analog-digital conversion capacitors are connected to the analog input voltage node.
Thereafter, the first switch disconnects the common node from the first voltage node, and the control unit sets the other ends of the plurality of analog-digital conversion capacitors to a high level according to an output voltage of the latch circuit. Connected to a node or a low-level node, and the connection state of the other ends of the plurality of analog-digital conversion capacitors is output as a digital value obtained by converting the analog voltage of the analog input voltage node into a digital value. The analog-digital converter according to claim 4 or 5.

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