JP2012151589A

JP2012151589A - Terminal structure of chip type electronic component

Info

Publication number: JP2012151589A
Application number: JP2011007637A
Authority: JP
Inventors: Masaaki Kametani; 雅明亀谷
Original assignee: MATSUE ELMEC CORP
Current assignee: MATSUE ELMEC CORP
Priority date: 2011-01-18
Filing date: 2011-01-18
Publication date: 2012-08-09

Abstract

PROBLEM TO BE SOLVED: To facilitate passage of an ultra-high-speed signal reaching to 20-30 GHz, in a chip type electronic component being connected with a mounting circuit pattern.SOLUTION: A signal processing circuit 17 is embedded in an electronic component body 1. Signal input terminals 3A, 3B have side surface electrodes 3AS, 3BS formed on the outer surface of the electronic component body 1, and lower surface electrodes 3AL, 3BL formed on the lower surface of the electronic component body 1 and connected with the side surface electrodes 3AS, 3BS. A signal processing circuit 17 is connected to the way of the lower surface electrodes 3AL, 3BL or the side surface electrodes 3AS, 3BS through vias 19AV, 19BV formed in the body 1.

Description

本発明はチップ型電子部品の端子構造に係り、特に、チップ部品に内蔵した信号処理回路と外部の実装基板との間で、超高速信号を劣化させることなく入出力させることが可能な端子構造の改良に関する。 The present invention relates to a terminal structure of a chip-type electronic component, and in particular, a terminal structure capable of inputting / outputting an ultrahigh-speed signal without deteriorating between a signal processing circuit built in the chip component and an external mounting board. Regarding improvements.

近年、電子機器の高速化が著しく、それに搭載される電子部品も高速化実現のための提案が求められている。 In recent years, the speed of electronic equipment has been remarkably increased, and proposals for speeding up the electronic components mounted on the electronic equipment have been demanded.

一方、最近多用される高速シリアル伝送の分野において、例えばＵＳＢ（universal serial bus）３．０規格では伝送速度が５Ｇｂｐｓであるが、次世代の規格では１０〜２０Ｇｂｐｓ程度の伝送速度が考えられている。 On the other hand, in the field of high-speed serial transmission that is frequently used recently, for example, the USB (universal serial bus) 3.0 standard has a transmission speed of 5 Gbps, but the next-generation standard has a transmission speed of about 10 to 20 Gbps. .

このような伝送速度を確保するため、伝送回路は、電子機器で使用するクロック周波数５〜１０ＧＨｚの３倍の高調波までの信号伝送が求められ、１５〜３０ＧＨｚの通過帯域を必要とする。 In order to ensure such a transmission rate, the transmission circuit is required to transmit signals up to three times higher harmonics than the clock frequency of 5 to 10 GHz used in the electronic device, and requires a pass band of 15 to 30 GHz.

さらに、ノイズ対策の観点から、伝送回路として差動信号線路が用いられるから、差動信号線路用のチップ型電子部品が求められている。 Furthermore, since a differential signal line is used as a transmission circuit from the viewpoint of noise countermeasures, a chip-type electronic component for the differential signal line is required.

この種のチップ型電子部品例えば遅延線ＤＬは、例えば図１１に示すように、遅延線素子を内蔵したチップ型の遅延線本体１の外周に、一方の差動信号を入力する信号入力端子３Ａおよび他方の差動信号を入力する信号入力端子３Ｂを形成するとともに、一方の差動信号を出力する信号出力端子５Ａおよび他方の差動信号を出力する信号出力端子５Ｂを形成して構成されている。 This type of chip-type electronic component, for example, the delay line DL, as shown in FIG. 11, for example, is a signal input terminal 3A for inputting one differential signal to the outer periphery of a chip-type delay line body 1 incorporating a delay line element. And a signal input terminal 3B for inputting the other differential signal, a signal output terminal 5A for outputting one differential signal, and a signal output terminal 5B for outputting the other differential signal. Yes.

このような遅延線ＤＬは、実装基板７に載置され、この実装基板７に形成された差動信号入力用の信号線路９Ａ、９Ｂおよび差動信号出力用の信号線路１１Ａ、１１Ｂに対し、信号入力端子３Ａ、３Ｂおよび信号出力端子５Ａ、５Ｂを例えばリフロー半田法によって接続して使用される。 Such a delay line DL is placed on the mounting substrate 7, and the differential signal input signal lines 9A and 9B and the differential signal output signal lines 11A and 11B formed on the mounting substrate 7, The signal input terminals 3A and 3B and the signal output terminals 5A and 5B are connected and used by, for example, a reflow soldering method.

なお、遅延線ＤＬには信号入出力端子３Ａ、３Ｂ、５Ａ、５Ｂ以外にグランド端子も形成され、実装基板７にもそれに接続させるグランドパッドが形成される場合が多い。 In addition to the signal input / output terminals 3A, 3B, 5A, and 5B, a ground terminal is also formed on the delay line DL, and a ground pad to be connected to the mounting board 7 is often formed.

しかし、差動信号は互いに逆相関係の２つの信号が伝搬するため、遅延線内部のグランド導体で信号が打ち消されてグランド端子へは信号が流れず、グランド端子なしでも正常に動作する。そのため、グランド端子を形成しない差動信号用遅延線も実用化されている。 However, since two differential signals propagate in opposite phases, the signal is canceled by the ground conductor inside the delay line, and the signal does not flow to the ground terminal, and operates normally without the ground terminal. Therefore, a differential signal delay line that does not form a ground terminal has been put into practical use.

さらに、本発明は、主に信号入出力端子に関する改善提案であるから、便宜上、グランド端子およびグランドパッドの具体的な図示および説明を省略する（以下同じ。）。 Furthermore, since the present invention is mainly an improvement proposal related to signal input / output terminals, for the sake of convenience, specific illustration and description of the ground terminals and the ground pads are omitted (the same applies hereinafter).

遅延線ＤＬは、図１２に示すように、例えば３枚の誘電体基板１３ａ、１３ｂ、１３ｃを積層して上述した遅延線本体１を形成するとともに、それら誘電体１３ａ、１３ｂ間に内部線路１５ａ、１５ｂを、誘電体１３ｂ、１３ｃ間に内部線路１５ａ、１５ｂと対面するグランド導体１５ｃを形成して信号処理回路としての遅延線素子１７を有している。 As shown in FIG. 12, the delay line DL forms, for example, the above-described delay line body 1 by laminating three dielectric substrates 13a, 13b, and 13c, and an internal line 15a between the dielectrics 13a and 13b. 15b is formed with a ground conductor 15c facing the internal lines 15a and 15b between the dielectrics 13b and 13c, and has a delay line element 17 as a signal processing circuit.

しかも、遅延線ＤＬは、遅延線本体１の側面に側面電極３ＡＳ、３ＢＳを、下面には側面電極３ＡＳ、３ＢＳに接続された下面電極３ＡＬ、３ＢＬを、上面には側面電極３ＡＳ、３ＢＳに接続された上面電極３ＡＵ、３ＢＵを形成し、内部線路１５ａ、１５ｂを側面電極３ＡＳ、３ＢＳの途中に接続して構成されており、例えば、下面電極３ＡＬ、３ＢＬが実装基板７の信号線路９Ａ、９Ｂに接続される。 In addition, the delay line DL is connected to the side electrodes 3AS and 3BS on the side surface of the delay line main body 1, the lower surface electrodes 3AL and 3BL connected to the side surface electrodes 3AS and 3BS on the lower surface, and the side electrodes 3AS and 3BS on the upper surface. The upper electrodes 3AU and 3BU are formed, and the internal lines 15a and 15b are connected to the side electrodes 3AS and 3BS. For example, the lower electrodes 3AL and 3BL are connected to the signal lines 9A and 9B of the mounting substrate 7, respectively. Connected to.

側面電極３ＡＳ、３ＢＳ、下面電極３ＡＬ、３ＢＬおよび上面電極３ＡＵ、３ＢＵによって上述した信号入力端子３Ａ、３Ｂが形成されており、信号出力端子５Ａ、５Ｂについても、図示はしないが同様に形成されている。 The above-described signal input terminals 3A and 3B are formed by the side electrodes 3AS and 3BS, the lower surface electrodes 3AL and 3BL, and the upper surface electrodes 3AU and 3BU. The signal output terminals 5A and 5B are also formed in the same manner although not shown. Yes.

ところで、側面電極３ＡＳ〜５ＢＳは、内部線路１５ａ、１５ｂと信号線路９Ａ〜１１Ｂとの電気的な接続のみならず、半田付け時に、半田の濡れ上がりによってフィレットを形成させ、半田付けをより確実なものとするためにも必要である。 By the way, the side electrodes 3AS to 5BS form not only electrical connection between the internal lines 15a and 15b and the signal lines 9A to 11B, but also form a fillet by solder wetting during soldering, thereby making soldering more reliable. It is also necessary to make things.

このような端子構造を有する遅延線ＤＬの特性を電磁界シミュレーションにより求めると、図１３に示すように、その差動信号通過特性がＳｄｄ２１（Ａ）、差動信号反射特性（リターンロス特性）がＳｄｄ１１（Ａ）のようになる。 When the characteristics of the delay line DL having such a terminal structure are obtained by electromagnetic field simulation, the differential signal passing characteristic is Sdd21 (A) and the differential signal reflection characteristic (return loss characteristic) is as shown in FIG. It becomes like Sdd11 (A).

すなわち、２２ＧＨｚ以上の大部分の周波数において、差動信号通過特性が−３ｄＢ以下に減衰するとともに、差動信号反射特性も−３ｄＢ以上で全反射に近くなり、２２ＧＨｚ以上の周波数では使用に適さない。 That is, at most frequencies of 22 GHz or more, the differential signal passing characteristic is attenuated to -3 dB or less, and the differential signal reflection characteristic is close to total reflection at -3 dB or more, and is not suitable for use at a frequency of 22 GHz or more. .

そして、上述した遅延線ＤＬは、電磁界シミュレーションでの電磁界分布から考えて、近似的に図１４の等価回路のように示すことが可能である。 The delay line DL described above can be approximately shown as the equivalent circuit of FIG. 14 in view of the electromagnetic field distribution in the electromagnetic field simulation.

すなわち、破線で囲った遅延線素子１７は、４端子回路として最も単純な差動マイクロストリップ線路の例で示してあり、４つの入出力端子３Ａ、３Ｂ、５Ａ、５Ｂに各々４端子インピーダンス回路Ｚｔが接続されている。４端子インピーダンス回路Ｚｔは、等価インダクタンスＬｔおよび等価キャパシタンスＣｓ、Ｃｔの梯子型回路である。 That is, the delay line element 17 surrounded by a broken line is shown as an example of the simplest differential microstrip line as a four-terminal circuit, and each of the four input / output terminals 3A, 3B, 5A, and 5B has a four-terminal impedance circuit Zt. Is connected. The 4-terminal impedance circuit Zt is a ladder circuit having an equivalent inductance Lt and equivalent capacitances Cs and Ct.

このような等価回路のマイクロストリップ線路は、遅延時間を８ｐｓ、特性インピーダンスを９５Ω、等価インダクタンスＬｔを０．５ｎＨ、等価キャパシタンスＣｓを０．０６ｐＦ、Ｃｔを０．１ｐＦとすると、その差動信号通過特性Ｓｄｄ２１（Ｂ）および差動反射特性Ｓｄｄ１１（Ｂ）が、図１３で示されるように、電磁界シミュレーションで求めたＳｄｄ２１（Ａ）およびＳｄｄ１１（Ａ）と概略一致する。 Such a microstrip line having an equivalent circuit has a delay time of 8 ps, a characteristic impedance of 95Ω, an equivalent inductance Lt of 0.5 nH, an equivalent capacitance Cs of 0.06 pF, and a Ct of 0.1 pF. The characteristic Sdd21 (B) and the differential reflection characteristic Sdd11 (B) roughly match Sdd21 (A) and Sdd11 (A) obtained by electromagnetic field simulation, as shown in FIG.

この種の従来公報として、例えば特開平６−１６４２１２号公報（特許文献１）の電子部品の端子構造のように、板状の金属端子を樹脂成型で形成したケースに収容した機能部品のアース・インピーダンスを小さくすることにより、周波数特性を改善する提案がある。 As this type of conventional publication, for example, as in the terminal structure of an electronic component disclosed in Japanese Patent Laid-Open No. 6-164212 (Patent Document 1), a functional component grounded in a case in which a plate-shaped metal terminal is formed by resin molding. There is a proposal to improve the frequency characteristics by reducing the impedance.

さらに、特開平９−２２８３１号公報（特許文献２）のように、機能電子回路を収容したチップ型電子部品の浮遊容量を小さくし、周波数特性を改善する提案もある。 Further, as disclosed in Japanese Patent Application Laid-Open No. 9-22831 (Patent Document 2), there is also a proposal for improving the frequency characteristics by reducing the stray capacitance of a chip-type electronic component containing a functional electronic circuit.

特開平６−１６４２１２号公報JP-A-6-164212 特開平９−２２８３１号公報JP-A-9-22831

しかしながら、上述した従来構成では、その寸法や誘電体基板１３ａ〜１３ｃの誘電率にもよるが、差動信号の周波数が１０〜１５ＧＨｚまでならば、実用可能な通過特性を得ることが可能であるものの、差動信号の周波数が２０ＧＨｚを超えて３０ＧＨｚにも達すると、実用可能な通過特性を得ることが困難であった。 However, in the above-described conventional configuration, depending on the dimensions and the dielectric constants of the dielectric substrates 13a to 13c, if the frequency of the differential signal is 10 to 15 GHz, it is possible to obtain a practical pass characteristic. However, when the frequency of the differential signal exceeds 20 GHz and reaches 30 GHz, it is difficult to obtain a practical pass characteristic.

上述した特許文献１、２についても同様のことがいえる。 The same can be said for Patent Documents 1 and 2 described above.

さらに、図１２に示した電極構造では、内部線路１５ａ、１５ｂと側面電極３ＡＳ、３ＢＳとの接続箇所が伝搬信号にとっての分岐点となるため、信号の一部が上面電極３ＡＵ、３ＢＵ方向へ伝搬し、上面電極３ＡＵ、３ＢＵが開放終端であるためそこで反射する。 Furthermore, in the electrode structure shown in FIG. 12, since the connection point between the internal lines 15a and 15b and the side electrodes 3AS and 3BS is a branch point for the propagation signal, a part of the signal propagates in the direction of the top electrode 3AU and 3BU. However, since the upper surface electrodes 3AU and 3BU are open ends, they are reflected there.

すなわち、側面電極３ＡＳ、３ＢＳにおける内部線路１５ａ、１５ｂより上の部分は終端開放線路であり、伝送電路上に枝のように接続された終端開放線路が終端開放スタブと呼ばれ、通過特性を劣化させる要因となる。 That is, the portions above the internal lines 15a and 15b in the side electrodes 3AS and 3BS are open-ended lines, and the open-ended line connected like a branch on the transmission line is called the open-ended stub, which deteriorates the passing characteristics. It becomes a factor to make.

しかしながら、現状のセラミック積層部品における側面電極形成は、製造コスト等の理由により、図１２に示すように下面電極３ＡＬ、３ＢＬから上面電極３ＡＵ、３ＢＵまで達する形状に仕上げる手法が主流で、無理して下面電極３ＡＬ、３ＢＬから内部線路１５ａ、１５ｂまでの高さに抑えると量産性が劣り、大幅なコストアップにつながる。 However, the formation of side electrodes in the current ceramic laminated parts is mainly done by a method of finishing from the bottom electrodes 3AL and 3BL to the top electrodes 3AU and 3BU as shown in FIG. Suppressing the height from the bottom electrodes 3AL, 3BL to the internal lines 15a, 15b results in poor mass productivity and a significant cost increase.

従って、現状では、図１２の構成で、内部線路１５ａ、１５ｂの形成面高さを最適化することが重要であり、内部線路１５ａ、１５ｂの形成面を上面電極３ＡＵ、３ＢＵに近づけると、側面電極３ＡＳ、３ＢＳは終端開放スタブとして機能し難くなる。 Therefore, at present, it is important to optimize the formation surface height of the internal lines 15a and 15b in the configuration of FIG. 12, and when the formation surface of the internal lines 15a and 15b is brought close to the upper surface electrodes 3AU and 3BU, It becomes difficult for the electrodes 3AS and 3BS to function as a terminal open stub.

一方、下面電極３ＡＬ、３ＢＬから内部線路１５ａ、１５ｂまでの距離が長くなるので、図１４における等価インダクタンスＬｔが増加し、通過特性の劣化を引き起こす。 On the other hand, since the distance from the bottom electrodes 3AL and 3BL to the internal lines 15a and 15b is increased, the equivalent inductance Lt in FIG. 14 is increased, and the pass characteristics are deteriorated.

逆に、内部線路１５ａ、１５ｂの形成面を下面電極３ＡＬ、３ＢＬに近づけると、等価インダクタンスＬｔは減少する一方、側面電極３ＡＳ、３ＢＳが終端開放スタブとして機能し易くなるため、内部線路１５ａ、１５ｂの形成面高さの最適化は容易ではない。 On the contrary, when the formation surface of the internal lines 15a and 15b is brought close to the lower surface electrodes 3AL and 3BL, the equivalent inductance Lt decreases, but the side electrodes 3AS and 3BS easily function as an open termination stub. It is not easy to optimize the height of the formation surface.

本発明はそのような課題を解決するためになされたもので、実装回路パターンに接続するチップ型電子部品において、２０ＧＨｚ〜３０ＧＨｚまでの超高速差動信号を低損失で通過させ易くしたチップ型電子部品の端子構造の提供を目的とする。 The present invention has been made to solve such a problem, and in a chip-type electronic component connected to a mounting circuit pattern, an ultrahigh-speed differential signal from 20 GHz to 30 GHz is easily passed with low loss. The purpose is to provide a terminal structure for parts.

そのような課題を解決するために本発明の請求項１に係るチップ型電子部品の端子構造は、信号を処理する信号処理回路が内部に埋設されたチップ型電子部品本体と、このチップ型電子部品本体の外部側面に形成された側面電極と、このチップ型電子部品本体の下面に形成されその側面電極が接続されるとともに外部の実装基板パターンに接続される下面電極と、そのチップ型電子部品本体の内部に形成されるとともにその下面電極方向へ伸び、その下面電極、又はその下面電極とその信号処理回路の形成面との間における側面電極の途中に接続されるビアとを具備している。 In order to solve such a problem, a terminal structure of a chip-type electronic component according to claim 1 of the present invention includes a chip-type electronic component main body in which a signal processing circuit for processing a signal is embedded, and the chip-type electronic component. Side electrode formed on the outer side surface of the component main body, lower surface electrode formed on the lower surface of the chip-type electronic component main body to which the side electrode is connected and connected to the external mounting board pattern, and the chip-type electronic component It is formed inside the main body and extends in the direction of the lower surface electrode, and includes a lower surface electrode or a via connected in the middle of the side surface electrode between the lower surface electrode and the formation surface of the signal processing circuit. .

本発明の請求項２に係るチップ型電子部品の端子構造は、上記ビアが、下面電極と信号処理回路の形成面との間において、前記側面電極の途中に１箇所以上接続された構成である。 The terminal structure of the chip-type electronic component according to claim 2 of the present invention is configured such that the via is connected to one or more places in the middle of the side electrode between the lower surface electrode and the formation surface of the signal processing circuit. .

本発明の請求項３に係るチップ型電子部品の端子構造は、上記信号処理回路の上記下面電極からの高さを、そのチップ型電子部品本体の高さの１／２以下とした構成である。 The terminal structure of the chip-type electronic component according to claim 3 of the present invention is configured such that the height of the signal processing circuit from the bottom electrode is ½ or less of the height of the chip-type electronic component main body. .

本発明の請求項４に係るチップ型電子部品の端子構造は、上記ビアが、そのチップ型電子部品本体の上面に形成され側面電極が接続される上面電極方向に延び、その上面電極、又はそれら上面電極と信号処理回路の形成面との間における側面電極の途中に接続された構成である。 In the terminal structure of the chip type electronic component according to claim 4 of the present invention, the via is formed on the upper surface of the chip type electronic component main body and extends in the direction of the upper surface electrode to which the side surface electrode is connected. It is the structure connected in the middle of the side electrode between the upper surface electrode and the formation surface of the signal processing circuit.

本発明の請求項５に係るチップ型電子部品の端子構造は、上記ビアが、上面電極と信号処理回路の形成面との間において、側面電極の途中に１箇所以上接続された構成である。 The terminal structure of the chip-type electronic component according to claim 5 of the present invention is configured such that the via is connected to one or more places in the middle of the side electrode between the upper surface electrode and the signal processing circuit formation surface.

本発明の請求項６に係るチップ型電子部品の端子構造は、上記ビアが、その下面電極又は上面電極との接続部分以外がこれより大径に形成されてなる構成である。 A terminal structure of a chip-type electronic component according to a sixth aspect of the present invention is a structure in which the via is formed with a diameter larger than that of a portion other than a connection portion with the lower surface electrode or the upper surface electrode.

本発明の請求項７に係るチップ型電子部品の端子構造は、上記ビアが、僅かな間隔をおいて並列形成された複数本のものからなる構成である。 According to a seventh aspect of the present invention, there is provided a terminal structure for a chip-type electronic component comprising a plurality of vias formed in parallel with a small gap therebetween.

このような本発明の請求項１に係るチップ型電子部品の端子構造では、信号処理回路が内部に埋設されたチップ型電子部品本体の外部側面に側面電極を、このチップ型電子部品本体の下面にはその側面電極が接続されるとともに外部の実装基板パターンに接続される下面電極を形成し、そのチップ型電子部品本体の内部には、その信号処理回路に接続されるとともにその下面電極間方向へ延び、その下面電極、又はその下面電極とその信号処理回路の形成面との間における側面電極の途中に接続されるビアを形成したから、超高速差動信号が上記ビアを経由する最短経路で実装基板パターンと信号処理回路との間を流れ、実装回路パターンとチップ型電子部品との間において、２０ＧＨｚ〜３０ＧＨｚに達する超高速差動信号を低損失で通過させ易い。 In such a terminal structure of a chip type electronic component according to claim 1 of the present invention, the side electrode is provided on the outer side surface of the chip type electronic component body in which the signal processing circuit is embedded, and the lower surface of the chip type electronic component body. The side electrode is connected to the external mounting substrate pattern and the bottom electrode is connected to the external mounting substrate pattern. The chip-type electronic component main body is connected to the signal processing circuit and the direction between the bottom electrodes A via that is connected to the lower surface electrode or the side surface electrode between the lower surface electrode and the formation surface of the signal processing circuit, so that the ultrahigh-speed differential signal passes through the via. Flows between the mounting board pattern and the signal processing circuit, and passes an ultrahigh-speed differential signal reaching 20-30 GHz with low loss between the mounting circuit pattern and the chip-type electronic component. Easy to.

本発明の請求項２に係るチップ型電子部品の端子構造では、上記ビアが、上記側面電極の途中に１箇所以上接続された構成であるから、上記ビアと上記側面電極の並列回路を形成することでそれらのインダクタンスを小さく抑えることができ、良好な特性が得られる。 In the terminal structure of the chip-type electronic component according to claim 2 of the present invention, since the via is connected to one or more places in the middle of the side electrode, a parallel circuit of the via and the side electrode is formed. Therefore, those inductances can be kept small, and good characteristics can be obtained.

本発明の請求項３に係るチップ型電子部品の端子構造では、上記信号処理回路の上記下面電極からの高さが、そのチップ型電子部品本体の高さの１／２以下となる構成であるから、上記ビアの全長が短くなってインダクタンスを小さく抑えることが可能で、良好な特性が得られる。 In the terminal structure of the chip type electronic component according to claim 3 of the present invention, the height of the signal processing circuit from the lower surface electrode is ½ or less of the height of the chip type electronic component main body. Therefore, the overall length of the via is shortened, and the inductance can be kept small, and good characteristics can be obtained.

本発明の請求項４に係るチップ型電子部品の端子構造では、上記ビアが、側面電極に接続された上面電極方向へも延び、その上面電極、又は上面電極と信号処理回路の形成面との間における側面電極の途中に接続された構成であるから、チップ型電子部品の上面と下面を入れ替えて実装しても特性に差が生じ難く、マーキングやテーピングの方向性を省略して製造コストや実装コストを削減することが可能である。 In the terminal structure of the chip-type electronic component according to claim 4 of the present invention, the via also extends in the direction of the upper surface electrode connected to the side electrode, and the upper surface electrode or the upper surface electrode and the formation surface of the signal processing circuit Since the structure is connected in the middle of the side electrodes, the difference in characteristics is not likely to occur even if the upper and lower surfaces of the chip-type electronic component are replaced, and the manufacturing cost and the directionality of marking and taping are omitted. Mounting costs can be reduced.

本発明の請求項５に係るチップ型電子部品の端子構造では、上記ビアが、上面電極と信号処理回路の形成面との間における側面電極の途中に１箇所以上接続された構成であるから、それらビアと側面電極の並列回路を形成することでそれらのインダクタンスを小さく抑えることが容易で、良好な特性が得られる。 In the terminal structure of the chip-type electronic component according to claim 5 of the present invention, since the via is connected to one or more places in the middle of the side electrode between the upper surface electrode and the formation surface of the signal processing circuit, By forming a parallel circuit of these vias and side electrodes, it is easy to keep their inductance small, and good characteristics can be obtained.

本発明の請求項６に係るチップ型電子部品の端子構造では、上記ビアが、その下面電極又は上面電極との接続部分以外がこれより大径に形成されているから、形状の大型化を抑えつつビア部分の導体インダクタンスを小さくすることが可能で、良好な特性の維持が可能である。 In the terminal structure of the chip-type electronic component according to claim 6 of the present invention, since the via is formed with a diameter larger than that of the lower surface electrode or the connection portion with the upper surface electrode, the increase in shape is suppressed. However, it is possible to reduce the conductor inductance of the via portion and maintain good characteristics.

本発明の請求項７に係るチップ型電子部品の端子構造では、上記ビアが、僅かな間隔をおいて並列形成された複数本のものからなるから、等価的に大径のビアと同等の特性となり、ビアを加工形成するうえで大径のビア形成が困難な場合でも、所望の特性を得やすい。 In the terminal structure of the chip type electronic component according to claim 7 of the present invention, since the via is composed of a plurality of vias formed in parallel at a slight interval, it has the same characteristics as the large-diameter via. Therefore, even when it is difficult to form a large-diameter via in forming a via, desired characteristics are easily obtained.

本発明に係るチップ型電子部品の端子構造の実施の形態を示す断面図（図２中のＸ−Ｘ’間断面）である。It is sectional drawing (cross section between X-X 'in FIG. 2) which shows embodiment of the terminal structure of the chip-type electronic component which concerns on this invention. 図１のチップ型電子部品の端子構造に係る分解斜視図である。It is a disassembled perspective view which concerns on the terminal structure of the chip-type electronic component of FIG. 図１のチップ型電子部品の端子構造に係る要部斜視図である。It is a principal part perspective view which concerns on the terminal structure of the chip-type electronic component of FIG. 図１に示すチップ型電子部品の差動信号に対する通過特性図である。FIG. 2 is a pass characteristic diagram for a differential signal of the chip-type electronic component shown in FIG. 本発明に係るチップ型電子部品の端子構造を適用した別の実施の形態を示す要部斜視図である。It is a principal part perspective view which shows another embodiment to which the terminal structure of the chip-type electronic component which concerns on this invention is applied. 本発明に係るチップ型電子部品の端子構造を適用した別の実施の形態を示す断面図である。It is sectional drawing which shows another embodiment to which the terminal structure of the chip-type electronic component which concerns on this invention is applied. 図６のチップ型電子部品の端子構造に係る要部斜視図である。It is a principal part perspective view which concerns on the terminal structure of the chip-type electronic component of FIG. 本発明に係るチップ型電子部品の端子構造を適用した別の例の実施の形態を示す断面図である。It is sectional drawing which shows embodiment of another example to which the terminal structure of the chip-type electronic component which concerns on this invention is applied. 図８のチップ型電子部品の端子構造に係る要部斜視図である。It is a principal part perspective view which concerns on the terminal structure of the chip-type electronic component of FIG. 本発明に係るチップ型電子部品の端子構造を適用した別の実施の形態を示す要部斜視図である。It is a principal part perspective view which shows another embodiment to which the terminal structure of the chip-type electronic component which concerns on this invention is applied. 従来のチップ型電子部品とそれを搭載する実装基板との関係を示す分解斜視図である。It is a disassembled perspective view which shows the relationship between the conventional chip-type electronic component and the mounting substrate which mounts it. 従来のチップ型電子部品の内部構成を示す断面図である。It is sectional drawing which shows the internal structure of the conventional chip-type electronic component. 図１２に示すチップ型電子部品および図１４の等価回路が示す差動信号に対する通過特性図および反射特性図である。FIG. 15 is a transmission characteristic diagram and a reflection characteristic diagram for the differential signal shown by the chip-type electronic component shown in FIG. 図１２に示すチップ型電子部品の信号端子を近似的に表現した等価回路である。13 is an equivalent circuit that approximately represents signal terminals of the chip-type electronic component shown in FIG.

以下、本発明に係るチップ型電子部品の端子構造の実施の形態を図面を参照して説明する。なお、従来例と共通する部分には同一の符号を付す。 Embodiments of a terminal structure of a chip type electronic component according to the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the part which is common in a prior art example.

図１および図２は本発明に係るチップ型電子部品の端子構造の実施の形態を示す断面図および分解斜視図である。 1 and 2 are a sectional view and an exploded perspective view showing an embodiment of a terminal structure of a chip-type electronic component according to the present invention.

図１および図２において、遅延線本体１は、例えば４枚の薄い方形の誘電体基板１３ａ、１３ｂ、１３ｃ、１３ｄを積層一体化してチップ型に形成されている。 1 and 2, the delay line main body 1 is formed in a chip shape by, for example, laminating and integrating four thin rectangular dielectric substrates 13a, 13b, 13c, and 13d.

それら誘電体１３ａ、１３ｂ間には内部線路１５ａ、１５ｂが、誘電体１３ｂ、１３ｃ間には内部線路１５ａ、１５ｂと対面するグランド導体１５ｃが形成され、信号処理回路としての遅延線素子１７が遅延線本体１内に形成されている。内部線路１５ａ、１５ｂおよびグランド線路１５ｃの詳細は後述する。 The internal lines 15a and 15b are formed between the dielectrics 13a and 13b, and the ground conductor 15c facing the internal lines 15a and 15b is formed between the dielectrics 13b and 13c. The delay line element 17 as a signal processing circuit is delayed. It is formed in the wire body 1. Details of the internal lines 15a and 15b and the ground line 15c will be described later.

遅延線本体１の外周には、図１では図示しない実装基板７（図１１参照）に接続される信号入力端子３Ａ、３Ｂおよび信号出力端子５Ａ、５Ｂ（図１では図示せず。）が形成されている。 On the outer periphery of the delay line body 1, signal input terminals 3A and 3B and signal output terminals 5A and 5B (not shown in FIG. 1) connected to a mounting substrate 7 (see FIG. 11) not shown in FIG. 1 are formed. Has been.

信号入力端子３Ａ、３Ｂは、側面電極３ＡＳ、３ＢＳ、下面電極３ＡＬ、３ＢＬおよび上面電極３ＡＵ、３ＢＵを有して形成されている（図３参照）。 The signal input terminals 3A and 3B have side electrodes 3AS and 3BS, lower surface electrodes 3AL and 3BL, and upper surface electrodes 3AU and 3BU (see FIG. 3).

側面電極３ＡＳ、３ＢＳは、遅延線本体１にあって対向する両側面の一方の端部において、上下（誘電体基板１３ａ〜１３ｄの厚み）方向に延びる一対の帯状に形成されている。 The side electrodes 3AS and 3BS are formed in a pair of strips extending in the vertical direction (thickness of the dielectric substrates 13a to 13d) at one end of both opposing side faces in the delay line main body 1.

下面電極３ＡＬ、３ＢＬは、遅延線本体１（誘電体基板１３ｄ）の下面において、この縁部に側面電極３ＡＳ、３ＢＳに寄せて形成され、側面電極３ＡＳ、３ＢＳに接続されている。 The lower surface electrodes 3AL and 3BL are formed on the lower surface of the delay line main body 1 (dielectric substrate 13d) so as to be close to the side surface electrodes 3AS and 3BS, and are connected to the side surface electrodes 3AS and 3BS.

上面電極３ＡＵ、３ＢＵは、遅延線本体１（誘電体基板１３ａ）の上面において、この縁部に側面電極３ＡＳ、３ＢＳに寄せて形成され、側面電極３ＡＳ、３ＢＳに接続されている。 The upper surface electrodes 3AU and 3BU are formed on the upper surface of the delay line main body 1 (dielectric substrate 13a) at the edge thereof so as to approach the side surface electrodes 3AS and 3BS, and are connected to the side surface electrodes 3AS and 3BS.

信号出力端子５Ａ、５Ｂは、図２および図３に示すように、側面電極５ＡＳ、５ＢＳ、下面電極５ＡＬ、５ＢＬおよび上面電極５ＡＵ、５ＢＵを有している。 As shown in FIGS. 2 and 3, the signal output terminals 5A and 5B have side electrodes 5AS and 5BS, bottom electrodes 5AL and 5BL, and top electrodes 5AU and 5BU.

側面電極５ＡＳ、５ＢＳは、遅延線本体１の対向側面の他方の端部において、上下（誘電体基板１３ａ〜１３ｄの厚み）方向に一対の帯状に形成されている。 The side electrodes 5AS and 5BS are formed in a pair of strips in the vertical direction (thickness of the dielectric substrates 13a to 13d) at the other end of the opposing side surface of the delay line body 1.

下面電極５ＡＬ、５ＢＬは、遅延線本体１（誘電体基板１３ｄ）の下面において、この縁部に側面電極５ＡＳ、５ＢＳに寄せて形成され、側面電極５ＡＳ、５ＢＳに接続されている。 The lower surface electrodes 5AL and 5BL are formed on the lower surface of the delay line main body 1 (dielectric substrate 13d) at the edge thereof so as to approach the side surface electrodes 5AS and 5BS, and are connected to the side surface electrodes 5AS and 5BS.

上面電極５ＡＵ、５ＢＵは、遅延線本体１（誘電体基板１３ａ）の上面において、この縁部に側面電極５ＡＳ、５ＢＳに寄せて形成され、側面電極５ＡＳ、５ＢＳに接続されている。 The upper surface electrodes 5AU and 5BU are formed on the edge of the upper surface of the delay line body 1 (dielectric substrate 13a) so as to approach the side surface electrodes 5AS and 5BS, and are connected to the side surface electrodes 5AS and 5BS.

側面電極３ＡＳ、３ＢＳおよび側面電極５ＡＳ、５ＢＳは、誘電体基板１３ａ〜１３ｄの端面に個別に形成され、図３に示すように、それらが連結一体化されており、下面電極３ＡＬ、３ＢＬ、５ＡＬ、５ＢＬが上述した図１１の実装基板７の信号線路９Ａ、９Ｂ、１１Ａ、１１Ｂに接続される。 The side electrodes 3AS, 3BS and the side electrodes 5AS, 5BS are individually formed on the end surfaces of the dielectric substrates 13a to 13d, and are connected and integrated as shown in FIG. 5BL is connected to the signal lines 9A, 9B, 11A, and 11B of the mounting substrate 7 of FIG. 11 described above.

なお、図２において、下面電極３ＡＬ、３ＢＬ、５ＡＬ、５ＢＬは、便宜上、誘電体基板１３ｄから分離して図示されている。 In FIG. 2, the lower surface electrodes 3AL, 3BL, 5AL, and 5BL are illustrated separately from the dielectric substrate 13d for convenience.

内部線路１５ａ、１５ｂは、図２に示すように、誘電体１３ｂ上の中央部において後述するビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶ間に、側面電極３ＡＳ（３ＢＳ）と５ＡＳ（５ＢＳ）間方向に延び、互いに僅かな間隔で平行形成されるとともに、各々の両端部が屈曲形成されてビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶに接続されている。 As shown in FIG. 2, the internal lines 15a and 15b extend in the direction between the side electrodes 3AS (3BS) and 5AS (5BS) between vias 19AV, 19BV, 21AV, and 21BV, which will be described later, at the center on the dielectric 13b. In addition to being formed in parallel with each other at a slight interval, both end portions thereof are bent and connected to the vias 19AV, 19BV, 21AV, and 21BV.

グランド導体１５ｃは、誘電体１３ｃ上の中央部にあってビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶ間にて、内部線路１５ａ、１５ｂと対面するよう幅広形状で、側面電極３ＡＳ（３ＢＳ）と５ＡＳ（５ＢＳ）間方向に形成されている。 The ground conductor 15c is in the center on the dielectric 13c and has a wide shape so as to face the internal lines 15a and 15b between the vias 19AV, 19BV, 21AV, and 21BV, and the side electrodes 3AS (3BS) and 5AS (5BS). ) Is formed in the inter-direction.

図１に戻って、遅延線本体１（誘電体基板１３ａ〜１３ｄ）内には、左右の側面電極３ＡＳ、３ＢＳから僅かな間隔ｇだけ内部に寄った位置に、下面電極３ＡＬ、３ＢＬから内部線路１５ａ、１５ｂの形成面までの高（厚み）で延びる導電性のビア１９ＡＶ、１９ＢＶが、１端子当り１本ずつ側面電極３ＡＳ、３ＢＳと並行に形成されている。 Returning to FIG. 1, in the delay line main body 1 (dielectric substrates 13a to 13d), the internal lines from the bottom electrodes 3AL and 3BL are located at a position slightly inward from the left and right side electrodes 3AS and 3BS. Conductive vias 19AV and 19BV extending to a height (thickness) up to the formation surface of 15a and 15b are formed in parallel with the side electrodes 3AS and 3BS, one for each terminal.

内部線路１５ａ、１５ｂは、誘電体基板１３ｂ上面すなわちその形成面において、ビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶの各々上端に接続されている。 The internal lines 15a and 15b are connected to the upper ends of the vias 19AV, 19BV, 21AV, and 21BV on the top surface of the dielectric substrate 13b, that is, the formation surface thereof.

左右の側面電極５ＡＳ、５ＢＳに対しても、図２に示すように、ビア２１ＡＶ、２１ＢＶが並行に形成され、誘電体基板１３ｂ上面すなわちその形成面において、内部線路１５ａ、１５ｂの出力側がビア２１ＡＶ、２１ＢＶの上端にそれぞれ接続されている。 As shown in FIG. 2, vias 21AV and 21BV are also formed in parallel to the left and right side electrodes 5AS and 5BS. On the upper surface of the dielectric substrate 13b, that is, the formation surface thereof, the output side of the internal lines 15a and 15b is the via 21AV. , 21BV are respectively connected to the upper ends.

ビア１９ＡＶ、１９ＢＶは、図１および図３に示すように、各々の下部すなわち下面電極３ＡＬ、３ＢＬの近傍では細い小径部１９ＡＶＮ、１９ＢＶＮを有し、下面電極３ＡＬ、３ＢＬからはみ出さないようになっており、その他の大部分が大径に形成されている。 As shown in FIGS. 1 and 3, the vias 19AV and 19BV have thin small-diameter portions 19AVN and 19BVN near the lower portions, that is, the lower surface electrodes 3AL and 3BL, and do not protrude from the lower surface electrodes 3AL and 3BL. Most of the others are formed in large diameters.

ビア２１ＡＶ、２１ＢＶについても、同様に小径部２１ＡＶＮ、２１ＢＶＮが形成されている。 Similarly, the small diameter portions 21AVN and 21BVN are formed in the vias 21AV and 21BV.

このような図１に係るチップ型電子部品の端子構造では、外部からの差動信号が、下面電極３ＡＬ（３ＢＬ）からビア１９ＡＶ（１９ＢＶ）を経由して最短距離で内部線路１５ａ、１５ｂに到達する。 In such a terminal structure of the chip-type electronic component according to FIG. 1, an external differential signal reaches the internal lines 15a and 15b from the bottom electrode 3AL (3BL) via the via 19AV (19BV) at the shortest distance. To do.

信号出力端子５Ａ、５Ｂについても、信号が出力される違いはあるが、動作的には信号入力端子３Ａ、３Ｂと同様である。 The signal output terminals 5A and 5B are also similar in operation to the signal input terminals 3A and 3B, although there is a difference that signals are output.

本発明者は、このような図１に係るチップ型電子部品の端子構造に関し、次のような実例において電磁界シミュレーションによる解析を行った。 The inventor has analyzed the terminal structure of the chip-type electronic component according to FIG. 1 by electromagnetic field simulation in the following example.

すなわち、上述した図１１と同様に、遅延線ＤＬの外径寸法を長さ２ｍｍ、幅１．２ｍｍ、高さ０．７３ｍｍとし、遅延線本体１の外周には、幅０．３ｍｍ、厚さ０．０２５ｍｍの側面電極３ＡＳ、３ＢＳ、５ＡＳ、５ＢＳを形成した。 That is, as in FIG. 11 described above, the outer diameter of the delay line DL is 2 mm in length, 1.2 mm in width, and 0.73 mm in height, and the outer periphery of the delay line main body 1 has a width of 0.3 mm and a thickness. 0.025 mm side electrodes 3AS, 3BS, 5AS, 5BS were formed.

さらに、本発明の説明を明確にするため、遅延線ＤＬを単なる伝搬時間２０ｐｓの差動マイクロストリップ線路と考え、誘電体基板１３ａ〜１３ｅの誘電率を４．６、ビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶの径を０．１６ｍｍ、小径部１９ＡＶＮ、１９ＢＶＮ、２１ＡＶＮ、２１ＢＶＮの径および高さをそれぞれ０．０８ｍｍと０．１ｍｍ、間隔ｇを０．０５ｍｍとし、遅延線本体１の高さをｔ、下面電極３ＡＬ、３ＢＬ、５ＡＬ、５ＢＬから内部線路１５Ａ、１５Ｂまでの高さをｈとした構成において、高さｔとｈの比「ｈ／ｔ」が「０．２５」、「０．５」および「０．７５」の３つの場合について解析した。 Further, in order to clarify the explanation of the present invention, the delay line DL is considered as a differential microstrip line having a simple propagation time of 20 ps, and the dielectric constants of the dielectric substrates 13a to 13e are 4.6, vias 19AV, 19BV, 21AV, The diameter of 21BV is 0.16 mm, the diameters and heights of the small diameter portions 19AVN, 19BVN, 21AVN, and 21BVN are 0.08 mm and 0.1 mm, respectively, the interval g is 0.05 mm, the height of the delay line body 1 is t, In the configuration in which the height from the bottom electrode 3AL, 3BL, 5AL, 5BL to the internal lines 15A, 15B is h, the ratio “h / t” between the heights t and h is “0.25”, “0.5”. And three cases of “0.75” were analyzed.

その解析結果として、図４のＳｄｄ２１ｎｅｗ(１)〜（３）に示す通過特性が得られた。ここで
Ｓｄｄ２１ｎｅｗ(１)：ｈ／ｔ＝０．７５
Ｓｄｄ２１ｎｅｗ(２)：ｈ／ｔ＝０．５
Ｓｄｄ２１ｎｅｗ(３)：ｈ／ｔ＝０．２５
であり、図４のＳｄｄ２１ｏｌｄは、図１１に示した従来構成において高さｔとｈの比「ｈ／ｔ」を「０．５」とした場合に相当する。 As a result of the analysis, pass characteristics shown in Sdd21new (1) to (3) in FIG. 4 were obtained. Here, Sdd21new (1): h / t = 0.75
Sdd21new (2): h / t = 0.5
Sdd21new (3): h / t = 0.25
4 corresponds to the case where the ratio “h / t” between the heights t and h is “0.5” in the conventional configuration shown in FIG. 11.

従来例の通過特性Ｓｄｄ２１ｏｌｄでは、図４から明らかなように、１５ＧＨｚから特性が下降し始め、３８ＧＨｚで再びピークとなる波状特性を示す。 As apparent from FIG. 4, the pass characteristic Sdd21old of the conventional example shows a wave-like characteristic that starts to decrease from 15 GHz and peaks again at 38 GHz.

これに対して、本発明に係る遅延線ＤＬは、従来例と同じｈ／ｔ＝０．５の条件で比較すると、２３ＧＨｚ付近から下降が始まり、次のピークは４０ＧＨｚを超えており、大幅に通過特性が向上している。 On the other hand, the delay line DL according to the present invention starts to decrease from around 23 GHz when compared under the same h / t = 0.5 condition as the conventional example, and the next peak exceeds 40 GHz. The passing characteristics are improved.

このように通過特性が向上した理由は、磁界強度分布を基に考察すれば、高周波信号の大部分の成分が、ビア１９ＡＶ、１９ＢＶを経由した最短経路で下面電極３ＡＬ、３ＢＬから信号線路１５ａ、１５ｂへ流れ、同様にビア２１ＡＶ、２１ＢＶを経由した最短経路で信号線路１５ａ、１５ｂから下面電極５ＡＬ、５ＢＬへ流れることにより、図１４の等価回路における入出力経路の等価端子インダクタンスＬｔが減少したためであることが分かる。 The reason why the pass characteristic is improved in this way is that, based on the magnetic field strength distribution, most components of the high-frequency signal are transmitted from the bottom electrodes 3AL, 3BL to the signal line 15a, via the shortest path via the vias 19AV, 19BV. This is because the equivalent terminal inductance Lt of the input / output path in the equivalent circuit of FIG. 14 is reduced by flowing from the signal lines 15a and 15b to the lower surface electrodes 5AL and 5BL through the shortest path via the vias 21AV and 21BV. I understand that there is.

すなわち、信号入力端子３Ａ、３Ｂ側について説明を付け加えると、下面電極３ＡＬ、３ＢＬの近傍には、入力した高周波信号によって形成される磁界が分布する。 That is, when the signal input terminals 3A and 3B are described further, the magnetic field formed by the input high-frequency signal is distributed in the vicinity of the lower surface electrodes 3AL and 3BL.

その磁界の強度は、下面電極３ＡＬ、３ＢＬから高さ方向に離れるにつれ小さくなり、代わってビア１９ＡＶ、１９ＢＶにあって対面する互いの内側に磁束が多く現れるようになる。 The strength of the magnetic field decreases as the height of the magnetic field increases from the lower surface electrodes 3AL and 3BL, and a large amount of magnetic flux appears on the insides of the vias 19AV and 19BV instead facing each other.

高周波電流（図示せず）は、金属の表面の磁界に覆われた部分に集中して流れるので、下面電極３ＡＬ、３ＢＬに入力された高周波電流は、磁界に覆われた小径部１９ＡＶＮ、１９ＢＶＮの表面を経由してビア１９ＡＶ、１９ＢＶに達し、ビア１９ＡＶ、１９ＢＶ表面をそれらの対向する内側に向かって斜めに流れる。これにより、高周波電流が信号線路１５ａ、１５ｂへ最短距離で流れる。 Since the high frequency current (not shown) concentrates on the portion of the metal surface covered with the magnetic field, the high frequency current input to the lower surface electrodes 3AL and 3BL is applied to the small diameter portions 19AVN and 19BVN covered with the magnetic field. The vias 19AV and 19BV are reached via the surface, and flow obliquely through the surfaces of the vias 19AV and 19BV toward the opposite sides thereof. Thereby, the high frequency current flows to the signal lines 15a and 15b at the shortest distance.

そして、側面電極３ＡＳ、３ＢＳは、下面電極３ＡＬ、３ＢＬから見て終端開放線路であるが、側面電極３ＡＳ、３ＢＳ表面を覆う磁界が下面電極３ＡＬ、３ＢＬのごく近傍に限定され、側面電極３ＡＳ、３ＢＳを流れる高周波電流が極めて少ないから、これら側面電極３ＡＳ、３ＢＳが終端開放スタブとして機能し難い。 The side electrodes 3AS, 3BS are open termination lines as viewed from the bottom electrodes 3AL, 3BL, but the magnetic field covering the surface of the side electrodes 3AS, 3BS is limited to the very vicinity of the bottom electrodes 3AL, 3BL, and the side electrodes 3AS, 3BL, Since the high-frequency current flowing through 3BS is extremely small, these side electrodes 3AS and 3BS are unlikely to function as a terminal open stub.

信号出力端子５Ａ，５Ｂ側については説明を省略するが、信号入力端子３Ａ，３Ｂ側と同様である。 Although the description of the signal output terminals 5A and 5B is omitted, it is the same as the signal input terminals 3A and 3B.

一方、上述した図１２の従来例では、高周波電流が側面電極３ＡＳ、３ＢＳを経由するため、図１に比べ伝送経路が長く、側面電極３ＡＳ、３ＢＳのインダクタ成分が大きくなり、図１３に示す４端子インピーダンス回路Ｚｔの遮断周波数を下げ易い。 On the other hand, in the conventional example of FIG. 12 described above, since the high-frequency current passes through the side electrodes 3AS and 3BS, the transmission path is longer than that in FIG. 1, and the inductor components of the side electrodes 3AS and 3BS are large. It is easy to lower the cutoff frequency of the terminal impedance circuit Zt.

さらに、図示はしないが、内部線路１５ａと側面電極３ＡＳとの交点および内部線路１５ｂと側面電極３ＢＳとの交点において磁界が強く、しかも、磁界はこれら交点の上下に均等に分布するため、高周波電流がこれら側面電極３ＡＳ、３ＢＳ表面上を内部線路１５ａ、１５ｂより上の領域まで流れる。 Further, although not shown in the drawing, the magnetic field is strong at the intersection of the internal line 15a and the side electrode 3AS and the intersection of the internal line 15b and the side electrode 3BS, and the magnetic field is evenly distributed above and below these intersections. Flows on the surface of these side electrodes 3AS and 3BS to the region above the internal lines 15a and 15b.

しかしながら、側面電極３ＡＳ、３ＢＳの内部線路１５ａ、１５ｂより上の領域は、何も接続されない終端開放線路と等価のため、側面電極３ＡＳ、３ＢＳが終端開放スタブとなり、多重反射や共振を起こして周波数特性を劣化させ易い。 However, since the regions above the internal lines 15a and 15b of the side electrodes 3AS and 3BS are equivalent to the open termination line to which nothing is connected, the side electrodes 3AS and 3BS become open termination stubs, causing multiple reflections and resonances. It is easy to deteriorate the characteristics.

以上のような理由で、図１に示す構成は、図１２の構成に比べ、通過特性Ｓｄｄ２１が改善される。もっとも、図１の構成においても、ｈ／ｔ＝０．７５の場合では、ｈ／ｔが０．２５と、０．５の場合に比べて特性が悪くなる。 For the reasons described above, the configuration shown in FIG. 1 improves the pass characteristic Sdd21 compared to the configuration shown in FIG. However, even in the configuration of FIG. 1, when h / t = 0.75, the characteristics are worse than when h / t is 0.25, which is 0.5.

その理由は、図３において、ビア１９ＡＶ、１９ＢＶの長さが長くなると、下面電極３ＡＬ、３ＢＬの上部の磁界が、間隔ｇの幅でより高い範囲まで分布するようになり（図示せず）、高周波電流が側面電極３ＡＳ、３ＢＳ表面を上側に向かって流れ、側面電極３ＡＳ、３ＢＳが終端開放スタブとなって特性を劣化させるから、と考えられる。 The reason for this is that in FIG. 3, when the length of the vias 19AV and 19BV is increased, the magnetic field above the lower surface electrodes 3AL and 3BL is distributed to a higher range with the width of the gap g (not shown). It is considered that the high frequency current flows upward on the surface of the side electrodes 3AS and 3BS, and the side electrodes 3AS and 3BS become terminal open stubs to deteriorate the characteristics.

従って、ｈ／ｔが可能な限り小さくなるよう設計することが望ましい。 Therefore, it is desirable to design so that h / t is as small as possible.

もっとも、設計の段階でｈ／ｔ＞０．５となっても、ビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶを、上面電極３ＡＵ、３ＢＵ、５ＡＵ、５ＢＵに接続し直して、上面電極方向にのみ延ばす構成にした後、上面と下面を入れ替えれば、ｈ／ｔ＜０．５の条件を満たすことが可能である。 However, even if h / t> 0.5 at the design stage, the vias 19AV, 19BV, 21AV, and 21BV are reconnected to the upper surface electrodes 3AU, 3BU, 5AU, and 5BU, and extend only in the direction of the upper surface electrode. Then, if the upper surface and the lower surface are switched, the condition of h / t <0.5 can be satisfied.

このようにすれば、ｈ／ｔ＞０．５となるケースは、実質的に起こり難くすることが可能で、良好な特性を得るための条件をｈ／ｔ≦０．５とすることが可能である。 In this way, the case where h / t> 0.5 can be substantially prevented, and the condition for obtaining good characteristics can be h / t ≦ 0.5. It is.

上述した説明では、間隔ｇを０．０５ｍｍとしたが、この値を大きくすると、ビア１９ＡＶ〜２１ＢＶが遅延線本体１内部により配置され、遅延線素子１７の配線領域を狭めることになるので好ましくない。 In the above description, the interval g is set to 0.05 mm. However, if this value is increased, the vias 19AV to 21BV are disposed inside the delay line body 1 and the wiring area of the delay line element 17 is narrowed. .

また、間隔ｇが逆により小さくなる場合は、一般的なセラミック積層部品の製造技術上の制約から、内部ビアは製品端面から一定の距離を保つことが要求される。従って、間隔ｇの値が０．０５ｍｍ程度が現実的である。 On the other hand, when the gap g becomes smaller due to the reverse, the internal via is required to maintain a certain distance from the end face of the product due to restrictions in manufacturing technology of general ceramic laminated parts. Therefore, it is realistic that the value of the gap g is about 0.05 mm.

要は、ビア１９ＡＶ〜２１ＢＶは、遅延線本体１内部において、側面電極３ＡＳ、３ＢＳと遅延線素子１７の形成領域までの間に形成すればよい。 In short, the vias 19AV to 21BV may be formed within the delay line body 1 and between the side electrodes 3AS and 3BS and the formation region of the delay line element 17.

さらに、本発明に係るチップ型電子部品の端子構造では、ビア１９ＡＶ〜２１ＢＶに対して下面電極３ＡＬ〜５ＢＬおよび上面電極３ＡＵ〜５ＢＵを重ねるように接続しているが、一般的なセラミック積層部品の製造工程では、上面電極および下面電極の寸法は外部電極形成装置の能力で決まってしまい、任意の寸法まで大きくすることは製造コストとの関係で困難な場合が多い。 Furthermore, in the terminal structure of the chip type electronic component according to the present invention, the lower surface electrodes 3AL to 5BL and the upper surface electrodes 3AU to 5BU are connected so as to overlap the vias 19AV to 21BV. In the manufacturing process, the dimensions of the upper surface electrode and the lower surface electrode are determined by the capability of the external electrode forming apparatus, and it is often difficult to increase the size to an arbitrary size because of the manufacturing cost.

従って、下面電極３ＡＬ〜５ＢＬは、ビア１９ＡＶ〜２１ＢＶを完全に収容できる程の寸法には設定できない場合が起こり得る。 Therefore, there may occur a case where the lower surface electrodes 3AL to 5BL cannot be set to a size that can completely accommodate the vias 19AV to 21BV.

しかし、下面電極３ＡＬ〜５ＢＬの近傍のみ小径部１９ＡＶＮ〜２１ＢＶＮとすれば、ビア１９ＡＶ〜２１ＢＶの径を小さくすることなく下面電極３ＡＬ〜５ＢＬに接続できるので、下面電極３ＡＬ〜５ＢＬと内部線路１５ａ、１５ｂとの伝送距離を短くするとともに、等価端子インダクタンスＬｔを小さくすることが可能である。 However, if the small-diameter portions 19AVN to 21BVN are provided only in the vicinity of the lower surface electrodes 3AL to 5BL, the vias 19AV to 21BV can be connected to the lower surface electrodes 3AL to 5BL without reducing the diameter, so that the lower surface electrodes 3AL to 5BL and the internal lines 15a, It is possible to shorten the transmission distance to 15b and reduce the equivalent terminal inductance Lt.

図５は本発明に係るチップ型電子部品の端子構造の別の実施の形態である。 FIG. 5 shows another embodiment of a terminal structure of a chip type electronic component according to the present invention.

図１に示した実施の形態では、ビア１９ＡＶ〜２１ＢＶが小径部１９ＡＶＮ〜２１ＢＶＮを介して下面電極３ＡＬ〜５ＢＬに接続されていた。 In the embodiment shown in FIG. 1, the vias 19AV to 21BV are connected to the lower surface electrodes 3AL to 5BL via the small diameter portions 19AVN to 21BVN.

図５に示す構成では、小径部１９ＡＶＮ〜２１ＢＶＮがなく、ビア１９ＡＶ〜１９ＢＶは下面電極３ＡＬ〜３ＢＬ近傍において、図示しない誘電体基板１３ｃ、１３ｄ間に形成された分岐線路２３ＡＩ、２３ＢＩを介して側面電極３ＡＳ、３ＢＳの途中に接続されている。 In the configuration shown in FIG. 5, there are no small-diameter portions 19AVN to 21BVN, and the vias 19AV to 19BV are side surfaces in the vicinity of the bottom electrodes 3AL to 3BL via branch lines 23AI and 23BI formed between the dielectric substrates 13c and 13d (not shown). It is connected in the middle of the electrodes 3AS and 3BS.

ビア２１ＡＶ〜２１ＢＶは、下面電極５ＡＬ〜５ＢＬ近傍において、分岐線路２５ＡＩ、２５ＢＩを介して側面電極５ＡＳ、５ＢＳの途中に接続されている。その他の構成は図１と同様である。 The vias 21AV to 21BV are connected in the middle of the side electrodes 5AS and 5BS via branch lines 25AI and 25BI in the vicinity of the bottom electrodes 5AL to 5BL. Other configurations are the same as those in FIG.

このような図５の構成では、入力信号が下面電極３ＡＬ、３ＢＬから側面電極３ＡＳ、３ＢＳを通って分岐線路２３ＡＩ、２３ＢＩまで流れ、さらに分岐線路２３ＡＩ、２３ＢＩを経由してビア１９ＡＶ、１９ＢＶに達し、ビア１９ＡＶ、１９ＢＶ表面をそれらの対向する内側に向かって斜めに流れ、信号線路１５ａ、１５ｂへ最短距離で到達する。 In such a configuration of FIG. 5, the input signal flows from the bottom electrodes 3AL and 3BL to the branch lines 23AI and 23BI through the side electrodes 3AS and 3BS, and further reaches the vias 19AV and 19BV via the branch lines 23AI and 23BI. The vias 19AV and 19BV flow obliquely toward the inner surfaces of the vias 19AV and 19BV, and reach the signal lines 15a and 15b with the shortest distance.

出力信号は、同様に、信号線路１５ａ、１５ｂから分岐線路２５ＡＩ、２５ＢＩへ向かってビア２１ＡＶ、２１ＢＶ表面を最短距離で流れ、分岐線路２５ＡＩ、２５ＢＩから側面電極５ＡＳ，５ＢＳを通って下面電極５ＡＬ、５ＢＬに達する。 Similarly, the output signal flows from the signal lines 15a and 15b to the branch lines 25AI and 25BI through the surfaces of the vias 21AV and 21BV with the shortest distance, and from the branch lines 25AI and 25BI through the side electrodes 5AS and 5BS, the bottom electrode 5AL, Reach 5BL.

この場合、図１の構成に比べ、側面電極３ＡＳ〜５ＢＳを経由する分、信号の電流経路が長くなり、等価信号端子インダクタンスＬｔが大きくなるように考えられるが、分岐線路２３ＡＩ〜２５ＢＩを遅延線本体１の下面から０．１ｍｍの位置に配置しての電磁界シミュレーションでは、殆ど差のない特性が得られる。 In this case, as compared with the configuration of FIG. 1, it is considered that the current path of the signal becomes longer and the equivalent signal terminal inductance Lt is increased by the amount of passing through the side electrodes 3AS to 5BS, but the branch lines 23AI to 25BI are connected to the delay line. In the electromagnetic field simulation arranged at a position of 0.1 mm from the lower surface of the main body 1, characteristics with almost no difference are obtained.

この理由としては、図示はしないが、高周波電流の電流密度分布を電磁界シミュレーションで確認すると、図１における小径部１９ＡＶＮ〜２１ＢＶＮを流れる電流が、これら円筒形状の表面を均一に流れず、側面電極３ＡＳ〜５ＢＳと対向する半円部に集中している。 The reason for this is not shown, but when the current density distribution of the high-frequency current is confirmed by electromagnetic field simulation, the current flowing through the small diameter portions 19AVN to 21BVN in FIG. It is concentrated in the semicircle facing 3AS-5BS.

一方、図５の構成では、電流が側面電極３ＡＳ〜５ＢＳ上を分岐線路２３ＡＩ〜２５ＢＩの幅に広がって流れるため、等価信号端子インダクタンスＬｔが上昇することなく、同等となるためであると考えられる。 On the other hand, in the configuration of FIG. 5, the current flows over the side electrodes 3AS to 5BS over the width of the branch lines 23AI to 25BI, so that the equivalent signal terminal inductance Lt does not increase and becomes equal. .

この構成では、ビア１９ＡＶ〜２１ＢＶが下面電極３ＡＬ、３ＢＬに直接接続されていないから、ビア１９ＡＶ〜２１ＢＶと側面電極３ＡＳ〜５ＢＳとの間隔ｇに対し、下面電極３ＡＬ〜５ＢＬの張り出し寸法を十分に確保でない場合、又は下面電極３ＡＬ〜５ＢＬを形成し難い場合に有用である。 In this configuration, since the vias 19AV to 21BV are not directly connected to the lower surface electrodes 3AL and 3BL, the projecting dimension of the lower surface electrodes 3AL to 5BL is sufficiently large with respect to the gap g between the vias 19AV to 21BV and the side surface electrodes 3AS to 5BS. This is useful when it is not ensured or when it is difficult to form the lower surface electrodes 3AL to 5BL.

図６および図７は本発明に係るチップ型電子部品の端子構造に関する別の実施の形態である。 6 and 7 show another embodiment relating to a terminal structure of a chip-type electronic component according to the present invention.

この構成では、図１の構成に対し、誘電体基板１３ａ，１３ｂ間および１３ｃ、１３ｄ間に形成された分岐線路２３ＡＩ〜２５ＢＩを追加して、ビア１９ＡＶ〜２１ＢＶの両端を側面電極３ＡＳ〜５ＢＳの途中にも接続している。 In this configuration, branch lines 23AI to 25BI formed between the dielectric substrates 13a and 13b and between 13c and 13d are added to the configuration of FIG. 1, and both ends of the vias 19AV to 21BV are connected to the side electrodes 3AS to 5BS. It is also connected on the way.

このような構成にすることにより、図７に示すように、磁界分布は、側面電極３ＡＳ〜５ＢＳとビア１９ＡＶ〜２１ＢＶとの間には存在しなくなる。 With this configuration, the magnetic field distribution does not exist between the side electrodes 3AS to 5BS and the vias 19AV to 21BV as shown in FIG.

その理由としては、分岐線路２３ＡＩ〜２５ＢＩの追加により、側面電極３ＡＳ〜５ＢＳとビア１９ＡＶ〜２１ＢＶとは並列回路を構成し、これらの並列回路間は等電位で電界が形成されなくなったためであると考えられる。 This is because the side electrodes 3AS to 5BS and the vias 19AV to 21BV constitute a parallel circuit due to the addition of the branch lines 23AI to 25BI, and an electric field is no longer formed at an equipotential between these parallel circuits. Conceivable.

その結果、側面電極３ＡＳ〜５ＢＳ上を流れる高周波電流も図１の構成以上に減少する。そのため側面電極３ＡＳ〜５ＢＳの終端開放スタブとしての機能がより弱まり、図１の構成に比べてわずかではあるが特性が改善される。 As a result, the high-frequency current flowing on the side electrodes 3AS to 5BS is also reduced beyond the configuration of FIG. Therefore, the functions of the side electrodes 3AS to 5BS as the terminal open stubs are weakened, and the characteristics are improved to a slight extent as compared with the configuration of FIG.

なお、ビア１９ＡＶ〜２１ＢＶは、下面電極３ＡＬ〜５ＢＬと遅延線素子１７の形成面との間において、側面電極３ＡＳ〜５ＢＳの途中に１箇所以上接続されれば、本発明の目的達成が可能である。 The vias 19AV to 21BV can achieve the object of the present invention if they are connected at least one place in the middle of the side surface electrodes 3AS to 5BS between the lower surface electrodes 3AL to 5BL and the surface on which the delay line element 17 is formed. is there.

図８および図９は本発明に係るチップ型電子部品の端子構造の別の実施の形態である。 8 and 9 show another embodiment of the terminal structure of the chip-type electronic component according to the present invention.

この構成は、上述した構成と比較した場合、ビア１９ＡＶ〜２１ＢＶを、遅延線素子１７の形成面と上面電極３ＡＵ〜５ＢＵの間において、上面電極３ＡＵ〜５ＢＵ方向にも伸ばしたものである。 In this configuration, the vias 19AV to 21BV are extended in the direction of the upper surface electrodes 3AU to 5BU between the formation surface of the delay line element 17 and the upper surface electrodes 3AU to 5BU, as compared with the above-described configuration.

内部線路１５ａ、１５ｂは、それぞれビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶの途中に直接接続されるとともに、分岐線路２３ＡＩ、２３ＢＩ、２５ＡＩ、２５ＢＩを介して側面電極３ＡＳ、３ＢＳ、５ＡＳ、５ＢＳの途中にも接続されている。 The internal lines 15a and 15b are directly connected in the middle of the vias 19AV, 19BV, 21AV, and 21BV, and also in the middle of the side electrodes 3AS, 3BS, 5AS, and 5BS through the branch lines 23AI, 23BI, 25AI, and 25BI. It is connected.

さらに、ビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶの上下両端が、分岐線路２３ＡＩ、２３ＢＩ、２５ＡＩ、２５ＢＩを介して上面電極３ＡＵ、３ＢＵ、５ＡＵ、５ＢＵおよび下面電極３ＡＬ、３ＢＬ、５ＡＬ、５ＢＬの近傍において、側面電極３ＡＳ、３ＢＳ、５ＡＳ、５ＢＳの途中に接続されたものである。 Further, the upper and lower ends of the vias 19AV, 19BV, 21AV, 21BV are in the vicinity of the upper surface electrodes 3AU, 3BU, 5AU, 5BU and the lower surface electrodes 3AL, 3BL, 5AL, 5BL via the branch lines 23AI, 23BI, 25AI, 25BI. The side electrodes 3AS, 3BS, 5AS, and 5BS are connected in the middle.

この構成においても、下面電極３ＡＬ〜５ＢＬや上面電極３ＡＵ〜５ＢＵの張り出し寸法を十分に確保でない場合、又は下面電極３ＡＬ〜５ＢＬや上面電極３ＡＵ〜５ＢＵを形成し難い場合に有用である。 This configuration is also useful when the projecting dimensions of the lower surface electrodes 3AL to 5BL and the upper surface electrodes 3AU to 5BU are not sufficiently secured, or when it is difficult to form the lower surface electrodes 3AL to 5BL and the upper surface electrodes 3AU to 5BU.

このような構成では、遅延線本体１の上面と下面を入れ替えて実装しても、高周波電流が側面電極３ＡＳ〜５ＢＳおよびビア１９ＡＶ〜２１ＢＶを流れる点で、経路の条件が上述した構成と同様になり、特に、ｈ／ｔ＝０．５の場合、特性差が極めて小さくなることが期待できる。 In such a configuration, even if the upper and lower surfaces of the delay line main body 1 are replaced and mounted, the high-frequency current flows through the side electrodes 3AS to 5BS and the vias 19AV to 21BV, so that the path condition is the same as the configuration described above. In particular, when h / t = 0.5, the characteristic difference can be expected to be extremely small.

これにより、遅延線本体１の上面と下面を区別することなく実装可能となるため、実装コストの削減のみならず、製造時の方向性マーキングやテーピング時の方向性管理を省略でき、製造コストも削減可能となる。 As a result, the delay line main body 1 can be mounted without distinguishing the upper surface and the lower surface, so that not only the mounting cost can be reduced, but also the directional marking at the time of manufacturing and the directivity management at the time of taping can be omitted, and the manufacturing cost is also reduced. Reduction is possible.

この構成でも、分岐電極２３ＡＩ〜２５ＢＩを遅延線ＤＬの底面から０．１ｍｍ上がった位置と、遅延線ＤＬの上面から０．１ｍｍ下がった位置に形成したとき、電磁界シミュレーションでの差動信号に対する通過特性が、図１、図５および図６の場合と殆ど同等の特性となり、ｈ／ｔ＞０．５の場合で比較すると、むしろ図１の場合よりも若干優れた特性が得られる。 Even in this configuration, when the branch electrodes 23AI to 25BI are formed at a position 0.1 mm above the bottom surface of the delay line DL and at a position 0.1 mm below the top surface of the delay line DL, the differential signals in the electromagnetic field simulation are detected. The pass characteristics are almost the same as those shown in FIGS. 1, 5 and 6. Compared with the case where h / t> 0.5, the characteristics slightly better than those shown in FIG. 1 are obtained.

その理由は、図６の構成と同様、側面電極３ＡＳ〜５ＢＳとビア１９ＡＶ〜２１ＢＶとが並列回路を構成し、これらの並列回路間では等電位で電磁界が形成されず、側面電極３ＡＳ〜５ＢＳの終端開放スタブとしての機能が図１の構成より弱まるからであると考えられる。 The reason is that the side electrodes 3AS to 5BS and the vias 19AV to 21BV form a parallel circuit as in the configuration of FIG. 6, and an electromagnetic field is not formed between these parallel circuits with an equal potential, and the side electrodes 3AS to 5BS. It is considered that this is because the function as a terminal open stub becomes weaker than the configuration of FIG.

なお、ビア１９ＡＶ〜２１ＢＶは、上面電極３ＡＵ〜５ＢＵと遅延線素子１７の形成面との間において、側面電極３ＡＳ〜５ＢＳの途中に１箇所以上接続されれば本発明の目的達成が可能であるし、遅延線本体１の上面に形成され側面電極３ＡＳ〜５ＢＳが接続された上面電極３ＡＵ〜５ＢＵに接続する構成も可能である。 The vias 19AV to 21BV can achieve the object of the present invention if they are connected to one or more places in the middle of the side electrodes 3AS to 5BS between the upper surface electrodes 3AU to 5BU and the surface on which the delay line element 17 is formed. In addition, it is possible to connect to the upper surface electrodes 3AU to 5BU formed on the upper surface of the delay line body 1 and connected to the side surface electrodes 3AS to 5BS.

図１０は上述した本発明に係るチップ型電子部品の端子構造の考え方を拡張した実施の形態である。 FIG. 10 shows an embodiment in which the concept of the terminal structure of the chip-type electronic component according to the present invention is expanded.

これまでの構成は、上面電極３ＡＵ、３ＢＵ、５ＡＵ、５ＢＵおよび下面電極３ＡＬ、３ＢＬ、５ＡＬ、５ＢＬに対し、各々１本のビア１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶを形成するものであった。 In the configuration so far, one via 19AV, 19BV, 21AV, 21BV is formed for each of the upper surface electrodes 3AU, 3BU, 5AU, 5BU and the lower surface electrodes 3AL, 3BL, 5AL, 5BL.

これに対し、図１０の構成は、図９の構成におけるビア１９ＶＡ〜２１ＶＢを、僅かな間隔を平行にして配置した各々２本の小径なビア１９ＡＶａ、１９ＡＶｂ、１９ＢＶａ、１９ＢＶｂ、２１ＡＶａ、２１ＡＶａ、２１ＡＶｂ、２１ＢＶａ、２１ＢＶｂとしたものである。 On the other hand, the configuration of FIG. 10 has two small diameter vias 19AVa, 19AVb, 19BVa, 19BVb, 21AVa, 21AVa, and 21AVb in which the vias 19VA to 21VB in the configuration of FIG. , 21BVa, 21BVb.

セラミック積層加工において、ビアの形成にはレーザー加工を使うことが多いため、レーザーのビーム径にもよるが、一般的にはビア径を大きくし難く、更に、他の加工方法でビア径を大きくしても、焼成時に歪みを起こし易いという問題がある。 In ceramic lamination processing, laser processing is often used to form vias, so although it depends on the laser beam diameter, it is generally difficult to increase the via diameter, and the via diameter can be increased by other processing methods. However, there is a problem that distortion is likely to occur during firing.

この点、本構成は、そのような問題を回避するために、製造工程上および品質上現実的な径のビアを複数本並べ、大径のビアと同等の特性を得るものである。 In this respect, in this configuration, in order to avoid such a problem, a plurality of vias having diameters realistic in terms of the manufacturing process and quality are arranged, and characteristics equivalent to those of the large diameter via are obtained.

このような構成で、ビア１９ＡＶａ〜２１ＢＶｂの径を０．０８ｍｍ、各入出力端子３Ａ〜５Ｂにおける１端子当たりの隣接するビアどうしの距離を０．１６ｍｍ、側面電極３ＡＳ〜５ＢＳとビア１９ＡＶａ〜２１ＢＶｂとの間隔ｇを０．１ｍｍとし、電磁界シミュレーションを行ったところ、図示はしないが図９の構成とほぼ同等の特性が得られている。 With such a configuration, the diameter of the vias 19AVa to 21BVb is 0.08 mm, the distance between adjacent vias per terminal in each of the input / output terminals 3A to 5B is 0.16 mm, the side electrodes 3AS to 5BS and the vias 19AVa to 21BVb When the electromagnetic field simulation was performed with the distance g between the two and the first electrode being 0.1 mm, characteristics substantially equivalent to the configuration of FIG. 9 were obtained although not shown.

なお、図１０の構成では、ビア１９ＡＶａ〜２１ＢＶｂは、側面電極３ＡＳ〜５ＢＳと平行に２本並べているが、側面電極３ＡＳ〜５ＢＳと垂直に並べることも可能であるし、１端子当たり３本以上にしても良い。 In the configuration of FIG. 10, two vias 19AVa to 21BVb are arranged in parallel with the side electrodes 3AS to 5BS. However, the vias 19AVa to 21BVb can be arranged perpendicular to the side electrodes 3AS to 5BS, and three or more are provided per terminal Anyway.

さらに、図９における分岐線路２３ＡＩ〜２５ＢＩは、常に両者を同時に形成する必要はない。例えば、下面電極３ＡＬ〜５ＢＬは、十分な張り出し形成可能であるうえ、ビア１９ＡＶ〜２１ＢＶを接続できる。 Furthermore, the branch lines 23AI to 25BI in FIG. 9 need not always be formed at the same time. For example, the lower surface electrodes 3AL to 5BL can be formed with sufficient overhanging and can be connected to the vias 19AV to 21BV.

しかし、上面電極３ＡＵ〜５ＢＵは、十分な張り出し形成ができない場合、分岐線路２３ＡＩ〜２５ＢＩを上面電極３ＡＵ〜５ＢＵ近傍にのみ形成し、ビア１９ＡＶ〜２１ＢＶを接続すればよい。 However, if the upper surface electrodes 3AU to 5BU cannot be sufficiently extended, the branch lines 23AI to 25BI may be formed only in the vicinity of the upper surface electrodes 3AU to 5BU and the vias 19AV to 21BV may be connected.

これまで、本発明の主な目的である２０ＧＨｚ〜３０ＧＨｚに及ぶ超高速信号を伝送できるチップ型電子部品の信号端子の端子構造の新しい提案について説明してきた。 Until now, the new proposal of the terminal structure of the signal terminal of the chip-type electronic component which can transmit the ultra high-speed signal ranging from 20 GHz to 30 GHz, which is the main object of the present invention, has been described.

しかし、本発明の要旨である、信号入出力端子３Ａ、３Ｂ、５Ａ、５Ｂを側面電極３ＡＳ〜５ＢＳとビア１９ＡＶ〜２１ＢＶとの並列回路に分けて形成した構成から得られる効果、すなわち、信号端子の等価インダクタンスを減少させる効果は、信号端子だけに限らない。 However, the effect obtained from the configuration formed by dividing the signal input / output terminals 3A, 3B, 5A, and 5B into parallel circuits of the side electrodes 3AS to 5BS and the vias 19AV to 21BV, that is, the signal terminal, The effect of reducing the equivalent inductance is not limited to the signal terminal.

具体的なシミュレーションの結果は示さないが、信号入出力端子３Ａ〜５Ｂだけでなく、例えばグランド端子に適用しても効果が期待できる。 Although the result of the specific simulation is not shown, the effect can be expected when applied to not only the signal input / output terminals 3A to 5B but also the ground terminal, for example.

さらに、本発明は、単なる回路部品としてのチップ型電子部品、例えばチップキャパシタのようなチップ型電子部品の端子に適用しても、端子の等価インダクタンスを低減できるので、特性の改善が可能となる。 Furthermore, even if the present invention is applied to a terminal of a chip-type electronic component as a simple circuit component, for example, a chip-type electronic component such as a chip capacitor, the equivalent inductance of the terminal can be reduced, so that the characteristics can be improved. .

１遅延線本体（電子部品本体）
３Ａ、３Ｂ信号入力端子
３ＡＳ、３ＢＳ、５ＡＳ、５ＢＳ側面電極
３ＡＬ、３ＢＬ、５ＡＬ、５ＢＬ下面電極
３ＡＵ、３ＢＵ、５ＡＵ、５ＢＵ上面電極
５Ａ、５Ｂ信号出力端子
７実装基板
９Ａ、９Ｂ、１１Ａ、１１Ｂ信号線路
１３ａ、１３ｂ、１３ｃ、１３ｄ、１３ｅ誘電体基板
１５ａ、１５ｂ内部線路
１５ｃグランド導体
１７遅延線素子（信号処理回路）
１９ＡＶ、１９ＢＶ、２１ＡＶ、２１ＢＶ、１９ＡＶａ、１９ＡＶｂ、１９ＢＶａ、１９ＢＶｂ、２１ＡＶａ、２１ＡＶｂ、２１ＢＶａ、２１ＢＶｂビア
１９ＡＶＮ、１９ＢＶＮ、２１ＡＶＮ、２１ＢＶＮ小径部
２３ＡＩ、２３ＢＩ、２５ＡＩ、２５ＢＩ分岐線路
ＤＬ遅延線（電子部品）
ｇ間隔
Ｚｔ４端子インピーダンス回路
Ｌｔ等価インダクタンス
Ｃｓ等価キャパシタンス
Ｃｔ等価キャパシタンス 1 Delay line body (electronic parts body)
3A, 3B Signal input terminals 3AS, 3BS, 5AS, 5BS Side electrode 3AL, 3BL, 5AL, 5BL Bottom electrode 3AU, 3BU, 5AU, 5BU Top electrode 5A, 5B Signal output terminal 7 Mounting substrate 9A, 9B, 11A, 11B Signal Lines 13a, 13b, 13c, 13d, 13e Dielectric substrates 15a, 15b Internal line 15c Ground conductor 17 Delay line element (signal processing circuit)
19AV, 19BV, 21AV, 21BV, 19AVa, 19AVb, 19BVa, 19BVb, 21AVa, 21AVb, 21BVa, 21BVb Via 19AVN, 19BVN, 21AVN, 21BVN Small-diameter portion 23AI, 23BI, 25AI, 25BI Branch line DL Delay line
g Distance Zt 4-terminal impedance circuit Lt Equivalent inductance Cs Equivalent capacitance Ct Equivalent capacitance

Claims

A chip-type electronic component body in which a signal processing circuit for processing a signal is embedded;
Side electrodes formed on the outer side surface of the chip-type electronic component body,
A lower surface electrode formed on the lower surface of the chip-type electronic component main body and connected to the external mounting substrate pattern while being connected to the side electrode;
Formed inside the chip-type electronic component main body, connected to the signal processing circuit and extending in the direction of the lower surface electrode, the lower surface electrode or the side surface between the lower surface electrode and the formation surface of the signal processing circuit Vias connected in the middle of the electrodes;
A terminal structure of a chip-type electronic component, comprising:

2. The terminal structure of a chip type electronic component according to claim 1, wherein at least one via is connected between the lower surface electrode and the formation surface of the signal processing circuit in the middle of the side surface electrode.

The terminal structure of a chip-type electronic component according to claim 1 or 2, wherein a height of the signal processing circuit from the lower surface electrode is ½ or less of a height of the chip-type electronic component main body.

The via is formed on an upper surface of the chip-type electronic component body and extends in a direction of an upper surface electrode to which the side electrode is connected, and the side surface between the upper surface electrode or the upper surface electrode and the formation surface of the signal processing circuit. The terminal structure of the chip-type electronic component according to claim 1, which is connected in the middle of the electrode.

5. The terminal structure of a chip type electronic component according to claim 4, wherein at least one via is connected between the upper surface electrode and the formation surface of the signal processing circuit in the middle of the side electrode.

The terminal structure of a chip-type electronic component according to any one of claims 1 to 5, wherein the via is formed with a diameter larger than that of a portion other than a connection portion with the lower surface electrode or the upper surface electrode.

The terminal structure of a chip-type electronic component according to claim 1, wherein the via includes a plurality of vias formed in parallel at a slight interval.