JP2012147307A - High frequency power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency power amplifier that can suppress power consumption more efficiently than before.SOLUTION: A high frequency power amplifier includes: an input side transistor 10 source-grounded and connected at a gate terminal to an input node for inputting a signal; and a plurality of output side transistors 20, 30 gate-grounded, commonly connected at a source terminal to a drain terminal of the input side transistor 10 and connected at a drain terminal to an output node for outputting an output signal. The output side transistors 20, 30 are each biased with a different gate-source voltage.

Description

  The present invention relates to a high frequency power amplifier mainly used for a radio communication device.

  A conventional power amplifier uses a transistor (such as a field effect transistor (FET) or a bipolar transistor), grounds the common terminal of the transistor, applies a bias voltage to the transistor, and causes a direct current to flow. Is gained to amplify the AC signal input from the input terminal.

  FIG. 5 is a circuit example of a conventional power amplifier using FETs as transistors. In FIG. 5, the source terminal of the FET 120 is grounded, the gate terminal is the input terminal, and the drain terminal is the output terminal. A circuit 100 including capacitors 101 and 102 and an inductor 103 is an input impedance matching circuit. A circuit 110 including capacitors 112 and 113 and an inductor 111 is an output impedance matching circuit.

  The inductor 130 applies a drain voltage to the FET 120 and simultaneously serves as part of the output matching circuit. The inductor 105 applies the gate voltage of the FET 120 and at the same time functions as a part of the input matching circuit. Terminals 140 and 160 are DC voltage terminals.

  For example, when the wireless communication system employs a modulation scheme such as ASK (Amplitude Shift Keying), linearity is required for the gain of the power amplifier. Therefore, the FET 120 is biased to class A when importance is attached to the linearity of the gain. However, in general, a power amplifier consumes the largest amount of power among wireless communication devices, so that it is required to suppress power consumption (improve efficiency). Therefore, FET 120 is often biased to class AB.

  FIG. 6 is another circuit example of a conventional power amplifier. In this circuit example, FETs 200 and 210 are stacked in two stages. A transistor having a structure in which two stages are stacked in this way is called a cascode-connected transistor. When the drain-source withstand voltage of the FET is high, the drain voltage can be increased in FIG. 5, so that sufficient power can be taken out. However, when the drain-source withstand voltage of the FET is low, there is a technique in which the FETs are stacked in two stages and the DC voltage applied between the drains and sources of the FETs 200 and 210 is reduced as in the circuit example of FIG. Generally adopted. Here, in FIG. 6, a circuit composed of the inductor 220 and the capacitor 221 is a circuit for applying a gate voltage to the output side FET 210, and the circuit components having the same reference numerals as those in FIG. 5 are the same as those in FIG. 5. It is prepared for the purpose.

  In the circuit of FIG. 6, a 0.13 μm nMOSFET is used as the FET, the operating frequency is 5.8 GHz, the power supply voltage is 2.0V at the terminal 140, and the input side FET 200 is biased to the class AB at the terminal 160. Appropriate voltage is applied to the terminal 230 to bias the output side FET 210 to class AB. FIG. 7 shows input / output characteristics of the circuit of FIG. 6 under this bias voltage condition. As a general figure of merit for evaluating the gain linearity of the current amplifier, the output power when the gain is 1 dB lower than when the signal is small is used. This output power is called P1 dB. In FIG. 7, the horizontal axis represents the input power to the power amplifier, the characteristic 301 represents the output power, and the characteristic 302 represents the power added efficiency. In this circuit, point A has an output value of P1 dB of 15 dBm, and point B has a power added efficiency of 17% at the time of P1 dB output.

Japanese Patent Laid-Open No. 2004-194063 JP 2002-335135 A

Michele Vaiana, Giuseppe Gramegna and Mario Paparo, "A Wideband Fully Integrated 0.25μm BiCMOS 5GHz Medium Power Amplifier", IEEE Bipolar / BiCMOS Circuits and Technology, 2004.Proceedings of the 2004 Meeting, September 2004, pp.314-317. Jie Weng; Hella, M., "A 5-GHz SiGe RF-Driven Cascode Power Amplifier", Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on, August 2006, pp.285-288.

However, in the circuit of FIG. 6, since the FETs 200 and 201 are biased to class AB, the power added efficiency is low. Therefore, it is difficult to suppress the power consumption of the entire wireless communication device.
Here, the power added efficiency is calculated by the following equation.

  In order to reduce the power consumption of wireless communication devices, it is essential to increase the efficiency of the power amplifier. Accordingly, an object of the present invention is to provide a high-frequency power amplifier capable of suppressing power consumption with higher efficiency than before.

A first configuration of a high-frequency power amplifier according to the present invention includes: an input side transistor having a source grounded or an emitter grounded, and a gate terminal or a base terminal connected to an input node to which an input signal is input;
A plurality of output-side transistors that are grounded at the gate or base, and are connected in parallel between the drain terminal or collector terminal of the input-side transistor and an output node from which an output signal is output. ,
Each of the output side transistors is biased by a different gate-source voltage or base-emitter voltage.

  According to this configuration, a plurality of output side transistors are connected so that the channels are in parallel, and each output side transistor is biased by applying a different gate-source voltage to each output side transistor. The voltage that is turned on differs from the voltage input to the source terminal (or emitter terminal). Therefore, as the input voltage input from the input-side transistor to the source terminal (or emitter terminal) of each output-side transistor increases, each output-side transistor is sequentially turned on in order of increasing bias voltage. Gain linearity is ensured over a wide area. In addition, when the input voltage is low, only the transistor with the low bias voltage is turned on and the other transistors are turned off, so that the total through current is reduced and the power consumption can be suppressed.

  Here, various transistors such as a field effect transistor, a bipolar transistor, and an insulated gate bipolar transistor can be used as the input side transistor and each output side transistor. Further, the number of output side transistors is not particularly limited as long as it is plural (two or more).

  The first configuration of the high-frequency power amplifier according to the present invention is the resistive voltage dividing for applying a bias voltage to the gate terminal or the base terminal of the output-side transistor for each of the output-side transistors in the first configuration. And a common power supply voltage is applied to each of the resistance voltage dividing circuits.

  With this configuration, the gates or bases of the output transistors can be biased by the same power source, so that the high-frequency power amplifier can be reduced in size and can be easily controlled.

  As described above, according to the present invention, in the structure in which the transistors are cascode-connected, the rear-stage transistors are divided into a plurality of transistors, and the rear-stage transistors are biased so that the input voltages for turning on the rear-stage transistors become different voltages. By doing so, it becomes possible to simultaneously realize the gain linearity and the power added efficiency of the high-frequency power amplifier.

1 is a circuit diagram of a high frequency power amplifier according to Embodiment 1 of the present invention. FIG. It is a figure which shows an example of the input-output characteristic of the high frequency power amplifier of FIG. It is a circuit diagram of the high frequency power amplifier concerning Example 2 of the present invention. It is a circuit diagram of the high frequency power amplifier concerning Example 3 of the present invention. It is a circuit example of the conventional power amplifier which used FET as a transistor. It is another circuit example of the conventional power amplifier. It is a figure which shows the input-output characteristic of the power amplifier of FIG.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  1 is a circuit diagram of a high-frequency power amplifier according to a first embodiment of the present invention.

  In FIG. 1, the high-frequency power amplifier of this embodiment includes an input terminal 1, an output terminal 2, power supply terminals 62, 63, 64, 160, an input side transistor 10, output side transistors 20, 30, capacitors 41, 42, 52, 53, 61, 81 and inductors 43, 51, 60, 70, 80, 150 are provided. In this embodiment, an n-type FET is used as the input-side transistor 10 and the output-side transistors 20 and 30. These transistors are bipolar transistors, insulated gate bipolar transistors (IGBT, Insulated gate bipolar). transistor) or the like, or a p-type transistor.

  The capacitors 41 and 42 and the inductor 43 are connected in a T shape to constitute an input impedance matching circuit 40. Further, the inductor 51 and the capacitors 52 and 53 are connected in a T shape to constitute the output impedance matching circuit 50.

  The output side transistors 20 and 30 have channels connected in parallel. The input side transistor 10 and the parallel circuit of the output side transistors 20 and 30 are connected in series between the ground plane and the power supply terminal 63. Has been.

  The input side transistor 10 has a source terminal grounded, a drain terminal connected to the source terminals of the output side transistors 20 and 30, and a gate terminal connected to the gate bias power supply terminal 160 via the inductor 150. An input node that is a common connection node between the inductor 150 and the gate terminal of the input-side transistor 10 is connected to the input terminal 1 via the input impedance matching circuit 40. The input side transistor 10 constitutes a common source amplifier circuit.

  The output side transistor 20 has a drain terminal connected to the drain bias power supply terminal 63 via the inductor 70, and a gate terminal connected to the gate bias power supply terminal 62 via the inductor 60. A common connection node between the gate terminal of the output-side transistor 20 and the inductor 60 is grounded via a capacitor 61 for AC bypass (for noise removal). The output-side transistor 20 constitutes a grounded gate amplifier circuit.

  The output transistor 30 has a drain terminal connected to the drain bias power supply terminal 63 via the inductor 70, and a gate terminal connected to the gate bias power supply terminal 64 via the inductor 80. A common connection node between the gate terminal of the output-side transistor 30 and the inductor 80 is grounded via a capacitor 81 for AC bypass (for noise removal). The output side transistor 30 forms a grounded gate amplifier circuit.

  The output node, which is a common connection node of the drain terminals of the output side transistors 20 and 30, is connected to the output terminal 2 via the output impedance matching circuit 50.

  The input side transistor 10 and the output side transistor 20 are each biased to class AB, and the output side transistor 30 is biased to class B.

  The inductor 70 also functions as a part of the output impedance matching circuit 50, and the inductor 150 also functions as a part of the input impedance matching circuit 40.

  In FIG. 1, the difference from the conventional power amplifier shown in FIG. 6 is that, among the two cascode-connected transistors, the output transistor at the rear stage is replaced with two output-side transistors whose channels are connected in parallel. Is a point. 1 corresponds to the input-side FET 200 in FIG. 6, and the output-side transistors 20 and 30 in the subsequent stage in FIG. 1 correspond to the output-side FET 210 in FIG. The input impedance matching circuit 40 in FIG. 1 corresponds to the input impedance matching circuit 100 in FIG. 6, and the output impedance matching circuit 50 in FIG. 1 corresponds to the output impedance matching circuit 110 in FIG. The power-side inductors 150, 60, and 80 correspond to the inductors 150 and 220 in FIG. 6, and the noise eliminating capacitors 61 and 81 in FIG. 1 correspond to the capacitor 221 in FIG.

  The operation of the high-frequency power amplifier of the present embodiment configured as described above will be described below.

  The signal input from the input terminal 1 passes through the input impedance matching circuit 40 and is input to the gate terminal of the input side transistor 10. Since the input side transistor 10 is biased to class AB, it has a gain. The signal amplified by the input side transistor 10 is input to the source terminals of the output side transistors 20 and 30. Both the output side transistors 20 and 30 operate as a grounded-gate amplifier circuit.

  Here, when the output signal from the input side transistor 10 is small (in the case of low power), most of the output signal is input to the output side transistor 20. This is because the output-side transistor 30 is biased to class B, so that it does not turn on unless a large signal is input, almost no direct current flows, and its input impedance is very high. Therefore, in this case, the output side transistor 30 has no gain. On the other hand, since the output side transistor 20 is biased to class AB, a direct current flows and is turned on, and its input impedance is much smaller than that of the output side transistor 30 and has a gain.

  Thus, the signal amplified by the input side transistor 10 is further amplified by the output side transistor 20, passes through the output impedance matching circuit 50, and is output from the output terminal 2.

  On the other hand, when the power of the signal input to the input terminal 1 increases sufficiently, the output power of the input side transistor 10 also increases. Accordingly, the class B bias output side transistor 30 is also turned on, and the amplified input signal is output from both the output side transistor 20 and the output side transistor 30.

  Therefore, when the input power is small, the cascode-connected input side transistor 10 and the output side transistor 20 operate. When the input power increases, the output side transistor 30 is also turned on. All of the side transistors 20 and 30 operate. In this case, since the channel size of the output-side transistor at the subsequent stage of the cascode connection increases, the output power can be increased.

  Further, of the output side transistors 20 and 30 at the subsequent stage of the cascode connection, one output side transistor 20 is biased to class AB, so the efficiency is not high, but the other output side transistor 30 is biased to class B. So the efficiency is high. Therefore, the efficiency of the entire high-frequency power amplifier can be made higher than that of the conventional circuit (FIGS. 5 and 6).

  FIG. 2 is a diagram illustrating an example of input / output characteristics of the high-frequency power amplifier of FIG. Here, as the input-side transistor 10 and the output-side transistors 20 and 30, nMOSFETs having a design rule of 0.13 μm were used, and the operating frequency was 5.8 GHz. Further, each DC bias voltage is 2.0 V at the power supply terminal 63, the voltage at the power supply terminal 160 is a voltage suitable for biasing the input side transistor 10 to class AB, and the voltage at the power supply terminal 62 is the output side transistor 20. And the voltage at the power supply terminal 64 are set to voltages suitable for biasing the output-side transistor 30 to class B.

  In FIG. 2, the horizontal axis represents the input power (dBm) to the high-frequency power amplifier, the left vertical axis represents the output power (dBm) of the high-frequency power amplifier, and the right vertical axis represents the current billion added efficiency (%) of the high-frequency power amplifier. To express. A characteristic 401 is a change characteristic of output power with respect to input power, and a characteristic 402 is a change characteristic of power added efficiency with respect to input power. In this circuit, the point C is an output value of P1 dB, which is 17 dBm. Point D is the power added efficiency at the time of P1 dBm output, which is 33%.

  When the characteristics of FIG. 2 are compared with the characteristics of the conventional example of FIG. 6, it can be confirmed that both the output power and the power added efficiency are improved. Therefore, according to the high-frequency power amplifier of this embodiment shown in FIG. 1, a power amplifier with higher output and higher efficiency than the conventional power amplifier can be realized, which is effective in reducing the power consumption of the wireless communication device. I understand that there is.

  In this embodiment, the input side transistor 10 is biased to class AB, but the input side transistor 10 may be configured to be biased to class A.

  FIG. 3 is a circuit diagram of a high frequency power amplifier according to the second embodiment of the present invention. 3, the same components as those in FIG. 1 are denoted by the same reference numerals.

  The high-frequency power amplifier of this embodiment includes an input terminal 1, an output terminal 2, an input side transistor 10, output side transistors 20, 30, 35, capacitors 41, 42, 52, 53, 61, 81, 82, inductors 43, 51. , 70, resistors 66, 83, 84, 85 and power supply terminals 62, 63, 64, 65, 160. The circuit of FIG. 3 differs from the circuit of FIG. 1 in that the inductors 60, 80, and 150 are replaced with resistors 66, 83, and 85, respectively, and the output side of the subsequent stage in a two-stage cascode-connected transistor The number of transistors is three, and a new grounded base amplification circuit (output-side transistor 35, resistor 84, and capacitor 82) is provided after the cascode connection.

  Here, the output side transistor 20 is biased to class AB, the output side transistor 30 is biased to class B, and the output side transistor 35 is biased to class C, and is turned on at a higher input voltage than the output side transistor 30.

  As described above, in this embodiment, the number of output-side transistors connected in parallel at the subsequent stage of the cascode connection is increased to more than two, and the bias condition of each output-side transistor is changed from normally-on (Class A or Class AB) to normally. By dividing into off (class B, class C), the output transistors in the subsequent stage are turned on sequentially as the input power increases, so the linearity region of the gain is further expanded, and higher output and higher efficiency are achieved. It is possible to plan.

  Further, resistors 85, 66, 83, and 84 can be used in the base bias voltage application circuit of each output side transistor.

  In this embodiment, an example in which there are three output transistors at the subsequent stage of the cascode connection is shown. However, in the present invention, the number of output transistors at the subsequent stage is set to four or more by the same configuration. You can also.

  FIG. 4 is a circuit diagram of a high-frequency power amplifier according to Embodiment 3 of the present invention. 4, the same components as those in FIG. 3 are denoted by the same reference numerals.

The high-frequency power amplifier of this embodiment includes an input terminal 1, an output terminal 2, an input side transistor 10, output side transistors 20, 30, 35, capacitors 41, 42, 52, 53, 61, 81, 82, inductors 43, 51. , 70, resistors 66, 83, 84, 85, 91, 92, 93 and power terminals 63, 90, 160. The circuit of FIG. 4 is different from the circuit of FIG.
The power source side terminals of the resistors 66, 83, 84 connected to the gate terminals of the output side transistors 20, 30, 35 at the subsequent stage of the cascode connection are connected to the common power source terminal 90. The gate voltages of the output side transistors 20, 30, and 35 are determined by voltage dividing resistors 99 and 91, voltage dividing resistors 83 and 92, and voltage dividing resistors 84 and 93, respectively. Therefore, since the gate terminals of the output transistors 20, 30 and 35 in the subsequent stage can be biased by the single power supply terminal 90, the high-frequency power amplifier can be reduced in size and can be easily controlled.

1 Input terminal 2 Output terminal 10 Input side transistor (FET)
20, 30, 35 Output side transistor (FET)
40 Input impedance matching circuit 50 Output impedance matching circuit 41, 42, 52, 53, 61, 81 Capacitors 43, 51, 60, 70, 80, 85 Inductors 62, 63, 64, 90, 160 Power supply terminals 66, 83, 84 , 85, 91, 92, 93 Resistor 200, 210 Transistor (FET)
DESCRIPTION OF SYMBOLS 100 Input impedance matching circuit 110 Output impedance matching circuit 101,102,112,113,221 Capacitor 103,111,130,150,220 Inductor 140,160,230 Power supply terminal

Claims (2)

An input side transistor that is grounded at the source or emitter, and whose gate terminal or base terminal is connected to an input node to which an input signal is input, and
A plurality of output-side transistors that are grounded at the gate or base, and are connected in parallel between the drain terminal or collector terminal of the input-side transistor and an output node from which an output signal is output. ,
Each of the output side transistors is biased by a different gate-source voltage or base-emitter voltage.   Each of the output side transistors includes a resistance voltage dividing circuit that applies a bias voltage to the gate terminal or base terminal of the output side transistor, and a common power supply voltage is applied to each of the resistance voltage dividing circuits. The high-frequency power amplifier according to claim 1, wherein

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