JP2012147133A - Sampling rate conversion device, and sampling rate conversion method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sampling rate conversion device and a sampling rate conversion method capable of reducing memory capacity for storing a filter coefficient required for interpolation and realizing sampling rate conversion by a package with a smaller circuit scale compared with the conventional art.SOLUTION: A sampling rate conversion device has: a sampling timing generation part 1 generating input and output sampling rate timings; a filter coefficient storing memory 3-1 storing a filter coefficient; filter coefficient storing memories 3-2 and 3-3 storing difference values of filter coefficients; a filter coefficient controller 6 controlling the reading out of data from a read address corresponding to a phase counter value to the filter coefficient storing memories 3-1 to 3-3; an accumulation and addition part 7 adding the data read out from the filter coefficient storing memories 3-1 to 3-3 to generate the filter coefficient; and a transversal filter part 2 performing convolution of an input digital signal and the filter coefficient from the accumulation and addition part 7.

Description

  The present invention relates to a sampling rate conversion device and a sampling rate conversion method for converting a sampling rate of a digital signal.

  Conventionally, sampling rate conversion for a digital signal can be realized by combining signal interpolation (oversampling) and decimation. When converting to a sampling rate of N / M times (N and M are positive integers) with respect to the original sampling rate before conversion, N times oversampling is performed by interpolation, and then N times the number of the interpolated N times A signal converted to a sampling rate of N / M times can be obtained by extracting M samples from the signal. However, a digital filter for oversampling needs to have frequency characteristics that do not cause aliasing when a signal is converted to a sampling rate of N / M times. In addition, when interpolating to N times oversamples, unnecessary filter computation can be reduced by using a polyphase filter, and interpolation processing can be realized with a small computation amount (circuit scale).

  The sampling rate of the digital signal can be converted to an arbitrary sampling rate by adjusting N and M using the sampling rate conversion of N / M times shown above (see, for example, Non-Patent Document 1). .

Nishimura Yoshikazu, Communication System Design by Digital Signal Processing, CQ Publisher, p. 85-89

  However, according to the prior art described in Non-Patent Document 1, the filter coefficient of the digital filter is switched at equal intervals to perform an N-times oversampling interpolation process, and then every M pieces from the interpolated N-times signal. A signal converted to a sampling rate of N / M times can be obtained by extracting a sample in (5). However, as the value of N for oversampling increases, the filter coefficient necessary for interpolation increases, and the circuit scale (filter coefficient) The number of registers or memories for storing the memory increases, which makes circuit mounting difficult.

  The present invention has been made in view of the above, and it is possible to reduce the memory capacity for storing the filter coefficients necessary for interpolation, and to realize the sampling rate conversion with a smaller circuit scale than the conventional one. An object is to provide a conversion device and a sampling rate conversion method.

  In order to solve the above-described problems and achieve the object, a sampling rate conversion apparatus according to the present invention generates a sampling timing for generating an input sampling rate timing of an input digital signal and an output sampling rate timing after the sampling rate conversion. A filter coefficient storage unit that stores in advance a sequence of filter coefficients discretized at a predetermined time interval, and a filter coefficient stored in the filter coefficient storage unit and discrete at a time interval shorter than the predetermined time interval. A filter coefficient difference storage unit that stores in advance a series of difference values at least on the first floor from the converted filter coefficient, and the filter coefficient storage unit and the filter coefficient difference storage unit are initialized at the input sampling rate timing And at the output sampling rate timing A filter coefficient control unit that performs control of reading data from a read address corresponding to a new phase counter value, and the filter coefficient control unit when signal interpolation is required at a time interval shorter than the predetermined time interval. And a cumulative addition unit that generates a set of filter coefficients by adding the data read from the filter coefficient storage unit and the filter coefficient difference storage unit under the read control, respectively, at the input sampling rate timing. A product-sum operation is performed on the digital signal consisting of a set of samples input by samples and held in a shift register and a set of filter coefficients output from the accumulator, and the product is calculated at the output sampling rate timing. By outputting the sum operation result, the digital signal after sampling rate conversion is output. Characterized in that it comprises a transversal filter section for outputting.

  According to the present invention, it is possible to reduce the memory capacity for storing the filter coefficients necessary for the interpolation, and to realize the sampling rate conversion with an implementation having a smaller circuit scale than the conventional one.

FIG. 1 is a diagram illustrating a configuration example of a sampling rate conversion apparatus according to the first embodiment. FIG. 2 is a diagram illustrating a configuration example of the filter coefficient storage memory 3-1. FIG. 3 is a diagram illustrating a configuration example of the filter coefficient storage memory 3-2. FIG. 4 is a diagram illustrating a configuration example of the filter coefficient storage memory 3-3. FIG. 5 is a diagram illustrating a configuration example of the sampling rate conversion apparatus according to the second embodiment. FIG. 6 is an explanatory diagram for explaining the coefficient interpolation processing by the coefficient interpolation unit 20.

  Embodiments of a sampling rate conversion apparatus and a sampling rate conversion method according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating a configuration example of a sampling rate conversion apparatus according to the present embodiment. As shown in FIG. 1, the sampling rate converter includes a sampling timing generator 1 that generates an input sampling rate timing of an input digital signal Ain and an output sampling rate timing after the sampling rate conversion, and an input digital signal Ain. And a filter coefficient storage for storing a discretized filter coefficient at predetermined time intervals, and a transversal filter unit 2 that generates a digital signal Aout after sampling rate conversion by performing a product-sum operation (convolution operation) of the filter coefficient A memory coefficient, a filter coefficient storage memory 3-2 for storing predetermined time difference information from the filter coefficients stored in the filter coefficient storage memory 3-1, and a filter coefficient stored in the filter coefficient storage memory 3-2 ( A predetermined time difference from the difference value) A filter coefficient storage memory 3-3 for storing information, a filter coefficient control section 6 for performing read address control on the filter coefficient storage memories 3-1 to 3-3 at an instruction timing from the sampling timing generation section 1, and a filter A cumulative addition unit 7 that outputs the filter coefficient obtained by cumulatively adding the values read from the coefficient storage memories 3-1 to 3-3 to the transversal filter unit 2;

  Next, the operation of the present embodiment will be described. First, an input sampling clock (input sampling rate timing) of the digital signal Ain input to the transversal filter unit 2 by the sampling timing generation unit 1 and an output sampling clock (output sampling rate timing) of the digital signal Aout after the sampling rate conversion. Is generated and output to the filter coefficient control unit 6, the cumulative addition unit 7, and the transversal filter unit 2.

  The input digital signal Ain is input to the transversal filter unit 2 sample by sample at the timing of the input sampling clock. The transversal filter unit 2 includes a shift register (not shown) that stores the input digital signal Ain over a plurality of samples, and the sampled data is stored in the shift register one sample at a time of the input sampling clock. Is done.

The filter coefficient control unit 6 includes a phase counter unit (not shown) that counts the sampling phase with respect to the digital signal Ain, and this phase counter unit updates the counter value at the timing of the output sampling clock. That is, for example, the phase counter unit can count the sampling phase with respect to the input digital signal Ain by initializing the counter value with the input sampling clock and updating the counter value with the output sampling clock. For example, if the input sampling rate is 1 MHz and the output sampling rate is 10 MHz, the output sampling rate is 10 times the input sampling rate, so 10 times the output sampling time corresponds to the input sampling time interval. Therefore, by preparing a phase counter from 0 to 9, and incrementing the phase counter at the output sampling time interval, the phase difference between the input sampling rate and the output sampling rate can be obtained, and the x / 10 phase of the input sampling time It is sufficient to select a filter coefficient for interpolating a signal whose timing is shifted by (x is a phase counter value). Note that even when the output sampling rate is a non-integer multiple of the input sampling rate, it is possible to cope with this, for example, by using a phase counter (0 to 1023) having a time resolution of 1/1024 of the input sampling rate. The amount of phase shift Δθ per rate can be obtained by the following equation.
Δθ = 1024 × input sampling rate / output sampling rate In this case, by incrementing the phase counter by the above Δθ at the time interval of the output sampling rate, the timing of x / 1024 phase (x is the phase counter value) of the input sampling time. It is sufficient to select a filter coefficient for interpolating the shifted signal. If Δθ is not divisible, it can be rounded off by rounding off. Needless to say, the present invention is not limited to these examples. Further, the filter coefficient control unit 6 decodes the read addresses of the filter coefficient storage memories 3-1 to 3-3 corresponding to the phase counter value from the phase counter value. That is, the filter coefficient control unit 6 converts the phase counter value and obtains the read addresses of the corresponding filter coefficient storage memories 3-1 to 3-3. Here, the decoding method for the read address is not particularly limited as long as it converts the read coefficient to the read address storing the filter coefficient corresponding to the phase counter value indicating the sampling phase of the input digital signal Ain. There is no limitation about.

  The filter coefficient storage memory 3-1 stores filter coefficients for signal interpolation corresponding to the sampling phase of the input digital signal Ain or signal interpolation close to the sampling phase. This filter coefficient is a coefficient of an interpolation filter or a decimation filter, and a filter coefficient having a frequency characteristic for removing aliasing noise generated when up-sampling or down-sampling is used.

  The filter coefficient storage memory 3-2 is stored in the filter coefficient storage memory 3-1 as a filter coefficient with a time resolution higher than the time sample interval of the filter coefficient stored in the filter coefficient storage memory 3-1. It is a memory for storing a difference value from the filter coefficient (filter coefficient difference value). Therefore, the filter coefficient storage memory 3-2 is used when a filter coefficient intended for signal interpolation with higher time resolution than the filter coefficient memory 3-1 is required.

  Similarly, the filter coefficient storage memory 3-3 is stored in the filter coefficient storage memory 3-2 as a filter coefficient with a time resolution higher than the time sample interval of the filter coefficient stored in the filter coefficient storage memory 3-2. This is a memory for storing a difference value (filter coefficient difference value) from the filter coefficient difference value. In this embodiment, an example is described in which a memory for storing difference information on the first floor and the second floor is provided, for example, but a memory for storing difference information on higher floors, for example, according to the required time resolution. It can also be provided.

  The accumulating unit 7 stores the filter coefficient in the filter coefficient storage memory 3-1 when the filter coefficient for signal interpolation with higher time resolution than the filter coefficient stored in the filter coefficient storage memory 3-1 is required. The filtered filter coefficient and the filter coefficient difference value stored in the filter coefficient storage memory 3-2 are added, or the filter coefficient stored in the filter coefficient storage memory 3-1 and the filter coefficient storage memory 3-2 are added. And the filter coefficient difference value respectively stored in the filter coefficient storage memory 3-3 is added to generate a filter coefficient for signal interpolation with higher time resolution.

  The transversal filter unit 2 stores the input digital signal Ain in the shift register over a plurality of samples, and outputs the digital signal consisting of a set of samples stored in the shift register and the cumulative addition unit 7. A product-sum operation is performed on the set of filter coefficients (that is, a convolution operation), and a product-sum operation result is output in accordance with the timing of the output sampling clock from the sampling timing generation unit 1. This output result is the digital signal Aout after the sampling rate conversion.

  Next, the details of the filter coefficient storage memories 3-1 to 3-3 in the present embodiment will be described with reference to FIGS.

  FIG. 2 is a diagram illustrating a configuration example of the filter coefficient storage memory 3-1. In FIG. 2, the number of taps N of the filter coefficient is, for example, 5, and T indicates one sample period of the input digital signal Ain. Address 0 stores a reference filter coefficient of 5 taps (A0, A4, A8, A12, A16). "Address 1" stores a set of filter coefficients (A1, A5, A9, A13, A17) when T / 4 time is shifted from the filter coefficient of "Address 0". T / 4 represents the time resolution in this case. Similarly, “address 2” stores a set of filter coefficients (A2, A6, A10, A14, A18) when T / 4 time deviates from the filter coefficient of “address 1”. 3 ”stores a set of filter coefficients (A3, A7, A11, A15, A19) when the T / 4 time is shifted from the filter coefficient of“ address 2 ”.

FIG. 3 is a diagram illustrating a configuration example of the filter coefficient storage memory 3-2. In FIG. 3, filter coefficient difference values B0 to B19 are stored in the filter coefficient storage memory 3-2. When the filter coefficient values shifted by T / 8 from the respective filter coefficients A0 to A19 stored in the filter coefficient storage memory 3-1 shown in FIG. It is represented by the formula (1).
Bx = Dx−Ax (x: 0 to 19) (1)
Here, the expression (1) represents, for example, B0 = D0−A0 as a whole.

FIG. 4 is a diagram illustrating a configuration example of the filter coefficient storage memory 3-3. In FIG. 4, filter coefficient difference values C0, y to C19, y (y: 0,1) are stored in the filter coefficient storage memory 3-3. Each filter coefficient A0 to A19 stored in the filter coefficient storage memory 3-1 is E0,0 to E19,0 with the filter coefficient values shifted by T / 16 and stored in the filter coefficient storage memory 3-1. The filter coefficient value obtained by shifting the time by T / 16 to the filter coefficient obtained by adding the filter coefficients A0 to A19 and the filter coefficients B0 to B19 stored in the filter coefficient storage memory 3-2 is E0. , 1 to E19,1, C0,0 to C19,0 and C0,1 to C19,1 are represented by the following formulas (2) and (3).
Cx, 0 = Ex, 0−Ax (x: 0 to 19) (2)
Cx, 1 = Ex, 1-Ax-Bx (x: 0 to 19) (3)
Here, the expression (2) represents, for example, C0,0 = E0,0-A0, and the expression (3) generally represents, for example, C0,1 = E0,1-A0-B0.

  Therefore, for example, when obtaining a filter coefficient shifted by T / 2 time with respect to address 0 of the filter coefficient storage memory 3-1, the filter coefficient stored at "address 2" of the filter coefficient storage memory 3-1. You can lead. That is, the filter coefficient control unit 6 controls to read out one set of filter coefficients stored in “address 2” of the filter coefficient storage memory 3-1 to the cumulative addition unit 7. Are output to the transversal filter unit 2, and the transversal filter unit 2 calculates the product sum of the one set of filter coefficients and the one set of digital signals Ain held in the shift register.

Further, for example, when obtaining filter coefficients shifted by 3T / 8 time, the filter coefficients (A1, A5, A9, A13, A17) stored at “address 1” of the filter coefficient storage memory 3-1, Using the filter coefficient difference values (B1, B5, B9, B13, B17) stored at “address 1” of the filter coefficient storage memory 3-2, the cumulative addition unit 7 calculates the following equation (4). If you do it, you can find it.
Dx = Ax + Bx (x: 1, 5, 9, 13, 17) (4)
That is, the filter coefficient control unit 6 has a set of filter coefficients stored at “address 1” of the filter coefficient storage memory 3-1, and “1” stored at “address 1” of the filter coefficient storage memory 3-2. Control is performed so that the set of filter coefficient difference values is read out to the cumulative addition unit 7, and the cumulative addition unit 7 calculates the above formula (4) for the one set of filter coefficients and the one set of filter coefficient difference values to obtain 1 After obtaining the set of filter coefficients, the set of filter coefficients is output to the transversal filter unit 2, and the transversal filter unit 2 outputs the set of filter coefficients and the set of digital signals Ain held in the shift register. The sum of products with is calculated.

Further, for example, when obtaining a filter coefficient shifted by 7T / 16 time, filter coefficients (A1, A5, A9, A13, A17) stored at “address 1” of the filter coefficient storage memory 3-1, The filter coefficient difference value (B1, B5, B9, B13, B17) stored at “address 1” of the filter coefficient storage memory 3-2 and “address 3” of the filter coefficient storage memory 3-3 Using the filter coefficient difference values (C1, 1, C5, 1, C9, 1, C13, 1, C17, 1), the cumulative addition unit 7 can calculate the following equation (5). .
Ex, 1 = Ax + Bx + Cx, 1 (x: 1, 5, 9, 13, 17) (5)

When a higher resolution is required, the maximum time resolution of the filter coefficient storage memories 3-1 to 3-3 (T / 16 in the illustrated example) is obtained by rounding off the phase counter value.
) To obtain the filter coefficient.

  As described above, according to the present embodiment, the filter coefficient of the time interval having a lower time resolution with respect to one sample period is stored in the filter coefficient storage memory 3-1 (filter coefficient storage unit). In order to generate a filter coefficient at a time interval with high time resolution, only a difference value from the filter coefficient stored in the filter coefficient storage memory 3-1 is stored in the filter coefficient storage memory 3-2 (filter coefficient difference storage unit). Further, in order to generate a filter coefficient at a time interval with higher time resolution, the filter coefficient stored in the filter coefficient storage memory 3-1 and the filter coefficient difference value stored in the filter coefficient storage memory 3-2 are added. Only the difference value with the generated filter coefficient is stored in the filter coefficient storage memory 3-3 (filter coefficient difference storage unit), and when necessary According to the resolution filter coefficient, the necessary information is read from each memory and added to generate a high resolution filter coefficient. In contrast to the configuration in which all must be stored in the memory, only the difference information, which is less information, may be stored in the memory (filter coefficient storage memories 3-2 and 3-3). Therefore, the memory capacity can be greatly reduced as compared with the conventional case.

  In particular, since the amount of information becomes smaller as the difference information becomes higher resolution, the memory reduction effect becomes greater when the resolution of the filter coefficient is increased. Further, by adopting a configuration in which difference information for generating a filter coefficient with a higher time resolution from a filter coefficient with a lower time resolution is stored in stages, a memory is used when generating a filter coefficient with a desired time resolution. Since the necessary information to be read out can be kept small, the present embodiment has the effect of reducing the data volume to be read and the effect of reducing the amount of calculation at the time of addition for restoring the filter coefficient. .

Embodiment 2. FIG.
In the first embodiment described above, in order to generate a filter coefficient with a high time resolution, a difference value from a filter coefficient with a lower time resolution is stored in a memory, and the filter coefficient and the difference value with a low time resolution are added. In this embodiment, when a further reduction in memory is desired, the amount of information becomes smaller as the difference information with higher time resolution is generated. Instead of storing the difference information in the memory, the difference information is generated by interpolation.

  FIG. 5 is a diagram illustrating a configuration example of the sampling rate conversion apparatus according to the present embodiment. In FIG. 5, the coefficient interpolation unit 20 interpolates the difference information of the filter coefficient stored in the filter coefficient storage memory 3-2 to generate a filter coefficient with higher time resolution. That is, in FIG. 5, a coefficient interpolation unit 20 is provided instead of providing the filter coefficient storage memory 3-3. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  Next, the operation of the present embodiment will be described. First, the sampling timing generation unit 1 generates an input sampling clock of the digital signal Ain input to the transversal filter unit 2 and an output sampling clock of the digital signal Aout after the sampling rate conversion, and the input sampling clock is the transversal filter unit. 2 and the output sampling clock is output to the filter coefficient control unit 6, the cumulative addition unit 7 and the transversal filter unit 2.

  The input digital signal Ain is input to the transversal filter unit 2 sample by sample at the timing of the input sampling clock. The transversal filter unit 2 includes a shift register (not shown) that stores the input digital signal Ain over a plurality of samples, and the sampled data is stored in the shift register one sample at a time of the input sampling clock. Is done.

  The filter coefficient control unit 6 includes a phase counter unit (not shown) that counts the sampling phase with respect to the digital signal Ain, and this phase counter unit updates the counter value at the timing of the output sampling clock. That is, for example, the phase counter unit can count the sampling phase with respect to the input digital signal Ain by initializing the counter value with the input sampling clock and updating the counter value with the output sampling clock. Further, the filter coefficient control unit 6 decodes the read addresses of the filter coefficient storage memories 3-1 to 3-2 corresponding to the phase counter value from the phase counter value. That is, the filter coefficient control unit 6 converts the phase counter value and obtains the read addresses of the corresponding filter coefficient storage memories 3-1 to 3-2. Here, the decoding method for the read address is not particularly limited as long as it converts the read coefficient to the read address storing the filter coefficient corresponding to the phase counter value indicating the sampling phase of the input digital signal Ain. There is no limitation about.

  The filter coefficient storage memory 3-1 stores filter coefficients for signal interpolation corresponding to the sampling phase of the input digital signal Ain or signal interpolation close to the sampling phase. The filter coefficient may be close to that even if it does not strictly correspond to the sampling phase of the digital signal Ain.

  The filter coefficient storage memory 3-2 is stored in the filter coefficient storage memory 3-1 as a filter coefficient with a time resolution higher than the time sample interval of the filter coefficient stored in the filter coefficient storage memory 3-1. It is a memory for storing a difference value from the filter coefficient (filter coefficient difference value). Therefore, the filter coefficient storage memory 3-2 is used when a filter coefficient intended for signal interpolation with higher time resolution than the filter coefficient memory 3-1 is required.

  When the coefficient interpolation unit 20 is requested to have a time resolution higher than the time resolution expressed by the filter coefficient difference value stored in the filter coefficient storage memory 3-2, the difference information in the filter coefficient storage memory 3-2. Are interpolated (for example, linear interpolation) to generate filter coefficient difference information at a higher temporal resolution.

  The cumulative addition unit 7 is stored in the filter coefficient memory 3-1 when a filter coefficient for signal interpolation with a higher time resolution than the filter coefficient stored in the filter coefficient memory 3-1 is required. Are added to the filter coefficient difference value stored in the filter coefficient storage memory 3-2 or stored in the filter coefficient storage memory 3-2 and the filter coefficient stored in the filter coefficient memory 3-1. The filter coefficient difference value generated by the coefficient interpolation unit 20 and the filter coefficient difference value generated by coefficient interpolation are added to generate a filter coefficient for signal interpolation with higher temporal resolution.

  The transversal filter unit 2 stores the input digital signal Ain in the shift register over a plurality of samples, and performs a product-sum operation on the digital signal stored in the shift register and the filter coefficient output from the cumulative addition unit 7 Then, the product-sum operation result is output in accordance with the timing of the output sampling clock from the sampling timing generator 1. This output result is the digital signal Aout after the sampling rate conversion.

  Next, details of the filter coefficient storage memory 3-1, the filter coefficient storage memory 3-2, and the coefficient interpolation unit 20 in the present embodiment will be described with reference to FIGS. 2, 3, and 6. FIG. 2 and 3 are the same as those in the first embodiment, and thus the description thereof is omitted.

  FIG. 6 is an explanatory diagram for explaining the coefficient interpolation processing by the coefficient interpolation unit 20. FIG. 6 illustrates an example in which Cx, y (x: 0 to 19, y: 0,1) described in the first embodiment is obtained by interpolation. As shown in FIG. 4, the filter coefficients A0 to A19 and the filter coefficient values shifted in time by T / 16 are stored as E0,0 to E19,0 in the filter coefficient storage memory 3-1, and the filter coefficients Time T / 16 is obtained for the filter coefficient obtained by adding the filter coefficients A0 to A19 stored in the storage memory 3-1 and the filter coefficients B0 to B19 stored in the filter coefficient storage memory 3-2. In the case where the filter coefficient values shifted from are E0,1 to E19,1, C0,0 to C19,0 and C0,1 to C19,1 are expressed by the above formulas (2) and (3).

For example, when the coefficient interpolation unit 20 interpolates C1, 1, C5, 1, C9, 1, C13, 1, C17, 1, for example, the difference information stored in the filter coefficient storage memory 3-2 is used. Thus, it can be calculated by the following equations (6) to (10).
C1,1 = (A2-A1-B1) / 2 (6)
C5,1 = (A6-A5-B5) / 2 (7)
C9,1 = (A10−A9−B9) / 2 (8)
C13,1 = (A14−A13−B13) / 2 (9)
C17,1 = (A18−A17−B17) / 2 (10)

Therefore, for example, when obtaining filter coefficients shifted by 7T / 16 time, a set of filter coefficients (A1, A5, A9, A13, A17) stored at "address 1" of the filter coefficient storage memory 3-1. ), A set of filter coefficient difference values (B1, B5, B9, B13, B17) stored at “address 1” of the filter coefficient storage memory 3-2 and a set of filters calculated by the coefficient interpolation unit 20 Using the coefficient difference values (C1, 1, C5, 1, C9, 1, C13, 1, C17, 1), the cumulative adder 7 may perform the calculation of the following equation (11).
Ex, 1 = Ax + Bx + Cx, 1 (x: 1, 5, 9, 13, 17) (11)
Further, when a higher resolution is required, a higher temporal resolution filter coefficient can be generated by generating a higher temporal resolution filter coefficient difference value in the coefficient interpolation unit 20.

  As described above, filter coefficients at intervals with a low time resolution for one sample period are stored in the filter coefficient storage memory 3-1 (filter coefficient storage unit), and filter coefficients at intervals with a higher time resolution are generated. Therefore, only the difference value from the filter coefficient stored in the filter coefficient storage memory 3-1 is stored in the filter coefficient storage memory 3-2 (filter coefficient difference storage unit), and the filter having an interval higher in time resolution than that is stored. In order to generate a coefficient, a difference value between the filter coefficient stored in the filter coefficient storage memory 3-1 and the filter coefficient generated by adding the filter coefficient stored in the filter coefficient storage memory 3-2 is obtained by interpolation. Depending on the filter coefficient of the required time resolution, the necessary information from each memory and the filter coefficient difference value obtained by interpolation are read. Since a high-resolution filter coefficient is generated by adding and adding, a memory (filter coefficient storage memory 3-3) for storing the filter coefficient difference value required in the first embodiment is provided. Since the necessary filter coefficient difference value is calculated by interpolation, the memory capacity can be further reduced as compared with the first embodiment.

  In addition, this effect utilizes the fact that the amount of difference information of the filter coefficient, which has a high time resolution, is small, and has the effect that the error due to interpolation can be greatly reduced compared to the value obtained by directly interpolating the filter coefficient. There is an effect of reducing the memory capacity and at the same time reducing the interpolation error.

  The present invention is useful as a sampling rate conversion apparatus and a sampling rate conversion method for converting a sampling rate of a digital signal waveform into a different sampling rate.

DESCRIPTION OF SYMBOLS 1 Sampling timing production | generation part 2 Transversal filter part 3-1 to 3-3 Filter coefficient memory 6 Filter coefficient control part
7 Cumulative addition unit 20 Coefficient interpolation unit

Claims (6)

A sampling timing generation unit that generates an input sampling rate timing of an input digital signal and an output sampling rate timing after sampling rate conversion, and a filter coefficient storage unit that pre-stores a sequence of filter coefficients discretized at a predetermined time interval When,
A filter coefficient difference storage unit that stores in advance a series of at least first-order difference values between the filter coefficient stored in the filter coefficient storage unit and the filter coefficient discretized at a time interval shorter than the predetermined time interval; ,
The filter coefficient storage unit and the filter coefficient difference storage unit are controlled to read data from a read address corresponding to a phase counter value that is initialized at the input sampling rate timing and updated at the output sampling rate timing. A filter coefficient control unit to perform;
Data read from the filter coefficient storage unit and the filter coefficient difference storage unit under the read control of the filter coefficient control unit when signal interpolation at a time interval shorter than the predetermined time interval is necessary A cumulative adder that generates a set of filter coefficients by adding
Performing a product-sum operation on the digital signal consisting of a set of samples input sample by sample at the input sampling rate timing and held in a shift register and a set of filter coefficients output from the cumulative adder, A transversal filter unit that outputs a digital signal after conversion of the sampling rate by outputting the product-sum operation result at the output sampling rate timing;
A sampling rate conversion device comprising: The filter coefficient difference storage unit stores the difference value for each rank of the difference,
The filter coefficient control unit reads out one set of filter coefficients from the filter coefficient storage unit according to the time resolution required for the signal interpolation, and sets one set of the filter coefficients from the filter coefficient difference storage unit for each rank. Read the difference value
The cumulative addition unit cumulatively adds a set of filter coefficients read from the filter coefficient storage unit and a set of difference values read from the filter coefficient difference storage unit for each rank. The sampling rate conversion apparatus according to claim 1, wherein the set of filter coefficients is generated. A sampling timing generation unit that generates an input sampling rate timing of an input digital signal and an output sampling rate timing after sampling rate conversion, and a filter coefficient storage unit that pre-stores a sequence of filter coefficients discretized at a predetermined time interval When,
A filter coefficient difference storage unit that stores in advance a series of at least first-order difference values between the filter coefficient stored in the filter coefficient storage unit and the filter coefficient discretized at a time interval shorter than the predetermined time interval; ,
The filter coefficient storage unit and the filter coefficient difference storage unit are controlled to read data from a read address corresponding to a phase counter value that is initialized at the input sampling rate timing and updated at the output sampling rate timing. A filter coefficient control unit to perform;
When signal interpolation with a time resolution higher than the time resolution represented by the highest order difference value stored in the filter coefficient difference storage unit is necessary, interpolation is performed using the highest order difference value. A coefficient interpolation unit that generates a higher order difference value than the highest order difference value, and
One set is obtained by adding the data read from the filter coefficient storage unit and the filter coefficient difference storage unit respectively under the readout control of the filter coefficient control unit and the difference value generated by the coefficient interpolation unit. A cumulative adder for generating filter coefficients of
Performing a product-sum operation on the digital signal consisting of a set of samples input sample by sample at the input sampling rate timing and held in a shift register and a set of filter coefficients output from the cumulative adder, A transversal filter unit that outputs a digital signal after conversion of the sampling rate by outputting the product-sum operation result at the output sampling rate timing;
A sampling rate conversion device comprising: The filter coefficient difference storage unit stores the difference value for each rank of the difference,
The filter coefficient control unit reads out one set of filter coefficients from the filter coefficient storage unit according to the time resolution required for the signal interpolation, and sets one set of the filter coefficients from the filter coefficient difference storage unit for each rank. Read the difference value
The cumulative addition unit includes a set of filter coefficients read from the filter coefficient storage unit, a set of difference values read from the filter coefficient difference storage unit for each rank, and the coefficient interpolation unit. The sampling rate conversion apparatus according to claim 3, wherein the set of filter coefficients is generated by cumulatively adding the generated set of the difference values. A sampling timing generation step for generating an input sampling rate timing of the input digital signal and an output sampling rate timing after the sampling rate conversion;
A filter coefficient storage unit that pre-stores a series of filter coefficients discretized at a predetermined time interval, and a filter coefficient stored in the filter coefficient storage unit and discretized at a time interval shorter than the predetermined time interval Corresponds to the phase counter value that is initialized at the input sampling rate timing and updated at the output sampling rate timing for the filter coefficient difference storage unit that stores in advance a series of difference values of at least the first floor with the filter coefficient A data reading step for reading data from the read address to be performed;
When signal interpolation at a time interval shorter than the predetermined time interval is necessary, a set of filter coefficients can be obtained by adding data read from the filter coefficient storage unit and the filter coefficient difference storage unit, respectively. A cumulative addition step to generate,
A product-sum operation is performed on the digital signal composed of a set of samples input sample by sample at the input sampling rate timing and the set of filter coefficients obtained in the cumulative addition step, and at the output sampling rate timing. A product-sum operation step for outputting the digital signal after the sampling rate conversion by outputting the product-sum operation result,
A sampling rate conversion method comprising: A sampling timing generation step for generating an input sampling rate timing of the input digital signal and an output sampling rate timing after the sampling rate conversion;
A filter coefficient storage unit that pre-stores a series of filter coefficients discretized at a predetermined time interval, and a filter coefficient stored in the filter coefficient storage unit and discretized at a time interval shorter than the predetermined time interval Corresponds to the phase counter value that is initialized at the input sampling rate timing and updated at the output sampling rate timing for the filter coefficient difference storage unit that stores in advance a series of difference values of at least the first floor with the filter coefficient A data reading step for reading data from the read address to be performed;
When signal interpolation with a time resolution higher than the time resolution represented by the highest order difference value stored in the filter coefficient difference storage unit is necessary, interpolation is performed using the highest order difference value. A coefficient interpolation step for generating a higher order difference value than the highest order difference value;
A cumulative addition step of generating a set of filter coefficients by adding the data read from each of the filter coefficient storage unit and the filter coefficient difference storage unit and the difference value generated by the coefficient interpolation unit;
A product-sum operation is performed on the digital signal composed of a set of samples input sample by sample at the input sampling rate timing and the set of filter coefficients obtained in the cumulative addition step, and at the output sampling rate timing. A product-sum operation step for outputting the digital signal after the sampling rate conversion by outputting the product-sum operation result,
A sampling rate conversion method comprising:

Images