JP2012147009A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device with a fuse.SOLUTION: A semiconductor device is composed of an electric-fusion relief fuse 4a and a testing fuse 4b provided on a layer M4 among layers M1-M6 forming a multilayer wiring formed on a main surface of a semiconductor substrate 11, a pair of conductor plates 10a provided on the layers M2 and M6 near the fuse 4a, and a pair of conductor plates 10b provided on the layers M3 and M5 near the fuse 4b. The distance between the fuse 4b and the conductor plate 10b is shorter than the distance between the fuse 4a and the conductor plate 10a.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology that is effective when applied to a semiconductor device including a fuse that can be cut by an electric fusing type.

  Memory LSIs such as DRAM (Dynamic Random Access Memory) and non-volatile memory (EEPROM) that can be electrically written and erased are redundant to remedy defects (defects) that occur in the manufacturing process. By providing the function, the reliability and the manufacturing yield of the semiconductor device are improved. This is because a memory cell column and a memory cell row (redundant circuit) for defect relief are prepared in advance in a semiconductor device, and when a defective memory cell column is generated in the memory array, the defective memory cell is entered. This is a defect relief function in which a desired memory operation is performed by inputting an address signal to a memory cell column for defect relief.

  For example, when a defective memory cell is replaced with a defect relief memory cell, it is necessary to store an address (defective address) for specifying the defective memory cell. In general, such a defect address is stored by a device called a fuse (FUSE) in accordance with whether the fuse is cut or not. That is, switching between a defective memory cell and a memory cell for defect relief is performed by cutting a fuse connected to the address switching circuit. Although there are various types of fuses, a fuse that can be cut by current / voltage is referred to as an electrically blown fuse.

  Japanese Unexamined Patent Application Publication No. 2005-39220 (Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2005-57186 (Patent Document 2) disclose a technique for cutting a fuse mounted on a semiconductor substrate with a smaller current or voltage. Has been. Patent Document 1 shows a structure in which a plurality of conductors constituting a fuse are folded back. Patent Document 2 shows a structure in which a fuse is surrounded by a conductive plate. All of these structures facilitate cutting the fuse by accumulating heat generated in the fuse when a current is passed through the fuse.

JP-A-2005-39220 JP 2005-57186 A

  The present inventors have studied an electric fusing type (electric cutting type) fuse (FUSE) disposed in a layer among a plurality of wiring layers (multilayer wiring) formed on the main surface of the semiconductor substrate. ing. This electric fusing type fuse stores 1-bit information in accordance with cutting / non-cutting, and is used for repairing defects such as memory cells using the stored data.

  This electric fusing type fuse (hereinafter, simply referred to as “fuse”) cuts (cuts) the wiring by passing a current through the wiring (fuse wiring) constituting the fuse and raising the wiring temperature. For this reason, the possibility of cutting is greatly affected by the resistance of the fuse itself. That is, when the actual fuse shape (minimum dimension) varies due to manufacturing variations and the resistance increases, the fuse cannot be cut under a predetermined cutting condition (current / voltage). Therefore, when the fuse becomes difficult to cut under a predetermined cutting condition or cannot be cut, there is a problem that the fuse cannot play a role of defect relief.

  Therefore, in order to determine whether or not a designed fuse is formed as a defect relief for a defective memory cell, a screening test such as resistance measurement is performed by passing a current through the fuse after the formation. Here, the planar shape of the fuse to be subjected to the screening test (hereinafter referred to as “test fuse”) is different from the actual planar shape of the defect repair fuse (hereinafter referred to as “rescue fuse”). The fuse is not cut. For example, when the planar shape of the relief fuse and the test fuse is a straight shape, the length is the same, the relief fuse width is different from about 0.12 μm, and the test fuse width is different from about 3 μm. . However, since the planar shapes are different, an accurate screening test such as resistance measurement cannot be performed.

  In addition, if the relief fuse and the test fuse have the same planar shape, the resistance varies due to manufacturing variations, so the test cannot be performed under a predetermined cutting condition, and the test is performed under the predetermined cutting condition. Doing so may break the test fuse.

  An object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Another object of the present invention is to provide a technique in which a fuse can be hardly affected by manufacturing variations.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device according to the present invention is provided in the vicinity of the first fuse and the electrofused first fuse and the second fuse provided in the intermediate layer of the multilayer wiring formed on the main surface of the semiconductor substrate. A first conductive plate and a second conductive plate provided in the vicinity of the second fuse, and the gap between the second fuse and the second conductive plate is between the first fuse and the first conductive plate. It is closer to the conductive plate.

  In the method of manufacturing the semiconductor device according to the present invention, the resistance value of the second fuse is measured by applying a predetermined current / voltage to the second fuse and measuring the resistance value of the second fuse. This is identified as the resistance value of one fuse.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the manufacturing technique of a semiconductor device of the present invention, it is an object to provide a technique in which a fuse can improve reliability as a defect relief for a memory cell or the like.

It is explanatory drawing which shows the structure of the semiconductor device in Embodiment 1 of this invention. FIG. 2 is an explanatory diagram showing a main part of the semiconductor device in FIG. 1. FIG. 2 is an explanatory diagram illustrating an equivalent circuit for one bit of the fuse macro in FIG. 1. FIG. 4 is a flowchart for cutting the fuse in FIG. 3. It is a top view of the fuse in Embodiment 1 of this invention. It is sectional drawing of the XX line in FIG. It is a top view of the fuse in Embodiment 2 of this invention. It is sectional drawing of the XX line in FIG. It is a top view of the fuse in Embodiment 3 of this invention. It is sectional drawing of the XX line in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The semiconductor device according to the first embodiment of the present invention is an electric fusing type (electric cutting type) fuse arranged in an intermediate layer of a plurality of wiring layers (multilayer wiring) formed on a main surface of a semiconductor substrate. (FUSE). This electric fusing type fuse (hereinafter simply referred to as “fuse”) stores 1-bit information according to its cutting (blowing) / non-cutting (non-blowing), and using the stored data, a memory cell, etc. It is used for defect repair. In the semiconductor device according to the first embodiment, a fuse macro is configured by gathering a plurality of fuses, and a memory macro including a memory array in which a plurality of memory cells are gathered and arranged in a matrix, for example. It is configured.

  FIG. 1 shows the configuration of the semiconductor device according to the first embodiment. A fuse macro 1 constituting a redundant circuit portion composed of memory cell columns for repairing defects and memory cell rows (arrays of rows and columns) is shared by various memory macros 2 and 3. For this reason, address information for relief and the like is supplied to each of the memory macros 2 and 3 by the fuse macro 1. The memory macros 2 and 3 include a memory array. For example, the memory macro 2 includes a DRAM (Dynamic Random Access Memory), and the memory macro 3 includes an SRAM (Static Random Access Memory). It is composed of

  FIG. 2 shows the area of the fuse 4 of the fuse macro 1. A plurality of fuses 4 constituting one bit and a plurality of determination circuits 5 are arranged side by side. A buffer storage circuit 6 is arranged in the peripheral area of the fuse 4 and the determination circuit 5 to adjust the data processing speed with the memory macros 2 and 3. Depending on whether the fuse 4 is cut or not cut, 1-bit information is stored, and defective memory cells are repaired using data such as memory cell addresses stored in the memory array.

  FIG. 3 shows an equivalent circuit for one bit of the fuse macro 1. The fuse 4 and the determination circuit 5 are connected to the drain (D) side of the field effect transistor Q for cutting the fuse 4. An AND circuit 7 is connected to the gate (G) side of the field effect transistor Q via a shifter circuit 6. The AND circuit 7 performs a logical operation based on the cutting data (relief data, etc.), the cutting bit determination data, and the cutting signal. If all these inputs are “H”, for example, the gate ( G) outputs a signal for cutting the fuse 4.

  In the first embodiment, the cutting data is cutting information stored in the flip-flop circuit 8a, and is “H” or “L”. Further, the cutting bit determination data is information on a cutting target stored in the flip-flop circuit 8b, and is set to “H” only for the cutting target. Further, the cutting signal is set to “H” for all the fuses 4. As a result, when all the inputs to the AND circuit 7 become “H”, the field effect transistor Q is turned on, a current flows through the fuse 4, and the fuse 4 is cut. In the first embodiment, the shape and the like of the fuse 4 are adjusted so that the minimum current that can cut the fuse 4 is about 20 mA.

  FIG. 4 shows a flow chart when the fuse 4 is cut. First, the presence / absence of data in the flip-flop circuit 8a shown in FIG. 3 is confirmed, and it is determined whether or not a certain fuse 4 (hereinafter referred to as “target fuse”) is to be cut. Next, it is determined whether or not the target fuse is a non-defective product / defective product. Here, whether or not the target fuse is a non-defective product / defective product is grasped from the result of a screening test performed in advance.

  Next, when the target fuse is a non-defective product, the cutting information is stored in the flip-flop circuit 8b. Thereby, all the inputs to the AND circuit 7 described above become “H”, the field effect transistor Q is turned on, a current flows through the target fuse, and the target fuse is cut. Thereafter, an operation test of the repaired memory cell is performed.

  5 and 6 show a planar shape and a cross-sectional shape of the fuse 4 in the first embodiment, respectively. 2 is an enlarged view of the main part of the fuse macro 1 shown in FIG.

  As shown in FIGS. 5 and 6, this fuse 4 has a first fuse 4a and a second fuse 4b, both of which are of an electric fusing type in which a current flows by a predetermined voltage and is cut. Each role is different.

  The semiconductor device according to the first embodiment is provided on a semiconductor substrate 11, a multilayer wiring composed of layers M1 to M6 formed on the main surface of the semiconductor substrate 11, and an intermediate layer M4 of the multilayer wiring. An electric fusing type fuse 4a, an electric fusing type fuse 4b provided in the same layer as the layer M4 and having the same shape as the fuse 4a, and a conductive plate 10a for preventing the fuse 4a from being scattered at the time of cutting; And a conductive plate 10b for preventing the fuse 4b from scattering at times. As described above, the conductive plate 10a and the conductive plate 10b are provided in the vicinity of the fuse 4a and the fuse 4b as shields for preventing the surroundings from being contaminated when cut. 5 shows the fuse 4a and the fuse 4b provided in the layer M4, but the conductive plate 10a and the layer M5 (or layer M3) provided in the layer M6 (or layer M2) are provided. A conductive plate 10b is also shown.

  The fuse 4 is made of a conductor having a width a, a length b, and a thickness c, and its planar shape is a shape (linear shape) extending in one direction (the direction of the length b) as shown in FIG. . For example, the width a is about 0.12 μm, the length b is about 8 to 10 μm, and the thickness c is about 140 to 180 μm. One of the fuses 4 is electrically connected to an electrode 9a on the VDD power supply side and the other is electrically connected to an electrode 9b on the VSS power supply side, and current is supplied to the fuse 4 by a predetermined voltage between the electrodes 9a and 9b. Flowing. Note that the width a of the fuse 4 is determined from the minimum processing size in order to facilitate cutting, and is as wide as possible until just before the fuse 4.

  As shown in FIG. 6, the fuse 4 a and the fuse 4 b are provided in a layer M <b> 4 that is an intermediate layer of, for example, six layers of multilayer wiring formed on the main surface of the semiconductor substrate 11. The semiconductor substrate 11 is made of, for example, a p-type single crystal silicon substrate, and a field effect transistor Q for cutting the fuse 4 is formed on the main surface thereof. The field effect transistor Q is, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor), and includes a gate electrode 12 made of conductive polycrystalline silicon, and n-type semiconductor regions formed on both sides in a self-aligning manner. A source / drain 13 and a gate insulating film 14 under the gate electrode 12.

  On top of this field effect transistor Q, for example, a multilayer wiring composed of six layers M1 to M6 is formed, and wirings 15a to 15f are provided in interlayer insulating films that insulate and isolate each layer. The wirings 15a to 15f are formed by, for example, a CMP (Chemical Mechanical Polishing) method, and have copper (Cu) as a main component. The wiring 15a of the layer M1 and the source / drain 13 of the field effect transistor Q are electrically connected via a contact 16, and the wirings 15a to 15f are electrically connected to each other via vias 17a to 17e. ing. As described above, the vias 17b to 17e arranged in the vicinity of the fuse 4a and the fuse 4b also serve as a shield for preventing the surroundings from being contaminated when the fuse 4a and the fuse 4b are cut.

  Such a field effect transistor Q and the multilayer wiring above it can be formed by a known technique. For example, after forming the field effect transistor Q, an interlayer insulating film is deposited to flatten the uneven step, and a connection hole is formed on the source / drain 13 and the gate electrode 12, and then the conductive film is buried, and the contact is formed. After forming 16, film formation and processing for forming the wiring 15a of the first layer M1 are performed. Next, after an interlayer insulating film is deposited and planarized on the wiring 15a, a connection hole with the wiring 15b of the second layer M2 and a wiring groove of the wiring 15b are formed, and the connection hole and the wiring groove are electrically conductive. The film is embedded to form vias 17a and wirings 15b. At this time, a CMP method is used. For the three or more layers M3 to M6, after repeating this cycle, a passivation film is deposited and an external electrode is formed.

  Of the layers M1 to M6 of the multilayer wiring, the fuse 4a and the fuse 4b are provided together with the wiring 15d in the layer M4. The fuse 4a and the fuse 4b are also formed at the same time as the wiring 15d by using the CMP method. ) As a main component. Therefore, it can be said that the fuse 4a and the fuse 4b are composed of wiring (fuse wiring). An example of an electrically blown fuse is made of polysilicon, for example. However, in order to narrow the width of the fuse wiring so that it can be easily cut, one made of copper that can be further miniaturized is more suitable.

  The layer M2 is provided with the conductive plate 10a together with the wiring 15b. The conductive plate 10a is also formed at the same time as the wiring 15b by using the CMP method, and has copper (Cu) as a main component. The layer M6 is provided with the conductive plate 10a together with the wiring 15f. The conductive plate 10a is also formed at the same time as the wiring 15f using the CMP method, and is mainly composed of copper (Cu). For this reason, it can be said that the conductive plate 10a is composed of wiring. The pair of conductive plates 10a of the layer M2 and the layer M6 is provided in the vicinity of the fuse 4a and in the upper layer M6 and the lower layer M2 of the layer M4, and prevents scattering when the fuse 4a is cut. It plays the role of

  The layer M3 is provided with the conductive plate 10b together with the wiring 15c. The conductive plate 10b is also formed at the same time as the wiring 15b by using the CMP method, and is mainly composed of copper (Cu). The layer M5 is provided with the conductive plate 10b together with the wiring 15e. The conductive plate 10b is also formed at the same time as the wiring 15e by using the CMP method, and is mainly composed of copper (Cu). Therefore, it can be said that the conductive plate 10b is composed of wiring. The pair of conductive plates 10b of the layer M3 and the layer M5 are provided in the vicinity of the fuse 4b and in the layer M5 that is the upper layer of the layer M4 and the layer M3 that is the lower layer, and are used to prevent scattering when the fuse 4b is cut. It plays the role of As will be described later, the conductive plate 10b also serves as a heat radiating plate for dissipating heat when a current flows through the fuse 4b to generate heat.

  By the way, after the field effect transistor Q, the multilayer wiring, the passivation film, the external electrode, and the like are formed, in the first embodiment, whether or not the designed fuse 4a is formed for defect relief of the defective memory cell. Therefore, a screening test such as resistance value (wiring resistance value) measurement is performed by applying a current / voltage to the fuse 4b. In the screening test, no current / voltage is applied to the fuse 4a.

  Of the fuses 4 provided in the intermediate layer M4, the fuse 4a is used for defect repair (rescue fuse) and is an electrically blown fuse. The fuse 4a serves as a redundant function for relieving a defective (defective) memory cell generated in a manufacturing process in a memory LSI such as a DRAM or a nonvolatile memory capable of electrical writing and erasing. is there. For example, when a defective memory cell is replaced with a spare, it is necessary to store an address (defective address) for specifying the defective memory cell. Such a defect address is stored by the fuse 4a in accordance with the cutting / non-cutting of the fuse 4a. That is, switching between the defective memory cell and the memory cell for defect repair is performed by cutting the fuse 4a connected to the address switching circuit. For this reason, in a situation where switching is required, the fuse 4a must be cut (blown) by a predetermined current / voltage, and the resistance value of the fuse 4a must be as designed.

  In the first embodiment, the resistance value of the fuse 4b is identified as the resistance value of the fuse 4a by measuring the resistance value of the fuse 4b in the screening test. Further, the fuse 4a that is not cut at a predetermined current / voltage is detected from the identified resistance value. Thus, it is possible to determine whether or not the fuse 4a is an element having a function for defect repair, that is, whether it is a good product or a defective product, without applying a predetermined current / voltage to the fuse 4a.

  When the resistance value of the fuse 4a increases due to manufacturing variations, the fuse cannot be cut under a predetermined cutting condition (current / voltage), and such a semiconductor device cannot perform a normal function. However, since the defective fuse 4a is determined and removed by the screening test in the first embodiment, a semiconductor device having the fuse 4a determined as a non-defective product can be formed. For this reason, the reliability and manufacturing yield of the semiconductor device can be improved.

  On the other hand, the fuse 4b of the fuses 4 is used for a screening test (testing fuse), and is an electrically blown fuse having the same shape as the fuse 4a. The fuse 4b serves to determine whether or not the fuse 4a is cut under a predetermined cutting condition as defect relief for the defective memory cell. Specifically, a screening test is performed on the fuse 4b under a predetermined cutting condition, the measured resistance value of the fuse 4b is identified as the resistance value of the fuse 4a, and if the resistance value is within a predetermined range, the fuse It is determined that 4a is cut under a predetermined cutting condition.

  By the way, the fuse 4b that is a test fuse is not cut even if a screening test is performed under a predetermined cutting condition in which the fuse 4a that is a relief fuse is cut. That is, even if a screening test is performed on the fuse 4b having the same resistance value as that of the fuse 4a under a predetermined cutting condition, the fuse 4b is not cut. In the first embodiment, as shown in FIG. 6, a pair of conductive plates 10b are provided in the upper layer M5 and the lower layer M3 of the fuse 4b provided in the layer M4. Therefore, even when a current / voltage is applied to the fuse 4b under a predetermined cutting condition and the fuse 4b generates heat, the conductive plate 10b serves as a heat dissipation plate to dissipate the heat generated by the fuse 4b, thereby cutting the fuse 4b. This is thought to be difficult. In other words, by providing the conductive plate 10b in the vicinity of the fuse 4b, it is considered that heat from the fuse 4b is not easily accumulated and the fuse 4b is difficult to cut. Therefore, the conductive plate 10b has a role of dissipating heat in addition to preventing the above-described fuse 4b from being scattered when the fuse 4b is cut.

  On the other hand, a pair of conductive plates 10a are provided in the upper layer M6 and the lower layer M2 of the fuse 4a provided in the layer M4. However, the conductive plate 10a is considered to play a greater role in preventing scattering when the fuse 4a is cut than by dissipating heat.

  As shown in FIGS. 5 and 6, the shapes of the conductive plate 10a and the conductive plate 10b are the same, but the layers on which they are provided are different. That is, the distance between the fuse 4b and the conductive plate 10b (distance y2) is closer than the distance between the fuse 4a and the conductive plate 10a (distance y1). For example, the distance y1 is about 600 μm, and the distance y2 is about 200 μm.

  Due to this conductive plate 10b, there is little effect of accumulating heat generated in the fuse 4b when a current / voltage is applied to the fuse 4b, and the fuse 4b is not easily cut, but is unlikely to be cut.

  Therefore, by arranging the fuse 4b, which is the same shape as the relief fuse 4a, but cannot be cut, the current flowing through the fuse 4a under a predetermined cutting condition can be measured and screened. It is possible to detect a memory macro including the fuse 4a having an unbreakable resistance value that was found during the test. Further, the screening test time can be shortened by feeding back the result.

(Embodiment 2)
In the first embodiment, in the intermediate layer of the multilayer wiring, between the first fuse (rescue fuse) and the nearest wiring, the second fuse (test fuse) and the nearest wiring An explanation has been given of the case where the interval is equal. In the second embodiment, a case where the distance between the first fuse and the nearest wiring is closer than between the second fuse and the nearest wiring will be described. The rest is the same as in the first embodiment, and a description thereof will be omitted.

  7 and 8 show a planar shape and a cross-sectional shape of the fuse 4 in the second embodiment, respectively. Note that the main part of the fuse macro 1 shown in FIG. 2 is enlarged and shown in FIG.

  As shown in FIGS. 7 and 8, the fuse 4 has a first fuse 4a and a second fuse 4b, both of which are of an electric fusing type in which a current flows by a predetermined voltage and is cut.

  The semiconductor device according to the second embodiment is provided in a semiconductor substrate 11, a multilayer wiring composed of layers M1 to M6 formed on the main surface of the semiconductor substrate 11, and an intermediate layer M4 of the multilayer wiring. An electric fusing type fuse 4a, an electric fusing type fuse 4b provided in the same layer as the layer M4 and having the same shape as the fuse 4a, and a conductive plate 10a for preventing the fuse 4a from being scattered at the time of cutting; And a conductive plate 10b for preventing the fuse 4b from scattering at times. Furthermore, the wiring line 15e closest to the fuse 4a is provided in the layer M4, and the wiring line 20e closest to the fuse 4b is provided in the layer M4. As described above, the conductive plate 10a and the conductive plate 10b are provided in the vicinity of the fuse 4a and the fuse 4b as shields for preventing the surroundings from being contaminated when cut. FIG. 7 shows the fuse 4a and the fuse 4b provided in the layer M4, but they are provided in the conductive plate 10a and the layer M5 (or layer M3) provided in the layer M6 (or layer M2). A conductive plate 10b is also shown.

  As shown in FIG. 8, the distance between the fuse 4b and the wiring 20 (distance x2) is closer than the distance between the fuse 4a and the wiring 20 (distance x1). For example, the distance x1 is about 2 μm, and the distance x2 is about 0.4 μm. As will be described later, the manufacturing variation of the fuse 4a can be prevented by providing the wiring 20 in the vicinity of the fuse 4b.

  The fuse 4 is made of a conductor having a width a, a length b, and a thickness c. As shown in FIG. 7, the planar shape is a shape (linear shape) extending in one direction (direction of the length b). . For example, the width a is about 0.12 μm, the length b is about 10 μm, and the thickness c is about 140 to 180 μm. One of the fuses 4 is electrically connected to an electrode 9a on the VDD power supply side and the other is electrically connected to an electrode 9b on the VSS power supply side, and current is supplied to the fuse 4 by a predetermined voltage between the electrodes 9a and 9b. Flowing. Note that the width a of the fuse 4 is determined from the minimum processing size in order to facilitate cutting, and is as wide as possible until just before the fuse 4.

  Among the multilayer wiring layers M1 to M6, the layer M4 is provided with the fuse 4a, the fuse 4b, and the wiring 20 together with the wiring 15d. The fuse 4a, the fuse 4b, and the wiring 20 are also connected to the wiring 15d by using the CMP method. It is formed at the same time and has copper (Cu) as a main component. Therefore, it can be said that the fuse 4a and the fuse 4b are composed of wiring (fuse wiring).

  The wiring 20 is an electrically independent dummy wiring, and is not electrically connected to, for example, the fuse 4b and the wiring 15d, and is disposed between the fuse 4a and the wiring 15d in the layer M4. By making the wiring 20 electrically independent in this way, it is possible to prevent a short circuit through the wiring 20 even when the fuse 4b is cut at the time of the test and scattered to reach the wiring 20. it can.

  Thus, the fuse 4a, which is a relief fuse, is composed of a wiring with a minimum processing dimension in order to facilitate cutting. Further, in order to prevent peripheral contamination when the fuse 4a is cut, the fuse 4a is arranged at a certain distance from the adjacent wiring 15d, and therefore is in a sparse state. Further, as shown in FIG. 2, the fuses 4a arranged at both ends of the fuse array are concerned with the influence of manufacturing variations such as flattening.

  Therefore, as shown in the second embodiment, the fuses 4b as test fuses are arranged at both ends of the fuse row, and the electrically independent wiring 20 is arranged between the fuse 4b and the wiring 15d. Thus, the layer M4 can be planarized. That is, manufacturing variations in the shape of the fuse 4a can be reduced.

(Embodiment 3)
In the first embodiment, the linear fuse whose planar shape extends in one direction has been described. In the third embodiment, a fuse having a shape in which the planar shape extends in one direction and then turns back at least once will be described. The rest is the same as in the first embodiment, and a description thereof will be omitted.

  9 and 10 show the planar shape and the cross-sectional shape of the fuse 4 in the third embodiment, respectively. Note that the main part of the fuse macro 1 shown in FIG. 2 is enlarged and shown in FIG.

  As shown in FIG. 9 and FIG. 10, the fuse 4 has a first fuse 4a and a second fuse 4b, both of which are of an electric fusing type in which a current flows by a predetermined voltage and is cut. Each role is different.

  The semiconductor device according to the third embodiment is provided on a semiconductor substrate 11, a multilayer wiring composed of layers M1 to M6 formed on the main surface of the semiconductor substrate 11, and an intermediate layer M4 of the multilayer wiring. An electric fusing type fuse 4a, an electric fusing type fuse 4b provided in the same layer as the layer M4 and having the same shape as the fuse 4a, and a conductive plate 10a for preventing the fuse 4a from being scattered at the time of cutting; And a conductive plate 10b for preventing the fuse 4b from scattering at times. As described above, the conductive plate 10a and the conductive plate 10b are provided in the vicinity of the fuse 4a and the fuse 4b as shields for preventing the surroundings from being contaminated when cut. 9 shows the fuse 4a and the fuse 4b provided in the layer M4, but the conductive plate 10a and the layer M5 (or layer M3) provided in the layer M6 (or layer M2) are provided. A conductive plate 10b is also shown.

  The fuse 4 is made of a conductor and has a shape in which the planar shape extends in one direction and then turns back at least once as shown in FIG. One of the fuses 4 is electrically connected to an electrode 9a on the VDD power supply side and the other is electrically connected to an electrode 9b on the VSS power supply side, and current is supplied to the fuse 4 by a predetermined voltage between the electrodes 9a and 9b. Flowing. In the present application, “turning back” refers to a portion (corner portion) that turns back more than 90 degrees in the planar shape of the fuse 4.

  Of the multilayer wiring layers M1 to M6, the layer M4 is provided with a fuse 4a and a fuse 4b together with the wiring 15d. The fuse 4a and the fuse 4b are also formed at the same time as the wiring 15d using the CMP method, and copper ( Cu) as a main component. Therefore, it can be said that the fuse 4a and the fuse 4b are composed of wiring (fuse wiring).

  As described above, the fuse 4 according to the third embodiment is kept at a relatively high temperature when the voltage / current is applied as compared with the linear shape only by adopting a planar shape having a corner portion. Therefore, the fuse 4a can be cut by a smaller voltage / current, and for example, the reliability of a semiconductor device having a memory macro can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the planar shape of the relief fuse and the test fuse is a shape that extends in one direction or a shape that extends in one direction and then turns back at least once, but the shape of each fuse is If it is the same.

  Further, for example, in the first embodiment, the case where the test fuses are provided at both ends of the fuse array composed of the fuses for repair has been described. However, the present invention is not limited to the both ends of the fuse array. It can also be applied within.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 1 Fuse macro 2, 3 Memory macro 4, 4a, 4b Fuse 5 Judgment circuit 6 Shifter circuit 7 AND circuit 8a, 8b Flip-flop circuit 9a, 9b Electrode 10a, 10b Conductive plate 11 Semiconductor substrate 12 Gate electrode 13 Source / drain 14 Gate Insulating films 15a, 15b, 15c, 15d, 15e, 15f Wiring 16 Contact 17 Via 20 Wiring M1, M2, M3, M4, M5, M6 Layer Q Field effect transistor

Claims (9)

A semiconductor substrate;
Multilayer wiring formed on the main surface of the semiconductor substrate;
Provided in an intermediate layer of the multilayer wiring;
An electric fusing type second fuse having the same shape as the first fuse, provided in the same layer as the intermediate layer;
A pair of first conductive plates provided in the vicinity of the first fuse and in the upper and lower layers of the intermediate layer;
A method of manufacturing a semiconductor device having a pair of second conductive plates provided in the vicinity of the second fuse and in an upper layer and a lower layer of the intermediate layer,
A resistance value of the second fuse is identified as a resistance value of the first fuse by applying a predetermined current / voltage to the second fuse and measuring a resistance value of the second fuse. A method for manufacturing a semiconductor device.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first fuse that is not cut at the predetermined current / voltage is detected.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a distance between the second fuse and the second conductive plate is smaller than a distance between the first fuse and the first conductive plate. . A first wiring provided in the intermediate layer and nearest to the first fuse;
A second wiring provided in the intermediate layer and nearest to the second fuse and electrically independent;
The method of manufacturing a semiconductor device according to claim 1, wherein a distance between the second fuse and the second wiring is smaller than a distance between the first fuse and the first wiring.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first fuse, the second fuse, the first wiring, and the second wiring are simultaneously formed using a CMP method.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the first fuse, the second fuse, the first wiring, and the second wiring are mainly composed of copper. In the intermediate layer,
A plurality of the first fuses arranged in a row;
5. The method of manufacturing a semiconductor device according to claim 4, wherein the second fuse is disposed at an end of the row.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first fuse and the second fuse have a planar shape extending in one direction.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first fuse and the second fuse have shapes in which a planar shape extends in one direction and then turns back at least once. 3.

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