JP2012145619A - Method of manufacturing electro-optic device and electro-optic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress electrostatic breakdown of a transistor.SOLUTION: A method for manufacturing an electro-optic device has steps of: forming a first transistor on a substrate; forming a first insulation film on the substrate on which the first transistor is formed; etching the first insulation film to form a first through hole connecting to the first transistor; forming a first conductor film having a first part which is connected to the first transistor via the first through hole and a second part which is not connected to the first part on the first insulation film ; forming a second insulation film on the first conductor film; etching the second insulation film to form a second through hole and a third through hole connecting to each of the first part and the second part of the first conductor film; and forming a second conductor film for electrically connecting the first part and the second part of the first conductor film through the second through hole and the third through hole on the second insulation film.

Description

  The present invention relates to a technique for suppressing electrostatic breakdown during manufacture of an electro-optical device.

The electrostatic breakdown of transistors during the production of electro-optical devices such as liquid crystal display devices has become a problem. Patent Document 1 discloses a technique of forming a short-circuit wiring for preventing electrostatic breakdown and then cutting the short-circuit wiring.

JP-A-11-95257

In Patent Document 1, it is necessary to introduce a new process for cutting the short-circuit wiring after the formation of the transistor, and there is a problem that the process becomes complicated.
The present invention provides a technique for suppressing electrostatic breakdown of a transistor without introducing a process for forming and cutting a short-circuit wiring.

The present invention provides a transistor forming step of forming a first transistor on a substrate, a first insulating film forming step of forming a first insulating film on the first transistor, and the first insulating film through the first insulating film. A first conductor film forming step of forming a first conductor film having a first portion connected to a transistor and a second portion electrically separated from the first portion on the first insulating film;
A second insulating film forming step of forming a second insulating film on the first conductive film; and electrically connecting the first portion and the second portion of the first conductive film through the second insulating film. And a second conductor film forming step of forming a second conductor film to be connected on the second insulating film.
According to this manufacturing method, the electrostatic breakdown of the first transistor based on the antenna effect of the wiring pattern using the first conductor film can be suppressed without introducing a process of forming and cutting the short-circuit wiring. .

In a preferred aspect, in the first conductor film, no other conductor film of the same layer may exist between the first portion and the second portion.
According to this manufacturing method, bridge connection is not performed in order to avoid other wiring, but is divided in order to avoid an antenna effect, and then bridge connection is performed. Therefore, electrostatic breakdown of the first transistor based on the antenna effect of the wiring pattern using the first conductor film can be suppressed without introducing a process of forming and cutting the short-circuit wiring.

In another preferred embodiment, the first transistor has a source electrode, and has a resistance forming step of forming a resistance element having one end connected to the source electrode before the first insulating film forming step, The first through hole may communicate with the other end of the resistance element.
According to this manufacturing method, electrostatic breakdown through the source electrode of the first transistor can be suppressed.

In still another preferred aspect, the resistance value of the resistance element may be larger than the channel resistance of the first transistor.
According to this manufacturing method, electrostatic breakdown through the source electrode of the first transistor can be suppressed.

In still another preferred embodiment, the resistance value of the resistance element may be 1 kΩ or more.
According to this manufacturing method, electrostatic breakdown through the source electrode of the first transistor can be suppressed.

In still another preferred embodiment, the first portion and the second portion of the first conductive film may be used as a lead wiring.
According to this manufacturing method, electrostatic breakdown based on the antenna effect of the routing wiring can be suppressed.

In still another preferred embodiment, at least one of the first conductor film and the second conductor film may be used as a capacitor electrode or a shield electrode.
According to this manufacturing method, the electrostatic breakdown of the first transistor can be suppressed by using the conductor film used as another wiring pattern.

In still another preferred embodiment, in the transistor forming step, a second transistor constituting a pixel may be formed in addition to the first transistor.
According to this manufacturing method, when the second transistor constituting the pixel and the first transistor not constituting the pixel are manufactured by the same process, electrostatic breakdown of the first transistor can be suppressed.

According to another aspect of the present invention, there is provided a substrate, a transistor formed on the substrate, a first insulating film formed on the substrate on which the transistor is formed, and the first insulating film. A first through hole that communicates, a first portion connected to the transistor through the first through hole, and a second portion that is not connected to the first portion;
A first conductor film formed on the insulating film, a second insulating film formed on the first conductor film, and a second insulating film formed on the second insulating film and leading to the first portion of the first conductor film. A second through hole, and the second
A third through hole formed in the insulating film and leading to the second portion of the first conductor film; and formed on the second insulating film, through the second through hole and the third through hole, An electro-optical device having a first conductor film and a second conductor film that electrically connects the first portion and the second portion of the first conductor film is provided.
According to the electro-optical device, the electrostatic breakdown of the first transistor based on the antenna effect of the wiring pattern using the first conductor film can be suppressed without introducing a process of forming and cutting the short-circuit wiring. it can.

1 is a diagram illustrating a configuration of an electro-optical device 1 according to an embodiment. The figure which shows the equivalent circuit of the pixel P. 3 is a schematic diagram showing a cross-sectional structure of the electro-optical device 1. FIG. 3 is a flowchart showing a method for manufacturing the element substrate 10. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the element substrate 10. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of the element substrate 10. It is a figure explaining the problem of the electrostatic breakdown which concerns on a prior art. The cross-sectional schematic diagram explaining the manufacturing process of periphery routing wiring. The cross-sectional schematic diagram explaining the manufacturing process of periphery routing wiring. The cross-sectional schematic diagram explaining the manufacturing process of periphery routing wiring. FIG. 9 is a schematic cross-sectional view of an electro-optical device 1 according to Modification 1. FIG. 6 is a schematic cross-sectional view of an electro-optical device 1 according to Modification 2.

1. Configuration FIG. 1 is a diagram illustrating a configuration of an electro-optical device 1 according to an embodiment. FIG. 1A is a diagram schematically illustrating a planar configuration of the electro-optical device 1. FIG.1 (b) is a figure which shows typically the cross-sectional structure of the cut surface in the FF 'line | wire of Fig.1 (a). The electro-optical device 1 includes an element substrate 10 and
The counter substrate 20 and the liquid crystal layer 50 are included. The electro-optical device 1 is a liquid crystal device used as a light valve of a liquid crystal projector, for example.

The electro-optical device 1 includes an element substrate 10, a counter substrate 20, and a liquid crystal layer 50. The element substrate 10 has a transparent substrate such as glass or quartz. The element substrate 10 is the counter substrate 2.
More than 0, specifically, the depth (the length when viewing from F to F ′) is long. Since the element substrate 10 and the counter substrate 20 are aligned on the back side (F ′ side), the element substrate 10 protrudes on the near side (F side). This protruding portion functions as the terminal portion 10a. A terminal 104 is provided in the terminal portion 10a.

The counter substrate 20 has a transparent substrate such as glass or quartz. The element substrate 10 and the counter substrate 20 are connected by a sealing material 40 arranged in a frame shape. Element substrate 1
A liquid crystal layer 50 is sealed between 0 and the counter substrate 20.

Of the surface of the element substrate 10 on the liquid crystal layer 50 side, inside the portion surrounded by the sealing material 40,
A pixel region E is provided. In the pixel region E, a plurality of pixels P are arranged in a matrix. In the element substrate 10, a data line driving circuit 180 and a scanning line driving circuit 102 are provided between the sealing material 40 and the pixel region E. Data line drive circuit 1
80 and the scanning line driving circuit 102 are TFTs (Thin Film Trs) formed on the element substrate 10.
ansistor). The data line driving circuit 180 is provided along the side facing the terminal portion 10a. Two scanning line driving circuits 102 are provided along each of two sides orthogonal to this side. The terminal 104 is a terminal for inputting a signal from an external circuit. The terminal 104 is connected to the data line driving circuit 180 and the scanning line driving circuit 102 through the wiring 105a. The two scanning line driving circuits 102 are connected by a wiring 105b.

On the surface of the element substrate 10 on the liquid crystal layer 50 side, the pixel electrode 70, the TFT 30, and the alignment film 18 are formed.
And signal lines are formed. The pixel electrode 70 is provided for each pixel P. TFT
Reference numeral 30 denotes a switching element that controls data writing to the pixel electrode 70, that is, voltage application. The alignment film 18 is a film for giving a predetermined azimuth angle and pretilt angle to liquid crystal molecules, and is formed of, for example, an organic material such as polyimide or an inorganic material such as silicon oxide.

On the surface of the counter substrate 20 on the liquid crystal layer 50 side, a parting portion 21, a planarization layer 22, a common electrode 23, and an alignment film 24 are formed. The parting unit 21 is provided to shield the peripheral circuit from light in order to prevent optical malfunction in the peripheral circuit (data line driving circuit 180, scanning line driving circuit 102, etc.). The parting portion 21 is formed of a metal material such as Ni or Cr, a metal compound such as an oxide thereof, or a resin containing a light-shielding pigment. The parting part 21 is formed in a frame shape so as to overlap the peripheral circuit in a plan view. The planarization layer 22 has a parting portion 21.
Is a layer for planarizing the counter substrate 20 formed with, for example, an inorganic material such as silicon oxide or an organic material such as an acrylic resin, and is formed of a light-shielding material.
The common electrode 23 is formed using a material having transparency and conductivity, such as ITO. The alignment film 24 is the same as the alignment film 18.

The common electrode 23 is electrically connected to the wiring 105 c of the element substrate 10 by conducting portions 106 provided at the four corners of the counter substrate 20. The wiring 105 c extends to the terminal portion 10 a and is connected to the terminal 104.

The wiring 105a, the wiring 105b, and the wiring 105c are formed of a metal material such as Al or an alloy thereof, for example. The terminal 104 is obtained by further applying Au plating to Al. In the terminal portion 10a, the wiring 105a and the wiring 10 are so exposed that only the terminal 104 is exposed.
5b and the wiring 105c are covered with a protective film (not shown).

FIG. 2 is a diagram illustrating an equivalent circuit of the pixel P. The electro-optical device 1 includes m scanning lines 3a,
n data lines 6a. The scanning line 3a and the data line 6a are electrically insulated and arranged in directions perpendicular to each other. When viewed from the plane of FIG. 1A, the pixel P has the scanning line 3.
It is provided corresponding to the intersection of a and the data line 6a. That is, the pixels P are arranged in a matrix of m rows and n columns. The scanning line driving circuit 102 applies to each of the m scanning lines 3a.
Operation signals SC1, SC2, SC3,..., SCm are supplied. The operation signal SC is a signal that sequentially becomes H (High) level exclusively. The data line driving circuit 180 includes n data lines 6a.
Are supplied with data signals D1, D2, D3,..., Dn indicating images.

The pixel P includes a TFT 30, a liquid crystal layer 50, and a storage capacitor 60. The gate electrode of the TFT 30 is connected to the scanning line 3a. The source electrode of the TFT 30 is connected to the data line 6a. The drain electrode of the TFT 30 is connected to the pixel electrode 70. Liquid crystal layer 5
0 is sandwiched between the pixel electrode 70 and the common electrode 23. The liquid crystal molecules of the liquid crystal layer 50 are aligned according to the potential difference between the pixel electrode 70 and the common electrode 23. A voltage is applied to the common electrode 23 via the common potential line LCCOM. One end of the storage capacitor 60 is connected to the pixel electrode 70, and the other end is connected to the capacitor line 3b. That is, the storage capacitor 60 is connected to the liquid crystal layer 50 in parallel. A voltage VCOM is applied to the capacitance line 3b from an external circuit. That is, the storage capacitor 60 holds a charge corresponding to the potential difference between the pixel electrode 70 and the capacitor line 3b. When the H level scanning signal SC is input, the TFT 30 is turned on, and the scanning line 3a and the pixel electrode 70 are brought into conduction. At this time, the data signal D supplied to the data line 6a
A voltage corresponding to is written into the pixel electrode 70. The liquid crystal layer 50 and the storage capacitor 60 hold the written voltage for a certain period.

FIG. 3 is a schematic diagram showing a cross-sectional structure of the electro-optical device 1 (particularly in the vicinity of the element substrate 10). The element substrate 10 has a multilayer wiring structure in which a semiconductor layer and a plurality of wiring layers are formed on a substrate 101. In this example, the electro-optical device 1 includes the semiconductor layer 1 in order from the side closer to the substrate 101.
1 has a so-called three-layer wiring structure having a first wiring layer 13, a second wiring layer 15, and a third wiring layer 17. Each layer is insulated by an interlayer insulating film.

The semiconductor layer 11 includes a light shielding film 111, an insulating film 112, a semiconductor film 113, an insulating film 114, and a conductor film 115. The light shielding film 111 is a film that defines an opening region of each pixel P. The light shielding film 111 is formed of a metal film such as Ti (titanium) or Cr (chromium), for example,
It is patterned in a lattice shape in a plane. The insulating film 112 is a layer serving as a base on which the semiconductor film 113 is formed. The insulating film 112 is made of, for example, silicon oxide. The semiconductor film 113 includes a channel region 113c that functions as a channel of the TFT 30, a source region 113s that functions as a source, and a drain region 113d that functions as a drain. The semiconductor film 113 is made of, for example, polycrystalline silicon (polysilicon).
The insulating film 114 functions as a gate insulating film of the TFT 30. The insulating film 114 is made of, for example, S
It is formed of iO ₂ (silicon oxide). The conductor film 115 is formed by the scanning line 3a or the TFT 3
It has a gate electrode 115g that functions as a zero gate electrode and a resistor 115r that functions as a resistance element. The conductor film 115 is made of, for example, conductive polysilicon. In FIG. 3, in order to prevent the drawing from being complicated, the insulating film 114 is drawn only on the TFT 30, but actually, the insulating film 114 and the conductor film 115 are below the insulating film 114. It is formed over the entire surface.

The interlayer insulating film 12 is a layer for insulating the semiconductor layer 11 and the first wiring layer 13. The interlayer insulating film 12 is made of, for example, silicon oxide. A contact hole 121 and a contact hole 122 are provided in the interlayer insulating film 12. Contact hole 121
The contact hole 122 is a hole penetrating the interlayer insulating film 12 and the insulating film 114 and is used for electrical connection between the semiconductor layer 11 and the first wiring layer 13. In FIG. 3, the contact hole 121 and the contact hole 122 are drawn so as not to penetrate the insulating film 114 in order to prevent the drawing from becoming complicated. The insulating film 114 is penetrated. The same applies to other drawings.

The first wiring layer 13 includes a conductor film 131, a dielectric film 132, and a conductor film 133. The conductive film 131 is an electrode for obtaining electrical connection with the semiconductor layer 11 through the contact hole 121 or the contact hole 122. Further, the conductor film 131 may be used as one electrode in the capacitor. The conductor film 131 is made of, for example, conductive polysilicon. The dielectric film 132 is made of, for example, silicon oxide and functions as a dielectric in the capacitor element. The capacitor electrode 133e is used as the other electrode of the capacitor. The data line 6a and the capacitor electrode 133e are made of, for example, Al (aluminum).

The interlayer insulating film 14 is a layer for insulating the first wiring layer 13 and the second wiring layer 15. The interlayer insulating film 14 is made of, for example, silicon oxide. A contact hole 141 and a contact hole 142 are provided in the interlayer insulating film 14. Contact hole 14
1 and the contact hole 142 are holes penetrating the interlayer insulating film 14, and the first wiring layer 1
3 and the second wiring layer 15 are used for electrical connection.

The second wiring layer 15 has a conductor film 151. The conductor film 151 includes a shield electrode 151s and a relay electrode 151b. The shield electrode 151s functions as a shield that shields electromagnetic waves. The relay electrode 151b includes an upper layer (third wiring layer 17) and a lower layer (first wiring layer 13).
It is an electrode which relays electrical connection with. The shield electrode 151s and the relay electrode 151b are made of, for example, aluminum.

The interlayer insulating film 16 is a layer for insulating the second wiring layer 15 and the third wiring layer 17. The interlayer insulating film 16 is made of, for example, silicon oxide. A contact hole 161 is provided in the interlayer insulating film 16. The contact hole 161 is a hole that penetrates the interlayer insulating film 16 and is used for electrical connection between the second wiring layer 15 and the third wiring layer 17.

The third wiring layer 17 has a conductor film 171. The conductor film 171 functions as the pixel electrode 70. The conductor film 171 is made of ITO. An alignment film 18 is formed on the third wiring layer 17.

2. Manufacturing Method FIG. 4 is a flowchart showing a manufacturing method of the element substrate 10, and FIGS. 5 and 6 are schematic cross-sectional views illustrating manufacturing steps of the element substrate 10.
In step S1 (light-shielding film forming step), a metal film is formed on the substrate 101 by sputtering using Ti or Cr as a target. The formed metal film is patterned to form a light shielding film 111 (FIG. 5A).
In step S2 (insulating film formation process), plasma CVD (Chemical Vapor Deposit)
An insulating film 112 is formed by depositing silicon oxide by a vapor phase process such as ion). The insulating film 112 is formed so as to cover the substrate 101 and the light shielding film 111 (FIG. 5B).
The insulating film 112 has a thickness of about 200 nm to 400 nm.

In step S3 (semiconductor film formation step), the low pressure chemical vapor deposition (Low Pressure Che
An amorphous silicon film is formed by mical vapor deposition (hereinafter referred to as LPCVD) or plasma CVD. The amorphous silicon film is subjected to heat treatment, and the amorphous silicon film is polycrystallized. Thus, a polysilicon film is formed. Impurities (such as phosphorus) are selectively implanted into the polysilicon film to form a source region 113s, a drain region 113d, and a channel region 113c.
In step S4 (gate insulating film forming step), silicon oxide is deposited by a vapor phase process such as plasma CVD to form the insulating film 114 as a gate insulating film (FIG. 5C).
. The thickness of the insulating film 114 is approximately 20 nm to 50 nm.

In step S5 (gate electrode forming step), a conductive polysilicon film is formed by LPCVD. The polysilicon film is patterned to form the gate electrode 115g or the resistor 115r (FIG. 5D).
In steps S1 to S5, in addition to the pixel circuit structure, peripheral circuit structures are also formed.

In step S6 (interlayer insulating film forming step), silicon oxide is deposited by PECVD to form the interlayer insulating film 12 (FIG. 5E). The thickness of the interlayer insulating film 12 is about 1
400 nm.
In step S7 (CMP process), the interlayer insulating film 12 is subjected to CMP (Chemical Mechanica
l Polishing) and flattened.
In step S8 (etching process), HF, CHF3, CF4, or SF6
The interlayer insulating film 12 is etched by dry etching using a gas such as the above or a mixed gas thereof as an etching gas. Thus, the contact hole 121 and the contact hole 122 are formed (FIG. 6A). In this example, the contact hole 121
Leads to the source region 113s, and the contact hole 122 leads to the drain region 113d.

In step S9 (relay electrode forming step), a conductive polysilicon film is formed on the interlayer insulating film 12 as the conductor film 131 by the LPCVD method. Conductive polysilicon is also formed in the contact hole 121 and the contact hole 122. The conductor film 131 is patterned (FIG. 6B). The thickness of the conductive polysilicon film is approximately 100 nm.
In step S10 (dielectric film forming step), a silicon oxide film is formed as the dielectric film 132 by plasma CVD. The dielectric film 132 is formed so as to cover the conductor film 131. The thickness of the dielectric film 132 is approximately 50 nm to 100 nm.
In step S11 (etching step), for the portion for forming the data line 6a,
The dielectric film 132 is removed by dry etching.

In step S12 (data line / capacitor line forming step), a conductive polysilicon film is formed. Further, an aluminum film is formed on the conductive polysilicon film. Thus, a film having a two-layer structure of conductive polysilicon and aluminum is formed as the conductor film 133. The conductor film 133 is patterned to form the data line 133d and the capacitor electrode 133e. The thickness of the conductor film 133 is approximately 200 nm to 400 nm.

In step S13 (interlayer insulating film forming step), silicon oxide is deposited by the plasma CVD method, and the interlayer insulating film 14 is formed. The thickness of the interlayer insulating film 14 is approximately 400 nm.
To 600 nm.
In step S14 (etching process), the interlayer insulating film 1 is dry-etched.
4 is etched. By etching, a contact hole 141 and a contact hole 142 are formed. In this example, the contact hole 141 communicates with the conductor film 131 that functions as one electrode of the capacitor. The contact hole 142 leads to the capacitive electrode 133e that functions as the other electrode of the capacitive element.

In step S15 (shield electrode / relay electrode forming step), an aluminum film is first formed, and then a titanium nitride film is formed. Thus, a film having a two-layer structure of aluminum and titanium nitride is formed as the conductor film 151. The conductor film 151 is patterned,
The shield electrode 151s and the relay electrode 151m are formed. The thickness of the conductor film 151 is approximately 200 nm to 400 nm.

In step S16 (interlayer insulating film forming step), silicon oxide is deposited by plasma CVD, and the interlayer insulating film 16 is formed. The thickness of the interlayer insulating film 16 is approximately 400 nm.
To 600 nm.
In step S17 (etching process), the interlayer insulating film 1 is formed by dry etching.
6 is etched. A contact hole 161 is formed by etching. In this example, the contact hole 161 communicates with the relay electrode 151m.

In step S18 (pixel electrode formation step), the sputtering method or the vapor deposition method is used.
An O film is formed. The ITO film is patterned to form a conductor film 171. Conductor film 1
The thickness of 71 is about 100 nm to 150 nm.
In step S19 (alignment film forming step), a droplet discharge method, flexographic printing, or CV
Polyimide is formed as an alignment film 18 by D (FIG. 6C). The alignment film 18 is subjected to a rubbing process that rubs its surface in a predetermined direction. Thus, the element substrate 10 is manufactured.

3. FIG. 7 is a diagram for explaining a problem of electrostatic breakdown according to the prior art. As shown in FIG. 1, the electro-optical device 1 has routing wiring. Here, the “lead-out wiring” is a wiring connected to a transistor in the peripheral circuit, and means a wiring having a length of 7 mm and a width of about 10 μm or more. In the case of a liquid crystal device for a 0.5 inch light valve, the display area E
The length of the wiring is equal to or longer than the short side (about 7 mm). This corresponds to input / output signal lines for supplying or outputting various input signals to the transistors in the peripheral circuit and connection wiring for connecting the transistors in the peripheral circuit. In a long wiring such as a routing wiring, a transistor constituting a peripheral circuit connected to the routing wiring may cause electrostatic breakdown due to an antenna effect in the aluminum film during patterning (etching) of the wiring. There is. The electrostatic breakdown due to the antenna effect means that charges are accumulated in the wiring layer (in this case, an aluminum film) during the process, for example, in a plasma etching step in wiring patterning, and the transistor is electrostatically broken due to the accumulated charges. As the length of the wiring is longer, charges are more likely to accumulate due to the antenna effect, and the possibility of electrostatic breakdown increases.

8, FIG. 9, and FIG. 10 are schematic cross-sectional views illustrating the manufacturing process of the lead wiring connected to the transistor of the peripheral circuit. The outline of the manufacturing method of the electro-optical device 1 has been described with reference to FIGS. 4, 5, and 6. In particular, the pixel transistor (TFT 30) has been described.
The transistors in the peripheral circuit are formed in the same process.

FIG. 8A is a diagram showing a state when step S5 (gate electrode formation step) is completed. A peripheral circuit transistor and a resistor 115r are formed. In the example of FIG. 8, in the peripheral circuit transistors, the right side in the figure is the source region 113s and the left side in the figure is the drain region 113d. The resistor 115r is formed for the purpose of suppressing electrostatic breakdown of the transistors in the peripheral circuit. The resistance value of the resistor 115r is larger than the channel resistance of the transistor in the peripheral circuit, and is, for example, 1 kΩ or more. In step S6 (interlayer insulating film forming step), the interlayer insulating film 12 is formed (FIG. 8B). Step S8 (etching process)
In FIG. 8, a contact hole 123, a contact hole 124, and a contact hole 125 are formed (FIG. 8C). The contact hole 123 communicates with the source region 113s of the peripheral circuit transistor. The contact hole 124 and the contact hole 125 communicate with one end and the other end of the resistor 115r. Here, contact hole 12
In particular, reference numeral 3 denotes a contact hole formed in a transistor of a peripheral circuit to which a lead wiring is connected. Here, in order to prevent the drawing from becoming complicated, the wiring to the drain region 113d of the transistor in the peripheral circuit is not shown.

In step S9 (relay electrode forming step), a conductor film 131 is formed on the interlayer insulating film 12 (FIG. 8D). In step S12 (data line / capacitance electrode formation step),
A conductor film 133 is formed on the conductor film 131 (FIG. 9A). Further, the conductor film 131
Then, the conductive film 133 is patterned (etched) to form an electrode (FIG. 9B).
). By the patterning, the conductor film 131 and the conductor film 133 are divided into a plurality of regions. These plural regions are fragments of the routing wiring, specifically, the first portion 501 (conductor film 13).
1a and the conductor film 133a), the second part 502 (the part consisting of the conductor film 131b and the conductor film 133b), and the third part 503 (the conductor film 131c and the conductor film 133c).
Part). Each fragment has a predetermined length (for example, 60 μm corresponding to 3 pixels).
) Has a length not exceeding. Between two adjacent pieces, there is a wiring pattern (conductor film 13).
1 or other portion of the conductor film 133 is not formed and is electrically insulated. As described above, in the electro-optical device 1, the routing wiring is divided into a plurality of pieces having a short length in the first wiring layer 13, so that it is compared with the wiring that is not divided into the plurality of pieces shown in FIG. 7. The antenna effect is difficult to occur. That is, the lead wiring of the electro-optical device 1 is less likely to accumulate charges during the etching process of the conductor film than the wiring that is not divided into a plurality of pieces. Even if the conductive film 131 and the conductive film 133 are patterned by dry etching, the conductive film 131 and the conductive film 133 are immediately divided into a plurality of regions, so that the influence of the antenna effect is not a problem. Further, in the segment of the routing wiring, between the first portion 501 and the second portion 502 and between the second portion 502 and the third portion 503,
A conductor film for forming another wiring in the same layer is not formed. That is, it is not divided in order to avoid other wiring, but is divided in order to avoid the antenna effect.

In step 13 (interlayer insulating film forming step), the interlayer insulating film 14 is formed on the conductor film 133.
Is formed (FIG. 9C). In step S14 (etching step), contact hole 143, contact hole 144, contact hole 145, and contact hole 146 are formed (FIG. 10A). The contact hole 143 has a first portion 501.
Leads to. The contact hole 144 and the contact hole 145 are formed in the second portion 50.
2 to one end and the other end. The contact hole 146 communicates with the third portion 503. In step S15 (shield electrode / intermediate electrode formation step), a conductor film 151 is formed on the interlayer insulating film 14 (FIG. 10B). The conductor film 151 is patterned,
A fourth portion 151a and a fifth portion 151b are formed. The fourth portion 151 a is a wiring that connects the first portion 501 and the second portion 502. The fifth portion 151b includes the second portion 50.
2 and the third portion 503. Thus, the lead wiring is formed using the two wiring layers of the first wiring layer 13 and the second wiring layer 15.

In summary, the manufacturing method of the electro-optical device 1 includes a transistor formation step (steps S3 to S5) for forming a first transistor (peripheral circuit transistor) on the substrate 101;
Insulating layer forming step of forming an interlayer insulating film 12 on the peripheral circuit transistor (step S6)
), A first etching step (step S8) for etching the interlayer insulating film 12 to form a first through hole (contact hole 125) leading to the first transistor, and the first transistor through the first through hole. A first conductor film that forms a first conductor film (conductor film 131 and conductor film 133) having a first part 501 connected to the first part 501 and a second part 502 not connected to the first part 501 on the interlayer insulating film 12. A forming step (step S9 and step S12), a second insulating film forming step (step S13) for forming the interlayer insulating film 14 on the first conductor film,
A second through hole (contact hole 143) and a third through hole (contact hole 144) communicating with the first portion 501 and the first portion 502 of the first conductor film are formed by etching the interlayer insulating film 14. The etching process (step S14) and the second conductor film that electrically connects the first portion 501 and the first portion 502 of the first conductor film via the second through hole and the third through hole are formed as the interlayer insulating film 14. A second conductor film forming step (step S15) to be formed thereon. In this way, since the short pieces (the first portion 501 and the first portion 502) are connected to form a long lead wiring, compared with the case where the long wiring in the single wiring layer is used as the lead wiring, Transistors are less susceptible to electrostatic breakdown.

4). Other Embodiments The present invention is not limited to the above-described embodiments, and various modifications can be made. Hereinafter, some modifications will be described. Two or more of the following modifications may be used in combination.

4-1. Modification 1
FIG. 11 is a schematic cross-sectional view of the electro-optical device 1 according to the first modification. In the embodiment, the example in which the routing wiring is a wiring connected to the source electrode of the transistor of the peripheral circuit has been described. However, the routing wiring may be connected to a wiring connected to the source electrode of the TFT 30 and an electrode other than the source electrode of the TFT 30. FIG. 11 shows an example in which the routing wiring is connected to the gate electrode of the TFT 30.

4-2. Modification 2
FIG. 12 is a schematic cross-sectional view of the electro-optical device 1 according to the second modification. In the embodiment, the example in which the length L1 of the routing wiring fragment in the first wiring layer 13 and the length L2 of the connection portion of the routing wiring in the second wiring layer 15 have a relationship of L1> L2 has been described. In other words, in the embodiment, the example in which the pieces of the lead wiring are formed in the first wiring layer 13 and these pieces are connected in the second wiring layer 15 that is higher than that is described. However, the length L
1 and the length L2 may be L1 ≦ L2. That is, a piece of routing wiring may be formed in the second wiring layer 15, and these pieces may be connected in the first wiring layer 13 below it.

4-3. Other Modifications Wiring to be subjected to the above-described electrostatic breakdown countermeasure is not limited to routing wiring. Any other wiring such as the wiring connecting the scanning lines 3a, the data lines 6a, and the driver circuits may be subjected to the above-described countermeasure against electrostatic breakdown.
In the above-described embodiment, the resistor 115r is also formed in the gate electrode formation process in step S5. That is, the gate electrode forming process also functions as a resistance forming process. However, the resistor 115r may not be formed. In this case, contact hole 12
5 is formed at a position leading to the source region 113s, and the first portion 501 and the source region 113s.
Are directly connected without a resistor 115r.

In the embodiment, the lead wiring is formed using the first wiring layer 13 and the second wiring layer 15. However, the wiring layer used as the routing wiring is not limited to this. Three wiring layers of the first wiring layer 13, the second wiring layer 15, and the third wiring layer 17 may be used as the routing wiring. Alternatively, the second wiring layer 15 and the third wiring layer 17 may be used as the lead wiring. In still another example, when the electro-optical device 1 has a multilayer wiring structure having four or more layers, two or more wiring layers of these wiring layers may be used as the routing wiring.

The manufacturing process described in FIG. 4 is merely an example, and the manufacturing process of the electro-optical device 1 is not limited to this. In addition, the materials and film forming methods used are examples, and are not limited to those described in the embodiment. For example, although the example in which the first wiring layer 13 has a two-layer structure of the conductor film 131 (polysilicon) and the conductor film 133 (aluminum) has been described, the first wiring layer 13 has, for example, an aluminum single-layer structure. May be. Alternatively, a structure in which a barrier layer such as TiN (titanium nitride) is sandwiched between polysilicon and aluminum may be used.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Element board | substrate, 11 ... Semiconductor layer, 12 ... Interlayer insulation film, 13 ... 1st wiring layer, 14 ... Interlayer insulation film, 15 ... 2nd wiring layer, 16 ... Interlayer insulation film, 17 ... 3rd wiring layer, 1
8 ... Alignment film, 20 ... Counter substrate, 21 ... Parting part, 22 ... Planarization layer, 23 ... Common electrode, 24
... alignment film, 30 ... TFT, 40 ... sealing material, 50 ... liquid crystal layer, 60 ... storage capacitor, 70 ... pixel electrode, 101 ... substrate, 102 ... scanning line drive circuit, 104 ... terminal, 106 ... conduction part, 111
... Light shielding film, 112 ... Insulating film, 113 ... Semiconductor layer, 114 ... Insulating film, 115 ... Conductive film,
DESCRIPTION OF SYMBOLS 1 ... Contact hole, 122 ... Contact hole, 123 ... Contact hole, 124
Contact hole 125 Contact hole 131 Conductor film 132 Dielectric film
133 ... conductor film, 141 ... contact hole, 142 ... contact hole, 143 ... contact hole, 144 ... contact hole, 145 ... contact hole, 146 ... contact hole, 151 ... conductor film, 161 ... contact hole, 171 ... conductor film, 180 ... data line driving circuit, 501 ... first part, 502 ... second part, 503 ... third part

Claims (9)

A transistor forming step of forming a first transistor on the substrate;
A first insulating film forming step of forming a first insulating film on the first transistor;
A first portion connected to the first transistor via the first insulating film and the first portion;
A first conductor film forming step of forming a first conductor film having a second portion electrically separated from the portion on the first insulating film;
A second insulating film forming step of forming a second insulating film on the first conductor film;
Forming a second conductor film on the second insulating film, the second conductor film electrically connecting the first portion and the second portion of the first conductor film via the second insulating film; A method for manufacturing an electro-optical device. 2. The manufacturing method according to claim 1, wherein in the first conductor film, no other conductor film of the same layer exists between the first portion and the second portion. The manufacturing method according to claim 1, further comprising a resistance forming step of forming a resistance element between the first portion and the first transistor in the first conductor film. The manufacturing method according to claim 3, wherein a resistance value of the resistance element is larger than a channel resistance of the first transistor. The manufacturing method according to claim 4, wherein the resistance value of the resistance element is 1 kΩ or more. The manufacturing method according to claim 1, wherein the first portion and the second portion of the first conductive film are used as lead wirings. The manufacturing method according to any one of claims 1 to 6, wherein at least one of the first conductor film and the second conductor film is used as a capacitor electrode or a shield electrode. 8. The manufacturing method according to claim 1, wherein, in the transistor forming step, a second transistor constituting a pixel is formed in addition to the first transistor. A substrate,
A transistor formed on the substrate;
A first insulating film formed on the substrate on which the transistor is formed;
A first through hole formed in the first insulating film and leading to the transistor;
A first conductor film formed on the first insulating film, the first conductor film having a first part connected to the transistor through the first through-hole and a second part separated from the first part;
A second insulating film formed on the first conductor film;
A second through hole formed in the second insulating film and leading to the first portion of the first conductor film;
A third through hole formed in the second insulating film and leading to the second portion of the first conductor film;
A second conductor film formed on the second insulating film and electrically connecting the first part and the second part of the first conductor film via the second through hole and the third through hole And an electro-optical device.

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