JP2012142838A - Signal shaping device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal shaping device that allows a fast operation corresponding to a high clock frequency and allows a precise duty ratio adjustment.SOLUTION: The signal shaping device has a pulse signal generation section 11 for generating a pulse signal of a predetermined pulse width, and a duty ratio adjustment section 12 for controlling the duty ratio of the pulse signal. The pulse signal generation section 11 includes a flip-flop circuit 101 for receiving a clock signal, and a delay circuit 102 for delaying an output signal of the flip-flop circuit 101 to output a single phase pulse signal having a pulse width corresponding to the delay mount. The duty ratio adjustment section 12 converts the single phase pulse signal output from the delay circuit 102 into differential pulse signals comprising a first pulse signal and a second pulse signal reversed in polarity, and controls the delay mount of the delay circuit 102 such that the pulse signal has a target duty ratio according to a difference between an average voltage of the first pulse signal and an average voltage of the second pulse signal.

Description

  The present invention relates to a signal shaping device that outputs a pulse signal shaped to an arbitrary duty ratio.

  As a signal shaping device, a flip-flop circuit that divides the clock signal input to the clock terminal ck by two at the rising timing and a flip-flop circuit that divides the clock signal input to the clock terminal ck by two at the falling timing And a delay element that delays one of the Q outputs, and an EXOR circuit that performs these EXOR operations (see, for example, Patent Document 1). In this signal shaping device, since the pulse width is corrected so as to be widened by the delay time of the delay element, a pulse signal having a predetermined duty ratio corresponding to the delay time of the delay element can be obtained.

Japanese Patent Laid-Open No. 2006-67414

  By the way, the signal shaping device can be configured to include a pulse signal generation unit 21 and a duty ratio width adjustment unit 22 as shown in FIG.

  In the pulse signal generator 21, the D flip-flop circuit 201 shapes the clock signal to generate a Q output. The Q output of the D flip-flop circuit 201 is delayed by the delay circuit 202 to become a pulse signal having an arbitrary pulse width. On the other hand, the control pulse signal generation circuit 203 generates a control pulse signal in synchronization with the falling timing of the pulse signal, and supplies the control pulse signal to the set terminal set of the D flip-flop circuit 201 through the OR circuit 204.

  In the duty ratio width adjustment unit 22, the phase comparison circuit (PFD circuit) 211 compares the phase of the clock signal with the phase of the pulse signal, and outputs the comparison result to the charge pump circuit 212. The charge pump circuit 212 accumulates charges according to the comparison result of the phase comparison circuit 211. The low-pass filter circuit 213 outputs a voltage obtained by integrating the charge accumulated in the charge pump circuit 212 to the delay circuit 202.

  FIG. 11 is a schematic diagram illustrating a configuration example of the phase comparison circuit 211 used in the duty ratio adjustment unit 22. In the phase comparison circuit 211, a clock signal is input to the clock terminal ck of one D flip-flop circuit 221, and a pulse signal is input to the clock terminal ck of the other D flip-flop circuit 222. The D flip-flop circuits 221 and 222 generate a Q output using the input clock signal and pulse signal. The Q outputs of the D flip-flop circuits 221 and 222 are input to the delay circuit 224 through the AND circuit 223, and the output of the delay circuit 224 is input to the R terminals of the two D flip-flop circuits 221 and 222 as a reset signal.

  As described above, when the signal shaping device 2 includes the pulse signal generation unit 21 and the duty ratio width adjustment unit 22, the phase comparison circuit 211 compares the phases of the clock signal and the pulse signal, and based on the comparison result. To shape the pulse signal. However, since the phase comparison circuit 211 uses the delay by the delay circuit, there is a limit to high-speed operation. For this reason, the signal shaping device 2 including the phase comparison circuit 211 is also not suitable for high-speed operation, and there is a problem that the operation frequency is limited.

  The pulse signal generated based on the clock signal is delayed with respect to the clock signal by a delay in the D flip-flop circuit 201, the control pulse signal generation circuit 203, the OR circuit 204, and the like. For this reason, in the signal shaping device 2 that compares the phase difference between the clock signal and the pulse signal and shapes the pulse signal based on the comparison result, an error occurs in the adjustment of the duty ratio by the delay of the pulse signal. That is, there is a problem that it is difficult to adjust the duty ratio with high accuracy. In addition, since the delay amount of the pulse signal is constant regardless of the signal frequency, the influence of the error increases as the frequency increases.

  The present invention has been made in view of this point, and an object of the present invention is to provide a signal shaping device capable of high-speed operation corresponding to a high clock frequency and adjusting the duty ratio with high accuracy.

  The signal shaping device of the present invention is a signal shaping device having a pulse signal generation unit that generates a pulse signal having a predetermined pulse width, and a duty ratio adjustment unit that controls a duty ratio of the pulse signal, and the pulse signal generation unit The unit includes a flip-flop circuit to which a clock signal is input, and a delay circuit that delays the output signal of the flip-flop circuit and outputs a single-phase pulse signal having a pulse width corresponding to the delay amount, The duty ratio adjusting unit converts the single-phase pulse signal output from the delay circuit into a differential pulse signal composed of a first pulse signal and a second pulse signal whose polarities are inverted with respect to each other. Based on the difference between the average voltage and the average voltage of the second pulse signal, the delay amount of the delay circuit is controlled so that the pulse signal has a target duty ratio. It is characterized in.

  According to this configuration, since the phase comparison circuit is not used for adjusting the duty ratio, a signal delay caused by the phase comparison circuit does not occur. That is, there is no limitation on the operating frequency due to the signal delay of the phase comparison circuit. For this reason, it is possible to cope with a sufficiently high clock frequency. In addition, since the duty ratio control signal is generated from the pulse signal, an error caused by the delay of the pulse signal does not occur unlike the case where the control signal is generated using the clock signal and the pulse signal. For this reason, the duty ratio can be adjusted with high accuracy. The influence of the error becomes particularly significant at a high frequency. For this reason, this configuration is extremely effective when a signal in a high frequency region is used.

  The signal shaping device of the present invention includes a plurality of pulse signal generation units that generate a pulse signal having a predetermined pulse width, and a pulse signal generation unit that is provided at an input stage of the plurality of pulse signal generation units and is to supply a clock signal. A demultiplexer that selects based on a band selection signal; a multiplexer that is provided at an output stage of the plurality of pulse signal generation units and selects a pulse signal generation unit from which a pulse signal is to be extracted based on the band selection signal; and the multiplexer A duty ratio adjusting unit for controlling a duty ratio of the pulse signal generated in the pulse signal generating unit selected in step (a), wherein each of the pulse signal generating units is a flip-flop to which a clock signal is input. Circuit and the output signal of the flip-flop circuit are delayed to have a pulse width corresponding to the delay amount A delay circuit that outputs a single-phase pulse signal, and the duty ratio adjustment unit is configured to generate a single-phase pulse signal output from the delay circuit based on a first pulse signal and a second pulse signal that have opposite polarities. A delay pulse of the delay circuit so that the pulse signal has a target duty ratio based on the difference between the average voltage of the first pulse signal and the average voltage of the second pulse signal. The operating frequency range is widened by controlling the amount and combining the plurality of pulse signal generation units.

  According to this configuration, since the phase comparison circuit is not used for adjusting the duty ratio, a signal delay caused by the phase comparison circuit does not occur. That is, there is no limitation on the operating frequency due to the signal delay of the phase comparison circuit. For this reason, it is possible to cope with a sufficiently high clock frequency. In addition, since the duty ratio control signal is generated from the pulse signal, an error caused by the delay of the pulse signal does not occur unlike the case where the control signal is generated using the clock signal and the pulse signal. For this reason, the duty ratio can be adjusted with high accuracy. Further, since the plurality of pulse signal generation units arranged in parallel are provided, a pulse signal with the duty ratio adjusted can be obtained using the pulse signal generation unit suitable for the frequency of the clock signal. For this reason, it is possible to generate a pulse signal in a sufficiently wide frequency range.

  In the signal shaping device of the present invention, the duty ratio adjustment unit controls the delay amount of the delay circuit so that a difference between the average voltage of the first pulse signal and the average voltage of the second pulse signal becomes a predetermined value. You may do it. In the signal shaping device of the present invention, the duty ratio adjuster may be configured so that a delay amount of the delay circuit is such that a difference between an average voltage of the first pulse signal and an average voltage of the second pulse signal becomes zero. May be controlled. In the signal shaping device of the present invention, the delay circuit may be configured by a voltage control delay line in which a delay amount is adjusted according to an input voltage.

  In the signal shaping device of the present invention, the duty ratio adjustment unit converts the single-phase pulse signal from the pulse signal generation unit into a differential pulse signal composed of a first pulse signal and a second pulse signal. A differential charge pump circuit that averages outputs of the single-phase differential conversion circuit and outputs an average voltage of the first pulse signal and an average voltage of the second pulse signal, and the differential charge pump circuit A duty ratio control for outputting a voltage corresponding to a difference between an average voltage of the first pulse signal and an average voltage of the second pulse signal as a duty ratio control signal for controlling a delay amount of the delay circuit. And a signal output unit.

  In the signal shaping device of the present invention, an in-phase component removal circuit for removing an in-phase component from the output of the single-phase differential conversion circuit may be provided at a subsequent stage of the single-phase differential conversion circuit.

  According to the present invention, there is provided a signal shaping device capable of high-speed operation corresponding to a high clock frequency and adjusting the duty ratio with high accuracy.

It is a block diagram which shows the structural example of the signal shaping apparatus which concerns on embodiment. It is a schematic diagram which shows the structural example and output waveform of a single phase differential conversion circuit. It is a wave form diagram which shows the signal waveform output from each circuit element of a pulse signal generation part. It is a wave form diagram which shows the signal waveform output from each circuit element of a duty ratio adjustment part. It is a graph which shows the simulation result in case the duty ratio of a clock signal is 20%. It is a graph which shows the simulation result in case the duty ratio of a clock signal is 50%. It is a graph which shows the simulation result in case the duty ratio of a clock signal is 80%. It is a block diagram which shows the structural example (The structural example using the several pulse signal generation part arrange | positioned in parallel) of the signal shaping apparatus which concerns on embodiment. It is a schematic diagram which shows the operable frequency range of a some pulse signal production | generation part. It is a block diagram which shows the structural example of a signal shaping apparatus. It is a block diagram which shows the structural example of the phase comparison circuit (PFD circuit) used for a signal shaping apparatus.

  FIG. 1 is a block diagram illustrating a configuration example of a signal shaping device according to an embodiment of the present invention. The signal shaping device 1 according to the present embodiment uses a pulse signal generation unit 11 that shapes a clock signal to generate a pulse signal with a duty ratio of 50%, and a pulse signal using the pulse signal from the pulse signal generation unit 11. A duty ratio adjusting unit 12 that generates a control signal (duty ratio control signal) used for the duty ratio control.

  The pulse signal generation unit 11 includes a D flip-flop circuit 101 that generates a rectangular wave corresponding to the clock signal, and a delay circuit 102 that delays the Q output of the D flip-flop circuit 101 in accordance with the duty ratio control signal. The output of the delay circuit 102 becomes a target pulse signal. The pulse signal generation unit 11 includes a control pulse signal generation unit 103 that generates a control pulse signal from the pulse signal that is the output of the delay circuit 102 and supplies the control pulse signal to the D flip-flop circuit 101. The control pulse signal generation unit 103 generates a control pulse signal using a pulse signal, a control pulse signal generation circuit 104, and a control pulse signal output from the control pulse signal generation circuit 104 or a trigger signal as a D flip-flop circuit 101. OR circuit 105 to be supplied to.

  The duty ratio adjustment unit 12 takes in the pulse signal and generates a duty ratio control signal that is a voltage signal. The duty ratio adjustment unit 12 includes a single-phase differential conversion circuit 111 that generates two pulse signals (differential pulse signals) in an inverted relationship using a single-phase pulse signal that is an output of the pulse signal generation unit 11. Have. Hereinafter, one of the differential pulse signals is referred to as a first pulse signal, and the other of the differential pulse signals is referred to as a second pulse signal.

  Further, the duty ratio adjusting unit 12 removes the common-mode component from the differential pulse signal that is the output of the single-phase differential conversion circuit 111, and the common-mode component removal circuit 112 removes the common-mode component. A differential charge pump circuit 113 for generating an average value of the voltage of the one pulse signal, and an average value of the voltage of the second pulse signal from which the in-phase component is removed. A duty ratio control signal output unit 114 is connected to the output terminal of the differential charge pump circuit 113. The duty ratio control signal output unit 114 uses the two average values output from the differential charge pump circuit 113 to generate a voltage corresponding to the difference between the two average values as a duty ratio control signal. The duty ratio control signal output unit 114 amplifies the difference between the two output voltages of the low-pass filter circuit 115 that integrates the two average values output from the differential charge pump circuit 113 and the low-pass filter circuit 115 and converts it into a current. And a low-pass filter circuit 117 that converts the output current of the voltage-current conversion circuit 116 into a voltage.

  A clock signal as an input signal is input to the clock terminal ck of the D flip-flop circuit 101, a control pulse signal generated in the control pulse signal generation unit 103 is input to the set terminal set, and a D flip-flop is input to the D terminal. A reference voltage (for example, the ground voltage GND) used for lowering the output of the circuit 101 is supplied. The D flip-flop circuit 101 outputs a reference voltage from the Q terminal in synchronization with the rising edge of the clock signal. That is, the D flip-flop circuit 101 operates so that the Q output falls in synchronization with the rising edge of the clock signal.

  The delay circuit 102 delays the Q output of the D flip-flop circuit 101 according to the voltage value of the duty ratio control signal so that a pulse signal with a duty ratio of 50% is obtained. Since the voltage value of the duty ratio control signal fluctuates so as to obtain a pulse signal having a duty ratio of 50% by controlling the delay amount of the delay circuit 102, the output of the delay circuit 102 has a target duty ratio of A 50% pulse signal can be obtained. As the delay circuit 102, for example, a voltage control delay line whose delay amount is adjusted according to the voltage value of the input duty ratio control signal is used.

  The control pulse signal generation circuit 104 generates a control pulse signal having a short pulse width in synchronization with the falling timing of the output of the delay circuit 102. The D flip-flop circuit 101 raises the Q output in response to the control pulse signal. Note that the Q output of the D flip-flop circuit 101 may be forcibly raised by a trigger signal.

  The single-phase differential conversion circuit 111 generates a first pulse signal and a second pulse signal that are in an inverted relationship using the single-phase pulse signal that is the output of the pulse signal generation unit 11. Here, as shown in FIG. 2A, the single-phase differential conversion circuit 111 can be configured by combining inverter circuits, for example. For this reason, the differential pulse that is strictly inverted due to the delay of the inverter circuit or the like, such as the first pulse signal shown in FIG. 2B and the second pulse signal shown in FIG. A pulse signal may not be obtained, and the differential pulse signal may include an in-phase component.

  The in-phase component removal circuit 112 removes the in-phase component in the first pulse signal and the second pulse signal as described above and outputs the result. As the in-phase component removal circuit 112, for example, a phase blending circuit can be applied. If the common-mode component in the first pulse signal and the second pulse signal is not a problem due to the above-described function of the common-mode component removal circuit 112, the common-mode component removal circuit 112 may be omitted.

  The differential charge pump circuit 113 averages the output of the single-phase differential conversion circuit 111 (the output of the common-mode component removal circuit 112 when the common-phase component removal circuit 112 is provided) and the average value of the voltage of the first pulse signal The average value of the voltage of the two-pulse signal is output. These two average values reflect the duty ratio of the first pulse signal and the second pulse signal.

  The duty ratio control signal output unit 114 uses two average values output from the differential charge pump circuit 113, generates a voltage corresponding to the difference, and outputs the voltage to the delay circuit 102 as a duty ratio control signal. The duty ratio control signal generated in this way has a voltage value reflecting the duty ratio of the current pulse signal. Further, the duty ratio control signal varies so that a pulse signal with a duty ratio of 50% can be obtained by controlling the delay amount of the delay circuit 102.

  Hereinafter, the operation of the signal shaping device 1 will be described with reference to FIGS. 3 and 4. In the following description, for the sake of simplicity, all signals expressed by voltages are described with the high voltage side as the power supply voltage Vdd and the low voltage side as the ground voltage GND (0 V). However, the present invention is not limited to this. Further, the signal waveforms shown in the drawings in the present embodiment are merely schematic for easy understanding, and details such as signal delay are not considered unless otherwise specified.

  FIG. 3A is a waveform diagram showing an example of the signal waveform of the clock signal, and FIG. 3B is a waveform diagram showing an example of the signal waveform of the Q output of the D flip-flop circuit 101. As shown in FIGS. 3A and 3B, the Q output of the D flip-flop circuit 101 falls at time t1 when the clock signal rises.

  FIG. 3C is a waveform diagram of the pulse signal output from the delay circuit 102. As shown in FIG. 3C, at time t1 ′ delayed by time Δt1 from time t1 when the Q output of the D flip-flop circuit 101 falls, the pulse signal output from the delay circuit 102 falls.

  FIG. 3D is a waveform diagram of the control pulse signal generated by the control pulse signal generation circuit 104. As shown in FIG. 3D, the control pulse signal generation circuit 104 raises the control pulse signal at the fall timing of the pulse signal that is the output of the delay circuit 102.

  When the above-described control pulse signal is input to the D flip-flop circuit 101 at time t1 ′, the D flip-flop circuit 101 raises the Q output in synchronization with the pulse of the control pulse signal (see FIG. 3B). ).

  4A is a schematic diagram illustrating an example of a signal waveform of the first pulse signal that is an output of the single-phase differential conversion circuit 111, and FIG. 4B is an output of the single-phase differential conversion circuit 111. FIG. It is a schematic diagram which shows the example of the signal waveform of a 2nd pulse signal. As shown in FIGS. 4A and 4B, the duty ratio of the pulse signal is not 50% (for example, A%) during the period from time t1 to time t2. In this case, the duty ratio of the first pulse signal is A%, and the duty ratio of the second pulse signal is (100−A)%. As described above, the first pulse signal and the second pulse signal are signals that are in an inverted relationship reflecting the duty ratio of the pulse signal.

  FIG. 4C is a waveform diagram showing an example of the average value of the first pulse signal that is the output of the differential charge pump circuit 113, and FIG. 4D is the output of the differential charge pump circuit 113. It is a wave form diagram which shows the example of the average value of a 2nd pulse signal. Since the first pulse signal and the second pulse signal reflect the duty ratio of the pulse signal, the average value of the voltage of the first pulse signal and the average value of the voltage of the second pulse signal are also determined by the duty ratio of the pulse signal. It becomes the reflected value. As shown in FIGS. 4C and 4D, in the period from time t1 to t2 when the duty ratio of the pulse signal is A%, the average value on the first pulse signal side is Vdd × A / 100, The average value on the two-pulse signal side is Vdd × (100−A) / 100.

  FIG. 4E is a waveform diagram illustrating an example of an output waveform of the duty ratio control signal output unit 114. When the duty ratio of the pulse signal is higher than 50% as in the period from time t1 to t2 shown in FIG. 4E, the difference between the average value on the first pulse signal side and the average value on the second pulse signal side (Differential voltage) is positive (or negative). In such a case, the duty ratio control signal output unit 114 outputs a duty ratio control signal having a voltage value higher than the reference value, thereby increasing the delay amount of the delay circuit 102 from the reference value.

  Then, at time t2 ′ delayed by time Δt2 from time t2, the pulse signal that is the output of the delay circuit 102 falls, and a pulse signal with a duty ratio closer to 50% is generated (FIG. 3C). reference). By repeating the above operation, a pulse signal having a duty ratio of 50% is obtained in a period from time tn-1 to tn after a predetermined time.

  Although the case where the duty ratio of the generated pulse signal is higher than 50% has been described here, the same applies to other cases. For example, when the duty ratio of the pulse signal is lower than 50%, the difference (difference voltage) between the average value on the first pulse signal side and the average value on the second pulse signal side is negative (or positive). In such a case, the duty ratio control signal output unit 114 outputs a duty ratio control signal having a voltage value lower than the reference value, thereby reducing the delay amount of the delay circuit 102 from the reference value. Further, when the duty ratio of the pulse signal is 50% as in the period from time tn-1 to tn shown in FIG. 3C, for example, the average value on the first pulse signal side and the second pulse signal side The difference (difference voltage) from the average value is zero. In this case, the duty ratio control signal output unit 114 outputs a duty ratio control signal whose voltage value is equal to the reference value, and adjusts the delay amount of the delay circuit 102 to the reference value.

  As described above, the signal shaping device 1 according to the present embodiment has a duty ratio of 50% by a feedback operation in which the difference between the average value of the first pulse signal and the average value of the second pulse signal is zero. A pulse signal is obtained. Thus, by using the difference between the average value of the first pulse signal and the average value of the second pulse signal depending on the duty ratio of the pulse signal, the duty ratio of the pulse signal can be controlled to 50%.

  In addition, what can be used as said duty ratio control signal is not restricted to the voltage corresponding to the difference of the average voltage of a 1st pulse signal, and the average voltage of a 2nd pulse signal. Information on the duty ratio may be extracted from the first pulse signal or the second pulse signal and used as a duty ratio control signal. The configuration of the duty ratio control signal output unit 114 can be appropriately changed according to the duty ratio control signal to be used.

  Computer simulation of the generated pulse waveform was performed using the circuit configuration of the signal shaping device 1 described above as a model. FIG. 5 is a graph showing a simulation result when the duty ratio of the clock signal is 20%, and FIG. 6 is a graph showing a simulation result when the duty ratio of the clock signal is 50%. These are graphs showing simulation results when the duty ratio of the clock signal is 80%. 5 to 7, (a) shows the waveform of the clock signal, (b) shows the waveform of the pulse signal shaped to the target duty ratio, and (c) shows the output of the differential charge pump circuit 113. (D) shows the duty ratio control signal from the duty ratio control signal output unit 114, respectively. The frequency of the clock signal was 3.2 GHz.

  As can be seen from FIGS. 5C to 7D, at the timing immediately after the start of the operation (for example, 0 ns to 200 ns), the output on the first pulse signal side of the differential charge pump circuit 113 and the second output There is a difference between the output on the pulse signal side and the output voltage from the duty ratio control signal output unit 114 is higher than the reference value. On the other hand, the difference between the first pulse signal output and the second pulse signal output of the differential charge pump circuit 113 decreases with time, and the output voltage from the duty ratio control signal output unit 114 converges to a reference value. For example, at the timing after 300 ns, there is almost no difference between the first pulse signal output and the second pulse signal output of the differential charge pump circuit 113, and the feedback signal from the duty ratio control signal output unit 114 is Stable at the reference value.

  Further, as shown in FIG. 5B, when the duty ratio of the clock signal is 20%, the duty ratio of the pulse signal is stabilized at about 50%, and as shown in FIG. Even when the duty ratio of the clock signal is 50%, the duty ratio of the pulse signal is stabilized at about 50%, and as shown in FIG. 7B, even when the duty ratio of the clock signal is 80%, The duty ratio of the pulse signal is stable at about 50%. Thus, it can be seen that by using the signal shaping device 1, a pulse signal having a target duty ratio can be obtained regardless of the value of the duty ratio of the clock signal.

  As described above, since the signal shaping device 1 does not use the phase comparison circuit that compares the phases of the clock signal and the pulse signal for controlling the duty ratio, the signal delay caused by the phase comparison circuit does not occur. That is, since there is no limitation on the operating frequency due to the signal delay of the phase comparison circuit, it is possible to handle a sufficiently high clock frequency (high-speed clock signal). Further, since the duty ratio control signal is generated using the pulse signal, the control error due to the delay of the pulse signal does not occur unlike the case where the duty ratio is controlled using the clock signal and the pulse signal. For this reason, the duty ratio can be adjusted with high accuracy. Since the influence of the control error described above becomes particularly significant at a high frequency, the signal shaping device 1 is extremely effective when a signal in a high frequency region is used.

  Here, if the delay amount variable range of the delay circuit in the pulse signal generation unit 11 is ½ or less or 1.5 times or more than the target delay amount, there is a risk of locking at the multiplied frequency. Therefore, it is difficult to widen the operable clock frequency range by expanding the delay amount variable range of the pulse signal generation unit 11.

  FIG. 8 shows a schematic configuration example of a signal shaping device capable of widening the operating frequency range. The signal shaping device 1 illustrated in FIG. 8 includes a demultiplexer 13, a plurality of pulse signal generation units 11-1 to 11-n, a multiplexer 14, and a duty ratio adjustment unit 12. As shown in FIG. 8, by providing a plurality of pulse signal generators 11-1 to 11-n in parallel, even if the delay amount of each of the pulse signal generators 11-1 to 11-n is not large, the whole Then, the delay amount variable range is expanded, and the operable clock frequency range can be widened.

  The demultiplexer 13 selects one of the pulse signal generation units 11-1 to 11-n according to a band selection signal corresponding to the frequency of the clock signal. The band selection signal is generated using a clock signal by a PLL circuit or the like.

  The pulse signal generation unit 11 has the same configuration (delay amount) as the pulse signal generation unit 11 illustrated in FIG. 1, but as illustrated in FIG. 9, the pulse signal generation unit 11 includes a plurality of pulse signal generation units 11-1 to 11-n. The operable frequency range is set so as to deviate from each other. As shown in the figure, the operable frequency ranges of the pulse signal generators 11-1 to 11-n are slightly overlapped between adjacent pulse signal generators, realizing a continuous wide operable frequency. Yes. As described above, since the operable frequency ranges overlap, any one of the plurality of pulse signal generation units 11 can be selected and used to support a wide frequency range. Note that the operable frequency ranges of the plurality of pulse signal generation units 11-1 to 11-n do not necessarily overlap. When it is not necessary to correspond to a continuous frequency range, such as when a frequency band to be used is determined in advance, adjacent operable frequency ranges may be discrete without overlapping.

  The duty ratio adjusting unit 12 is configured in the same manner as the duty ratio adjusting unit 12 shown in FIG. The multiplexer 14 switches the target pulse signal generation unit 11 in conjunction with the demultiplexer 13. The duty ratio adjustment unit 12 generates a duty ratio control signal using the pulse signal from the multiplexer 14. The duty ratio control signal from the duty ratio adjustment unit 12 is input to the pulse signal generation unit 11 in which the multiplexer 14 is selected by the demultiplexer 13.

  Further, the multiplexer 14 outputs the pulse signal of the pulse signal generation unit 11 selected by the band selection signal as the pulse signal of the signal shaping device 1.

  As described above, as shown in FIG. 8, the operable frequency ranges of the plurality of pulse signal generation units 11-1 to 11-n are connected to realize a large operable frequency range. It is possible to generate a pulse signal even in a wide frequency range that cannot be dealt with by the delay amount.

  As described above, since the signal shaping device 1 of the present invention does not use the phase comparison circuit for adjusting the duty ratio, the signal delay caused by the phase comparison circuit does not occur. That is, there is no limitation on the operating frequency due to the signal delay of the phase comparison circuit. For this reason, it is possible to cope with a sufficiently high clock frequency (high-speed clock signal). In addition, since the duty ratio control signal is generated using the pulse signal of the delay circuit, a control error caused by the delay of the pulse signal occurs as in the case where the duty ratio is controlled using the clock signal and the pulse signal. do not do. For this reason, the duty ratio can be adjusted with high accuracy. Since the influence of the control error described above becomes particularly significant at a high frequency, the signal shaping device 1 is extremely effective when a signal in a high frequency region is used.

  Further, by having a plurality of pulse signal generation units having different operable frequency ranges, it is possible to select the pulse signal generation unit 11 suitable for the frequency of the clock signal and adjust the duty ratio. For this reason, it is possible to generate a pulse signal in a wide frequency range that cannot be handled by one pulse signal generation unit 11.

  In addition, this invention is not limited to description of the said embodiment, It can change suitably in the aspect in which the effect is exhibited, and can be implemented.

  The signal shaping device of the present invention can be used, for example, in various electric circuits that use a clock signal having a duty ratio different from that of an input clock signal.

DESCRIPTION OF SYMBOLS 1 Signal shaping device 11 Pulse signal generation part 12 Duty ratio adjustment part 13 Demultiplexer 14 Multiplexer 101 D flip-flop circuit 102 Delay circuit 103 Control pulse signal generation part 104 Control pulse signal generation circuit 105 OR circuit 111 Single phase differential conversion circuit 112 In-phase Component removal circuit 113 Differential charge pump circuit 114 Duty ratio control signal output unit 115 Low-pass filter circuit 116 Voltage-current conversion circuit 117 Low-pass filter circuit

Claims (7)

A signal shaping device having a pulse signal generation unit that generates a pulse signal having a predetermined pulse width, and a duty ratio adjustment unit that controls the duty ratio of the pulse signal,
The pulse signal generation unit includes a flip-flop circuit to which a clock signal is input, a delay circuit that delays an output signal of the flip-flop circuit and outputs a single-phase pulse signal having a pulse width corresponding to the delay amount; With
The duty ratio adjusting unit converts the single-phase pulse signal output from the delay circuit into a differential pulse signal composed of a first pulse signal and a second pulse signal whose polarities are inverted with respect to each other. A signal shaping device that controls a delay amount of the delay circuit based on a difference between an average voltage and an average voltage of the second pulse signal so that the pulse signal has a target duty ratio. A plurality of pulse signal generators for generating a pulse signal having a predetermined pulse width and a pulse signal generator to be supplied with a clock signal provided at an input stage of the plurality of pulse signal generators are selected based on a band selection signal A demultiplexer, a multiplexer which is provided at an output stage of the plurality of pulse signal generation units and selects a pulse signal generation unit from which a pulse signal is to be extracted based on the band selection signal, and a pulse signal generation unit selected by the multiplexer A duty ratio adjusting unit for controlling the duty ratio of the pulse signal generated in the signal shaping device,
Each pulse signal generator includes a flip-flop circuit to which a clock signal is input, and a delay circuit that delays an output signal of the flip-flop circuit and outputs a single-phase pulse signal having a pulse width corresponding to the delay amount And comprising
The duty ratio adjusting unit converts the single-phase pulse signal output from the delay circuit into a differential pulse signal composed of a first pulse signal and a second pulse signal whose polarities are inverted with respect to each other. Based on the difference between the average voltage and the average voltage of the second pulse signal, the delay amount of the delay circuit is controlled so that the pulse signal has a target duty ratio,
A signal shaping device characterized in that the operable frequency range is widened by combining the plurality of pulse signal generation units.   The duty ratio adjusting unit controls a delay amount of the delay circuit so that a difference between an average voltage of the first pulse signal and an average voltage of the second pulse signal becomes a predetermined value. The signal shaping device according to claim 1 or 2.   The duty ratio adjusting unit controls a delay amount of the delay circuit so that a difference between an average voltage of the first pulse signal and an average voltage of the second pulse signal becomes zero. 4. The signal shaping device according to 3.   5. The signal shaping device according to claim 1, wherein the delay circuit includes a voltage control delay line in which a delay amount is adjusted in accordance with an input voltage. 6. The duty ratio adjuster is
A single-phase differential conversion circuit for converting a single-phase pulse signal from the pulse signal generation unit into a differential pulse signal composed of a first pulse signal and a second pulse signal;
A differential charge pump circuit that averages outputs of the single-phase differential conversion circuit and outputs an average voltage of the first pulse signal and an average voltage of the second pulse signal;
A duty ratio control signal for controlling a delay amount of the delay circuit using a voltage corresponding to a difference between an average voltage of the first pulse signal and an average voltage of the second pulse signal by using an output of the differential charge pump circuit. A duty ratio control signal output section that outputs as
The signal shaping device according to claim 1, comprising:   The signal shaping device according to claim 6, further comprising an in-phase component removal circuit that removes an in-phase component from an output of the single-phase differential conversion circuit, following the single-phase differential conversion circuit.

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