JP2012138465A - Group-iii nitride semiconductor light-emitting element manufacturing method, group-iii nitride semiconductor light-emitting element, lamp, electronic apparatus and machinery - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a group-III nitride semiconductor light-emitting element excellent in light permeability, light-emitting power output and reliability by forming an auxiliary electrode preventing current centralization, light absorption and multiple reflection occurring in high current conduction.SOLUTION: A manufacturing method of a group-III nitride semiconductor light-emitting element comprises: a step of sequentially laminating an n-type semiconductor layer, a luminescent layer and a p-type semiconductor layer on a substrate; a step of forming, on the p-type semiconductor layer, an insulation layer and a p-type electrode layer that is composed of a metal and has a p-type pad and a filamentous p-type auxiliary electrode part extending from the p-type pad; a step of forming a transparent electrode so as to cover the p-type semiconductor layer and the p-type electrode layer; and a step of forming a p-type bonding pad electrode at a location overlapping the p-type pad of the p-type electrode layer on the transparent electrode.

Description

  The present invention relates to a method for manufacturing a group III nitride semiconductor light emitting device, a group III nitride semiconductor light emitting device, a lamp, an electronic device, and a mechanical device.

  Conventionally, as a group III nitride semiconductor light emitting device used for a light emitting diode, an n type semiconductor layer, a light emitting layer, and a p type semiconductor layer made of a group III nitride semiconductor are laminated on a substrate made of a sapphire single crystal. Things are known. In general, such a group III nitride semiconductor light emitting device has a translucent electrode and a positive electrode (p-type bonding pad electrode) formed on a p-type semiconductor layer, and a negative electrode (n-type bonding pad) on an n-type semiconductor layer. Electrode). Further, the group III nitride semiconductor light-emitting device having such a configuration is configured to extract light from the p-type semiconductor layer side.

  As the group III nitride semiconductor light emitting device as described above, one in which an insulating layer is provided between a p-type bonding pad electrode and a translucent electrode is known (Patent Documents 1 and 2). According to the group III nitride semiconductor light emitting device described in Patent Documents 1 and 2, by providing an insulating layer at a position corresponding to the p-type bonding pad electrode, current concentration immediately below the p-type bonding pad electrode is suppressed. It is said that current diffusion to the translucent electrode is promoted. Further, as a method for preventing concentration of light emission near the p-type bonding pad electrode, a method of extending a linear auxiliary electrode from the p-type bonding pad electrode onto the translucent electrode is also known (Patent Document 2). . In order to further enhance the light diffusion effect, a method of forming an insulating layer at a corresponding position under the auxiliary electrode is also known.

JP 2008-250769 A JP 2008-192710 A

  However, when an insulating layer is formed on the p-type semiconductor layer, a translucent electrode is formed on the insulating layer, and an auxiliary electrode is formed on the translucent electrode so as to overlap the insulating layer, Light is reflected by the surface of the auxiliary electrode on the insulating layer side, and the light extraction efficiency is lowered. In addition, in a group III nitride semiconductor light-emitting device having an auxiliary electrode, the voltage is concentrated on the auxiliary electrode, and burns and holes are easily generated in the light-transmitting electrode around the auxiliary electrode. In particular, when the above configuration is applied to a large group III nitride semiconductor light-emitting device, this problem is particularly noticeable because the distance between the p-type bonding pad electrode and the n-type bonding pad electrode is increased.

  The present invention has been made in view of the above circumstances, and a group III nitride semiconductor having excellent light extraction efficiency, light output, and reliability by forming an auxiliary electrode that prevents current concentration and light reflection. An object is to provide a light-emitting element.

In order to achieve the above object, the present invention provides the following means.
[1] A step of sequentially laminating an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate, and an insulating layer, a p-type pad portion, and a p-type pad portion extending on the p-type semiconductor layer. A step of forming a p-type electrode layer made of metal having a linear p-type auxiliary electrode portion, a step of forming a translucent electrode so as to cover the p-type semiconductor layer and the p-type electrode layer, Forming a p-type bonding pad electrode at a position overlapping the p-type pad portion of the p-type electrode layer on the translucent electrode. A Group III nitride semiconductor comprising: Manufacturing method of light emitting element.
[2] The method for producing a group III nitride semiconductor light-emitting device according to [1], wherein the insulating layer is made of a film mainly composed of an amorphous phase.
[3] In the step of forming the p-type bonding pad electrode, the p-type bonding pad electrode is formed so as to fill the through-hole after forming a through-hole in the translucent electrode layer on the p-type pad portion. The method for manufacturing a group III nitride semiconductor light-emitting device according to [1] or [2], wherein the p-type bonding pad electrode and the p-type pad portion are bonded to each other.
[4] The method for producing a Group III nitride semiconductor light-emitting device according to any one of [1] to [3], wherein the p-type electrode layer is formed with a thickness of 5 nm to 30 nm.
[5] The method for producing a group III nitride semiconductor light-emitting device according to any one of [1] to [4], wherein the insulating layer is formed with a thickness of 2 nm to 100 nm.
[6] The group III nitride semiconductor light-emitting device according to any one of [1] to [5], wherein the p-type electrode layer is formed with a width smaller than the insulating layer by 0 nm to 2000 nm. Manufacturing method.
[7] The p-type electrode layer is made of at least one selected from the group consisting of Rh, Pd, Pt, Au, Ta, Nb, Ni, Ti, Cu, and Hf. [6] The method for producing a group III nitride semiconductor light-emitting device according to any one of [6].
[8] The method for producing a group III nitride semiconductor light-emitting element according to any one of [1] to [7], wherein the insulating layer is made of silicon oxide.
[9] A stacked semiconductor layer in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are sequentially stacked, and a p-type pad portion and a line extending from the p-type pad portion disposed on the p-type semiconductor layer A p-type electrode layer made of a metal having a p-type auxiliary electrode portion, an insulating layer disposed between the p-type electrode layer and the p-type semiconductor layer, the p-type semiconductor layer, and the p-type electrode A translucent electrode covering the layer, and a p-type bonding pad electrode formed on the translucent electrode at a position overlapping the p-type pad portion of the p-type electrode layer. A group III nitride semiconductor light emitting device characterized by the above.
[10] The group III nitride semiconductor light-emitting device according to [9], wherein the insulating layer is made of a film mainly composed of an amorphous phase.
[11] A through-hole is provided in the translucent electrode layer on the p-type pad portion, the p-type bonding pad electrode is inserted into the through-hole, and the p-type bonding pad electrode, the p-type pad portion, The group III nitride semiconductor light-emitting device according to [9] or [10], wherein
[12] The group III nitride semiconductor light-emitting device according to any one of [9] to [11], wherein the p-type electrode layer is formed with a thickness of 5 nm to 30 nm.
[13] The group III nitride semiconductor light-emitting device according to any one of [9] to [12], wherein the insulating layer is formed with a thickness of 2 nm to 100 nm.
[14] The group III nitride according to any one of [9] to [13], wherein the p-type auxiliary electrode portion is formed with a width smaller by 0 nm to 2000 nm than the insulating layer. Semiconductor light emitting device.
[15] The p-type electrode layer is made of at least one selected from the group consisting of Rh, Pd, Pt, Au, Ta, Nb, Ni, Ti, Cu, and Hf. [14] The group III nitride semiconductor light-emitting device according to any one of [14].
[16] The group III nitride semiconductor light-emitting device according to any one of [9] to [15], wherein the insulating layer is made of silicon oxide.
[17] A lamp comprising the group III nitride semiconductor light-emitting device according to any one of [9] to [16].
[18] An electronic device in which the lamp according to [17] is incorporated.
[19] A mechanical apparatus in which the electronic device according to [18] is incorporated.

According to the group III nitride semiconductor light emitting device of the present invention, the insulating layer is disposed between the p-type electrode layer and the p-type semiconductor layer, so that light emitted from the light-emitting layer of the stacked semiconductor layer is p-type. It does not directly contact the electrode layer, but is reflected by the insulating layer and returns to the laminated semiconductor layer, or is transmitted through the translucent electrode and emitted to the outside. Thereby, the light extraction efficiency is greatly increased. When an insulating layer is not disposed between the p-type electrode layer and the p-type semiconductor layer, when light emitted from the light emitting layer of the stacked semiconductor layer hits the p-type electrode layer, the light is emitted from the p-type semiconductor layer and the p-type electrode. Although it may be absorbed at the interface with the layer and the light extraction efficiency may be greatly reduced, such a problem does not occur in the present invention.
In addition, the current mainly flows through the path of the p-type pad, the p-type electrode layer, the translucent electrode, and the p-type semiconductor layer, but an insulating layer is disposed between the p-type electrode layer and the p-type semiconductor layer. Thus, current does not flow directly from the p-type electrode layer to the p-type semiconductor layer, but current flows to the p-type semiconductor layer through the translucent electrode covering the p-type electrode layer. As a result, current concentration is unlikely to occur and burn-in of the p-type semiconductor layer can be prevented. For this reason, it can prevent that a burn and a hole generate | occur | produce in a p-type semiconductor layer. Furthermore, since the p-type electrode layer is made of metal, a sufficient amount of current flows through the linear p-type auxiliary electrode portion, and current concentration can be suppressed.
As described above, the light extraction efficiency and reliability of the group III nitride semiconductor light emitting device can be improved.

According to the method for manufacturing a group III nitride semiconductor light emitting device of the present invention, the insulating layer and the p-type electrode layer are formed on the p-type semiconductor layer in the same process, so that the film thickness is smaller than that of the p-type bonding pad electrode. A p-type electrode layer can be formed without increasing the number of steps.
As described above, the manufacturing efficiency of the group III nitride semiconductor light emitting device having the auxiliary electrode can be improved.

FIG. 1 is a schematic cross-sectional view showing an example of a group III nitride semiconductor light emitting device manufactured using the method for manufacturing a group III nitride semiconductor light emitting device of the present invention. FIG. 2 is a schematic plan view showing an example of a group III nitride semiconductor light emitting device manufactured using the method for manufacturing a group III nitride semiconductor light emitting device of the present invention. FIG. 3 is a schematic plan view showing an example of a group III nitride semiconductor light-emitting device manufactured using the method for manufacturing a group III nitride semiconductor light-emitting device of the present invention. FIG. 4 is a schematic cross-sectional view for explaining a process for manufacturing the group III nitride semiconductor light-emitting device shown in FIG. FIG. 5 is a schematic cross-sectional view showing an example of a lamp including the group III nitride semiconductor light-emitting device shown in FIG.

  Hereinafter, the group III nitride semiconductor light emitting device 1 of the present invention will be described in detail with reference to FIG. Note that the drawings referred to in the following description may show the characteristic portions in an enlarged manner for the sake of convenience, and the dimensional ratios of the respective components are not always the same as the actual ones. In addition, the materials, dimensions, and the like exemplified in the following description are examples, and the present invention is not limited to them, and can be appropriately changed and implemented without changing the gist thereof.

FIG. 1 is a schematic cross-sectional view showing an example of a group III nitride semiconductor light emitting device 1 of the present invention.
A group III nitride semiconductor light emitting device 1 according to this embodiment shown in FIG. 1 includes a substrate 11, a laminated semiconductor layer 20 laminated on the substrate 11, and a translucent electrode 15 laminated on the upper surface of the laminated semiconductor layer 20. And a p-type bonding pad electrode 16 laminated on the translucent electrode 15 and an n-type electrode 17 laminated on the exposed surface 20 a of the laminated semiconductor layer 20.

The stacked semiconductor layer 20 is configured by stacking an n-type semiconductor layer 12, a light emitting layer 13, and a p-type semiconductor layer 14 in this order from the substrate 11 side. As shown in FIG. 1, the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14 are partially removed by means such as etching, and one part of the n-type semiconductor layer 12 is removed from the removed portions. The part is exposed. An n-type electrode 17 is stacked on the exposed surface 20 a of the n-type semiconductor layer 12.
The insulating layer 5 and the p-type electrode layer 40 are stacked on the p-type semiconductor layer 14. Further, the translucent electrode 15 is formed so as to cover the p-type semiconductor layer 14 and the p-type electrode layer 40. A p-type bonding pad electrode 16 is formed on the translucent electrode 15. The translucent electrode 15 and the p-type bonding pad electrode 16 constitute a p-type electrode 18.

As a semiconductor constituting the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14, a group III nitride semiconductor is preferably used, and a gallium nitride compound semiconductor is more preferably used. As the gallium nitride-based compound semiconductor constituting the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14 in the present invention, a general formula Al _x In _y Ga _1-xy N (0 ≦ x <1,0) Semiconductors having various compositions represented by ≦ y <1, 0 ≦ x + y <1) can be used without any limitation.

The group III nitride semiconductor light-emitting device 1 of the present embodiment is configured such that light can be emitted from the light-emitting layer 13 constituting the stacked semiconductor layer 20 by passing a current between the p-type electrode 18 and the n-type electrode 17. This is a face-up mount type light emitting element that extracts light from the light emitting layer 13 from the side where the p type bonding pad electrode 16 is formed. The group III nitride semiconductor light emitting device of the present invention may be a flip chip type light emitting device.
Hereinafter, each configuration will be described in detail.

<Substrate 11>
Examples of the substrate 11 include sapphire, SiC, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, A substrate made of neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium oxide, tungsten oxide, molybdenum oxide, or the like can be used. Among the above substrates, it is particularly preferable to use a sapphire substrate having a c-plane as a main surface.

(Buffer layer 21)
The buffer layer 21 may not be provided, but the difference in lattice constant between the substrate 11 and the base layer 22 is alleviated to form a C-axis oriented single crystal layer on the (0001) C plane of the substrate 11. It is preferable that it is provided in order to facilitate the process.

The buffer layer 21 is particularly preferably made of single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1), but is made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1). It doesn't matter.
The buffer layer 21 can be, for example, made of single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1) and having a thickness of 0.01 μm to 0.5 μm. If the thickness of the buffer layer 21 is less than 0.01 μm, the buffer layer 21 may not sufficiently obtain the effect of reducing the difference in lattice constant between the substrate 11 and the base layer 22. Further, when the thickness of the buffer layer 21 exceeds 0.5 μm, the film forming process time of the buffer layer 21 becomes long and the productivity is lowered although the function as the buffer layer 21 is not changed. There's a problem.

  When the buffer layer 21 having such a polycrystalline structure or a single crystal structure is formed on the substrate 11 by the MOCVD method or the sputtering method, the buffer function of the buffer layer 21 works effectively. The group III nitride semiconductor thus formed becomes a crystal film having good orientation and crystallinity.

(Underlayer 22)
As the material of the underlayer 22, it is particularly preferable to use Al _x Ga _1-x N (0 ≦ x <1) because the underlayer 22 with good crystallinity can be formed, but Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) may be used.
The film thickness of the underlayer 22 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. An Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness is increased. Further, the film thickness of the underlayer 22 is preferably 10 μm or less.
In order to improve the crystallinity of the underlayer 22, it is desirable that the underlayer 22 is not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added to the base layer 22.

<Laminated semiconductor layer 20>
(N-type semiconductor layer 12)
The n-type semiconductor layer 12 further includes an n-contact layer 12a and an n-cladding layer 12b.

(N contact layer 12a)
The n-contact layer 12a is a layer for providing the n-type electrode 17, and an exposed surface 20a for providing the n-type electrode 17 is partially formed as shown in FIG.
The thickness of the n contact layer 12a is preferably 0.5 to 5 μm, and more preferably 2 to 4 μm. When the film thickness of the n-contact layer 12a is within the above range, the crystallinity of the semiconductor is favorably maintained.

The n-contact layer 12a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1), An n-type impurity (dopant) is doped. When n-type impurity is contained in n contact layer 12a at a concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , From the viewpoint of maintaining good ohmic contact. The n-type impurity used for the n-contact layer 12a is not particularly limited, and examples thereof include Si, Ge, Sn, etc., Si and Ge are preferable, and Si is most preferable. In this embodiment, Si of about 5 × 10 ¹⁸ / cm ³ is contained as an n-type impurity (dopant).

  The n clad layer 12 b is provided between the n contact layer 12 a and the light emitting layer 13. The n-clad layer 12b is a layer for injecting carriers into the light-emitting layer 13 and confining carriers, and also serves as a buffer layer for the light-emitting layer 13 that alleviates the crystal lattice mismatch between the n-contact layer 12a and the light-emitting layer 13. Function. The n-clad layer 12b can be formed of AlGaN, GaN, GaInN, or the like. In the specification, the composition ratio of each element may be omitted and described as AlGaN or GaInN.

  The n-clad layer 12b may have a single layer structure or a superlattice structure. When the n clad layer 12b is a single layer, the thickness of the n clad layer 12b is preferably 5 nm to 500 nm, and more preferably 5 nm to 100 nm.

  In this embodiment, the n-clad layer 12b may be a single layer, but consists of 10 pairs (20 layers) to 40 pairs (80 layers) by repeatedly growing two thin film layers having different compositions. A superlattice structure is preferred. In the case where the n-clad layer 12b has a superlattice structure, if the number of thin film layers is 20 or more, the crystal lattice mismatch between the n-contact layer 12a and the light-emitting layer 13 is more effectively reduced. Therefore, the effect of improving the output of the group III nitride semiconductor light emitting device 1 becomes more remarkable. However, if the number of thin film layers exceeds 80, the superlattice structure may be easily disturbed, and the light emitting layer 13 may be adversely affected. Furthermore, there is a problem that the film forming process time of the n-clad layer 12b becomes long and productivity is lowered.

<Light emitting layer 13>
The light emitting layer 13 has a multiple quantum well structure in which a plurality of barrier layers 13a and well layers 13b are alternately stacked. The number of stacked layers in the multiple quantum well structure is preferably 3 to 10 layers, more preferably 4 to 7 layers.

(Well layer 13b)
The thickness of the well layer 13b is preferably in the range of 15 angstroms or more and 50 angstroms or less. When the film thickness of the well layer 13b is within the above range, a higher light emission output can be obtained.
The well layer 13b is preferably a gallium nitride compound semiconductor containing In. A gallium nitride compound semiconductor containing In is preferable because it emits strong light in the blue wavelength region. The well layer 13b can be doped with impurities. Moreover, it is preferable to use Si as a dopant in this embodiment. The dope amount is preferably about 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ .

(Barrier layer 13a)
The thickness of the barrier layer 13a is preferably in the range of 20 angstroms or more and less than 100 angstroms. If the thickness of the barrier layer 13a is too thin, flattening of the upper surface of the barrier layer 13a is hindered, leading to a decrease in light extraction efficiency and a decrease in aging characteristics. Moreover, when the film thickness of the barrier layer 13a is too thick, a drive voltage rises and light emission falls. Therefore, the thickness of the barrier layer 13a is more preferably 70 angstroms or less.
In addition to GaN and AlGaN, the barrier layer 13a can be formed of InGaN having a smaller In ratio than InGaN constituting the well layer. Among these, GaN is preferable. Further, the barrier layer 13a can be doped with impurities. Si is preferably used as the dopant in the present embodiment. The dope amount is preferably about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ .

<P-type semiconductor layer 14>
The p-type semiconductor layer 14 is generally composed of a p-cladding layer 14a and a p-contact layer 14b. Further, the p contact layer 14b can also serve as the p clad layer 14a.

(P-clad layer 14a)
The p-clad layer 14 a in the present embodiment is formed on the light emitting layer 13. The p-cladding layer 14a is a layer for confining carriers in the light emitting layer 13 and injecting carriers. The p-cladding layer 14a is not particularly limited as long as it has a composition larger than the band gap energy of the light emitting layer 13 and can confine carriers in the light emitting layer 13, but Al _x Ga _1-x N (0 ≦ x ≦ 0.4) is preferable. When the p-cladding layer 14a is made of such AlGaN, it is preferable in terms of confining carriers in the light-emitting layer 13.

The thickness of the p-cladding layer 14a is not particularly limited, but is preferably 1 to 400 nm, and more preferably 5 to 100 nm. The p-type doping concentration of the p-cladding layer 14a is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity. The p-cladding layer 14a may have a superlattice structure in which thin films are stacked a plurality of times.

  When the p-cladding layer 14a includes a superlattice structure, a p-type first layer made of a group III nitride semiconductor and a p-type second layer made of a group III nitride semiconductor having a composition different from that of the p-type first layer. The layers may be stacked. When the p-cladding layer 14a includes a superlattice structure, the p-cladding layer 14a may include a structure in which p-type first layers and p-type second layers are alternately and repeatedly stacked.

(P contact layer 14b)
The p contact layer 14b is a layer for providing a positive electrode. The p contact layer 14b is preferably made of Al _x Ga _1-x N (0 ≦ x ≦ 0.4) in terms of maintaining good crystallinity and good ohmic contact with the p ohmic electrode. . When the p-contact layer 14b contains p-type impurities (dopants) at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ and 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. From the viewpoint of maintaining good ohmic contact, preventing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, it is especially preferable to use Mg.

  The thickness of the p-contact layer 14b is not particularly limited, but is preferably 10 to 500 nm, and more preferably 50 to 200 nm. When the film thickness of the p contact layer 14b is within this range, it is preferable in terms of light emission output.

<N-type electrode 17>
The n-type electrode 17 also serves as a bonding pad, and is formed so as to be in contact with the exposed surface 20a where a part of the laminated semiconductor layer 20 is exposed. Therefore, when forming the n-type electrode 17, at least a part of the p-semiconductor layer 14 and the light-emitting layer 13 is removed to expose the n-type semiconductor layer 12, and on the exposed surface 20 a of the n-type semiconductor layer 12. An n-type electrode 17 also serving as a bonding pad is formed. The n-type electrode 17 is disposed at a position facing a p-type bonding pad electrode 16 and a p-type pad portion 40a described later. As the n-type electrode 17, various compositions and structures are known, and these known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.

<Insulating layer 5, p-type electrode layer 40>
The insulating layer 5 and the p-type electrode layer 40 are stacked on the p-contact layer 14b, and the insulating layer 5 is disposed between the p-type electrode layer 40 and the p-contact layer 14b.
The insulating layer 5 is composed of a first insulating layer 5a having substantially the same plan view shape as the p-type bonding pad electrode 16, and a linear second insulating layer 5b extending from the first insulating layer 5a. Yes. The first insulating layer 5 a is formed directly below the p-type bonding pad electrode 16.

The insulating layer 5 is preferably made of silicon oxide (SiO ₂ ) in terms of light transmittance. The material of the insulating layer 5 is not limited to silicon oxide, and a conventionally known insulating oxide film or the like can be used without any limitation.
The insulating layer 5 is preferably made of a film mainly composed of an amorphous phase.

The insulating layer 5 is preferably formed with a thickness of 2 nm to 100 nm. Furthermore, the insulating layer 5 is more preferably formed with a film thickness of 5 nm to 70 nm. By forming the insulating layer 5 with a film thickness within the above range, it is possible to prevent a decrease in light transmittance and prevent a current from flowing directly from the p-type electrode layer 40 to the p-type semiconductor layer 14.
On the other hand, if the thickness of the insulating layer 5 is less than 2 nm, the surface shape of the insulating layer 5 reflects the surface roughness of the p-contact layer 14b that is the base of the insulating layer 5, thereby forming on the insulating layer 5 This is not preferable because the p-type electrode layer 40 to be formed may be divided.
In addition, if the thickness of the insulating layer 5 exceeds 100 nm, the light transmittance of the insulating layer 5 is not preferable.

  The p-type electrode layer 40 has substantially the same plan view shape as the insulating layer 5 and is stacked on the insulating layer 5. The p-type electrode layer 40 is composed of a p-type pad portion 40a having substantially the same plan view shape as the p-type bonding pad electrode 16, and a linear p-type auxiliary electrode portion 40b extending from the p-type pad portion 40a. Yes. The p-type pad portion 40a is formed immediately below the p-type bonding pad electrode 16.

  The p-type electrode layer 40 is made of a metal, but is preferably made of at least one selected from the group consisting of Rh, Pd, Pt, Au, Ta, Nb, Ni, Ti, Cu and Hf. More preferably, it consists of at least one selected from the group consisting of Rh, Pd and Pt. The p-type electrode layer 40 may have a laminated structure of a plurality of metals.

The p-type electrode layer 40 is preferably formed with a film thickness of 5 nm to 30 nm. By forming the p-type electrode layer 40 with a film thickness within the above range, it is possible to prevent a decrease in light transmittance and to allow a sufficient current to flow.
On the other hand, when the film thickness of the p-type electrode layer 40 is less than 5 nm, the electrical resistance of the p-type electrode layer 40 increases. For this reason, current concentration tends to occur, which is not preferable. Moreover, when the film thickness of the p-type electrode layer 40 exceeds 30 nm, the light transmittance decreases, which is not preferable.

The p-type auxiliary electrode portion 40b is preferably formed with a width of 100 nm to 40000 nm. Furthermore, the p-type auxiliary electrode portion 40b is preferably formed with a width of 1000 nm to 10000 nm. By forming the p-type auxiliary electrode portion 40b with a width within this range, current concentration on the p-type auxiliary electrode portion 40b can be sufficiently suppressed, and the opening area of the light extraction surface can be sufficiently maintained.
On the other hand, if the width of the p-type auxiliary electrode portion 40b is less than 100 nm, the electric resistance of the p-type auxiliary electrode portion 40b is increased, and the light emission output of the semiconductor light-emitting element 1 is not preferable. On the other hand, if the width of the p-type auxiliary electrode portion 40b exceeds 40000 nm, the opening area of the light extraction surface becomes small, and the light emission output of the semiconductor light emitting device 1 decreases, which is not preferable.

  The width of the p-type electrode layer 40 is preferably smaller than the width of the insulating layer 5 by 0 nm to 2000 nm, and the difference is more preferable. By setting the difference between the width of the p-type electrode layer 40 and the width of the insulating layer 5 to 0 nm to 2000 nm, the surface on the p-type semiconductor layer 14 side of the p-type electrode layer 40 is entirely covered with the insulating layer 5. Therefore, the current flowing through the p-type electrode layer 40 flows to the p-type semiconductor layer 14 through the translucent electrode 15 covering the p-type electrode layer 40 and does not flow directly to the p-type semiconductor layer 14. Therefore, the p-type semiconductor layer 14 can be prevented from being burned. Further, since light emitted from the light emitting layer 13 does not directly hit the p-type electrode layer 40, the light emission is prevented from being absorbed by the p-type electrode layer 40. Therefore, the light emission output can be improved.

On the other hand, if the width of the p-type electrode layer 40 is larger than the width of the insulating layer 5, the current concentrates on the portion of the p-type electrode layer 40 that does not overlap the insulating layer 5, so that the light emission is not uniform.
In addition, if the width of the p-type electrode layer 40 is smaller than the width of the insulating layer 5 by more than 2000 nm, it is not preferable because the current diffusion from the p-type electrode layer 40 to the translucent electrode 15 is biased.

(Translucent electrode 15)
The translucent electrode 15 is formed so as to cover the p-type semiconductor layer 14 and the p-type electrode layer 40, and preferably has a low contact resistance with the p-type semiconductor layer 14. The translucent electrode 15 is preferably excellent in light transmissivity in order to efficiently extract light from the light emitting layer 13 to the outside of the group III nitride semiconductor light emitting device 1. In addition, the translucent electrode 15 preferably has excellent conductivity in order to diffuse current uniformly over the entire surface of the p-type semiconductor layer 14.

As a constituent material of the translucent electrode 15, any one of conductive oxide containing any one of In, Zn, Al, Ga, Ti, Bi, Mg, W, and Ce, zinc sulfide, or chromium sulfide is used. A translucent conductive material selected from the group consisting of: As the conductive oxide, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), AZO (aluminum zinc oxide (ZnO—Al ₂ O)) ₃ )), GZO (gallium zinc oxide (ZnO—Ga ₂ O ₃ )), fluorine-doped tin oxide, titanium oxide and the like.

  Moreover, the structure of the translucent electrode 15 may be any structure including a conventionally known structure. The translucent electrode 15 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 14, or may be formed in a lattice shape or a tree shape with a gap.

(P-type bonding pad electrode 16)
The p-type bonding pad electrode 16 also serves as a bonding pad, and is formed at a position overlapping the p-type pad portion 40a (immediately above the p-type pad portion 40a). As the p-type bonding pad electrode 16, various compositions and structures are known, and these known compositions and structures can be used without any limitation. For example, various structures using Au, Al, Ni, Cu, etc. are well known as bonding pads, and these known materials and structures can be used without any limitation. Here, for example, the p-type bonding pad electrode 16 made of a metal laminated film having a thickness in the range of 100 to 1500 nm can be used.

  The p-type bonding pad electrode 16 is preferably formed at a position facing the n-type electrode 17 so as to be as far as possible from the n-type electrode 17. If the p-type bonding pad electrode 16 is formed at a position close to the n-type electrode 17, current is concentrated between the p-type bonding pad electrode 16 and the n-type electrode 17, which is not preferable. Moreover, it is not preferable because a short circuit between the wires and between the balls occurs during bonding.

  The p-type bonding pad electrode 16 is preferably inserted into a through hole 15a provided in the translucent electrode 15 immediately above the p-type pad portion 40a. The width of the p-type bonding pad electrode 16 may be equal to or smaller than the width of the p-type pad portion 40a, and the p-type bonding pad electrode 16 and the p-type pad portion 40a may be directly bonded.

  Further, the p-type bonding pad electrode 16 has an electrode area that is as large as possible to facilitate the bonding operation, but it hinders extraction of emitted light. Conversely, if the electrode area of the p-type bonding pad electrode 16 is too small, the bonding operation becomes difficult and the product yield is reduced. Specifically, it is preferable that the diameter is slightly larger than the diameter of the bonding ball, and it is generally a circular shape in a plan view having a diameter of about 100 μm.

(Protective film layer)
The protective film layer (not shown) includes the upper surface and side surfaces of the translucent electrode 15, the exposed surface 20a of the n-type semiconductor layer 12, the side surfaces of the light-emitting layer 13 and the p-type semiconductor layer 14, the n-type electrodes 17 and p as required. It is formed so as to cover the side surface and the peripheral portion of the mold bonding pad electrode 16. By forming the protective film layer, it is possible to prevent moisture and the like from entering the group III nitride semiconductor light emitting device 1 and to suppress the deterioration of the group III nitride semiconductor light emitting device 1.
As the protective film layer, it is preferable to use an insulating material having a transmittance of 80% or more at a wavelength in the range of 300 to 550 nm. For example, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), niobium oxide (Nb ₂ O ₅ ), tantalum oxide (Ta ₂ O ₅ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), or the like can be used. Among these, SiO ₂ and Al ₂ O ₃ are more preferable because a dense film can be easily formed by CVD film formation.

  Next, the positional relationship between the p-type electrode layer 40 and the n-type electrode 17 will be described in detail. 2 and 3 are schematic plan views showing an example of the group III nitride semiconductor light emitting device 1 of the present invention. The p-type electrode layer 40 is actually formed under the translucent electrode 15, and the p-type bonding pad electrode 16 is formed immediately above the p-type pad portion 40a. In order to make the relationship easy to understand, the positions of the p-type pad portion 40a and the p-type auxiliary electrode portion 40b are shown in the drawing.

FIG. 2 shows a group III nitride semiconductor light emitting device 1 in which only one p-type auxiliary electrode portion 40b is formed. The p-type pad portion 40 a is provided at a position facing the n-type electrode 17. Further, the linear p-type auxiliary electrode portion 40 b extends along a line passing through the center of the p-type pad portion 40 a and the center of the n-type electrode 17.
Thus, when only one p-type auxiliary electrode portion 40b is formed, the configuration extends on a line passing through the center of the p-type bonding pad electrode 16 (p-type pad portion 40a) and the center of the n-type electrode 17. Thus, the current can be effectively diffused. For this reason, it is possible to effectively prevent light emission bias and concentration.

FIG. 3 shows a group III nitride semiconductor light emitting device 1 in which two p-type auxiliary electrode portions 40b are formed. The p-type auxiliary electrode portion 40 b extends from the p-type pad portion 40 a along the outer edge of the group III nitride semiconductor light-emitting element 1, and extends from a line passing through the center of the p-type pad portion 40 a and the center of the n-type electrode 17. They are arranged at the same interval.
As described above, when a plurality of p-type auxiliary electrode portions 40b are formed, the p-type auxiliary electrode portions 40b are preferably formed so as to extend along the outer edge of the group III nitride semiconductor light emitting device 1 and to have the same interval. . By adopting such a configuration, it is possible to effectively diffuse the current and to effectively prevent light emission bias and concentration.
The number and arrangement of the p-type auxiliary electrode portions 40b shown in FIGS. 2 and 3 are merely examples, and are not limited to those shown here.

  According to the group III nitride semiconductor light-emitting device 1 of the present invention, the insulating layer 5 is disposed between the p-type electrode layer 40 and the p-type semiconductor layer 14 so that light emitted from the light-emitting layer 13 is p. Instead of directly hitting the mold electrode layer 40, it is reflected by the insulating layer 5 and returns to the laminated semiconductor layer 20, or is transmitted through the translucent electrode 15 and emitted to the outside. Thereby, the light extraction efficiency of the group III nitride semiconductor light-emitting element 1 is significantly increased.

  In addition, since the insulating layer 5 is disposed between the p-type electrode layer 40 and the p-type semiconductor layer 14, a current does not flow directly from the p-type electrode layer 40 to the p-type semiconductor layer 14. A current flows through the p-type semiconductor layer 14 through the translucent electrode 15 covering 40. As a result, current concentration is unlikely to occur, and seizure of the p-type semiconductor layer 14 can be prevented. For this reason, it is possible to prevent scorching and holes from occurring in the p-type semiconductor layer 14. In addition, since the p-type electrode layer 40 is made of metal, a sufficient amount of current flows through the linear p-type auxiliary electrode portion 40b, and current concentration can be suppressed.

Further, since the insulating layer 5 is made of silicon oxide, the insulating layer 5 having a flat surface is formed. As a result, a p-type electrode layer 40 having a flat surface is formed on the insulating layer 5. Therefore, it is possible to prevent the current flowing in the p-type electrode layer 40 from being biased.
Further, since the insulating layer 5 is made of a film mainly composed of an amorphous phase, the surface of the insulating layer 5 becomes a very smooth surface. For this reason, even if the thin p-type electrode layer 40 is formed on the insulating layer 5, there is no possibility that the p-type electrode layer 40 is divided. Therefore, the p-type electrode layer 40 having a small thickness can be formed, the light emitted from the light emitting layer 13 can be transmitted without being blocked, and the light extraction efficiency can be improved.
The p-type electrode layer 40 is made of at least one selected from the group consisting of Rh, Pd, Pt, Au, Ta, Nb, Ni, Ti, Cu, and Hf, thereby forming the translucent electrode 15. The influence on the p-type electrode layer 40 due to the heat treatment is suppressed. Therefore, the p-type electrode layer 40 having high flatness and high light transmittance is formed.

In addition, since the p-type bonding pad electrode 16 is inserted into the through hole 15a provided in the translucent electrode 15 immediately above the p-type pad portion 40a, the current is transferred from the p-type bonding pad electrode 16 to the p-type electrode layer. 40 can flow efficiently. Further, since the p-type bonding pad electrode 16 and the p-type electrode layer 40 are directly bonded, the bonding strength between the p-type bonding pad electrode 16 and the translucent electrode 15 can be improved. For this reason, generation | occurrence | production of the defect in the case of bonding work can be prevented.
As described above, the light extraction efficiency and reliability of the group III nitride semiconductor light emitting device 1 can be improved.

  Next, a method for manufacturing the group III nitride semiconductor light emitting device 1 shown in FIG. 1 will be described in detail with reference to the drawings as appropriate. The drawings referred to in the following description are for explaining the present invention, and the size, thickness, dimensions, etc. of the respective parts shown in the figure are the dimensional relationships of the actual group III nitride semiconductor light-emitting element 1. Is different.

  First, the laminated semiconductor layer 20 shown in FIG. 4 is manufactured. The method for manufacturing the laminated semiconductor layer 20 includes the step of laminating the buffer layer 21 and the underlayer 22 on the substrate 11, and the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14 are sequentially laminated on the underlayer 22. Forming the insulating layer 5 and the p-type electrode layer 40 on the p-type semiconductor layer 14, and forming the translucent electrode 15 so as to cover the p-type semiconductor layer 14 and the p-type electrode layer 40. And the process of carrying out. Hereafter, each process is demonstrated in detail using FIG.

First, a substrate 11 made of sapphire or the like is prepared.
Next, the substrate 11 is placed in a growth chamber of an MOCVD apparatus (metal organic chemical vapor deposition apparatus), and a buffer layer 21 is formed on the substrate 11 by MOCVD.

(Underlayer 22 forming step)
Next, the base layer 22 is stacked on the buffer layer 21. In the present invention, the buffer layer 21 made of AlN is formed on the substrate 11 made of sapphire or the like by RF sputtering, and the base layer 22 is sequentially laminated on the substrate in the growth chamber of the MOCVD apparatus. Also good.
As the material of the underlayer 22, it is particularly preferable to use Al _x Ga _1-x N (0 ≦ x <1) because the underlayer 22 with good crystallinity can be formed, but Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) may be used.

The underlayer 22 is preferably formed with a film thickness of 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. An Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness is increased. The underlayer 22 is preferably formed with a thickness of 10 μm or less.
In order to improve the crystallinity of the underlayer 22, it is desirable that the underlayer 22 is not doped with impurities.

(N contact layer 12a lamination process)
Next, an n contact layer 12 a is laminated on the substrate having the base layer 22.
When the n-contact layer 12a is grown, the temperature of the substrate 11 is preferably in the range of 1000 ° C. to 1100 ° C.
Further, as a raw material for growing the n-contact layer 12a, a group III metal organic metal source such as trimethylgallium (TMG) and a nitrogen source such as ammonia (NH ₃ ) are used, and the group III layer is formed on the buffer layer by thermal decomposition. A nitride semiconductor layer is deposited. The pressure in the growth chamber of the MOCVD apparatus is preferably 15 to 80 kPa.

(N-cladding layer 12b formation process)
Next, the n clad layer 12b is formed on the n contact layer 12a. The step of forming the n-clad layer 12b having a superlattice structure includes an n-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less, and an III-layer having a thickness of 100 angstroms or less that is different in composition from the n-side first layer. It can be set as the process of repeatedly stacking 20 to 80 layers alternately with the n-side second layer made of a group nitride semiconductor. The n-side first layer and / or the n-side second layer is preferably made of a gallium nitride compound semiconductor containing In.

(Light emitting layer 13 formation process)
Next, the light emitting layer 13 having a multiple quantum well structure is formed. First, the well layers 13b and the barrier layers 13a are alternately and repeatedly stacked. At this time, the layers are stacked so that the barrier layer 13a is disposed on the n-type semiconductor layer 12 side and the p-type semiconductor layer 14 side.
The composition and film thickness of the well layer 13b and the barrier layer 13a can be appropriately set so as to have a predetermined emission wavelength. Moreover, the substrate temperature at the time of growing the light emitting layer 13 can be 600-900 degreeC, and it is preferable to use nitrogen gas as carrier gas.
Thereafter, the substrate 11 on which the layers up to the light emitting layer 13 are formed is taken out from the growth chamber of the MOCVD apparatus.

(P-type semiconductor layer 14 forming step)
Next, the p-type semiconductor layer 14 is formed. The p-type semiconductor layer 14 may be formed by sequentially stacking a p-cladding layer 14a and a p-contact layer 14b on the light emitting layer 13. When the p-clad layer 14a is a layer including a superlattice structure, a p-type first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less and a film having a composition different from that of the p-type first layer are used. A p-type second layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less may be alternately and repeatedly stacked.

(Insulating layer 5 and p-type electrode layer 40 forming step)
First, an insulating layer and a metal film are sequentially stacked on the p contact layer 14b.
Next, a photoresist pattern (resist mask) (not shown) is formed on the metal film. Next, using the resist mask as a mask, the metal film and the insulating layer are etched to form the insulating layer 5 and the p-type electrode layer 40 in the same shape. Alternatively, lift-off may be performed after the photoresist pattern is formed first and the insulating layer and the metal film are formed.

  By this patterning, a first insulating layer 5a and a p-type pad portion 40a having substantially the same plan view shape as a p-type bonding pad electrode 16 to be described later, and a linear second insulating layer extending from the first insulating layer 5a 5b and the p-type auxiliary electrode part 40b are formed. At this time, the formation position of the resist mask is adjusted so that the p-type pad portion 40a is located immediately below the position where the p-type bonding pad electrode 16 is to be formed.

(Translucent electrode 15 formation process)
Next, the translucent electrode 15 is laminated so as to cover the p-type semiconductor layer 14 and the p-type electrode layer 40.
Next, the translucent electrode 15 other than the predetermined region is removed by, for example, a generally known photolithography technique. In this etching, it is preferable to provide a through hole 15a that penetrates the translucent electrode 15 and exposes a part of the p-type electrode layer 40 (p-type pad portion 40a). At this time, the diameter of the through-hole 15a is formed smaller than the diameter of the p-type pad portion 40a.
Thereafter, patterning is performed by, for example, a photolithography technique, and a part of the laminated semiconductor layer 20 in a predetermined region is etched to expose a part of the n contact layer 12a.

Thereafter, the n-type electrode 17 is formed on the exposed surface 20a of the n-contact layer 12a, and a film thickness of, for example, 1400 nm is formed at a position corresponding to the p-type pad portion 40a of the p-type electrode layer 40 (above the p-type pad portion 40a). A p-type bonding pad electrode 16 made of a metal laminated film is formed. At this time, by forming the p-type bonding pad electrode 16 so as to fill the through hole 15a, the p-type bonding pad electrode 16 having a structure penetrating the translucent electrode 15 is formed.
As described above, the group III nitride semiconductor light emitting device 1 shown in FIG. 1 is manufactured.

  According to the method for manufacturing a group III nitride semiconductor light emitting device of the present invention, the insulating layer 5 and the p-type electrode layer 40 are formed on the p-type semiconductor layer 14 in the same process. For this reason, the p-type electrode layer 40 can be formed without increasing the number of steps.

<Lamp 3>
The lamp 3 of the present embodiment includes the group III nitride semiconductor light emitting device 1 of the present invention, and is a combination of the above group III nitride semiconductor light emitting device 1 and a phosphor. The lamp 3 of the present embodiment can have a configuration well known to those skilled in the art by means well known to those skilled in the art. For example, in the lamp 3 of the present embodiment, a technique for changing the emission color by combining the group III nitride semiconductor light emitting device 1 and the phosphor can be adopted without any limitation.

  FIG. 5 is a schematic cross-sectional view showing an example of a lamp including the group III nitride semiconductor light-emitting element 1 shown in FIG. The lamp 3 shown in FIG. 3 is of a shell type, and uses a group III nitride semiconductor light emitting device 1 shown in FIG. As shown in FIG. 5, the p-type bonding pad electrode 16 of the group III nitride semiconductor light emitting device 1 is connected to one of the two frames 31 and 32 (the frame 31 in FIG. 5) by a wire 33, and the group III The n-type electrode 17 (bonding pad) of the nitride semiconductor light emitting device 1 is connected to the other frame 32 by a wire 34, whereby the group III nitride semiconductor light emitting device 1 is mounted. Further, the periphery of the group III nitride semiconductor light emitting device 1 is sealed with a mold 35 made of a transparent resin.

  Since the lamp 3 of the present embodiment uses the group III nitride semiconductor light emitting device 1 described above, a high light emission output can be obtained.

  In addition, electronic devices such as backlights, mobile phones, displays, various panels, computers, game machines, and lighting incorporating the lamp 3 of the present embodiment, and mechanical devices such as automobiles incorporating such electronic devices are expensive. The group III nitride semiconductor light emitting device 1 capable of obtaining a light emission output is provided. In particular, in an electronic device driven by a battery such as a backlight, a mobile phone, a display, a game machine, and an illumination, it is possible to provide an excellent product including the group III nitride semiconductor light-emitting element 1 that can obtain a high light emission output. Therefore, it is preferable.

Hereinafter, the method for producing a Group III nitride semiconductor light-emitting device of the present invention will be described in more detail with reference to Examples, but the present invention is not limited to these Examples.
Example 1
The group III nitride semiconductor light-emitting device 1 shown in FIG. 1 was manufactured by the method described below.
In the group III nitride semiconductor light-emitting device 1 of Example 1, a buffer layer 21 made of AlN and a base layer 22 made of undoped GaN having a thickness of 6 μm were formed on a substrate 11 made of sapphire. Next, a p-cladding layer 14a made of Mg-doped single layer Al _0.07 Ga _0.93 N having a thickness of 20 nm and a p-contact layer 14b made of Mg-doped p-type GaN having a thickness of 170 nm were sequentially laminated on the light emitting layer 13. Next, the insulating layer 5 (first insulating layer 5a and second insulating layer 5b) and the p-type electrode layer 40 (p-type pad portion 40a and p-type auxiliary electrode portion 40b) are stacked on the p-contact layer 14b. . The insulating layer and the p-type electrode layer 40 were formed under the following conditions.

“Formation conditions of insulating layer 5 and p-type electrode layer 40”
The insulating layer 5 was formed to a thickness of 50 nm using amorphous silicon oxide (SiO ₂ ) as a material. The second insulating layer 5b was formed to a width of 5000 nm.
The p-type electrode layer 40 was formed using Pt as a material and having a thickness of 20 nm. The p-type auxiliary electrode portion 40b was formed to a width of 4000 nm. Moreover, the p-type pad part 40a was formed in the diameter 1000 nm smaller than the 2nd insulating layer 5b.

Thereafter, a translucent electrode 15 made of ITO having a thickness of 200 nm was formed on the p-contact layer 14b and the p-type electrode layer 40 by a generally known photolithography technique.
Next, etching was performed using a photolithography technique to form an exposed surface 20a of the n contact layer 12a in a desired region.
During this etching, a through hole 15a that penetrates the translucent electrode 15 and exposes a part of the p-type pad portion 40a was provided.

Next, an n-type electrode 17 having a two-layer structure of Ti / Au was formed on the exposed surface 20a of the n-contact layer 12a. Next, a p-type bonding pad electrode structure 16 having a three-layer structure composed of a metal reflective layer made of 200 nm Al, a barrier layer made of 80 nm Ti, and a bonding layer made of 1100 nm Au so as to fill the through-hole 15a. It was formed using a photolithography technique. As a result, the p-type bonding pad electrode 16 configured to penetrate the translucent electrode 15 was formed.
As described above, the group III nitride semiconductor light-emitting device 1 of Example 1 shown in FIG. 1 was obtained.

  The properties of the group III nitride semiconductor light-emitting device 1 of Example 1 obtained in this way were a forward voltage Vf = 3.10 V and a light emission output Po = 21.0 mW.

(Example 2)
Example 1 is the same as Example 1 except that the thickness of the insulating layer 5 in Example 1 is 5 nm, the thickness of the p-type electrode layer 40 is 5 nm, and the width of the second insulating layer 5b and the p-type auxiliary electrode portion 40b is 40000 nm. The same operation was performed, and the forward voltage Vf = 3.14 V and the light emission output Po = 21.3 mW.

Example 3
The same operation as in Example 1 was performed except that the film thickness of the p-type electrode layer 40 in Example 1 was set to 30 nm and the width of the p-type auxiliary electrode part 40b was set to 3000 nm. The light emission output Po was 20.9 mW.

Example 4
The same operation as in Example 1 was performed except that the thickness of the insulating layer 5 in Example 1 was set to 70 nm and the width of the second insulating layer 5b was set to 4000 nm, and the forward voltage Vf = 3.08 V and the light emission output. Po = 21.2 mW.

(Example 5)
The same operation as in Example 1 was performed except that the width of the second insulating layer 5b in Example 1 was changed to 6000 nm and the p-type electrode layer 40 was changed to Rh, and the forward voltage Vf = 3.07 V, the light emission output Po. = 20.9 mW.

(Example 6)
The same operation as in Example 1 was performed except that the thickness of the insulating layer 5 in Example 1 was set to 2 nm, and the forward voltage Vf was 3.10 V and the light emission output Po was 21.0 mW.

(Example 7)
The same operation as in Example 1 was performed except that the thickness of the insulating layer 5 in Example 1 was changed to 100 nm. The forward voltage Vf was 3.10 V and the light emission output Po was 20.9 mW.

(Example 8)
The same operation as in Example 1 was performed except that the material of the p-type electrode layer 40 of Example 1 was Pd, and the forward voltage Vf = 3.12 V and the light emission output Po = 20.8 mW.

Example 9
The same operation as in Example 1 was performed except that the through-hole 15a of Example 1 was not provided and the p-type bonding pad electrode 16 was formed on the translucent electrode 15 at a position overlapping the p-type pad portion 40a. The forward voltage Vf = 3.12 V and the light emission output Po = 21.1 mW.

(Comparative Example 1)
The same operation as in Example 1 was performed except that the insulating layer 5 of Example 1 was not formed, and the forward voltage Vf = 3.30 V and the light emission output Po = 20.0 mW.

(Comparative Example 2)
The same operation as in Example 1 was performed except that the material of the insulating layer 5 in Example 1 was TiO ₂ , and the forward voltage Vf = 3.29 V and the light emission output Po = 19.8 mW.

(Comparative Example 3)
Except for changing the film thickness of the p-type electrode layer 40 of Example 1 to 3 nm, the same operation as in Example 1 was performed, and the forward voltage Vf = 3.28 V and the light emission output Po = 19.9 mW.

(Comparative Example 4)
Except that the film thickness of the p-type electrode layer 40 in Example 1 was set to 50 nm, the same operation as in Example 1 was performed, and the forward voltage Vf = 3.10 V and the light emission output Po = 20.1 mW.

(Comparative Example 5)
The same operation as in Example 1 was performed except that the width of the second insulating layer 5b in Example 1 was changed to 3500 nm, and the forward voltage Vf = 3.25 V and the light emission output Po = 20.3 mW.

(Comparative Example 6)
The same operation as in Example 1 was performed except that the width of the second insulating layer 5b in Example 1 was set to 7500 nm, and the forward voltage Vf = 3.11 V and the light emission output Po = 19.4 mW.

(Comparative Example 7)
The same operation as in Example 1 was performed except that the thickness of the insulating layer 5 in Example 1 was changed to 1 nm, and the forward voltage Vf = 3.11 V and the light emission output Po = 19.5 mW.

(Comparative Example 8)
The same operation as in Example 1 was performed except that the thickness of the insulating layer 5 in Example 1 was 200 nm, and the forward voltage Vf = 3.12 V and the light emission output Po = 20.1 mW.

Table 1 shows the results of forward voltage and light emission output (Po) of the group III nitride semiconductor light emitting devices of Examples 1 to 9 and Comparative Examples 1 to 8.
The forward voltage Vf for the group III nitride semiconductor light emitting device 1 of the example and the comparative example is a voltage measured at a current application value of 20 mA by energization with a probe needle. Similarly, the light emission outputs (Po) of the Group III nitride semiconductor light emitting devices 1 of Examples and Comparative Examples are each mounted in a TO-18 can package, and the light emission output at an applied current of 20 mA is measured by a tester.

As shown in Table 1, all of the group III nitride semiconductor light-emitting devices 1 of Examples 1 to 9 have a relatively low forward voltage, a sufficiently high light emission output (Po), high brightness, and low consumption. It was electric power.
On the other hand, in Comparative Examples 1 to 8, the light emission output (Po) was low and the forward voltage was relatively high compared to Examples 1 to 9.

  By the above, the group III nitride semiconductor light-emitting device 1 of Example 1 to Example 10 can effectively improve the light emission output, compared with the group III nitride semiconductor light-emitting device 1 of Comparative Example 1, It was confirmed that a high light emission output was obtained.

DESCRIPTION OF SYMBOLS 1 ... Group III nitride semiconductor light-emitting device, 3 ... Lamp, 5 ... Insulating layer, 5a ... 1st insulating layer, 5b ... 2nd insulating layer, 12 ... n-type semiconductor layer, 12a ... n contact layer, 12b ... n-cladding layer, 13 ... light-emitting layer, 14 ... p-type semiconductor layer, 14b ... p-contact layer, 15 ... translucent electrode, 15a ... through-hole, 16 ... p-type bonding pad electrode, 22 ... underlayer, 40 ... p Type electrode layer 40a ... p-type pad part, 40b ... p-type auxiliary electrode part

Claims (19)

Sequentially stacking an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate;
Forming an insulating layer and a p-type electrode layer made of a metal having a p-type pad portion and a linear p-type auxiliary electrode portion extending from the p-type pad portion on the p-type semiconductor layer;
Forming a translucent electrode so as to cover the p-type semiconductor layer and the p-type electrode layer;
Forming a p-type bonding pad electrode at a position overlapping the p-type pad portion of the p-type electrode layer on the translucent electrode. A Group III nitride semiconductor comprising: Manufacturing method of light emitting element.   The method for manufacturing a group III nitride semiconductor light-emitting element according to claim 1, wherein the insulating layer is made of a film mainly composed of an amorphous phase. In the step of forming the p-type bonding pad electrode,
After forming a through-hole in the translucent electrode layer on the p-type pad portion, the p-type bonding pad electrode is formed so as to fill the through-hole, whereby the p-type bonding pad electrode and the p-type pad are formed. 3. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 1, wherein the mold pad portion is joined.   The method for producing a group III nitride semiconductor light-emitting device according to claim 1, wherein the p-type electrode layer is formed with a film thickness of 5 nm to 30 nm.   5. The method for producing a group III nitride semiconductor light-emitting device according to claim 1, wherein the insulating layer is formed with a film thickness of 2 nm to 100 nm.   6. The method for manufacturing a group III nitride semiconductor light-emitting device according to claim 1, wherein the p-type electrode layer is formed with a width smaller than the insulating layer by 0 nm to 2000 nm.   7. The p-type electrode layer is made of at least one selected from the group consisting of Rh, Pd, Pt, Au, Ta, Nb, Ni, Ti, Cu, and Hf. A method for producing a group III nitride semiconductor light-emitting device according to claim 1.   The method for manufacturing a group III nitride semiconductor light-emitting element according to claim 1, wherein the insulating layer is made of silicon oxide. a stacked semiconductor layer in which an n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are sequentially stacked;
A p-type electrode layer made of metal disposed on the p-type semiconductor layer and having a p-type pad portion and a linear p-type auxiliary electrode portion extending from the p-type pad portion;
An insulating layer disposed between the p-type electrode layer and the p-type semiconductor layer;
A translucent electrode covering the p-type semiconductor layer and the p-type electrode layer;
And a p-type bonding pad electrode formed on the translucent electrode at a position overlapping the p-type pad portion of the p-type electrode layer. element.   The group III nitride semiconductor light-emitting device according to claim 9, wherein the insulating layer is made of a film mainly composed of an amorphous phase.   A through hole is provided in the translucent electrode layer on the p-type pad portion, the p-type bonding pad electrode is inserted into the through-hole, and the p-type bonding pad electrode and the p-type pad portion are joined. The group III nitride semiconductor light-emitting device according to claim 9 or 10, wherein:   The group III nitride semiconductor light-emitting device according to any one of claims 9 to 11, wherein the p-type electrode layer is formed with a thickness of 5 nm to 30 nm.   The group III nitride semiconductor light-emitting device according to claim 9, wherein the insulating layer is formed with a thickness of 2 nm to 100 nm.   14. The group III nitride semiconductor light-emitting element according to claim 9, wherein the p-type auxiliary electrode portion is formed with a width smaller than the insulating layer by 0 nm to 2000 nm.   15. The p-type electrode layer is made of at least one selected from the group consisting of Rh, Pd, Pt, Au, Ta, Nb, Ni, Ti, Cu, and Hf. The group III nitride semiconductor light-emitting device according to one item.   The group III nitride semiconductor light-emitting device according to claim 9, wherein the insulating layer is made of silicon oxide.   A lamp comprising the group III nitride semiconductor light-emitting device according to any one of claims 9 to 16.   An electronic device comprising the lamp according to claim 17 incorporated therein.   19. A mechanical apparatus in which the electronic apparatus according to claim 18 is incorporated.

Images