JP2012134659A - Image processing device and image processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processing device and an image processing method capable of compressing both a multivalued image and a small-valued image with sufficient compressibility.SOLUTION: The image processing device comprises a coding part 204 which performs coding. When coding of the multivalued image is designated with a coding designation signal, the coding part 204 codes the multivalued image by a prediction error system using a prediction error value calculated by a prediction error generation processing part 301. When coding of the small-valued image is designated with the coding designation signal on the other hand, the coding part 204 codes the small-valued image by a coding system different from the prediction error system.

Description

  The present invention relates to an image processing apparatus and an image processing method.

  An image forming apparatus such as a printer temporarily stores input image data in a memory, reads the image data stored in the memory at a predetermined timing, and performs a printing operation. In this case, if the image data is stored in the memory as it is, a large-capacity memory is required and the cost increases. Therefore, generally, input image data is compression-encoded and stored in a memory.

  For example, in Patent Document 1, a binary image (low-value image) having a gradation number of 1 bit (gradation number “2”) and a multi-value image having a gradation number exceeding 1 bit are compressed at each time. A technique is disclosed in which encoding is performed by a prediction error method using a prediction error value that is a difference between a pixel value of a pixel to be encoded (“target pixel”) and a predicted value of the pixel value of the target pixel. .

  However, although the above-described prediction error method is a method suitable for compressing and encoding a multi-valued image, it is not suitable for compressing and encoding a small-valued image, so that a sufficient compression rate is obtained for a small-valued image. There is a problem that it is difficult.

  The present invention has been made in view of the above, and an object of the present invention is to encode both a multi-value image and a low-value image with a sufficient compression rate.

  In order to solve the above-described problems and achieve the object, the present invention provides a plurality of pixels constituting a multi-valued image having a gradation number exceeding a predetermined number or a low-value image having a gradation number equal to or less than the predetermined number. The first storage means in which each pixel value is written, the first readout means for reading out the pixel value of the target pixel to be encoded from the first storage means, and the pixel values of the pixels around the target pixel Based on the first predicted value calculating means for calculating the predicted value of the pixel value of the target pixel based on the prediction value calculated by the first predicted value calculating means and the pixel value of the target pixel. When encoding the multi-valued image with a first prediction error value calculation unit that calculates a prediction error value, encoding is performed by a prediction error method using the prediction error value calculated by the prediction error calculation unit. On the other hand, when encoding the low-value image, the pre- It characterized in that it comprises an encoding unit performs encoding in different encoding schemes and error method.

  Further, the present invention provides a first storage means in which pixel values of a plurality of pixels constituting a multi-value image having a predetermined number of gradations or a low-value image having a number of gradations less than the predetermined number are written. A first step of reading a pixel value of a target pixel that is an encoding target, and a second step of calculating a predicted value of the pixel value of the target pixel based on pixel values of pixels around the target pixel; A third step of calculating a prediction error value which is a difference between the predicted value calculated in the second step and a pixel value of the target pixel; and a third step when encoding the multi-valued image. On the other hand, when encoding is performed with the prediction error method using the prediction error value calculated in step 4, while encoding the low-value image, encoding is performed with an encoding method different from the prediction error method. And a step.

  According to the present invention, when encoding a multi-level image, encoding is performed using a prediction error method, while when encoding a low-value image, encoding is performed using a coding method different from the prediction error method. Therefore, an advantageous effect is achieved in that the compression ratio of the low-value image can be increased as compared with the configuration in which both the multi-value image and the low-value image are encoded by the prediction error method.

FIG. 1 is a schematic diagram illustrating a configuration example of a mechanism unit of an image forming apparatus to which an image processing apparatus according to an embodiment of the present invention can be applied. FIG. 2 is a block diagram illustrating an example of the configuration of the electrical / control apparatus in the image forming apparatus. FIG. 3 is a flowchart schematically showing an example of the overall operation of the image forming apparatus. FIG. 4 is a diagram illustrating an example of the configuration of the encoding unit. FIG. 5 is a diagram illustrating an example of the configuration of the prediction error generation processing unit. FIG. 6 is a diagram for explaining the peripheral pixels of the target pixel. FIG. 7 is a diagram for explaining a calculation method of the prediction process. FIG. 8 is a diagram illustrating an example of a code format. FIG. 9 is a diagram for explaining the encoding process of the present embodiment. FIG. 10A is a diagram for explaining flag processing in the slide search processing and the list search processing. FIG. 10-2 is a diagram for explaining flag processing in the slide search processing and the list search processing. FIG. 11A is a diagram for explaining the slide search process and the list search process when the flag process is performed. FIG. 11B is a diagram for explaining the slide search process and the list search process when the flag process is performed. FIG. 11C is a diagram for explaining slide search processing and list search processing when flag processing is performed. FIG. 11D is a diagram for explaining the slide search process and the list search process when the flag process is performed. FIG. 11-5 is a diagram for explaining slide search processing and list search processing when flag processing is performed. FIG. 11-6 is a diagram for explaining slide search processing and list search processing when flag processing is performed. FIG. 11-7 is a diagram for explaining the slide search process and the list search process when the flag process is performed. FIG. 11-8 is a diagram for explaining slide search processing and list search processing when flag processing is performed. FIG. 12 is a flowchart illustrating an example of the overall flow of the encoding process according to the present embodiment. FIG. 13 is a flowchart illustrating an example of detailed contents of the slide search process. FIG. 14 is a flowchart illustrating an example of detailed contents of the list search process. FIG. 15 is a flowchart illustrating an example of detailed contents of the slide addition process. FIG. 16 is a flowchart illustrating an example of detailed contents of the code generation process. FIG. 17 is a diagram illustrating an example of a detailed configuration of the encoding unit. FIG. 18 is a diagram illustrating an example of a hardware configuration of the slide / list generation processing unit. FIG. 19 is a diagram illustrating an example of the configuration of the decoding unit. FIG. 20 is a diagram illustrating an example of a detailed configuration of the prediction processing unit. FIG. 21 is a flowchart illustrating an example of the decoding process. FIG. 22 is a flowchart illustrating an example of a slide decoded value calculation process. FIG. 23 is a flowchart illustrating an example of an ESC decoded value calculation process. FIG. 24 is a diagram illustrating an example of a detailed configuration of the decoding unit. FIG. 25 is a diagram illustrating an example of a hardware configuration of the slide development unit.

  Hereinafter, an embodiment of an image processing apparatus according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an example of the structure of a mechanism unit of an image forming apparatus (referred to as a color printer) to which the image processing apparatus according to the present embodiment can be applied. In this embodiment, an example in which the image processing apparatus and the image processing method according to the present invention are applied to an image forming apparatus that is a color printer will be described. However, as long as image processing is performed on an image including a character image, However, the present invention is not limited to this. For example, the present invention can be applied to an image processing apparatus such as a copying machine, a facsimile machine, and a multifunction machine.

<Example of Printer Applicable to Embodiment>
The printer apparatus 200 illustrated in FIG. 1 forms four color (Y, M, C, K) images with independent image forming systems 1Y, 1M, 1C, and 1K, and synthesizes these four color images. This is a 4-drum tandem engine type image forming apparatus. Each of the image forming systems 1Y, 1M, 1C, and 1K includes a photoconductor as an image carrier, for example, small-diameter OPC (organic photoconductor) drums 2Y, 2M, 2C, and 2K, and the OPC drums 2Y, 2M, and 2C. The electrostatic latent images on the charging rollers 3Y, 3M, 3C, and 3K as charging means and the OPC drums 2Y, 2M, 2C, and 2K are developed with a developer from the upstream side of image formation so as to surround 2K. Developing devices 4Y, 4M, 4C, and 4K that generate toner images of Y, M, C, and K colors, cleaning devices 5Y, 5M, 5C, and 5K, and static eliminating devices 6Y, 6M, 6C, and 6K are arranged. .

  Beside each developing device 4Y, 4M, 4C, 4K, toner bottle units 7Y, 7M, 7C, 7K for supplying Y toner, M toner, C toner, K toner to the developing devices 4Y, 4M, 4C, 4K, respectively. Is arranged. Each image forming system 1Y, 1M, 1C, and 1K is provided with an independent optical writing device 8Y, 8M, 8C, and 8K. The optical writing devices 8Y, 8M, 8C, and 8K are laser diodes (laser light sources). LD) Light source 9Y, 9M, 9C, 9K, collimating lens 10Y, 10M, 10C, 10K, fθ lens 11Y, 11M, 11C, 11K, and other optical components, polygon mirrors 12Y, 12M, 12C, 12K as deflection scanning means And folding mirrors 13Y, 13M, 13C, 13K, 14Y, 14M, 14C, 14K, and the like.

  The image forming systems 1Y, 1M, 1C, and 1K are arranged vertically, and the transfer belt unit 15 is arranged on the right side so as to be in contact with the OPC drums 2Y, 2M, 2C, and 2K. The transfer belt unit 15 is rotationally driven by a drive source (not shown) with the transfer belt 16 stretched around rollers 17 to 20. A paper feed tray 21 storing transfer paper as a transfer material is disposed on the lower side of the apparatus, and a fixing device 22, a paper discharge roller 23, and a paper discharge tray 24 are disposed at the top of the apparatus.

  At the time of image formation, in each image forming system 1Y, 1M, 1C, 1K, the OPC drums 2Y, 2M, 2C, 2K are rotationally driven by a driving source (not shown), and the OPC drums by the charging rollers 3Y, 3M, 3C, 3K. The 2Y, 2M, 2C, and 2K are uniformly charged, and the optical writing devices 8Y, 8M, 8C, and 8K perform optical writing on the OPC drums 2Y, 2M, 2C, and 2K based on the image data of each color, so that the OPC drum Electrostatic latent images are formed on 2Y, 2M, 2C, and 2K.

  The electrostatic latent images on the OPC drums 2Y, 2M, 2C, and 2K are developed by developing devices 4Y, 4M, 4C, and 4K, respectively, to become toner images of colors Y, M, C, and K, while the paper feed tray 21 Then, the transfer paper is fed in the horizontal direction from the paper feed roller 25 and is conveyed vertically in the image forming systems 1Y, 1M, 1C and 1K by the transport system. This transfer paper is electrostatically held by the transfer belt 16 and conveyed by the transfer belt 16, and a transfer bias is applied by a transfer bias applying means (not shown), and Y on the OPC drums 2Y, 2M, 2C, 2K, A full color image is formed by sequentially superimposing and transferring toner images of M, C, and K colors. The transfer sheet on which the full-color image is formed is fixed to the full-color image by the fixing device 22 and is discharged to the discharge tray 24 by the discharge roller 23.

  FIG. 2 is a block diagram showing an example of the configuration of the electrical / control system of the printer apparatus 200 of FIG. In the example of FIG. 2, the printer device 200 includes a control unit 230, a main memory 210, and a printer engine 211. The control unit 230 includes a CPU (Central Processing Unit) 212, a CPU I / F 201, a main memory arbiter 202, a main memory controller 203, an encoding unit 204, a decoding unit 205, a gradation processing unit 206, A multiplex (MUX) 207 and an engine controller 208 are included.

  The CPU 212 controls the overall operation of the printer apparatus 200 in accordance with a program stored in the main memory 210. The CPU 212 is connected to the main memory arbiter 202 via the CPU I / F 201. The main memory arbiter 202 arbitrates access to the main memory 210 by the CPU 212, the encoding unit 204, the decoding unit 205, and the communication controller 209.

  The main memory 210 is connected to the main memory arbiter 202 via the main memory controller 203. The main memory controller 203 controls access to the main memory 210.

  The main memory 210 has a program area 210A, a PDL data storage area 210B, a CMYK band image data storage area 210C, a CMYK page code storage area 210D, and another area 210E. The program area 210A stores a program for the CPU 212 to operate. In the PDL data storage area 210B, for example, PDL data supplied from the computer 220 via the communication controller 209 is stored. The CMYK band image data storage area 210C stores CMYK band image data. The CMYK page code storage area 210D stores code data obtained by compression-coding band image data. The CMYK page code storage area 210D stores, for example, code data obtained by compression-coding CMYK band image data for one page. The area 210E stores data other than those described above.

  The encoding unit 204 encodes band image data stored in the main memory 210. Code data obtained by encoding band image data is supplied to the main memory 210 via the main memory arbiter 202 and the memory controller 203, and is written in the CMYK page code storage area 210D. The decoding unit 205 reads and decodes code data from the CMYK page code storage area 210D of the main memory 210 in synchronization with a printer engine 211 described later. When the decoding unit 205 executes a decoding process for a multi-value image in which the number of gradations exceeds a predetermined number, the decoded image data is supplied to the gradation processing unit 206 and subjected to the gradation processing to be multiplexed. 207. On the other hand, when the decoding unit 205 executes the decoding process of the low-value image having the number of gradations equal to or less than the predetermined number, the decoded image data is not supplied to the gradation processing unit 206 but is sent to the multiplex 207. Supplied directly. In this embodiment, image data having a gradation number of 2 bits (gradation number “4”) or less is a low-value image, and image data having a gradation number of more than 2 bits is a multi-value image. The value of the number of gradations for discriminating between an image and a multi-valued image can be arbitrarily set. For example, image data with a gradation number of 1 bit or less is used as a low-value image, and image data with a gradation number exceeding 1 bit. Can be a multi-valued image.

  The multiplex 207 transfers the image data (decoded image data) subjected to the gradation processing by the gradation processing unit 206 to the engine controller 208 when the decoding unit 205 executes the decoding process of the multilevel image. To do. On the other hand, the multiplex 207 transfers the image data (decoded image data) directly passed from the decoding unit 205 to the engine controller 208 when the decoding unit 205 executes the decoding process of the low-value image.

  The engine controller 208 controls the printer engine 211. In FIG. 1, only one of the CMYK color plates is described as the printer engine 211, and the other plates are omitted to avoid complications.

  The communication controller 209 controls communication via the network. For example, PDL (Page DESCription Language) data output from the computer 220 is received by the communication controller 209 via the network. The communication controller 209 transfers the received PDL data to the main memory 210 via the main memory arbiter 202 and the main memory controller 203.

  The network may be one that performs communication within a predetermined range such as a LAN (Local Area Network), or may be one that can communicate over a wider range than the Internet. The network is not limited to wired communication but may be wireless communication, or may be serial communication such as USB (Universal Serial Bus) or IEEE (Institute Electrical and Electronics Engineers) 1394.

  Next, an example of the overall operation of the printer apparatus 200 will be described with reference to FIG. FIG. 3 is a flowchart schematically showing an example of the overall operation when the printer apparatus 200 performs encoding and decoding of a multi-valued image.

  For example, PDL data generated by the computer 220 is received by the communication controller 209 via the network and stored in the PDL data storage area 210B of the main memory 210 (step S1). The CPU 212 reads the PDL data from the PDL data storage area 210B of the main memory 210 according to the path A, analyzes the PDL (step S2), and draws a multi-value CMYK band image based on the analysis result (step S3). The drawn CMYK band image data based on the drawn multi-value CMYK band image is stored in the CMYK band image data storage area 210C of the main memory 210 (step S4).

  The encoding unit 204 reads the CMYK band image data from the CMYK band image data storage area 210C according to the path B, and encodes it using the encoding method according to each embodiment of the present invention (step S5). Code data obtained by encoding the CMYK band image data is stored in the CMYK page code storage area 210D of the main memory 210 along the path C (step S6).

  The decoding unit 205 reads out the code data from the CMYK page code storage area 210D along the path D, decodes it into image data (step S7), and supplies the decoded image data to the gradation processing unit 206. The gradation processing unit 206 performs gradation processing on the multi-valued image supplied from the decoding unit 205 (step S8), and supplies it to the printer engine controller 208 along the path E. The engine controller 208 performs printout by controlling the engine 211 based on the supplied image data (step S9).

  In the overall operation when the printer device 200 encodes and decodes a low-value image, the gradation processing by the gradation processing unit 206 in step S8 described above is omitted, but other operations are as follows. This is almost the same as the contents of FIG.

<Outline of encoding process>
FIG. 4 shows an example of the configuration of the encoding unit 204 according to this embodiment. The encoding unit 204 includes a data reading unit 300, a prediction error generation processing unit 301, multiplexes 302 and 303, a slide / list generation processing unit 304, a code format generation processing unit 305, and a code writing unit 306. Have. In the present embodiment, the encoding unit 204 encodes the prediction error method using the prediction error value generated by the prediction error generation processing unit 301 when encoding a multi-valued image, while reducing the small value. When encoding an image, encoding is performed using an encoding method different from the prediction error method. Hereinafter, specific contents will be described in detail.

  The data reading unit 300 reads CMYK band image data for each version of CMYK from the CMYK band image data storage area 210 </ b> C of the main memory 210. At this time, CMYK band image data for each version of CMYK is sequentially read from the CMYK band image data storage area 210C in units of pixels by the data reading unit 300 for each scan line. Also, the CPU 212 sends an encoding designation signal for designating either multi-value image encoding or low-value image encoding to the data reading unit 300. When encoding of a multi-valued image is specified by the encoding specifying signal, the data reading unit 300 supplies the read pixel unit image data (pixel value) to the prediction error generation processing unit 301 at the subsequent stage, while When encoding of a small-value image is specified by the conversion specifying signal, the data reading unit 300 supplies the read pixel value to each of the multiplexes 302 and 303. In the present embodiment, when encoding of a small-value image is specified by the encoding specifying signal, the data reading unit 300 does not supply the read pixel value to the prediction error generation processing unit 301, but this is not limitative. Instead, the data reading unit 300 can supply the read pixel values to the prediction error generation processing unit 301 and the multiplexes 302 and 303 even when encoding of a small value image is designated.

  The prediction error generation processing unit 301 receives the pixel value of the pixel to be encoded (referred to as “target pixel”) read by the data reading unit 300, and calculates the predicted pixel value of the target pixel. Then, a prediction error value that is a difference between the calculated predicted pixel value and the pixel value of the target pixel received from the data reading unit 300 is calculated. More specific description will be given below.

  FIG. 5 is a diagram illustrating an example of a more detailed configuration of the prediction error generation processing unit 301. As illustrated in FIG. 5, the prediction error generation processing unit 301 includes a line memory control unit 307, a line memory 308, a prediction processing unit 309, and a prediction error processing unit 310. The line memory control unit 307 stores the pixel value read by the data reading unit 300 in the line memory 308. In the present embodiment, the line memory 308 can store pixel values for two lines, stores the pixel values supplied this time, and holds the pixel values for one line stored immediately before. Controlled by the memory control unit 307.

  More specifically, the line memory 308 can store pixel values for one line, and includes a first area in which pixel values of the target pixel are sequentially written and a line immediately before the line to which the target pixel belongs. And a second area in which pixel values of lines that have already been encoded are stored.

  Under the control of the line memory control unit 307, the pixel value of the target pixel and the pixel values of the three neighboring pixels of the target pixel are sequentially read from the line memory 308 and passed to the prediction processing unit 309. Here, the peripheral three pixels read from the line memory 308 are pixels that have already been encoded and are close to the target pixel. More specifically, as illustrated in FIG. 6, the immediately preceding pixel a in the scan order of the target pixel and the previous line in the scan order with respect to the current line to which the target pixel belongs, that is, the target pixel The pixel b located immediately above the target pixel in the line immediately above the line to which it belongs and the pixel c immediately before in the scanning order of the pixel b. In the following, the line to which the target pixel to be encoded belongs is called the current line, and the line immediately before the current line in the scan order is called the previous line.

The prediction processing unit 309 predicts the pixel value of the target pixel based on the pixel a, the pixel b, and the pixel c passed from the line memory control unit 307. In the present embodiment, the prediction processing unit 309 predicts the pixel value of the target pixel using a planar prediction method. As illustrated in FIG. 7, the plane prediction method includes a pixel a encoded immediately before the target pixel in the current line, a pixel b adjacent to each of the target pixel and the pixel a in the previous line, Using the pixel c, the following equation (1) is calculated to obtain the predicted value of the target pixel.
Predicted value = a + bc (1)

  Note that when the target pixel is the first pixel in the line scan order and when the current line is the first line in the scan order, the plane prediction value is assumed to be zero.

  Returning to FIG. 5 again, the description will be continued. The prediction error processing unit 310 calculates a prediction error value that is a difference between the pixel value of the target pixel and the planar prediction error value obtained by the prediction processing unit 309, and calculates the calculated prediction error value and the pixel value of the target pixel. Are sent to the subsequent multiplexes 302 and 303 (see FIG. 4).

  Returning to FIG. 4, the description will be continued. The encoding designation signal is sent from the CPU 212 to each of the multiplexes 302 and 303. Further, the pixel value of the target pixel read by the data reading unit 300 is supplied to one input end of the multiplex 302, and the pixel of the target pixel from the prediction error generation processing unit 301 is supplied to the other input end. A value is supplied. The pixel value of the target pixel read by the data reading unit 300 is supplied to one input end of the multiplex 303, and the prediction error value from the prediction error generation processing unit 301 is supplied to the other input end. The

  Here, when encoding of a multi-valued image is specified by the encoding specifying signal, the multiplex 302 receives the pixel value of the target pixel (supplied from the prediction error generation processing unit 301) supplied to the other input end. (Pixel value) is supplied to the subsequent slide / list generation processing unit 304 as ESC encoding data. In addition, the multiplex 303 uses the prediction error value supplied to the other input terminal (the prediction error value supplied from the prediction error generation processing unit 301) as Slide encoding data for the subsequent slide / list generation processing unit 304. To supply.

  On the other hand, when encoding of a low-value image is specified by the encoding specification signal, the multiplex 302 receives the pixel value of the target pixel supplied to one input end (pixel value supplied from the data reading unit 300). Is supplied to the subsequent slide / list generation processing unit 304 as ESC encoding data. Also, the multiplex 303 uses the pixel value of the target pixel supplied to one input terminal (the pixel value supplied from the data reading unit 300) as Slide encoding data to the subsequent slide / list generation processing unit 304. Supply.

  The slide / list generation processing unit 304 includes a FIFO (First In First Out) type slide storage unit that stores Slide encoding data sequentially input from the multiplex 303. In this embodiment, when encoding of a multi-valued image is specified by the encoding specifying signal, the slide encoding data sent from the multiplex 303 to the slide / list generation processing unit 304 is a prediction error value. In this case, prediction errors are sequentially input to the slide storage unit from one end. The slide storage unit stores the input prediction error value and moves the already stored prediction error value to the other end and stores it. On the other hand, when encoding of a low-value image is specified by the encoding specifying signal, the slide encoding data sent from the multiplex 303 to the slide / list generation processing unit 304 is the pixel value of the target pixel. In this case, the pixel value of the target pixel is sequentially input from one end to the slide storage unit. The slide storage unit stores the input pixel value and moves the already stored pixel value to the other end to store it.

  The slide / list generation processing unit 304 compares the supplied slide encoding data with each of the past slide encoding data stored in the slide storage unit. When encoding of a multi-valued image is specified by the encoding specification signal, the supplied prediction error value is compared with each of the past prediction error values stored in the slide storage unit, while the encoding specification signal is used. When encoding of a low-value image is designated, the supplied pixel value is compared with each of past pixel values stored in the slide storage unit.

  When the supplied slide encoding data matches the past slide encoding data, the slide / list generation processing unit 304 matches the input data string composed of the sequentially input slide encoding data. Then, a list search process is performed to search for a data sequence (referred to as “list”) made up of Slide encoding data already stored in the slide storage unit. When encoding of a multi-valued image is specified by an encoding specifying signal, and the supplied prediction error value matches the past prediction error value, prediction error value data that is sequentially input A data string (“list”) consisting of prediction error values that are already stored in the slide storage unit and that matches the input data string consisting of is searched. On the other hand, when encoding of a low-value image is specified by the encoding specifying signal and the supplied pixel value matches the past pixel value, the pixel values are sequentially input. For example, a search is made for a data string (“list”) that is identical to the input data string and that is composed of pixel values that are already stored in the slide storage unit.

  Then, the slide / list generation processing unit 304 obtains the length information Length indicating the length of the list obtained from the result of the list search process described above and the result of the list search process when the above comparison is performed. The address information Address indicating the position in the slide storage unit in which the start data of the list is stored is generated and sent to the code format generation processing unit 305 in the subsequent stage.

  On the other hand, if the supplied slide encoding data does not match any of the past slide encoding data in the slide storage unit, the slide / list generation processing unit 304 supplies from the multiplex 302. The obtained ESC encoding data is output as an ESC value to the subsequent code format generation processing unit 305. Further, the slide / list generation processing unit 304 outputs a comparison result flag SlideFLAG indicating the above-described comparison result to the code format generation processing unit 305 at the subsequent stage. If the comparison result is positive, the comparison result flag SlideFLAG is set to “1”, while if the comparison result is negative, the comparison result flag SlideFLAG is set to “0”. .

  The code format generation processing unit 305 generates an ESC code, a Slide code, and a line end code in the format illustrated in FIG. 8 from the supplied ESC value, address information Address, length information Length, and comparison result flag SlideFLAG. To do.

  The ESC code is obtained by encoding an ESC value. As shown in FIG. 8, the ESC code is formed by connecting a pixel value having a data length of 8 bits with a flag SlidFLAG having a data length of 1 bit and a value “0” as a header. In the Slide code, a comparison result flag SlideFLAG having a data length of 1 bit and a value “1” is used as a header, and then length information Length and address information Address each having a data length of 8 bits are sequentially connected. The line end code is a code indicating the line end, and is composed of data having a data length of 2 bits and a value of “11”. Note that the code format illustrated in FIG. 8 is an example, and the present invention is not limited to this.

  Each of the ESC code, Slide code, and line end code generated by the code format generation processing unit 305 is supplied to the code writing unit 306. The code writing unit 306 writes the supplied ESC code, Slide code, and line end code in the CMYK page code storage area 210D of the main memory 210 via the main memory arbiter 202 and the main memory controller 203.

  Next, an overview of the encoding process performed by the encoding unit 204 of the present embodiment will be described. The encoding unit 204 basically encodes data by repeating the slide search process and the list search process. The slide search process searches for past input data (Slide encoding data) stored in the slide storage unit that matches input data (Slide encoding data) of one unit (for example, 1 byte). If no data matching the input data is found in the past data in the slide storage unit, the input data itself is encoded using the ESC value.

  In the slide search process, when past input data in the slide storage unit that matches the input data is searched, the list search process described above is performed using the matched past data as a route. Then, the position in the slide storage unit of the past data that becomes the root of the list searched in the list search process is output as address information Address, and the length of the list is output as length information Length, and the information is encoded. .

  This will be described more specifically with reference to FIG. In the present embodiment, the slide storage unit has 128 registers connected in series and is configured as a FIFO (First In First Out), but in the example of FIG. 9, the numbers # 0 to # 15 are connected in series. Description will be made by paying attention to the 16 connected registers. Each register can store one unit (for example, 1 byte) of data. Hereinafter, a register included in the slide storage unit is referred to as a slide.

  In the process # 1, each slide in the slide storage unit has a new input order, that is, “a, b, c, a, a, b, c, a, b, c” from the right side to the left side in FIG. , D, b, c, a, c, a ”and 16 previously input data are already stored. First, input data “a” is input to the slide / list generation processing unit 304. Through the slide search process, the input data “a” is compared with each of the past input data stored in each slide to search for matching data. In the example of FIG. 9, it can be seen that the data stored in the slides with numbers # 0, # 3, # 4, # 7, # 13 and # 15 match the input data. Therefore, the data stored in the slides with these numbers is the route in the list search process.

  Since the data that matches the input data “a” is searched from the past data stored in each slide by the slide search process, the list search process of process # 2 is performed.

  In the process # 2, the past data stored in each slide is shifted to the left by 1, and the input data “a” input in the process # 1 is added to the slide with the number # 0 in the slide storage unit. At the same time, the next input data “c” is input to the slide / list generation processing unit 304. In the list search process, new slides (# 0, # 3, # 4, # 7, # 13, and # 15) in which data that matches the input data in the previous process # 1 are stored are newly added. Data that matches the correct input data “c” is searched.

  In the example of FIG. 9, the past data stored in the slides with the numbers # 0 and # 4 that match the input data in the process # 1 do not match the input data in the process # 2. On the other hand, in the process # 2, the past data stored in the slides of the numbers # 3, # 7, # 13 and # 15 is the data “c” and matches the new input data “c”.

  From the slide (# 0, # 3, # 4, # 7, # 13 and # 15) in which the data whose input data matches in the previous process # 1 is stored by the list search process of the process # 2, the process # 2 Since the data that matches the input data “c” is searched, the next process is a list search process. Since process # 2 is the starting point of the list search process, the length Length indicating the length of the list is set to the value “0”.

  In the process # 3, similarly to the process # 2 described above, the past data stored in each slide is shifted to the left by 1, and the input data “c” input in the process # 2 is stored in the slide storage unit. Add to slide # 0. At the same time, the next input data “b” is input to the slide / list generation processing unit 304. Then, among the slides, new input data “# 3, # 7, # 13, and # 15” from the slide (# 3, # 7, # 13, and # 15) in which past data matching the input data in the process # 1 and the immediately preceding process # 2 is stored. Search for data matching b ”.

  In the example of FIG. 9, the past data stored in the slide of number # 15 does not match the input data in process # 3. On the other hand, in the process # 3, the past data stored in the slides of the numbers # 3, # 7 and # 13 is “b”, which matches the new input data “b”. In the next process # 4, the past data stored in the slides of the numbers # 3, # 7 and # 13 are subjected to list search. That is, at the stage of the process # 3, the lists relating to the numbers # 3, # 7, and # 13 remain. In the process # 3, the length of the list is “1”, and the value of the length Length information is “1”.

  Such processing is repeated to obtain a data string having the longest list. In the example of FIG. 9, in the process # 5, the past data “c” stored in the slide of the number # 13 searched in the list in the immediately preceding process # 4 and the new input data “g” no longer match. The list is interrupted. Therefore, in process # 5, 1 is selected from the list remaining in the previous process # 4, and the list starts in the slide search process (process # 1 in the example of FIG. 9) immediately before the list search process. The position in the slide storage unit where data is stored is set as address information Address, and the length of the list is encoded as Slide information as length information Length. In the example of FIG. 9, the value of the address information Address is “13”, and the value of the length information Length is “3”.

  Further, in process # 5, a slide search process is performed on the input data “g”. In this example, since data “g” is not stored as past data in each slide, there is no matching data. In this case, the process proceeds to process # 6, and the ESC encoding data supplied to the slide / list generation processing unit 304 together with the input data “g” is used as an ESC value and encoded into an ESC code.

  When encoding to the ESC code is performed, the past data stored in each slide is shifted left by 1 in process # 7, and the input input in the previous list search process (process # 5) Data “g” is added to the slide of number # 0 in the slide storage unit. Then, the slide search process is performed on the next input data “b”.

  Here, since the slide storage unit can shift the data stored in each slide by the FIFO method, the list of matches with the input data is kept as it is while the next input data is stored. You can move on to processing.

  For example, in the example of FIG. 9, the input data matches the past data stored in the slides of numbers # 0, # 3, # 4, # 7, # 13 and # 15 in the process # 1. By sequentially shifting the data stored in each slide as new data is input, for example, for the slides of the numbers # 0, # 3, # 4, # 7, # 13 and # 15 in the process # 2. Thus, the next data is stored. Therefore, in the slide storage unit, the data stored in the slide with the number searched for the match in the slide search process is compared with the input data for each list search process, thereby matching the data string of the input data. A data string of past data can be searched.

  In this way, the list search process can be easily performed by adopting the FIFO method for the slide storage unit.

<Flag processing>
The slide search process and list search process described above are controlled by a flag. The flag process in the slide search process and the list search process will be described with reference to FIGS. 10-1 and 10-2.

  FIG. 10A illustrates an R flag RFLGm indicating the result of the slide search process. As illustrated in FIG. 10A, “a, b, c, a, a, b, c, a, b, c, When the input data “a” is input in a state where past data is stored as “d, b, c, a, c, a”, the numbers # 0, # 3, # 4, # 7, # In slides 13 and # 15, the input data matches the past data stored in each slide. Therefore, the R flags RFLG0, RFLG3, RFLG4, RFLG7, RFLG13, and RFLG15 corresponding to the slides of these numbers are set to a value “1” indicating that they match each other.

  As described above, when the input data matches the past data stored in each slide, the list search process is performed without performing the encoding process. At this time, the position of the R flag RFLGm with respect to each slide is fixed. If there is no past data stored in each slide that matches the input data, the ESC encoding data supplied to the slide / list generation processing unit 304 at the same time as the slide encoding data that is the input data is used as the ESC value. Is used to encode into an ESC code, and slide search processing is performed on the next input data.

  FIG. 10-2 illustrates an example of the W flag WFLGm indicating the result of the list search process. In the list search process, data that matches the newly input data is searched from the data stored in the slide in which the R flag RFLGm is “1” among the slides. If matching data is found, the value of the W flag WFLGm for the slide is set to a value “1” indicating that the data matches.

  In the example of FIG. 10-2, among the past data stored in each slide, the slides of numbers # 0, # 3, # 4, # 7, # 13 and # 15 whose R flag RFLGm is “1” are stored. A list search process is performed on the data stored in. Among these, since the data stored in the slides of the numbers # 3, # 7, # 13 and # 15 match the input data “c”, the values of the corresponding W flags WFLG3, WFLG7, WFLG13 and WFLG15 Is set to a value “1” indicating a match. Of the past input data stored in each slide, the slide in which the value of the W flag WFLGm is “1” includes the past data that matches the previous input data and the past that matches the current input data. Indicates that the input data is continuously stored.

  Next, the W flag WFLGm having a value “1” is searched. When the W flag WFLGm having this value “1” exists, each W flag WFLGm is set as a new R flag RFLGm, and the list search process is performed on the next input data in the same manner as described above.

  On the other hand, if the W flag WFLGm having a value “1” does not exist as a result of the search, this means that the list has been interrupted. In this case, one R flag RFLGm having a value of “1” is selected, and the slide address information Address corresponding to the selected R flag RFLGm and the length information Length at that time are encoded into a Slide code.

  Next, slide search processing and list search processing when the R flag RFLGm and the W flag WFLGm are used will be described with reference to FIGS. 11-1 to 11-8. In the example of FIGS. 11-1 to 11-8, as in the case of FIG. 9 described above, the description will be made by paying attention to the 16 registers connected in series of numbers # 0 to # 15. Each slide has “a, b, c, a, a, b, c, a, b, c, d, b, c, a, c, a” in the past in the new order, that is, in ascending order. It is assumed that the 16 pieces of input data (Slide encoding data) have already been stored.

  In this embodiment, encoding is performed by repeating the slide search process and the list search process. First, input data “a” is input, and slide search processing is performed (FIG. 11-1). Data that matches the input data (Slide encoding data) “a” is searched from each slide in the slide storage unit. If no data matching the input data is found from each slide, the ESC encoding data supplied to the slide / list generation processing unit 304 at the same time as the input data is used as an ESC value to encode into the ESC code. To do.

  When a slide storing data matching the input data is searched, the value of the R flag RFLGm corresponding to the slide is set to “1”, and the values of the other R flags RFLGm are set to “0”. In the example of FIG. 11A, the data stored in the slides with the numbers # 0, # 3, # 4, # 7, # 13 and # 15 match the input data. In this slide search process, a list is generated in the next list search process using the data that matches the input data as the root.

  Next, the stored contents of each slide are shifted one by one to the left, and the input data “a” input immediately before is added to the slide of number # 0. As described above, when a slide storing data that matches the input data is searched in the slide search process, the encoding process is not performed and the list search process (FIG. 11-2) is performed and the length information Length is set to “0”. " In addition, R flag RFLGm (R flags RFLG0, RFLG3, RFLG4, R # RFLG0, RFLG3, RFLG4, corresponding to slides (number # 0, # 3, # 4, # 7, # 13 and # 15 slides) in which data matching the input data is stored. RFLG7, RFLG13, and RFLG15) are set to “1”, and the values of the other R flags RFLGm are set to “0”.

  Next, as shown in FIG. 11B, input data “c” is input. In the list search process, a slide in which data matching the input data “c” is stored is searched for among slides having a corresponding R flag RFLGm value “1”. In the example of FIG. 11B, the data stored in the slides of the numbers # 3, # 7, # 13 and # 15 among the slides whose R flag RFLGm is “1” matches the input data. On the other hand, the slides of numbers # 0 and # 4 are missing. Therefore, as shown in FIG. 11B, the value of the W flag WFLGm (W flags WFLG3, WFLG7, WFLG13, and WFLG15) corresponding to the slide in which the data that matches the input data is stored is set to “1”. The value of the W flag WFLGm is set to “0”.

  Next, the stored contents of each slide are shifted one by one to the left, and the input data “c” input immediately before is added to the slide of number # 0. Also in this case, the encoding process is not performed, the process proceeds to the next list search process (FIG. 11C), and the length information Length is set to “1”. As illustrated in FIG. 11C, the value of the immediately preceding W flag WFLGm (the value of the W flag WFLGm in FIG. 11B) is set in the R flag RFLGm, and the R flag RFLGm is updated.

  Next, as shown in FIG. 11C, the input data “b” is input. In the list search process, among the slides with the corresponding R flag RFLG value “1”, a slide storing data that matches the input data “b” is searched. In the example of FIG. 11C, the data stored in the slides numbered # 3, # 7 and # 13 among the slides whose R flag RFLGm is “1” matches the input data. On the other hand, the slide of number # 15 has dropped out. Therefore, as shown in FIG. 11C, the value of the W flag WFLGm (W flags WFLG3, WFLG7 and WFLG13) corresponding to the slide storing the data matching the input data is set to “1”, and the other W flags The value of WFLGm is set to “0”.

  Next, the stored contents of each slide are shifted one by one to the left, and the input data “b” input immediately before is added to the slide of number # 0. Also in this case, the encoding process is not performed, the process proceeds to the next list search process (FIG. 11-4), and the length information Length is set to “2”. Then, as shown in FIG. 11-4, the value of the immediately preceding W flag WFLGm (the value of the W flag WFLGm in FIG. 11-3) is set in the R flag RFLGm, and the R flag RFLGm is updated.

  Next, as shown in FIG. 11-4, input data “d” is input. In the list search process, among the slides having the corresponding R flag RFLGm value “1”, a slide storing data that matches the input data “d” is searched. In the example of FIG. 11-4, the data stored in the slide with the number # 13 matches the input data. On the other hand, the slides of numbers # 3 and # 7 are missing. The value of the W flag WFLG13 corresponding to the slide storing the data that matches the input data is set to “1”.

  Next, the stored contents of each slide are shifted one by one to the left, and the input data “d” input immediately before is added to the slide of number # 0. Also in this case, the encoding process is not performed, and the process proceeds to the next list search process (FIG. 11-5), and the length information Length is set to “3”. As shown in FIG. 11-5, the value of the previous W flag WFLGm (the value of the W flag WFLGm in FIG. 11-4) is set in the R flag RFLGm, and the R flag RFLGm is updated.

  Next, as shown in FIG. 11-5, input data “a” is input. In the list search process, a slide in which data matching the input data “a” is stored is searched for among slides having the corresponding R flag RFLGm value “1”. In the example of FIG. 11-5, the slide of number # 13 is dropped, and there is no slide that stores data that matches the input data “a”. That is, there is no continuing list. Therefore, the position in the slide storage unit of the slide whose R flag RFLGm is “1” (the position of the number # 13 in the example of FIG. 11-5) is the address information Address, and the length information Length is “3”. These are encoded into a Slide code as shown in FIG. The values of the W flag WFLG are all “0”, and the process proceeds to the slide search process (FIG. 11-6).

  The slide search process after the list is interrupted is performed on the input data “a” in the previous list search process (FIG. 11-6). Data matching the input data “a” is searched from each slide in the slide storage unit. If no data matching the input data is found from each slide, the ESC encoding data supplied to the slide / list generation processing unit 304 simultaneously with the input data (Slide encoding data) is used as the ESC value. And encoding into an ESC code.

  When a slide storing data matching the input data is searched, the value of the R flag RFLGm corresponding to the slide is set to “1”. In the example of FIG. 11-6, the data stored in the slides of numbers # 3, # 4, # 7, # 8, and # 11 match the input data. In this slide search process, a list is generated in the next list search process using the data that matches the input data as the root.

  Next, the stored contents of each slide are shifted one by one to the left, and the input data “a” is added to the slide of number # 0. As described above, when a slide storing data that matches the input data is searched in the slide search process, the encoding process is not performed and the process proceeds to the list search process (FIG. 11-7), and the length information Length is set to “0”. " Also, R flag RFLGm (R flags RFLG3, RFLG4, RFLG7, RFLG8 and RFLG13) corresponding to slides (slides with numbers # 3, # 4, # 7, # 8 and # 13) in which data matching the input data is stored. ) Is set to “1”, and the values of the other R flags RFLGm are set to “0”.

  Next, as shown in FIG. 11-7, the input data “f” is input. In the list search process, a slide in which data matching the input data “f” is stored is searched for among slides having a corresponding R flag RFLGm value “1”. In the example of FIG. 11-7, since there is no slide storing data that matches the input data “f”, the values of the W flag WFLGm are all “0”, and the process proceeds to the slide search process (FIG. 11). -8).

  The slide search process here is performed on the input data “f” in the previous list search process (FIG. 11-8). Data matching the input data “f” is searched from each slide in the slide storage unit. In the example of FIG. 11-8, since data matching the input data is not searched from each slide, the ESC encoding data supplied to the slide / list generation processing unit 304 simultaneously with the input data (Slide encoding data). Is used as an ESC value to be encoded into an ESC code. Further, all the values of the R flag RFLGm are set to “0”.

  Then, the stored content of each slide is shifted one by one to the left, input data “f” is added to the slide of number # 0, and the process proceeds to encoding of the next input data.

<Details of encoding process>
Next, the encoding process according to the present embodiment will be described in more detail. FIG. 12 is an example of a flowchart showing the overall flow of the encoding process according to this embodiment. In the first step S10, the value of the comparison result flag SlideFLAG is initialized to “0”. In step S11, a flag LISTFLG indicating which one of the slide search process and the list search process is valid is initialized to a value “0” indicating that the slide search process is being performed.

  Next, in step S12, the data reading unit 300 reads the pixel value of one pixel (target pixel) to be encoded. In the next step S13, it is determined whether or not encoding of a multi-value image is specified by an encoding specifying signal, and if it is determined that encoding of a multi-value image is specified, the process proceeds to step S14. Migrate to In step S <b> 14, the line memory control unit 307 writes the pixel value of the target pixel read by the data reading unit 300 in the first area of the line memory 308. Here, the second area of the line memory 308 stores the pixel values of the line that is the line immediately before the line to which the target pixel belongs and has already been encoded. Then, under the control of the line memory control unit 307, the pixel value of the target pixel and the pixel values of the three surrounding pixels of the target pixel are read from the line memory 308 and supplied to the prediction processing unit 309.

  Next, in step S15, the prediction processing unit 309 calculates a predicted value of the pixel value of the target pixel based on the pixel values of the three surrounding pixels (the above-described pixel a, pixel b, and pixel c) of the target pixel, The calculated prediction value and the pixel value of the target pixel are supplied to the prediction error processing unit 310. In step S <b> 16, the prediction error processing unit 310 calculates a prediction error value that is a difference between the pixel value of the target pixel and the prediction value obtained by the prediction processing unit 309, and sends the calculated prediction error value to the multiplex 303. At the same time, the pixel value of the target pixel is supplied to the multiplex 302.

  The process proceeds to step S17, and the multiplex 302 sends the prediction error value supplied from the prediction error processing unit 310 to the slide / list generation processing unit 304 as Slide encoding data. Further, the multiplex 303 supplies the pixel value of the target pixel supplied from the prediction error processing unit 310 to the slide / list generation processing unit 304 as ESC encoding data. Then, the process proceeds to step S19.

  If it is determined in step S13 described above that encoding of a multi-value image is not specified, that is, encoding of a low-value image is specified, the process proceeds to step S18. In step S18, the multiplex 303 supplies the pixel value of the target pixel supplied from the data reading unit 300 to the slide / list generation processing unit 304 as Slide encoding data. In addition, the multiplex 302 supplies the pixel value of the pixel of interest supplied from the data reading unit 300 to the slide / list generation processing unit 304 as ESC encoding data. Then, the process proceeds to step S19.

  In step S19, it is determined whether or not the value of the flag LISTFLG is “1”. If it is determined that it is not “1”, it is determined that the current slide search process is valid, and the process proceeds to step S20. In step S20, the slide / list generation processing unit 304 executes a slide search process. Details of the slide search process will be described later.

  In the next step S21, the slide / list generation processing unit 304 performs a slide addition process for adding slide encoding data to the slide storage unit. Details of the Slide addition process will be described later. In the next step S22, it is determined whether or not the processing for all the pixels for one line has been completed. If it is determined that the process has not ended, the process returns to step S12 described above. On the other hand, if it is determined that the process has been completed, the process proceeds to step S23, and a line end code is output in step S23. In the next step S24, the pixel values of one line of pixels that have been encoded and written in the first area are overwritten in the second area. Then, the process proceeds to step S25, and it is determined whether or not the processes for all lines have been completed. If it is determined that the processing has been completed, the series of encoding processing ends. On the other hand, if it is determined that the process has not ended, the process returns to step S10 described above.

  If it is determined in step S19 described above that the value of the flag LISTFLG is “1”, it is determined that the current list search process is valid, and the process proceeds to step S26. In step S26, the slide / list generation processing unit 304 executes list search processing. Details of the list search process will be described later. After the list search process is performed in step S26, the process proceeds to step S21 described above.

  FIG. 13 is a flowchart showing detailed contents of the slide search process executed in step S20 of FIG. In the following, the x-th (0 ≦ x ≦ 127) slide in the slide storage unit is expressed as slide [x]. For example, the first slide in the slide storage unit is expressed as slide [0].

  First, in steps S30 to S32, the length information Length, the flag SFIINDFLG, and the variable IW are each initialized to a value “0”. The process proceeds to step S33, and it is determined whether or not the input data matches the past input data stored in the slide [IW]. If it is determined that they match, the process proceeds to step S34, the value of the flag SFINDFLG is set to “1”, and the value of the R flag RFLG [IW] is set to “1” in the next step S35.

  Then, the process proceeds to step S37, and it is determined whether or not the variable IW is less than the slide size, that is, less than the number of slides (here, “128”) that the slide storage unit has. If it is determined that the variable IW is less than the slide size, “1” is added to the variable IW in step S38, and the process returns to step S33. On the other hand, if it is determined in step S37 that the variable IW is greater than or equal to the slide size, the process proceeds to step S39.

  On the other hand, if it is determined in step S33 that the input data does not match the past input data stored in the slide [IW], the process proceeds to step S36, and the value of the R flag RFLG [IW] is “0”. " Then, the process proceeds to step S37.

  In step S39, it is determined whether or not the value of the flag SFINDFLG is “1”. When it is determined that the value of the flag SFINDFLG is not “1”, it is determined that past data matching the input data is not stored in the slide storage unit, and the process proceeds to step S40. In step S40, the comparison result flag SlideFLAG is set to “0”, and the code generation process is performed in the next step S41. Details of the code generation process will be described later.

  On the other hand, if it is determined in step S39 described above that the value of the flag SFINDFLG is “1”, it is determined that past input data that matches the input data is stored in the slide storage unit, and the next step S42 is performed. Thus, the value of the flag LISTFLG is set to “1”. That is, the list search process is valid.

  FIG. 14 is a flowchart showing detailed contents of the list search process executed in step S26 of FIG. First, in steps S50 and S51, the flag LFINDFLG and the variable IW are each initialized to the value “0”.

  In step S52, it is determined whether or not the input data matches the past input data stored in the slide [IW] and the value of the R flag RFLG [IW] is “1”. If it is determined that the respective conditions are satisfied, the process proceeds to step S53, the value of the W flag WFLG [IW] is set to “1”, and the value of the flag LFINDFLG is set to “1” in the next step S54. It is said. Then, the process proceeds to step S56.

  On the other hand, in step S52, the above condition is not satisfied, that is, the input data does not match the past input data stored in the slide [IW], or the value of the R flag RFLG [IW] is not “1”. Is determined, the process proceeds to step S55, and the value of the W flag WFLG [IW] is set to “0”. Then, the process proceeds to step S56.

  In step S56, it is determined whether or not the variable IW is less than the slide size. If it is determined that the variable IW is less than the slide size, “1” is added to the variable IW in step S57, and the process returns to step S52. On the other hand, if it is determined that the variable IW is greater than or equal to the slide size, the process proceeds to step S58.

  In step S58, it is determined whether or not the value of the flag LFINDFLG is “0”. If it is determined that the value is “0”, the process proceeds to step S59 to initialize the variable IW to the value “0”. In the next step S60, the value of the R flag RFLG [IW] is set to “0”. It is determined whether or not “1”. If it is determined that the value is “1”, the process proceeds to step S61.

  In step S61, the variable IW is set as address information Address, and in the next step S62, the slide size is substituted into the variable IW. Then, the process proceeds to step S63. In step S63, it is determined whether or not the variable IW is less than the slide size. If it is determined that the variable IW is less than the slide size, “1” is added to the variable IW in step S64, and the process returns to step S60.

  On the other hand, if it is determined in step S63 that the variable IW is equal to or larger than the slide size, the process proceeds to step S65, and the comparison result flag SlideFLAG is set to “1”. Then, the process proceeds to the next step S66, the code generation process is performed, and the series of processes ends. Details of the code generation process will be described later.

  If it is determined in step S58 that the value of the flag LFINDFLG is not “0”, the process proceeds to step S67, and the variable IW is initialized to the value “0”. In the next step S68, it is determined whether or not the value of the W flag WFLG [IW] is “0”. If it is determined that the value of the W flag WFLG [IW] is “0”, the value of the R flag RFLG [IW] is set to “0” in step S69, and the process proceeds to step S70. The On the other hand, if it is determined that the value of the W flag WFLG [IW] is not “0”, the value of the R flag RFLG [IW] remains unchanged and the process proceeds to step S70.

  In step S70, it is determined whether the variable IW is less than the slide size. If it is determined that the variable IW is less than the slide size, “1” is added to the variable IW in step S71, and the process returns to step S68. On the other hand, if it is determined in step S70 that the variable IW is equal to or larger than the slide size, the process proceeds to step S72, 1 is added to the length information Length, and the series of processes ends.

  FIG. 15 is a flowchart illustrating an example of detailed contents of the slide addition process executed in step S21 of FIG. First, in step S80, the variable IW is set to a value obtained by subtracting 1 from the number of slides. In the next step S81, the value of the slide [IW-1] is stored in the slide [IW]. In step S82, it is determined whether or not the variable IW exceeds “0”. If it is determined that the variable IW exceeds “0”, the process proceeds to step S83, and “1” is subtracted from the variable IW. Then, the process returns to step S81. On the other hand, if it is determined in step S82 that the variable IW is “0” or less, the process proceeds to step S84, and Slide encoding data is added to the slide [0]. When encoding of a multi-valued image is specified by the encoding specification signal, a prediction error value is added to the slide [0], while encoding of a low-value image is specified by the encoding specification signal. In this case, the pixel value of the target pixel is added to the slide [0].

  FIG. 16 is a flowchart showing an example of detailed contents of the code generation processing executed in each of step S41 in FIG. 13 and step S66 in FIG. First, in step S90, it is determined whether or not the value of the comparison result flag SlideFLAG is “1”. If it is determined that the value of the comparison result flag SlideFLAG is “1”, the process proceeds to step S91, and the comparison result flag SlideFLAG, the address information Address, and the length information Length are converted into the Slide code illustrated in FIG. Encoded.

  On the other hand, if it is determined that the value of the comparison result flag SlideFLAG is “0”, the process proceeds to step S92, and the comparison result flag SlideFLAG and the ESC encoding data (pixel value of the target pixel) are as shown in FIG. Are encoded into the ESC code illustrated in FIG.

  FIG. 17 shows an exemplary configuration of the encoding unit 204 in more detail. Note that, in FIG. 17, the same reference numerals are given to portions common to the above-described FIGS. 2, 4, and 5, and detailed description thereof is omitted. The encoding unit 204 includes a data reading unit 300, a line memory control unit 307, a line memory 308, a prediction processing unit 309, a prediction error processing unit 310, multiplexes 302 and 303, a slide / list generation processing unit 304, and a code format generation process. A main memory arbiter I / F 313, a data address generation unit 314, and a code address generation unit 315. Here, in the line memory 308, an area where the current line is stored (first area) is referred to as a current line memory, and an area where the previous line is stored (second area) is referred to as a previous line memory.

  The main memory arbiter I / F 313 is an I / F that enables connection with the main memory arbiter 202. The data address generation unit 314 generates a memory address when reading band image data from the CMYK band image data storage area 210 </ b> C of the main memory 210. The data reading unit 300 requests the main memory arbiter 202 to read the band image data specified by the memory address generated by the data address generation unit 314 via the main memory arbiter I / F 313. In response to this request, the band image data read from the CMYK band image data storage area 210C of the main memory 210 by the main memory arbiter 202 is supplied from the main memory arbiter 202 to the encoding unit 204, and the main memory arbiter The data is supplied to the data reading unit 300 via the I / F 313.

  The code address generation unit 315 generates a memory address to which the code writing unit 306 writes in the CMYK page code storage area 210D of the main memory 210. The code writing unit 306 then writes the code generated by the code format generation processing unit 305 in the CMYK code storage area 210D of the main memory 210 in accordance with the memory address generated by the code address generation unit 315. The main memory arbiter 202 is requested through the I / F 313. The main memory arbiter 202 writes the supplied code in the main memory 210 in accordance with this request.

<Hardware configuration example of slide / list generation processing unit>
FIG. 18 shows an example of the hardware configuration of the slide / list generation processing unit 304 described above. The slide / list generation processing unit 304 includes a slide search processing unit 320, a slide storage unit 321, a list search processing unit 322, and a controller 323.

  The controller 323 is composed of, for example, a microprocessor, and controls the operation of the slide / list generation processing unit 304. For example, the controller 323 performs operation control using a flag LISTFLG indicating which one of the above-described slide search process and list search process is valid.

  For example, one unit of Slide encoding data (prediction error value or pixel value) is input to the slide / list generation processing unit 304 every clock, and the slide search processing unit 320, the slide storage unit 321 and the list search processing are performed. Each of the units 322 is supplied. Further, the ESC encoding data (pixel value of the target pixel) is stored in the register 324. The pixel value stored in the register 324 is used as a data value when encoding the ESC code. In the following, one unit of data is assumed to be 1 byte.

  The slide storage unit 321 is composed of a register, and 128 Slide0, Slide1,..., Slide127 each storing one unit of data are connected in series. In addition, the output of each Slide 0, Slide 1,..., Slide 127 is supplied to the next slide, and one input terminal of a corresponding comparator 325 of the slide search processing unit 320 described later and the list search processing unit 322. The signal is supplied to one input terminal of the corresponding comparator 326.

  In the slide storage unit 321, a FIFO is composed of these 128 Slide 0, Slide 1,..., Slide 127, and the input Slide encoding data is sequentially sent from Slide 0 to Slide 1, Slide 2,.

The slide search processing unit 320 includes 128 comparators 325 ₀ , 325 ₁ ,..., 325 ₁₂₇ and a 128-input OR circuit 327. Each of the comparators 325 ₀ , 325 ₁ ,..., 325 ₁₂₇ compares the data input to one and the other input terminals, and outputs a value “1” if they match, and must match. Value “0” is output.

As described above, the outputs of Slide 0, Slide ₁ ,..., Slide ₁₂₇ included in the slide storage unit 321 are input to one input terminal of each of the comparators 325 ₀ , 325 ₁ ,. Further, the comparator 325 _0, 325 _1, ..., to the respective other input of 325 _127, for Slide encoded data is input.

The outputs of the comparators 325 ₀ , 325 ₁ ,..., 325 ₁₂₇ are input to a 128-input OR circuit 327 and multiplexed (MUX) 328 ₀ , 328 ₁ , 328 of a list search processing unit 322 described later. .., And 328, ₁₂₇ , respectively. The output of the OR circuit 327 is supplied to the controller 323 as the flag SFINDFLG. This flag SFINDFLG indicates whether or not at least one of the data of Slide 0, Slide 1,..., Slide 127 matches the input slide encoding data.

The list search processing unit 322 includes 128 comparators 326 ₀ , 326 ₁ ,..., 326 ₁₂₇ , multiplex (MUX) 328 ₁ , 328 ₂ ,..., 328 _n , and registers 329 ₀ , 329 ₁ ,. 329 ₁₂₇ , an address information generation unit 330, and a 128-input OR circuit 331. Each of the comparators 326 ₀ , 326 ₁ ,..., 326 ₁₂₇ compares the data input to one and the other input terminals, and outputs a value “1” if they match, and must match. Value “0” is output.

As described above, the outputs of Slide 0, Slide ₁ ,..., Slide ₁₂₇ included in the slide storage unit 321 are input to one input terminal of each of the comparators 326 ₀ , 326 ₁ ,. Further, Slide encoding data is input to the other input terminal of each of the comparators 326 ₀ , 326 ₁ ,..., 3260 ₁₂₇ .

Comparators 326 _0, 326 _1, ..., output of 326 _127, together with a W flag WFLGm, are input to the 128 input of the OR circuit 331, a multiplex 328 _0, 328 _1, ..., 328 ₁₂₇ Each is input to the other input terminal. The output of the OR circuit 331 is supplied to the controller 323 as a flag LFINDFLG. The flag LFINDFLG indicates that at least one of the W flags WFLG0, WFLG1,..., WFLG127 is “1”.

Multiplex 328 _0, 328 _1, ..., output of 328 _127, is the R flag RFLGm, the registers 329 _0, 329 _1, ..., stored in 329 _127. The multiplexes 328 ₀ , 328 ₁ ,..., 328 ₁₂₇ are controlled by the flag ListFLG supplied from the controller 323 via a path (not shown) to select one of the other terminals.

Wakashi, the value of the flag ListFLG is "0", if it is shown that the current slide search process is effective, multiplex 328 _0, 328 _1, ..., 328 _127, each of one input is input to an end, ₀ comparator 325 in the slide search processing unit 320, 325 _1, ..., register 329 ₀ output of 325 _127, 329 _1, ..., it is controlled to supply to the 329 _127.

On the other hand, the value of the flag ListFLG is "1", if it is shown that the current list search process is effective, multiplex 328 _0, 328 _1, ..., 328 _127, each of the other input terminal It is input, the comparator 326 _0, 326 ₁ in the list search unit 322, a ..., register 329 ₀ select 326 _127, 329 _1, ..., is controlled to supply to the 329 _127.

When the outputs from the multiplexes 328 ₀ , 328 ₁ ,..., 328 ₁₂₇ are supplied, the registers 329 ₀ , 329 ₁ ,..., 329 ₁₂₇ output the stored R flags RFLG 0, RFLG 1,. . That is, the register 329 _0, 329 _1, ..., R flag is stored in _{329 127 RFLG0, RFLG1, ...,} RFLG127 is multiplex 328 _0, 328 _1, ..., it is updated by the output from the 328 _127.

Register 329 _0, 329 _1, ..., 329 ₁₂₇ R flag outputted from RFLG0, RFLG1, ..., RFLG127 includes a comparator 326 _0, 326 _1, ..., as a control signal for controlling the operation of 326 _127, the comparator 326 _0, 326 _1, ..., it is supplied to the control end of 326 _127. For example, the comparator 326 _m (0 ≦ m ≦ 127) performs the comparison operation if the control signal supplied from the corresponding register 329 _m indicates the value “1”, and if the control signal indicates the value “0”. The comparison operation is not performed. This, 326 _0, 326 _1, ..., 326 ₁₂₇ respectively operate, 326 _0, 326 _1, ..., means that gradually narrowed by 326 ₁₂₇ its output.

The R flags RFLG0, RFLG1,..., RFLG127 output from the registers 329 ₀ , 329 ₁ ,..., 329 ₁₂₇ are also supplied to the address information generation unit 330. Address information generator 330, as described in the process # 5 in FIG. 9, when the list search process has been completed, the register _{329 0, 329 1, ...,} 329 127 R flag outputted from RFLG0, RFLG1, ... , RFLG127 selects an R flag RFLGm having a value of “1”, and outputs the number of the selected R flag RFLGm as address information Address. The address information Address output from the address information generation unit 330 is stored in the register 332 and supplied to the controller 323.

  Here, when there are a plurality of R flags RFLGm having a value of “1”, the address information generation unit 330 has a small slide number, that is, the R flag based on Slide closer to the input side in the slide storage unit 321. Select preferentially from RFLGm. This is because the Slide closer to the input is more likely to match the input data. At this time, in the code format described with reference to FIG. 8, it is preferable that the code having the smaller address information Address is a shorter code because the compression efficiency is increased.

  Based on the flag SFINDFLG supplied from the slide search processing unit 320, the flag LFINDFLG supplied from the list search processing unit 322, and the address information Address supplied from the address information generating unit 330, the controller 323 performs length information Length and A comparison result flag SlideFLAG is generated. The length information Length is stored in the register 333, and the comparison result flag SlideFLAG is stored in the register 334.

  Note that the address information Address, length information Length, and comparison result flag SlideFLAG stored in the registers 332 to 334, respectively, are read by the code format generation processing unit 305 and encoded according to the code format illustrated in FIG. (First code data) is generated. The pixel value of the target pixel stored in the register 324 is also read by the code format generation processing unit 305 and encoded according to the code format illustrated in FIG. 8 to generate code data (second code data).

In such a configuration, the slide search process is performed as follows. That is, the comparator 325 ₀ , 325 ₁ ,..., 325 ₁₂₇ performs comparison processing between the input data (Slide encoding data) and the past input data stored in Slide ₀ , Slide 1,. The comparison results are respectively supplied to the OR circuit 327 and the flag SFINDFLG is output. The result of the comparison, a multiplex 328 _0, 328 _1, ..., is also supplied to the 328 _127, between the slide search process is register 329 _0, 329 _1, ..., stored in 329 _127. According to the configuration of FIG. 18, this series of processing can be executed in one clock.

The list search process is performed as follows. That is, the comparator 326 ₀ , 326 ₁ ,..., 326 ₁₂₇ performs comparison processing between the input data and past input data stored in Slide 0, Slide 1,. At this time, the comparison operation of the comparators 326 ₀ , 326 ₁ ,..., 326 ₁₂₇ is controlled based on the values of the R flags RFLG 0, RFLG 1,..., RFLG ₁₂₇ stored in the registers 329 ₀ , 329 ₁ ,. The For example, R flag RFLG0, RFLG1, ..., if all the values of RFLG127 "0", the comparator 326 _0, 326 _1, ..., so that the 326 ₁₂₇ all the comparison operation is not performed. This state is a state in which the list search process is not performed.

The comparison results by the comparators 326 ₀ , 326 ₁ ,..., 326 ₁₂₇ are respectively supplied to the OR circuit 331 and the flag LFINDFLG is output. Each comparison result, multiplex 328 _0, 328 _1, ..., is supplied to 328 _127, among the list search process, the register 329 _0, 329 _1, ..., stored in 329 _127. The register _{329 0, 329 1, ...,} R flag RFLG0 stored in 329 _127, RFLG1, ..., RFLG127 is also held in the address information generation unit 330.

If the values stored in the registers 329 ₀ , 329 ₁ ,..., 329 ₁₂₇ are all “0”, the address information generation unit 330 sets the value among the R flags RFLG 0, RFLG 1,. The position of the R flag RFLGm of “1” is passed to the controller 323 as address information Address. According to the configuration of FIG. 18, a series of processing by this list search processing can be executed in one clock.

  According to the configuration of FIG. 18, the slide search processing unit 320 and the list search processing unit 322 are configured separately from each other, and the slide search processing unit 320 and the list search processing unit 322 share the slide storage unit 321. To do. Therefore, it is possible to execute the slide search processing by the slide search processing unit 320 and the list search processing by the list search processing unit 322 in parallel. Therefore, the encoding process can be further speeded up. In addition, according to the configuration of FIG. 18, the hardware scale can be reduced because a configuration such as a prefetch buffer or a large-scale matrix array is unnecessary.

<Decoding unit>
FIG. 19 shows an exemplary configuration of the decoding unit 205. In the decoding unit 205, the code reading unit 400 reads the code data encoded by the above-described encoding unit 204 from the CMYK page code storage area 210D of the main memory 210. The code data read by the code reading unit 400 is supplied to the code format analysis unit 401. The code format analysis unit 401 analyzes the supplied code data in accordance with the code format described with reference to FIG. 8 to obtain an ESC value indicating the pixel value of the pixel of interest, address information Address, length information Length, and comparison result flag SlideFLAG. Take out. These extracted data are supplied to the slide development unit 402.

  The slide development unit 402 has a slide storage unit in which a plurality of registers connected in series is configured as a FIFO. Each register is called a slide, and can store one unit (for example, 1 byte) of data. When decoding a multi-valued image, a prediction error value is stored in each slide of the slide storage unit. On the other hand, when decoding a low-value image, a pixel value is stored in each slide of the slide storage unit.

  When the comparison result flag SlideFLG supplied from the code format analysis unit 401 is “1”, the slide development unit 402 reads out the data stored in the register specified by the address information Address among the plurality of registers. Let it be Slide decoding value. When decoding a multi-valued image, the prediction error value stored in the register specified by the address information Address is read as a Slide decoded value, whereas when decoding a low-value image, the register specified by the address information Address In other words, the pixel value stored in is read as a slide decoded value.

  On the other hand, when the comparison result flag SlideFLG passed from the code format analysis unit 401 is “0”, the slide development unit 402 sets the ESC value passed from the code format analysis unit 401 as an ESC decoded value.

  In the present embodiment, the CPU 212 receives a decoding designation signal that designates either decoding of a multi-valued image or decoding of a low-valued image. When decoding of a multi-valued image is designated by the decoding designation signal, the slide development unit 402 supplies the comparison result flag SlideFLG, Slide decoded value, and ESC decoded value to the subsequent prediction processing unit 403. On the other hand, when decoding of a small-value image is designated by the decoding designation signal, the slide development unit 402 supplies the comparison result flag SlideFLG, Slide decoded value, and ESC decoded value to the multiplex 404 at the subsequent stage. In this embodiment, when decoding a small-value image, the slide development unit 402 does not supply the comparison result flag SlideFLG, the Slide decoded value, and the ESC decoded value to the prediction processing unit 403. Even in the case of decoding a small-value image, the slide development unit 402 can also supply the comparison result flag SlideFLG, Slide decoded value, and ESC decoded value to the prediction processing unit 403.

  FIG. 20 is a diagram illustrating an example of a more detailed configuration of the prediction processing unit 403. When the comparison result flag SlideFLAG and the Slide decoded value set to “1” are supplied from the slide development unit 402, the prediction processing unit 403 is read from the line memory 408 by the line memory control unit 407. A predicted value of the pixel value of the target pixel is calculated based on the pixel values of the decoded pixels a, b, and c (see FIG. 6) of the surrounding three pixels around the pixel to be decoded (target pixel). Then, the pixel value of the target pixel is calculated from the calculated predicted value and the slide decoded value (here, the predicted pixel value) passed from the slide development unit 402, and the calculated pixel value of the target pixel is It supplies to the multiplex 405 (refer FIG. 19).

  Note that the line memory 408 can store pixel values for two lines, that is, a decoding line that is being decoded and a decoded line that has just been decoded. Here, in the line memory 408, an area in which a decoded line is stored is referred to as a current line memory, and an area in which a decoded line is stored is referred to as a previous line memory. The line memory control unit 407 controls reading and writing of pixel values with respect to the line memory 408.

  On the other hand, when the comparison processing flag SlideFLAG set to “0” and the ESC decoded value are supplied from the slide development unit 402, the prediction processing unit 403 uses the supplied ESC decoded value as the pixel value of the target pixel. Is supplied to the subsequent multiplex 405 (see FIG. 19). At this time, the prediction processing unit 403 calculates the predicted value of the pixel value of the decoding target pixel (target pixel) in the same manner as described above. Then, the calculated predicted value is supplied to the slide developing unit 402. The slide development unit 402 calculates a prediction error value that is a difference between the prediction value supplied from the prediction processing unit 403 and the ESC value (pixel value of the target pixel) supplied from the code format analysis unit 401. Add the predicted error value to the slide.

  Returning to FIG. 19, the description will be continued. As shown in FIG. 19, the Slide decoding value from the slide development unit 402 is supplied to one input end of the multiplex 404, and the ESC decoding value from the slide development unit 402 is supplied to the other input end. The When the comparison result flag SlideFLAG set to “1” is supplied from the slide development unit 402, the multiplex 404 converts the pixel value indicated by the Slide decoded value supplied to one input terminal into the multiplex 405. To supply. On the other hand, when the comparison result flag SlideFLAG set to “0” is supplied from the slide development unit 402, the multiplex 404 converts the pixel value indicated by the ESC decoded value supplied to the other input terminal to the multiplex 404. Supply to plex 405.

  As shown in FIG. 19, the decoding designation signal described above is supplied from the CPU 212 to the multiplex 405. The pixel value from the prediction processing unit 403 is supplied to one input terminal of the multiplex 405, and the pixel value from the multiplex 404 is supplied to the other input terminal.

  Here, when decoding of a multi-valued image is designated by the decoding designation signal, the multiplex 405 supplies the pixel value supplied to one input end to the image writing unit 406. On the other hand, when decoding of a low-value image is designated by the decoding designation signal, the multiplex 405 supplies the pixel value supplied to the other input terminal to the image writing unit 406. The image writing unit 406 writes the pixel value supplied from the multiplex 405 to the CMYK band image data storage area 210 </ b> C of the main memory 210.

<Details of decryption processing>
FIG. 21 is a flowchart showing an example of processing in which the decoding unit 205 decodes code data encoded by the above-described encoding method of the present embodiment. It is assumed that the code reading unit 400 reads code data from the main memory 210 in advance. First, in step S100, the code format analysis unit 401 reads the header of the code data read by the code reading unit 400, and determines whether the subsequent code is an ESC code (step S101).

  If it is determined from the read header that the code is an ESC code, the process proceeds to step S102. In step S102, the code format analysis unit 401 reads a predetermined length bit following the header as a pixel value. The read pixel value is output to the slide development unit 402 as an ESC decoded value (step S103). In the next step S104, the slide expansion unit 402 executes a slide decoded value calculation process for calculating a slide decoded value. The detailed contents of the slide decoded value calculation process will be described later. In the next step S104, the slide development unit 402 performs a slide decoded value addition process for adding the slide decoded value to the slide storage unit (step S105). The slide decoding value addition process is performed by the same procedure as described in the flowchart of FIG. Then, the process proceeds to step S106. In step S <b> 106, the ESC decoded value, that is, the pixel value of the target pixel is written into the current line memory of the line memory 408.

  If it is determined in step S101 described above that the code is not an ESC code from the read header, it is determined whether the code is a Slide code (step S107). If it is determined in step S107 that the code is a Slide code, the process proceeds to step S108. In step S108, the code format analysis unit 401 reads bits having a predetermined length following the header as length information Length and address information Address. The read length information Length and address information Address are supplied to the slide development unit 402 together with the comparison result flag SlideFLAG.

  In the next step S109, the slide development unit 402 reads data (Slide decoded value) stored in the slide indicated by the address information Address among the slides in the slide storage unit. Then, the slide development unit 402 adds the read Slied decoded value to the slide (step S110). Then, the process proceeds to step S111. In step S111, the slide developing unit 402 executes an ESC decoded value calculation process for calculating an ESC decoded value. Details of the ESC decoded value calculation process will be described later.

  The process proceeds to step S112, and it is determined whether or not the length information Length is greater than “0”. If it is determined that the length information Length is “0” or less, the process proceeds to step S106, and the ESC decoded value is written in the current line memory of the line memory 408. On the other hand, if it is determined that the length information Length is greater than “0”, the process proceeds to step S113. In step S113, a value obtained by subtracting 1 from the current length information Length is set as new length information Length, and the process returns to step S109.

If it is determined in step S107 that the code is not a Slide code, the read code data is determined to be a line end code, and the process proceeds to step S114.
In step S114, the line memory control unit 407 overwrites the data in the current line memory on the previous line memory. Then, the process proceeds to step S115, and it is determined whether or not the decoding process for all lines has been completed. If it is determined that the decoding process for all lines has been completed, the series of processes ends. On the other hand, if it is determined that the decoding process for all lines has not been completed, the process returns to step S100.

  FIG. 22 is a flowchart showing an example of detailed contents of the slide decoded value calculation process executed in step S104 of FIG. First, in step S120, the slide developing unit 402 determines whether or not decoding of a multi-value image is specified by the above-described decoding specifying signal. If it is determined that multi-valued image decoding is designated, the slide development unit 402 sets the ESC decoded value supplied from the code format analysis unit 401 as the pixel value of the target pixel (step S121). In the next step S122, the slide development unit 402 calculates a predicted value of the pixel value of the target pixel. In the next step S123, the slide development unit 402 calculates a prediction error value that is a difference between the pixel value of the target pixel and the prediction value, and sets the calculated prediction error value as a slide decoded value (step S124).

  On the other hand, if it is determined in step S120 described above that decoding of a multi-valued image is not specified, that is, decoding of a low-valued image is specified, the slide developing unit 402 performs step S102 in FIG. The identified ESC decoded value is set as the Slide decoded value.

  FIG. 23 is a diagram showing an example of detailed contents of the ESC decoded value calculation process executed in step S111 of FIG. First, in step S130, the slide developing unit 402 determines whether or not decoding of a multi-valued image is specified by the above-described decoding specifying signal. When it is determined that multi-valued image decoding is designated, the slide development unit 402 sets the prediction error value supplied from the code format analysis unit 401 as a Slide decoded value (step S131). In the next step S132, the slide development unit 402 calculates a predicted value of the pixel value of the target pixel. In the next step S133, the slide development unit 402 calculates the pixel value of the target pixel from the prediction error value specified in step S131 and the prediction value specified in step S132. Then, the calculated pixel value of the target pixel is set as an ESC decoded value (step S134).

  On the other hand, if it is determined in step S130 described above that decoding of a multi-valued image is not specified, that is, decoding of a low-valued image is specified, the slide developing unit 402 performs step S109 in FIG. The identified Slide decoded value (in this case, the pixel value of the target pixel) is set as an ESC decoded value (step S135).

  FIG. 24 shows an exemplary configuration of the decoding unit 205 in more detail. Note that, in FIG. 24, the same reference numerals are given to the portions common to FIGS. 2 and 19 described above, and detailed description thereof is omitted. The decoding unit 205 includes a code reading unit 400, a code format analysis unit 401, a slide development unit 402, a prediction processing unit 403, a line memory control unit 407, a line memory 408, and an image writing unit 406. A main memory arbiter I / F 409 and a code address generation unit 410.

  The main memory arbiter I / F 409 is an I / F that enables connection with the main memory arbiter 202. The main memory arbiter I / F 409 transmits a write / read request (R / W signal) and a memory address to the main memory arbiter 202, thereby writing data into the main memory 210 and transferring data from the main memory 210. Read out.

  The code address generation unit 410 generates a memory address when reading code data from the CMYK page code storage area 210D of the main memory 210. The code reading unit 400 requests the main memory arbiter 202 to read the code data specified by the memory address generated by the code address generation unit 410 via the main memory arbiter I / F 409. In response to this request, the code data read from the CMYK page code storage area 210D of the main memory 210 by the main memory arbiter 202 is supplied to the code reading unit 400 via the main memory arbiter I / F 409.

<Hardware configuration of slide expansion unit>
FIG. 25 shows an example of the hardware configuration of the slide development unit 402. The slide development unit 402 includes a prediction error generation unit 480, a multiplex 490, a slide storage unit 500, a controller 501, and a multiplex 520.

  The controller 501 is composed of, for example, a microprocessor, and is supplied with address information Address, length information Length, and comparison result flag SlideFLAG, and controls the overall operation of the slide developing unit 402 based on these supplied data. For example, the controller 501 controls processing for adding data values to the slide in the slide storage unit 500, the operation of the multiplex 520, and the like.

The slide storage unit 500 is composed of registers, each of which includes a FIFO in which 128 slides 511 ₀ , 511 ₁ ,..., 511 ₁₂₇ each storing one unit of data are connected in series, and the FIFO. And a multiplex 510 connected at the head. The outputs of the slides 511 ₀ , 511 ₁ ,..., 511 ₁₂₇ are further supplied to the multiplex 520.

  The prediction error generation unit 480 generates a prediction error value from the prediction value of the pixel value of the pixel of interest supplied from the prediction processing unit 403 and the ESC value supplied from the code format analysis unit 410. The prediction error value generated by the prediction error generation unit 480 is supplied to the multiplex 490.

  The ESC value from the code format analysis unit 410 is supplied to one input terminal of the multiplex 490, and the prediction error value from the prediction error generation unit 480 is supplied to the other input terminal. The multiplex 490 is supplied with a decoding designation signal. The multiplex 490 supplies the prediction error value supplied to the other input end to the subsequent multiplex 510 when decoding of the multi-valued image is specified by the decoding specifying signal. In addition, when the decoding of the low-value image is designated by the decoding designation signal, the multiplex 490 supplies the ESC value (pixel value) supplied to one input terminal to the subsequent multiplex 510.

The multiplex 520 converts the data value stored in the slide 511 _Address from the data value stored in each slide 511 ₀ , 511 ₁ ,... 511 ₁₂₇ of the slide storage unit 500 according to the address information Address supplied from the controller 501. The selected data value is output as a slide decoded value.

  The Slide decoded value output from the multiplex 520 is supplied to one input terminal of the multiplex 510, and the output from the multiplex 490 is supplied to the other input terminal. The multiplex 510 is supplied with a comparison result flag SlideFLAG, and supplies data supplied to any input terminal to the slide in accordance with the value of the comparison result flag SlideFLAG. More specifically, when the value of the SlideFLAG is “1”, the multiplex 510 supplies the slide decoded value from the multiplex 520 supplied to one input terminal to the slide, and the value of the SlideFLAG is “0”. ", The output from the multiplex 490 supplied to the other input end is supplied to the slide.

<Action and effect>
As described above, in the present embodiment, when encoding a multi-valued image, a prediction error value that is a difference between a pixel value of a target pixel and a predicted value of the pixel value of the target pixel is used. When encoding with a prediction error method, when encoding a low-value image, encoding is performed with a different encoding method from the prediction error method. As compared with the configuration of encoding with, an advantageous effect that the compression rate of the low-value image can be increased is achieved. Further, in the multi-value image encoding process, when the input prediction error value does not match any of the prediction error values already stored in the slide storage unit, the input prediction error value is Since the pixel value of the obtained target pixel is encoded, the number of bits required for encoding can be reduced as compared with the configuration in which the input prediction error value itself is encoded. Thereby, there is an advantageous effect that the compression rate can be improved.

  In the above description, the present invention has been described as applied to a printer apparatus. However, this is an example, and the present invention is not limited to this example. That is, the present invention can also be applied to other apparatuses that perform lossless encoding of data using hardware.

200 Printer Device 202 Main Memory Arbiter 203 Main Memory Controller 204 Encoding Unit 205 Decoding Unit 206 Gradation Processing Unit 207 Multiplex 208 Engine Controller 209 Communication Controller 210B Data Storage Area 210C CMYK Band Image Data Storage Area 210A Program Area 210D CMYK Page Code Storage area 210 Main memory 300 Data reading unit 301 Prediction error generation processing unit 302 Multiplex 303 Multiplex 304 Slide / list generation processing unit 305 Code format generation processing unit 306 Code writing unit 307 Line memory control unit 308 Line memory 309 Prediction processing unit 310 Prediction error processing unit 400 Code reading unit 401 Code format analysis unit 402 Slide development unit 403 Prediction processing unit 406 Image writing unit 407 Line memory control unit 408 Line memory

JP 2002-344753 A

Claims (6)

A first storage means in which pixel values of a plurality of pixels constituting a multi-value image having a gradation number exceeding a predetermined number or a low-value image having a gradation number equal to or less than the predetermined number;
First reading means for reading out a pixel value of a target pixel to be encoded from the first storage means;
First predicted value calculation means for calculating a predicted value of a pixel value of the target pixel based on pixel values of pixels around the target pixel;
First prediction error value calculation means for calculating a prediction error value that is a difference between the prediction value calculated by the first prediction value calculation means and a pixel value of the target pixel;
When encoding the multi-valued image, encoding with the prediction error method using the prediction error value calculated by the prediction error calculating unit, while encoding the low-value image, An encoding unit that performs encoding using an encoding method different from the prediction error method,
An image processing apparatus. When encoding the multi-valued image, the prediction error value calculated by the prediction error calculation means is sequentially input from one end, and the input prediction error value is stored. Second storage means for moving and storing the stored prediction error value to the other end side;
When encoding the multi-valued image, the prediction error value input to the one end of the second storage unit is replaced with each of the prediction error values already stored in the second storage unit. A comparison means for comparing;
In the case of encoding the multi-valued image, and as a result of comparison by the comparison unit, the input prediction error value is identical to the prediction error value already stored in the second storage unit. And a search means for searching for a data string consisting of the prediction error values successively stored in the second storage means, which matches an input data string consisting of the prediction error values inputted sequentially. ,
Length information generating means for generating length information indicating the length of the data string searched by the searching means;
Address information generating means for generating address information indicating a position in the second storage means in which the start data of the data string searched by the search means is stored;
The encoding unit includes:
First code data generating means for encoding the length information generated by the length information generating means and the address information generated by the address information generating means to generate first code data;
As a result of the comparison by the comparison means, if the input prediction error value does not match any of the prediction error values already stored in the second storage means, the input A second code data generating unit that generates a second code data by encoding a pixel value of the target pixel for which a prediction error value is obtained;
The image processing apparatus according to claim 1. The second storage means stores the pixel value of the pixel of interest read by the reading means, which is sequentially input from one end when the low-value image is encoded, and has already been stored. Moving the pixel value to the other end side and storing it,
In the case of encoding the small-value image, the comparison unit uses the pixel value input to the one end of the second storage unit as the pixel value already stored in the second storage unit. Compared to each of the
The search means is a case where the low-value image is encoded, and the pixel value inputted as a result of comparison by the comparison means is already stored in the second storage means If it matches the value, search for a data string consisting of the pixel values stored in succession in the second storage means, which matches the input data string consisting of the pixel values sequentially input,
The second code data generation means is a case where the low-value image is encoded, and as a result of the comparison by the comparison means, the input pixel value is already stored in the second storage means. If the pixel value does not match any of the pixel values, the input pixel value is encoded to generate the second code data,
The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. Third storage means for storing the first code data and the second code data;
Second reading means for reading data stored in the third storage means;
Analyzing means for analyzing the type of the data read by the second reading means;
When the data is the first code data as a result of the analysis by the analyzing means, first specifying means for specifying the length information and the address information from the first code data;
When decoding the multi-valued image, and when the data is the first code data as a result of the analysis by the analyzing unit, the length information specified by the first specifying unit and Second specifying means for specifying the prediction error value of the pixel to be decoded using the address information;
Fourth storage means for storing pixel values of the pixels that have already been decoded;
When decoding the multi-valued image, and when the data is the first code data as a result of analysis by the analysis unit, pixel values of pixels around the pixel to be decoded Second predicted value calculating means for calculating the predicted value of the pixel value of the pixel to be decoded based on the read pixel values of the surrounding pixels,
When the multi-valued image is decoded and the data is the first code data as a result of the analysis by the analysis unit, the prediction error value specified by the second specification unit And first decoding means for obtaining and decoding the pixel value of the pixel to be decoded from the predicted value calculated by the second predicted value calculating means,
When the data is the second code data as a result of analysis by the analysis means, the second decoding means for obtaining and decoding the pixel value specified by the second code data,
The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. When decoding the small-value image and, as a result of analysis by the analysis unit, the data is the first code data, the length information specified by the first specification unit and Further comprising third decoding means for obtaining and decoding a pixel value of the pixel to be decoded using the address information;
The image processing apparatus according to claim 4. From the first storage means to which each pixel value of a plurality of pixels constituting a multi-valued image having a gradation number equal to or greater than a predetermined number or a low-value image having a gradation number lower than the predetermined number is written, A first step of reading a pixel value of a certain pixel of interest;
A second step of calculating a predicted value of the pixel value of the target pixel based on pixel values of pixels around the target pixel;
A third step of calculating a prediction error value which is a difference between the predicted value calculated in the second step and a pixel value of the target pixel;
When encoding the multi-valued image, encoding is performed by the prediction error method using the prediction error value calculated in the third step, while when encoding the low-value image, the prediction is performed. A fourth step of encoding with an encoding method different from the error method,
An image processing method.

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