JP6451221B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method.

  In an image forming apparatus such as a printer, input image data is temporarily stored in a memory, and the image data stored in the memory is read at a predetermined timing and printed. In this case, if the image data is stored in the memory as it is, a large-capacity memory is required and the cost of the apparatus increases. Therefore, generally, input image data is compressed and stored in a memory.

  In the image forming apparatus described above, a compression method using predictive coding is generally used. Predictive coding uses the property that the correlation between adjacent pixels is high in an image, predicts the pixel value of a target pixel to be encoded from the pixel values of the encoded pixels, and predicts the predicted value and the target pixel. The difference from the pixel value is encoded by entropy encoding.

  As a method conventionally used for this predictive coding, a plane prediction method, a LOCO-I (LOw COmplexity Lossless Compression for Images) method, and the like are known. The plane prediction method is adopted in a lossless encoding mode of JPEG (Joint Photographic Experts Group). The LOCO-I system is adopted in JPEG-LS (Joint Photographic Experts Group-LS), which is an international standardized compression encoding system. For example, Patent Document 1 discloses a technique for compressing image data using the LOCO-I method.

  However, the predictive coding techniques such as the above-described plane prediction method and LOCO-I method have been clarified as to the method of mounting on an integrated circuit, although the processing procedure of predictive coding and the processing procedure of decoding have been clarified. It has not been. Therefore, when the above method is simply implemented in an integrated circuit, there is a possibility that processing relating to image encoding and decoding cannot be performed efficiently.

  The present invention has been made in view of the above, and an object of the present invention is to provide an image processing apparatus and an image processing method capable of efficiently performing processing related to image encoding and decoding.

In order to solve the above-described problems and achieve the object, the present invention includes a storage unit capable of storing pixel values of at least two lines or more, and a plurality of arrays arranged on a processing target line from the storage unit. Reading means for reading out the pixel value of the target pixel and the pixel values of the peripheral pixels around the target pixel, and pixel values of the peripheral pixels around the target pixel read out by the reading means, each of the target pixels being processed A plurality of prediction means for predicting the pixel value of the pixel of interest , and the prediction means for the pixel value of the pixel of interest and the pixel of interest read by the reading means, each of the pixels of interest being processed. A plurality of first calculation means for calculating a prediction error value from a difference from the prediction value predicted by the first calculation means, a compression means for compressing each of the prediction error values calculated by the first calculation means, and the pressure A decoding means for decoding each of the prediction error values compressed by the means; a prediction value predicted by the prediction means for the target pixel and a prediction error value decoded by the decoding means for each target pixel; And a plurality of second calculation means for decoding the pixel value of the target pixel, respectively, and the second calculation means determines the pixel value of the decoded target pixel as the peripheral value of the target pixel. It inputs into the said prediction means used as a pixel .

  According to the present invention, it is possible to efficiently perform processing related to image encoding and decoding.

FIG. 1 is a diagram illustrating a configuration example of a color printer according to an embodiment. FIG. 2 is a block diagram illustrating a configuration example of the electrical / control device of the color printer. FIG. 3 is a diagram showing an example of the format of the main memory. FIG. 4 is a flowchart schematically showing an example of image processing in the color printer. FIG. 5 is a diagram illustrating a configuration example of the encoding unit. FIG. 6 is a diagram for explaining the reading order of the image band data from the first band data storage area. FIG. 7 is a diagram for explaining pixels used in the prediction process. FIG. 8 is a flowchart illustrating an example of prediction processing by the LOCO-I method. FIG. 9 is a flowchart illustrating an example of a prediction process using the planar prediction method. FIG. 10 is a diagram illustrating a configuration example of the decoding unit. FIG. 11 is a diagram illustrating a circuit configuration of the predictive coding processing unit. FIG. 12 is a timing chart for explaining the operation of the predictive coding processing unit. FIG. 13 is a diagram illustrating a circuit configuration of the predictive decoding processing unit. FIG. 14 is a timing chart for explaining the operation of the predictive decoding processing unit.

  Embodiments of an image processing apparatus and an image processing method according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram illustrating a configuration example of a color printer according to the present embodiment. In this embodiment, an example in which the image processing apparatus and the image processing method according to the present invention are applied to an image forming apparatus that is a color printer will be described. However, the present invention is limited to this as long as image processing is performed on an image. It is not a thing. For example, the present invention can be applied to an image processing apparatus such as a copying machine, a facsimile machine, and a multifunction machine.

  The color printer 100 in FIG. 1 forms four-color (Y, M, C, K) images with independent image forming systems 1Y, 1M, 1C, and 1K, and synthesizes these four-color images. This is an engine type image forming apparatus. Each of the image forming systems 1Y, 1M, 1C, and 1K includes a photoconductor as an image carrier, for example, a small-diameter OPC (organic photoconductor) drum 2Y, 2M, 2C, and 2K. The image forming systems 1Y, 1M, 1C, and 1K are provided around the OPC drums 2Y, 2M, 2C, and 2K, charging rollers 3Y, 3M, 3C, and 3K, developing devices 4Y, 4M, 4C, and 4K, and cleaning devices. 5Y, 5M, 5C, 5K, static eliminators 6Y, 6M, 6C, 6K, and the like. The charging rollers 3Y, 3M, 3C, and 3K function as a charging unit that charges each of the OPC drums 2Y, 2M, 2C, and 2K. The developing devices 4Y, 4M, 4C, and 4K develop the electrostatic latent images on the OPC drums 2Y, 2M, 2C, and 2K with a developer, respectively, to form toner images of Y, M, C, and K colors.

  Beside each developing device 4Y, 4M, 4C, 4K, toner bottle units 7Y, 7M, 7C, 7K for supplying Y toner, M toner, C toner, K toner to the developing devices 4Y, 4M, 4C, 4K, respectively. Is arranged. In addition, independent optical writing devices 8Y, 8M, 8C, and 8K are disposed in the image forming systems 1Y, 1M, 1C, and 1K, respectively. The optical writing devices 8Y, 8M, 8C, and 8K are laser diode (LD) light sources 9Y, 9M, 9C, and 9K as laser light sources, collimating lenses 10Y, 10M, 10C, and 10K, and fθ lenses 11Y, 11M, 11C, and 11K. , And other optical components. The optical writing devices 8Y, 8M, 8C, and 8K include polygon mirrors 12Y, 12M, 12C, and 12K as polarization scanning units, folding mirrors 13Y, 13M, 13C, 13K, 14Y, 14M, 14C, and 14K.

  The image forming systems 1Y, 1M, 1C, and 1K are arranged vertically, and the transfer belt unit 15 is arranged on the right side so as to be in contact with the OPC drums 2Y, 2M, 2C, and 2K. The transfer belt unit 15 is rotationally driven by a drive source (not shown) with the transfer belt 16 stretched around rollers 17 to 20. A paper feed tray 21 storing transfer paper as a transfer material is disposed on the lower side of the apparatus, and a fixing device 22, a paper discharge roller 23, and a paper discharge tray 24 are disposed at the top of the apparatus.

  At the time of image formation, in each image forming system 1Y, 1M, 1C, 1K, the OPC drums 2Y, 2M, 2C, 2K are rotationally driven by a driving source (not shown), and the OPC drums by the charging rollers 3Y, 3M, 3C, 3K. 2Y, 2M, 2C and 2K are uniformly charged. Then, the optical writing devices 8Y, 8M, 8C, and 8K perform optical writing on the OPC drums 2Y, 2M, 2C, and 2K on the basis of the image data of the respective colors, thereby electrostatically forming on the OPC drums 2Y, 2M, 2C, and 2K. A latent image is formed.

  The electrostatic latent images on the OPC drums 2Y, 2M, 2C, and 2K are developed by developing devices 4Y, 4M, 4C, and 4K, respectively, and become toner images of Y, M, C, and K colors. On the other hand, the transfer paper is fed in the horizontal direction from the paper feed tray 21 by the paper feed roller 25 and conveyed vertically in the image forming systems 1Y, 1M, 1C, and 1K by the transport system, and then electrostatically applied to the transfer belt 16. Is attracted and held and conveyed by the transfer belt 16. Then, a transfer bias is applied by a transfer bias applying means (not shown), and toner images of each color of Y, M, C, and K on the OPC drums 2Y, 2M, 2C, and 2K are sequentially superimposed and transferred onto the transfer paper. A full-color image is formed at the same time. The transfer sheet on which the full-color image is formed is fixed on the full-color image by the fixing device 22 and discharged to the discharge tray 24 by the discharge roller 23.

  The control of each part in the color printer 100 described above is performed by the electrical / control device 26.

  FIG. 2 is a block diagram illustrating a configuration example of the electrical / control device 26 of the color printer 100. In the example of FIG. 2, the electrical / control device 26 includes a CPU (Central Processing Unit) 200, an ASIC (Application Specific Integrated Circuit) 230, and a main memory 210. The ASIC 230 includes a CPU I / F 201, a main memory arbiter (ARB) 202, a main memory controller 203, an encoding unit 204, a decoding unit 205, a gradation processing unit 206, an engine controller 207, and a communication controller 208.

  The CPU 200 controls the overall operation of the color printer 100 according to a program stored in the main memory 210. The CPU 200 is connected to the main memory arbiter 202 via the CPU I / F 201. The main memory arbiter 202 arbitrates access to the main memory 210 by the CPU 200, the encoding unit 204, the decoding unit 205, and the communication controller 208.

  The main memory 210 is connected to the main memory arbiter 202 via the main memory controller 203. The main memory controller 203 controls access to the main memory 210. The main memory 210 stores the above-described program for operating the CPU 200 and drawing commands output from the CPU 200. The main memory 210 further stores various data such as band data and page compression data.

  The encoding unit 204 encodes image band data stored in the main memory 210. The encoded image band data (encoded band data) is supplied to the main memory 210 via the main memory arbiter 202 and the main memory controller 203 and is written in a page code storage area 303 described later. The decoding unit 205 reads out the encoded band data encoded by the encoding unit 204 and written in the main memory 210 from the main memory 210 in synchronization with a printer engine 211 described later. The decoded image band data is supplied to the gradation processing unit 206. The gradation processing unit 206 performs gradation processing on the image band data supplied from the decoding unit 205 and transfers the image band data to the engine controller 207.

  The engine controller 207 controls the printer engine 211. In FIG. 2, the C version is shown as the printer engine 211, and the M, Y, and K versions are omitted to avoid complication.

  The communication controller 208 controls communication via the network 221. For example, PDL (Page Description Language) data output from the computer 220 is received by the communication controller 208 via the network 221. The communication controller 208 transfers the received PDL data to the main memory 210 via the main memory arbiter 202 and the main memory controller 203.

  The network 221 may perform communication within a predetermined range such as a LAN (Local Area Network), or may be capable of communicating over a wider range than the Internet. The network 221 is not limited to wired communication, and may be wireless communication. Further, the network 221 may perform serial communication such as USB (Universal Serial Bus) or IEEE (Institute of Electrical and Electronics Engineers) 1394.

  FIG. 3 is a diagram illustrating an example of the format of the main memory 210. The program storage area 300 stores a program for the CPU 200 to operate. The PDL data storage area 301 stores PDL data supplied from the computer 220, for example. The first band data storage area 302 stores image band data to be compressed and encoded. The page code storage area 303 stores code data obtained by compressing and encoding image band data. The page code storage area 303 can store code data for a plurality of pages. The second band data storage area 304 stores image band data obtained by decoding the compression code.

  In the present embodiment, the first band data storage area 302 and the second band data storage area 304 include ARGB image band data holding A (attribute) and color values of R, G, and B color components. Stored. In the present embodiment, the ARGB image band data is 32-bit multi-value pixel image data (multi-value image) in which each attribute and each color component pixel has a bit depth of 8 bits. Note that the first band data storage area 302 and the second band data storage area 304 may be the same storage area.

  FIG. 4 is a flowchart schematically showing an example of image processing in the color printer 100. The operation of the color printer 100 will be schematically described with reference to the above-described FIG. 2 using the flowchart of FIG.

  For example, PDL data generated by the computer 220 is received by the communication controller 208 via the network 221 and stored in the PDL data storage area 301 of the main memory 210 (step S1). The CPU 200 reads the PDL data from the PDL data storage area 301 of the main memory 210, analyzes the PDL (step S2), and holds the A (attribute) and the ARGB band image that holds the color values of the respective RGB color components. Is drawn (step S3). The image band data based on the drawn band image is stored in the first band data storage area 302 of the main memory 210 (step S4). As described above, this image band data is a multi-value image in which each pixel has a bit depth of 32 bits.

  The encoding unit 204 reads the image band data from the first band data storage area 302 and performs compression encoding according to a predictive encoding method described later (step S5). The compression-encoded code data is stored in the page code storage area 303 of the main memory 210 (step S6).

  The decoding unit 205 reads and decodes the compression encoded data from the page code storage area 303 (step S7). The decoded image band data is written into the second band data storage area 304 of the main memory 210 and supplied to the gradation processing unit 206. The gradation processing unit 206 performs conversion to CMYK and various gradation processes on the image band data supplied from the decoding unit 205 (step S8). The image band data subjected to gradation processing is supplied to the printer engine 211 via the engine controller 207, for example (step S9). The printer engine 211 performs print output based on the supplied image band data.

  Details of the encoding unit 204 and the decoding unit 205 will be described below.

  FIG. 5 is a diagram illustrating a configuration example of the encoding unit 204. In the encoding unit 204, the image reading processing unit 400 reads image band data from the first band data storage area 302 of the main memory 210 for each line. At this time, as illustrated in FIG. 6, the image reading processing unit 400 sequentially reads image band data in units of pixels from the first band data storage area 302 for each scan line. Here, FIG. 6 is a diagram for explaining the reading order (scanning order) of the image band data from the first band data storage area 302.

  The predictive coding processing unit 401 functions as a reading unit of the present embodiment. The image band data read by the image reading processing unit 400 is stored in the line memory 402. The line memory 402 corresponds to the storage means of this embodiment, and has a storage capacity capable of storing image band data (pixel values) for at least two lines.

  The line memory 402 stores the data supplied this time under the control of the predictive coding processing unit 401 and holds the data for one line stored immediately before. For example, the line memory 402 has first and second areas each capable of storing pixels for one line. When the encoding of the pixel data for one line is completed, the line memory 402 is controlled to hold the pixel data of the area where the encoding is completed and write the pixel data of the next line to the other area. The

  In addition, the predictive coding processing unit 401 performs prediction processing using peripheral pixels around a pixel to be processed (target pixel) while accumulating image band data in the line memory 402.

  FIG. 7 is a diagram for explaining pixels used in the prediction process. The predictive coding processing unit 401 reads out the pixel value of the target pixel and the pixel values of peripheral pixels a, b, and c around the target pixel from the line memory 402. Here, the peripheral pixels a, b, and c read from the line memory 402 are pixels that have already been compressed and encoded. Specifically, the peripheral pixel a is an adjacent pixel on the same line (current line) as the target pixel. The peripheral pixels b and c are pixels on the previous line corresponding to the pixel position (column) of the target pixel and the peripheral pixel a on the current line.

  The predictive coding processing unit 401 performs a prediction process of predicting the pixel value of the target pixel using the pixel values of the surrounding pixels a, b, and c, and calculates a predicted value. Further, the predictive coding processing unit 401 compares the actual pixel value of the target pixel with the calculated predicted value, and calculates the difference value as a prediction error value.

  Here, a prediction processing method executed by the prediction encoding processing unit 401 will be described. The predictive coding processing unit 401 according to the present embodiment uses a LOCO-I method or a planar prediction method as a prediction method.

  Hereinafter, as illustrated in FIG. 7, the pixel adjacent to the left of the target pixel is described as the peripheral pixel a, the pixel adjacent above the target pixel is the peripheral pixel b, and the pixel in contact with the upper left of the target pixel is the peripheral pixel c To do. Further, description will be made assuming that pixel encoding is performed from the left to the right (horizontal direction) of the image in pixel units, and is performed from the top to the bottom (vertical direction) of the image in line units.

  First, the LOCO-I system will be described. In the LOCO-I method, the prediction value calculation method is switched according to the result of comparing the pixel value of the peripheral pixel c with the pixel values of the peripheral pixel a and the peripheral pixel b. FIG. 8 is a flowchart illustrating an example of prediction processing by the LOCO-I method. First, the predictive coding processing unit 401 determines whether or not the pixel value of the peripheral pixel c is equal to or greater than the pixel value of the peripheral pixel a and the pixel value of the peripheral pixel c is equal to or greater than the pixel value of the peripheral pixel b. (Step S11).

  If the predictive coding processing unit 401 determines that the pixel value of the peripheral pixel c satisfies the condition of step S11 (step S11; Yes), the process proceeds to step S12. In step S12, the predictive coding processing unit 401 compares the pixel value of the peripheral pixel a with the pixel value of the peripheral pixel b, and sets the smaller pixel value as the predicted value (step S12).

  When the predictive coding processing unit 401 determines that the pixel value of the peripheral pixel c does not satisfy the condition of step S11 (step S11; No), the predictive coding processing unit 401 proceeds to step S13. In step S13, the predictive coding processing unit 401 determines whether or not the pixel value of the peripheral pixel c is less than the pixel value of the peripheral pixel a and the pixel value of the peripheral pixel c is less than the pixel value of the peripheral pixel b. Is determined (step S13).

  When the predictive coding processing unit 401 determines that the pixel value of the peripheral pixel c satisfies the condition in step S13 (step S13; Yes), the process proceeds to step S14. In step S14, the predictive coding processing unit 401 compares the pixel value of the peripheral pixel a and the pixel value of the peripheral pixel b, and sets the pixel value having the larger value as the predicted value (step S14).

Further, when the predictive coding processing unit 401 determines that the pixel value of the peripheral pixel c does not satisfy the condition of Step S13 (Step S13; No), the process proceeds to Step S15. In other words, this means that one of the peripheral pixel a and the peripheral pixel b has a pixel value greater than or equal to the pixel value of the peripheral pixel c, and the other pixel value is less than the pixel value of the peripheral pixel c. To do. In step S15, the predictive coding processing unit 401 calculates the following expression (1) for the pixel values of the peripheral pixels a, b, and c, and sets the obtained value p as a predicted value (step S15).
p = a + b−c (1)

  Next, the plane prediction method will be described. FIG. 9 is a flowchart illustrating an example of a prediction process using the planar prediction method. In the case of the plane prediction method, the predictive coding processing unit 401 calculates the value p from the surrounding pixels a, b, and c by using the above formula (1), and uses the calculated value p as a predicted value (step S21). .

  Then, the predictive coding processing unit 401 calculates a difference between the pixel value of the target pixel and the predicted value obtained by the prediction process as a prediction error value. This prediction error value is supplied to the Huffman encoding processing unit 403.

  The Huffman encoding processing unit 403 functions as a compression unit of this embodiment. The Huffman encoding processing unit 403 compresses and encodes the prediction error value supplied from the prediction encoding processing unit 401 according to the Huffman encoding format. The code writing processing unit 404 stores the code data of the prediction error value compressed and encoded by the Huffman coding processing unit 403 in the page code storage area 303 of the main memory 210.

  Next, the decoding unit 205 will be described. FIG. 10 is a diagram illustrating a configuration example of the decoding unit 205. The decoding unit 205 decodes the image band data compressed and encoded by the encoding unit 204.

  Specifically, the code reading processing unit 500 reads code data from the page code storage area 303 of the main memory 210 for each line. The Huffman decoding processing unit 501 corresponds to the decoding unit of this embodiment. The Huffman decoding processing unit 501 acquires the prediction error value by decoding the code data read by the code reading processing unit 500 according to the Huffman decoding format. This prediction error value is supplied to the prediction decoding processing unit 502.

  The predictive decoding processing unit 502 corresponds to the reading unit of this embodiment. The predictive decoding processing unit 502 decodes the pixel value of the target pixel using peripheral pixels around the pixel to be decoded (target pixel), and sequentially stores the decoded pixel value (image line data) in the line memory 503. The line memory 503 corresponds to the storage unit of this embodiment, and has a storage capacity capable of storing image band data for at least two lines (current line and previous line).

  The line memory 503 stores the decoded data under the control of the predictive decoding processing unit 502 and holds the data for one line stored immediately before. For example, the line memory 503 has first and second areas each capable of storing pixels for one line. When the decoding of the pixel data for one line is completed, the line memory 503 is controlled to hold the pixel data of the area where the decoding is completed and write the pixel data of the next line to the other area.

  Specifically, the predictive decoding processing unit 502 reads out the pixel value of the target pixel described in FIG. 7 and the pixel values of the peripheral pixels a, b, and c around the target pixel from the line memory 503, and performs the above-described prediction process. Is used to calculate the predicted value. Here, the peripheral pixels a, b, and c read from the line memory 503 are pixels that have already been decoded.

  The predictive decoding processing unit 502 calculates the pixel value of the target pixel based on the predicted value of the target pixel calculated from the surrounding pixels a, b, and c and the prediction error value of the target pixel supplied from the Huffman decoding processing unit 501. Is decrypted. Specifically, the prediction decoding processing unit 502 decodes (restores) the pixel value of the target pixel by adding the prediction value of the target pixel and the prediction error value.

  Also, the predictive decoding processing unit 502 stores the target pixel for one line generated by decoding, that is, image band data for one line, in the line memory 503. The image band data stored in the line memory 503 is used for decoding (prediction processing) of the next line.

  The image writing processing unit 504 stores the image band data decoded by the predictive decoding processing unit 502 in the second band data storage area 304.

  By the way, the encoding unit 204 (predictive encoding processing unit 401) of the present embodiment has a circuit configuration capable of performing processing related to image encoding for a plurality of pixels (target pixel) in parallel. In addition, the decoding unit 205 (predictive decoding processing unit 502) of the present embodiment has a circuit configuration that can perform processing related to image decoding in parallel for a plurality of pixels (target pixel). Hereinafter, circuit configurations of the prediction encoding processing unit 401 and the prediction decoding processing unit 502 will be described.

  First, the circuit configuration of the predictive coding processing unit 401 will be described with reference to FIG. Here, FIG. 11 is a diagram illustrating a circuit configuration of the predictive coding processing unit 401.

  As shown in FIG. 11, the predictive coding processing unit 401 includes four image processing circuits 410a, 410b, 410c, and 410d. The image processing circuits 410a, 410b, 410c, and 410d use different pixels arranged continuously in the current line as the target pixel. Hereinafter, when the image processing circuits 410a, 410b, 410c, and 410d are not distinguished from each other, they are simply referred to as the image processing circuit 410.

  Each of the image processing circuits 410 includes a set of a prediction processing unit 411 corresponding to the prediction unit of the present embodiment and a prediction error calculation unit 412 corresponding to the first calculation unit of the present embodiment. The prediction processing unit 411 and the prediction error calculation unit 412 calculate a prediction value and a prediction error value by using image band data for two lines (current line and previous line) stored in the line memory 402.

  Focusing on the image processing circuit 410a, the image processing circuit 410a uses the pixel a2 in the current line as the pixel of interest. Therefore, the predictive coding processing unit 401 gives the pixel values of the pixels a1, b1, and c1 around the pixel a2 to the prediction processing unit 411 of the image processing circuit 410a and the pixel values of the peripheral pixels a, b, and c described in FIG. Input as pixel value. Also, the predictive coding processing unit 401 inputs the pixel value of the pixel a2 as the pixel value of the target pixel to the prediction error calculation unit 412 of the image processing circuit 410a.

  The prediction processing unit 411 of the image processing circuit 410a calculates the predicted value Pa2 by executing the above-described prediction processing on the pixel values of the pixels a1, b1, and c1. The prediction error calculation unit 412 of the image processing circuit 410a calculates a prediction error value Ea2 as a difference value by subtracting the prediction value Pa2 from the pixel value of the pixel a2.

  The image processing circuit 410b uses the pixel a3 on the current line as a target pixel. Therefore, the predictive coding processing unit 401 gives the pixel values of the pixels a2, b2, and b1 around the pixel a3 to the prediction processing unit 411 of the image processing circuit 410b and the pixel values of the peripheral pixels a, b, and c described in FIG. Input as pixel value. Also, the predictive coding processing unit 401 inputs the pixel value of the pixel a3 as the pixel value of the target pixel to the prediction error calculation unit 412 of the image processing circuit 410b.

  The prediction processing unit 411 of the image processing circuit 410b calculates the prediction value Pa3 by executing the above-described prediction processing on the pixel values of the pixels a2, b2, and b1. The prediction error calculation unit 412 of the image processing circuit 410b calculates a prediction error value Ea3 that is a difference value by subtracting the prediction value Pa3 from the pixel value of the pixel a3.

  The predictive coding processing unit 401 also inputs pixel values to the image processing circuits 410c and 410d in the same manner as the image processing circuits 410a and 410b. Thereby, the prediction processing unit 411 of the image processing circuits 410c and 410d calculates the prediction values Pa4 and Pa5 from the pixel values of the peripheral pixels around the target pixel (pixels a4 and a5), respectively. Further, the prediction error calculation unit 412 of the image processing circuits 410c and 410d calculates the prediction error values Ea4 and Ea5 by subtracting the prediction values Pa4 and Pa5 from the pixel value of the target pixel (pixels a4 and a5), respectively.

  By the way, between the image processing circuits 410 that use adjacent pixels on the current line as the target pixel, the prediction value and the prediction error value are calculated using the pixel value of the same pixel. For example, the pixel value of the pixel b1 on the previous line is used as the pixel value of the peripheral pixel b in the prediction processing unit 411 of the image processing circuit 410a, and the pixel of the peripheral pixel c in the prediction processing unit 411 of the image processing circuit 410b. Used as a value. Further, the pixel value of the pixel a2 on the current line is used as the pixel value of the target pixel in the prediction error calculation unit 412 of the image processing circuit 410a, and the pixel of the peripheral pixel a in the prediction processing unit 411 of the image processing circuit 410b. Used as a value.

  Therefore, the predictive coding processing unit 401 according to the present embodiment inputs the pixel value of each pixel simultaneously to each of the prediction processing units 411 having the same pixel as a peripheral pixel. In addition, the predictive coding processing unit 401 of the present embodiment sets the pixel value of the pixel to the prediction processing unit 411 that uses the same pixel as a peripheral pixel and the prediction error calculation unit 412 that uses the pixel as a target pixel. Input simultaneously. Thus, in the present embodiment, the entire predictive coding processing unit 401 operates as one combinational circuit in which a plurality of image processing circuits 410 are arranged in parallel.

  FIG. 12 is a timing chart for explaining the operation of the predictive coding processing unit 401. In the figure, “clk” means a reference clock. Also, in the figure, it is assumed that pixels b5-b12 are arranged subsequent to the pixels c1, b1-b4 on the previous line shown in FIG. Further, it is assumed that the pixels a6-a13 are arranged following the pixels a1-a5 on the current line, and the processing is performed in the order of the arrows shown in FIG.

  The prediction encoding processing unit 401 reads out pixel values from the image band data stored in the line memory 402 in synchronization with the reference clock, and inputs the pixel values to the image processing circuit 410. The pixel from which the pixel value is read is determined according to the number of image processing circuits 410 included in the predictive coding processing unit 401 and the pixel position where each image processing circuit 410 is the target pixel.

  Here, it is assumed that the predictive coding processing unit 401 includes four image processing circuits 410 (see FIG. 11), and these image processing circuits 410 use four consecutive pixels on the current line as a target pixel. In this case, the predictive coding processing unit 401 uses the pixel value of each target pixel to be encoded in the current process and the pixel adjacent to the target pixel and encoded in the previous process (hereinafter referred to as the previous pixel). Are read from the current line and input to the corresponding image processing circuit 410. Further, the predictive coding processing unit 401 reads out pixel values from pixels on the previous line corresponding to the pixel positions of each pixel of interest and the previous pixel, and inputs the pixel values to the corresponding image processing circuit 410.

  For example, when the pixel a2-a5 is the target pixel in the clock T1, the predictive coding processing unit 401 reads out the pixel values for the five pixels c1 and b1-b4 from the previous line, and the pixel a1- Read pixel values of 5 pixels a5. Also, in the next clock T2, when the pixel a6-a9 is the target pixel, the predictive coding processing unit 401 reads out the pixel values for five pixels b4-b8 from the previous line, and the pixel a5- Read out pixel values of 5 pixels a9. In addition, in the next clock T3, when the pixel a10-a13 is the target pixel, the predictive coding processing unit 401 reads out the pixel values for the five pixels b8-b12 from the previous line and the pixel a9- from the current line. Read out pixel values of 5 pixels of a13. Note that the final pixel values read from the previous line and the current line in the previous process (for example, the pixel values of the pixels b4 and a5 at the clock T1) are used for the process at the next clock (clock T2), so that the same pixel It may be configured to prevent multiple reading.

  The prediction processing unit 411 included in each of the image processing circuits 410 functions as a prediction unit. The prediction processing unit 411 calculates each predicted value of the target pixel by performing the above-described prediction processing based on the pixel value input from the prediction encoding processing unit 401, with each target pixel as a processing target. For example, the prediction processing unit 411 calculates predicted values Pa2 to Pa5 for the target pixel (pixels a2 to a5) based on the pixel value input at the clock T1. In addition, the prediction processing unit 411 calculates predicted values Pa6-Pa9 for the target pixel (pixels a6-a9) based on the pixel value input at the clock T2. In addition, the prediction processing unit 411 calculates the predicted values Pa10-Pa13 for the target pixel (pixels a10-a13) based on the pixel value input at the clock T3.

  Further, the prediction error calculation unit 412 included in each of the image processing circuits 410 functions as a first calculation unit. The prediction error calculation unit 412 treats each target pixel as a processing target, and the difference between the pixel value of the target pixel input from the prediction encoding processing unit 401 and the calculation result (prediction value) in the corresponding prediction processing unit 411 From these, a prediction error value is calculated. For example, the prediction error calculation unit 412 calculates the prediction error values Ea2-Ea5 from the pixel value of the target pixel (pixel a2-a5) input at the clock T1 and the prediction value Pa2-Pa5 of the target pixel. . Also, the prediction error calculation unit 412 calculates the prediction error values Ea6-Ea9 from the pixel value of the target pixel (pixels a6-a9) input at the clock T2 and the prediction values Pa6-Pa9 of the target pixel. . Further, the prediction error calculation unit 412 calculates prediction error values Ea10-Ea13 from the pixel value of the target pixel (pixels a10-a13) input at the clock T3 and the predicted value Pa10-Pa13 of the target pixel, respectively. .

  As described above, in the predictive coding processing unit 401 according to the present embodiment, each of the image processing circuits 410 operates independently, thereby encoding (predicting values and pixels of) a plurality of pixels (target pixels) constituting the current line. Calculation of prediction error value) is performed individually. Accordingly, since it is possible to encode a plurality of pixels of interest in parallel within a time (reference clock) serving as an operation reference, it is possible to efficiently perform processing related to image encoding.

  Next, the circuit configuration of the predictive decoding processing unit 502 will be described with reference to FIG. Here, FIG. 13 is a diagram illustrating a circuit configuration of the predictive decoding processing unit 502.

  As illustrated in FIG. 13, the predictive decoding processing unit 502 includes four image processing circuits 510a, 510b, 510c, and 510d, similarly to the predictive encoding processing unit 401. Hereinafter, when the image processing circuits 510a, 510b, 510c, and 510d are not distinguished from each other, they are simply referred to as the image processing circuit 510. In FIG. 13, the pixel values of the pixels a2-a5 are represented using the pixel names of the corresponding pixels.

  Each of the image processing circuits 510 includes a set of a prediction processing unit 511 corresponding to the prediction unit of the present embodiment and a decoding processing unit 512 corresponding to the second calculation unit of the present embodiment. The prediction processing unit 511 and the decoding processing unit 512 use the image band data for two lines (current line and previous line) stored in the line memory 503 to calculate a prediction value and decode a pixel value. As for the image band data of the current line stored in the line memory 503, the pixel value of the decoded pixel is updated (added) every time decoding of the pixel of interest is completed.

  Focusing on the image processing circuit 510a, the image processing circuit 510a uses the pixel a2 in the current line as the target pixel. Therefore, the predictive decoding processing unit 502 uses the pixel values of the pixels a1, b1, and c1 around the pixel a2 as the pixels of the peripheral pixels a, b, and c described in FIG. 7 with respect to the prediction processing unit 511 of the image processing circuit 510a. Enter as a value. The prediction processing unit 511 of the image processing circuit 510a calculates the prediction value Pa2 by executing the above-described prediction processing on the pixel values of the pixels a1, b1, and c1.

  The decoding processing unit 512 of the image processing circuit 510a restores the pixel value of the pixel a2 that is the target pixel by adding the prediction error value Ea2 for the pixel a2 decoded by the Huffman decoding processing unit 501 to the prediction value Pa2. To do.

  Here, similarly to the predictive encoding processing unit 401, the predictive decoding processing unit 502 performs pixel values of the pixels through a common path for each of the prediction processing units 511 having the same pixel as the surrounding pixels b and c. By supplying the pixel value of the pixel at the same time. The decoding processing unit 512 of the image processing circuit 510a supplies the decoded pixel value of the target pixel (pixel a2) to the prediction processing unit 511 of the next stage (image processing circuit 510b) that uses the target pixel as the peripheral pixel a. By doing so, the decoding result is fed back to the processing in the next stage.

  The image processing circuit 510b uses the pixel a3 on the current line as a target pixel. The prediction processing unit 511 of the image processing circuit 510b needs the pixel values of the pixels a2, b2, and b1 around the pixel a3, but the pixel value of the pixel a2 is determined from the prediction processing unit 511 of the previous stage (image processing circuit 510a). Entered. Therefore, the predictive decoding processing unit 502 inputs the pixel values of the pixels b2 and b1 around the pixel a3 as the pixel values of the peripheral pixels b and c described in FIG. 7 to the prediction processing unit 511 of the image processing circuit 510b. .

  The prediction processing unit 511 of the image processing circuit 510b calculates the predicted value Pa3 by executing the above-described prediction processing on the pixel values of the pixels a2, b2, and b1. The decoding processing unit 512 of the image processing circuit 510b restores the pixel value of the pixel a3 that is the target pixel by adding the prediction error value Ea3 for the pixel a3 decoded by the Huffman decoding processing unit 501 to the prediction value Pa3. To do. Also, the decoding processing unit 512 of the image processing circuit 510b supplies the decoded pixel value of the target pixel (pixel a3) to the prediction processing unit 511 of the next stage (image processing circuit 510c), so that the decoding result is output to the next stage. Input feedback to the process.

  The predictive decoding processing unit 502 also inputs pixel values to the image processing circuits 510c and 510d in the same manner as the image processing circuit 510b. Accordingly, the prediction processing units 511 of the image processing circuits 510c and 510d calculate the prediction values Pa4 and Pa5 from the pixel values of the peripheral pixels around the target pixel (pixels a4 and a5), respectively. Also, the decoding processing units 512 of the image processing circuits 510c and 510d restore the pixel values of the target pixels (pixels a4 and a5), respectively. Further, the decoding processing unit 512 of the image processing circuits 510c and 510d supplies the decoded pixel value of the target pixel (pixels a4 and a5) to the prediction processing unit 511 at the next stage. Although not shown in FIG. 13, a supply path for supplying the pixel value of the peripheral pixel a from the decoding processing unit 512 of the image processing circuit 510d to the prediction processing unit 511 of the image processing circuit 510a may be provided. In this case, when the image processing circuit 510a sets the pixel next to the pixel a5 that has become the target pixel (pixel a6) as the target pixel, the result restored by the decoding processing unit 512 of the image processing circuit 510d can be used. .

  As described above, the predictive decoding processing unit 502 according to the present embodiment inputs the pixel values of the pixels simultaneously to the prediction processing unit 511 having the same pixel as a peripheral pixel. In addition, the decoding processing unit 512 included in each of the image processing circuits 510 supplies the processing result (the pixel value of the target pixel) in the image processing circuit 510 of itself to the next-stage image processing circuit 510 (prediction processing unit 511). To do. Thus, in the present embodiment, the entire predictive decoding processing unit 502 operates as one combinational circuit in which a plurality of image processing circuits 510 are arranged in parallel.

  FIG. 14 is a timing chart for explaining the operation of the predictive decoding processing unit 502. In the figure, “clk” means a reference clock. Also, in the figure, it is assumed that pixels b5-b12 are arranged subsequent to the pixels c1, b1-b4 on the previous line shown in FIG. Further, it is assumed that pixels a2 to a13 are arranged following the pixel a1 on the current line, and processing is performed in the order of the arrows shown in FIG. In FIG. 14, the pixel values of the pixels a2-a13 are represented using the pixel names of the corresponding pixels.

  14 indicates the prediction value predicted by the prediction processing unit 511 of the image processing unit 510a illustrated in FIG. 13, and similarly, the prediction value PB-PD is the prediction processing of the image processing units 510b-510d. Each of the predicted values predicted by the unit 511 is shown. 14 indicates the pixel value decoded by the decoding processing unit 512 of the image processing unit 510a shown in FIG. 13, and similarly, the pixel value VB-VD indicates the decoding processing of the image processing units 510b-510d. Each of the pixel values decoded by the unit 512 is shown.

  The prediction decoding processing unit 502 reads out pixel values from the image band data stored in the line memory 503 in synchronization with the reference clock, and inputs the pixel values to the image processing circuit 510. The pixel from which the pixel value is read out is determined according to the number of image processing circuits 510 provided in the predictive decoding processing unit 502 and the pixel position that each image processing circuit 510 uses as a target pixel.

  Here, it is assumed that the predictive decoding processing unit 502 includes four image processing circuits 510 (see FIG. 13), and the image processing circuit 510 uses four consecutive pixels on the current line as a target pixel. In this case, the predictive decoding processing unit 502 calculates the pixel value of each target pixel to be decoded in the current process and the pixel adjacent to the target pixel and decoded in the immediately previous process (hereinafter referred to as the previous pixel). The pixel value is read from the current line and input to the corresponding image processing circuit 510.

  In addition, the predictive decoding processing unit 502 corresponds to the pixel positions of the pixel that the image processing circuit 510 performs as the pixel of interest and the pixel immediately before the pixel of interest for the image processing circuit 510 that performs the second and subsequent processes on the current line. The pixel values are read from the two pixels on the previous line. Then, the predictive decoding processing unit 502 inputs the read pixel value to the corresponding image processing circuit 510.

  As a result, for example, when the pixel a2-a5 is the target pixel in the clock T1, which is the first process, the predictive decoding processing unit 502 reads out the pixel value of the pixel a1 from the current line, and the pixel c1, Read out the pixel values of b1-b4. In addition, in the clock T2, when the subsequent pixels a6-a9 are set as the target pixel, the predictive decoding processing unit 502 reads out the pixel values of the pixels b4-b8 from the previous line. In addition, in the clock T3, when the subsequent pixels a10 to a13 are the target pixels, the predictive decoding processing unit 502 reads the pixel values of the pixels b8 to b12 from the previous line. In the second and subsequent processes, the pixel value of the target pixel (previous pixel) decoded in the previous process is input as feedback. Note that the last pixel value read from the previous line and the current line in the immediately preceding process (for example, the pixel value of the pixel b4 at the clock T1) is used for the process at the next clock (clock T2), thereby multiplexing the same pixel It may be configured to prevent reading.

  The Huffman decoding processing unit 501 inputs the decoding result of the prediction error value for the target pixel to the prediction decoding processing unit 502 in synchronization with the reference clock. For example, the Huffman decoding processing unit 501 inputs the prediction error values Ea2 to Ea5 of the pixels a2 to a5 to the prediction decoding processing unit 502 at the clock T1 that is the first process. At clock T2, the Huffman decoding processing unit 501 inputs the prediction error values Ea6-Ea9 of the pixels a6-a9 to the prediction decoding processing unit 502. Also, at clock T3, the Huffman decoding processing unit 501 inputs the prediction error values Ea10-Ea13 of the pixels a10-a13 to the prediction decoding processing unit 502.

  The prediction processing unit 511 included in each of the image processing circuits 510 calculates the predicted value of the target pixel by performing the above-described prediction processing in parallel based on the input pixel value. For example, the prediction processing unit 511 of the image processing circuit 510a that performs processing first on the current line uses the prediction value Pa2 for the target pixel (pixel a2) from the pixel values of the pixels a1, b1, and c1 input at the clock T1. Is calculated. In addition, the decoding processing unit 512 of the image processing circuit 510a decodes the pixel value of the pixel a2, which is the target pixel, by adding the predicted value Pa2 and the predicted error value Ea2. Then, the decoded pixel value of the pixel a2 is input to the next-stage image processing circuit 510b that performs the next processing.

  In the next-stage image processing circuit 510b, the prediction processing unit 511 performs the above-described prediction processing based on the input pixel value, thereby calculating the predicted value of the target pixel. For example, the prediction processing unit 511 of the image processing circuit 510b that processes the pixel a3 as the pixel of interest uses the pixel value of the pixel a2 decoded in the previous process and the pixel values of the pixels b2 and b1 input at the clock T1. A predicted value Pa3 for the pixel of interest (pixel a3) is calculated. The decoding processing unit 512 of the image processing circuit 510b decodes the pixel value of the pixel a3 that is the target pixel by adding the prediction value Pa3 and the prediction error value Ea3. The decoded pixel value of the pixel a3 is input to the next-stage image processing circuit 510c that performs the next processing.

  Also in the subsequent processing, the image processing circuit 510 calculates the predicted value of the pixel of interest while using the pixel value decoded in the immediately preceding processing, and decodes the pixel value of the pixel of interest.

  As described above, in the predictive decoding processing unit 502 of the present embodiment, each of the image processing circuits 510 operates independently, thereby individually restoring a plurality of pixels (target pixel) constituting the current line. This makes it possible to decode a plurality of pixels of interest in a pipeline process within a time (reference clock) serving as a reference for operation, so that a process related to decoding of an image can be performed efficiently. .

  As mentioned above, although embodiment of this invention was described, the said embodiment was shown as an example and is not intending limiting the range of invention. The above embodiment can be implemented in various other forms, and various omissions, replacements, changes, additions, and the like can be made without departing from the scope of the invention. Moreover, the said embodiment and its deformation | transformation are included in the range of the invention, the summary, and the invention described in the claim, and its equal range.

  For example, in the above-described embodiment, the example in which the present invention is applied to the color printer 100 has been described. However, the present invention is not limited to this, and may be applied to an apparatus such as a copying machine or an MFP (Multi Function Peripheral) having a printer function.

  In the above embodiment, the number of the image processing circuits 410 and the image processing circuits 510, that is, the number of processing stages constituting the combinational circuit is four. However, the present invention is not limited to this. Note that it is preferable that the number of the image processing circuits 410 and the image processing circuits 510 is a multiple of four from the viewpoint of the architecture related to memory management.

DESCRIPTION OF SYMBOLS 100 Color printer 204 Encoding part 205 Decoding part 400 Image reading process part 401 Prediction encoding process part 402 Line memory 403 Huffman encoding process part 404 Code writing process part 410 Image processing circuit 411 Prediction process part 412 Prediction error calculation part 500 Code reading processing unit 501 Huffman decoding processing unit 502 Predictive decoding processing unit 503 Line memory 504 Image writing processing unit 510 Image processing circuit 511 Prediction processing unit 512 Decoding processing unit

JP 2011-019095 A

Claims (5)

Storage means capable of storing pixel values of at least two lines or more;
Reading means for reading out the pixel values of a plurality of target pixels arranged on the processing target line and the pixel values of peripheral pixels around the target pixel from the storage unit;
A plurality of prediction means for processing each of the target pixels and predicting pixel values of the target pixels using pixel values of peripheral pixels around the target pixel read by the reading unit;
Each of the target pixels is a processing target, and a plurality of first error values are calculated from the difference between the pixel value of the target pixel read by the reading unit and the prediction value predicted by the prediction unit for the target pixel. A calculation means;
Compression means for compressing each of the prediction error values calculated by the first calculation means;
Decoding means for decoding each of the prediction error values compressed by the compression means;
A plurality of pixels for decoding each pixel value of the pixel of interest by adding each of the pixel of interest as a processing target and adding the prediction value predicted by the prediction unit and the prediction error value decoded by the decoding unit for the pixel of interest Second calculating means of
With
The second calculation unit inputs the decoded pixel value of the target pixel to the prediction unit using the target pixel as the peripheral pixel.
Image processing device. The image processing apparatus according to claim 1 , further comprising a combinational circuit in which a plurality of sets of the prediction unit and the first calculation unit are arranged in parallel. The image processing apparatus according to claim 1 , further comprising a combinational circuit in which a plurality of sets of the prediction unit and the second calculation unit are arranged in parallel. The image processing apparatus according to claim 2 or 3 , wherein the number of stages of the set constituting the combinational circuit is a multiple of four. An image processing method executed by an image processing apparatus,
The image processing apparatus includes storage means capable of storing pixel values of at least two lines or more,
A reading step of reading out pixel values of a plurality of target pixels arranged on the processing target line and pixel values of peripheral pixels around the target pixel from the storage unit;
A plurality of prediction steps for setting each of the target pixels as a processing target and using the pixel values of peripheral pixels around the target pixel read in the reading step to predict the pixel value of the target pixel;
Each of the target pixels is a processing target, and a plurality of first error values are calculated from the difference between the pixel value of the target pixel read by the reading step and the predicted value predicted by the prediction step for the target pixel. A calculation process;
A compression step of compressing each of the prediction error values calculated in the first calculation step;
A decoding step of decoding each of the prediction error values compressed in the compression step;
A plurality of pixels for decoding each pixel value of the target pixel by adding each of the target pixels to be processed and adding the prediction value predicted by the prediction step and the prediction error value decoded by the decoding step for the target pixel A second calculation step of
Including
In the second calculation step, the pixel value of the decoded target pixel is input to the prediction step using the target pixel as the peripheral pixel.
Image processing method.

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