JP2012129722A - Limiter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a limiter circuit that relieves a tradeoff relationship between leakage and withstanding power.SOLUTION: The limiter circuit includes: a PIN diode circuit 3 connected between an input terminal 1 and a ground; a coupling circuit 4 having a coupling input terminal 4a, a branch terminal 4b and a coupling output terminal 4c in which the coupling input terminal 4a is connected to the PIN diode circuit 3 and a high frequency signal input from the input terminal 1 branches from the branch terminal 4b; a capacitor 5 having one end connected to the coupling output terminal 4c; a PIN diode circuit 6 connected between the capacitor 5 and a ground; and a detection circuit 7 for supplying a positive bias current depending on the signal level of the high frequency signal input from the branch terminal 4b to a midpoint between the capacitor 5 and an output terminal 9. The PIN diode circuit 3 has a PIN diode 31 and a high frequency signal line 32 having a 1/4-wavelength electrical length at a required center frequency, and the PIN diode circuit 6 has a PIN diode 61.

Description

  The present invention relates to a limiter circuit that reduces unnecessary high-frequency signals and achieves both low leakage and high power durability.

  A conventional limiter circuit will be described with reference to FIG. FIG. 6 is a diagram showing a configuration of a conventional limiter circuit (see, for example, Patent Document 1).

  In FIG. 6, the conventional limiter circuit is connected in parallel with a high-frequency signal line 94 sandwiched between a coupling line 91 that branches a high-frequency signal from the input terminal 1, an input-side capacitor 92, and an output-side capacitor 96. PIN diode circuits 93 and 95 are provided, and a detection circuit 97 that supplies a DC bias corresponding to the signal level of the high-frequency signal input from the branch side of the coupling line 91 is provided.

  In this limiter circuit, when the signal level of the input high-frequency signal is sufficiently low, the DC diodes 93A and 95A can be regarded as equivalently open without being supplied with a DC bias from the detection circuit 97, and the input signal Is output to the output terminal 9.

  On the other hand, when the input signal level is sufficiently high, a DC bias corresponding to the signal level is supplied from the detection circuit 97, and a bias current flows through the PIN diodes 93A and 95A. At this time, the PIN diodes 93A and 95A can be regarded as equivalently short-circuited, and most of the input signal is reflected by the ground and returned to the input terminal 1. In this way, it operates as a limiter circuit that reduces unnecessary high-frequency signals.

JP 2007-6433 A

  However, the conventional limiter circuit has the following problems. A part of the input signal to the limiter circuit is input to the detection circuit 97 via the coupling line 91. The detection circuit 97 is driven when the input signal level exceeds a certain threshold value, and supplies a positive bias current to the PIN diodes 93A and 95A. The PIN diode circuits 93 and 95 are equivalently short-circuited when a current flows, and a limiter operation is performed by reflecting an input signal at the ground. Therefore, in order to reduce the leakage in the configuration of the conventional limiter circuit, it is necessary to increase the coupling amount of the coupling line 91 and increase the input signal level to the detection circuit 97.

  However, since the configuration of the conventional limiter circuit includes a coupling line 91 for branching a high-frequency signal on the input side of the PIN diode circuits 93 and 95, the coupling amount of the coupling line 91 is independent of the input signal level. The value is almost constant. Therefore, when the coupling amount of the coupling line 91 and the maximum input signal level input to the limiter circuit are determined, the maximum input signal level input to the detection circuit 97 via the coupling line 91 is determined, and the coupling line 91 is determined. As the coupling amount increases, the maximum input signal level input to the detection circuit 97 increases.

  Here, since the input signal level (withstand power) until the detection circuit 97 operates without being destroyed does not change, the detection circuit 97 is destroyed by the input signal to the lower limiter circuit as the coupling amount increases. The As described above, when the leakage is reduced by the conventional limiter circuit, the maximum input signal level is lowered due to the limitation of the power resistance of the detection circuit 97, that is, the power resistance of the limiter circuit. For this reason, the conventional limiter circuit has a problem that a trade-off relationship exists between the leakage amount and the power durability.

  The present invention has been made to solve the above-described problems. Even when the leakage is reduced, the power resistance of the detection circuit is maintained, and the trade-off relationship between the leakage amount and the power resistance is established. It is an object to obtain a limiter circuit that can be relaxed.

  A limiter circuit according to the present invention includes a first PIN diode circuit connected between an input terminal and a ground, a coupled input terminal, a branch terminal, and a coupled output terminal, and the coupled to the first PIN diode circuit. An input terminal is connected in series, and a high-frequency signal input from the input terminal via the coupling input terminal is branched from the branch terminal, and one end is connected to the coupling output terminal of the coupling circuit. A bias current corresponding to the signal level of the high-frequency signal input from the branch terminal of the coupling circuit, the second PIN diode circuit connected between the other end of the capacitor and the ground, and a branch terminal of the coupling circuit; A detection circuit that is supplied between the capacitor and the output terminal, and the first PIN diode circuit is provided between the input terminal and the ground. A first PIN diode connected; and a DC return line connected between the input terminal and the ground and having an electrical length of ¼ wavelength at a required center frequency, and the second PIN diode circuit includes: And a second PIN diode connected between the other end of the capacitor and the ground.

  According to the limiter circuit of the present invention, since the PIN diode that reflects the input signal is connected to the front stage of the coupling circuit, the input signal level is increased to the branch side of the coupling circuit as the input signal level increases. Accordingly, it is possible to obtain the same effect as that of increasing the power resistance of the detection circuit.

It is a figure which shows the structure of the limiter circuit which concerns on Embodiment 1 of this invention. It is a figure which shows the relationship between the input power of a limiter circuit, and the input power of a detection circuit. It is a figure which shows the structure of the limiter circuit based on Embodiment 2 of this invention. It is a figure which shows the structure of the limiter circuit based on Embodiment 3 of this invention. It is a figure which shows the structure of the limiter circuit based on Embodiment 4 of this invention. It is a figure which shows the structure of the conventional limiter circuit.

  Hereinafter, preferred embodiments of the limiter circuit of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
A limiter circuit according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 is a diagram showing a configuration of a limiter circuit according to Embodiment 1 of the present invention. In FIG. In addition, in each figure, the same code | symbol shows the same or equivalent part.

  1, the limiter circuit according to the first embodiment of the present invention includes an input terminal 1, a capacitor 2, a PIN diode circuit (first PIN diode circuit) 3, a coupling circuit 4, a capacitor 5, and a PIN. A diode circuit (second PIN diode circuit) 6, a detection circuit 7, a capacitor 8, and an output terminal 9 are provided.

  The PIN diode circuit 3 includes a PIN diode (first PIN diode) 31 and a high-frequency signal line (DC return line) 32. The coupling circuit 4 includes a coupling input terminal 4a, a branch terminal 4b, and a coupling output terminal 4c. Further, the PIN diode circuit 6 is provided with a PIN diode (second PIN diode) 61.

  In FIG. 1, a coupling circuit 4 is connected between an input terminal 1 and an output terminal 9. The capacitor 2 is connected between the input terminal 1 and the coupling input terminal 4 a of the coupling circuit 4, and the capacitor 8 is connected between the output terminal 9 and the coupling output terminal 4 c of the coupling circuit 4.

  The PIN diode 31 has an anode connected between the capacitor 2 and the coupling input terminal 4a of the coupling circuit 4, and a cathode connected to the ground. The high-frequency signal line 32 has one end connected between the capacitor 2 and the coupling input terminal 4a of the coupling circuit 4, and the other end connected to the ground. Here, the high frequency signal line 32 is set so that the electrical length is ¼ wavelength at the required center frequency. The parallel circuit of the PIN diode 31 and the high-frequency signal line 32 constitutes a self-detection type PIN diode circuit 3.

  The capacitor 5 is connected in series between the coupling output terminal 4 c of the coupling circuit 4 and the capacitor 8, and prevents the output bias current from the detection circuit 7 from flowing to the PIN diode 31.

  The PIN diode 61 constituting the PIN diode circuit 6 has an anode connected between the capacitors 5 and 8 and a cathode connected to the ground.

  The detection circuit 7 has an input side connected to the branch terminal 4b of the coupling circuit 4 and an output side connected between the PIN diode 61 and the capacitor 8 so that the signal level of the high-frequency signal input from the coupling circuit 4 is reached. Accordingly, a positive bias current (DC bias) is supplied between the capacitor 5 and the capacitor 8.

  Next, the operation of the limiter circuit according to the first embodiment will be described with reference to the drawings.

  The PIN diode circuit 3 including the PIN diode 31 and the high-frequency signal line 32 can be regarded as through because the PIN diode 31 is equivalently opened at a sufficiently low input signal level.

  On the other hand, since the current flows through the PIN diode 31 at a sufficiently high input signal level, the impedance decreases as the input signal level increases. In this case, the PIN diode 31 can be regarded as equivalently short-circuited, and the input signal is reflected by the ground and returned to the input terminal 1 side. The amount of reflection increases as the input signal level increases.

  Further, since the PIN diode circuit 6 to which the output bias current of the detection circuit 7 is supplied does not output a bias current from the detection circuit 7 at a sufficiently low input signal level, the PIN diode 61 is equivalently opened. The PIN diode circuit 6 can be regarded as through.

  On the other hand, at a sufficiently high input signal level, the detection circuit 7 is driven by the high-frequency signal input through the coupling circuit 4, and a current flows through the PIN diode 61 due to the bias current output from the detection circuit 7. Becomes low and the signal input to the PIN diode circuit 6 is reflected by the ground and returned to the input terminal 1 side. Since the bias current increases as the signal level input to the detection circuit 7 increases, the amount of reflection increases as the input signal level increases.

  In the limiter circuit according to the first embodiment, when the signal level of the high-frequency signal input from the input terminal 1 is sufficiently low, no positive bias current is supplied from the detection circuit 7 and the PIN diode circuits 3 and 6 are supplied. Since no current flows, both PIN diode circuits 3 and 6 can be regarded as equivalently through. Therefore, most of the input signals are output to the output terminal 9.

  On the other hand, when the signal level of the high-frequency signal input from the input terminal 1 is sufficiently high, a current flows through the PIN diode 31 and the PIN diode 61 in the previous stage. As a result, both PIN diodes 31 and 61 are equivalently short-circuited, and the input signal is reflected at each ground. Therefore, most of the input signal is returned to the input terminal 1 side. Thus, the limiter circuit is unnecessary because the bias current corresponding to the input signal level flows through the two PIN diodes 31 and 61. It operates as a limiter circuit that reduces high-frequency signals.

  Here, in the configuration of the limiter circuit according to the first embodiment, since the PIN diode circuit 3 is connected to the input terminal 1 side of the coupling circuit 4, a part of the input signal is reflected by the diode circuit 3. Is done. For this reason, the signal level input to the subsequent coupling circuit 4 is lower than the input signal, and the input signal level to the detection circuit 7 is also reduced. Furthermore, since the above effect becomes more prominent as the input signal level is higher, it is possible to obtain an effect equivalent to increasing the power resistance of the detection circuit 7.

  FIG. 2 is a diagram illustrating the relationship between the input power of the limiter circuit and the input power of the detection circuit.

  This figure shows a calculation example of input power of the conventional limiter circuit and the limiter circuit of the present invention (Embodiment 1-4). In the case of the conventional limiter circuit, it can be seen that the input power to the detection circuit is substantially proportional to the input power level to the limiter circuit. On the other hand, in the limiter circuit of the present invention, it can be seen that the higher the input power to the limiter circuit, the lower the input power to the detection circuit compared to the conventional limiter circuit. Here, in the example of the figure, the maximum input power of the conventional limiter circuit is limited to about 27 dBm by the maximum allowable input power of the detection circuit, whereas the limiter circuit of the present invention has the maximum input power. It can be 40 dBm or more. Therefore, even if the coupling amount is increased, the maximum input power can be increased, so that both low leakage and high input power (input signal level) can be achieved.

Embodiment 2. FIG.
A limiter circuit according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 3 is a diagram showing a configuration of a limiter circuit according to Embodiment 2 of the present invention.

  In FIG. 3, a PIN diode circuit 3 including a diode 31 and a high-frequency signal line 32 is connected to an arbitrary position on the main line between the coupling input terminal 4a and the coupling output terminal 4c of the coupling circuit 4. A PIN diode circuit 6 is connected between the capacitor 8 and the connection point between the output terminal of the detection circuit 7 and the capacitor 8. Other configurations are the same as those in the first embodiment.

  Next, the operation of the limiter circuit according to the second embodiment will be described with reference to the drawings.

  In the limiter circuit according to the second embodiment, when the signal level of the high-frequency signal input from the input terminal 1 is sufficiently low, no positive bias current is supplied from the detection circuit 7 and the PIN diodes 31 and 61 are also supplied. Since no current flows, the PIN diode circuits 3 and 6 can be regarded as equivalently through. Therefore, most of the input signals are output to the output terminal 9.

  On the other hand, when the signal level of the high-frequency signal input from the input terminal 1 is sufficiently high, a current flows through the PIN diodes 31 and 61. As a result, both PIN diode circuits 3 and 6 are equivalently short-circuited, and the input signal is reflected at each ground. Therefore, most of the input signal is returned to the input terminal 1 side. Thus, the limiter circuit is unnecessary because the bias current corresponding to the input signal level flows through the two PIN diodes 31 and 61. It operates as a limiter circuit that reduces high-frequency signals.

  In the configuration of the limiter circuit according to the second embodiment, as in the effect of the first embodiment, a part of the input signal is reflected by the PIN diode circuit 3 on the input terminal 1 side, and is sent to the coupling circuit 4 at the subsequent stage. The input signal level is lower than the input signal, and there is an effect that the input power to the detection circuit 7 is reduced.

  Here, in the configuration of the limiter circuit according to the second embodiment, the PIN diode circuit 3 is connected between the coupling input terminal 4 a and the coupling output terminal 4 c of the coupling circuit 4. When a current flows through the PIN diode 31 of the PIN diode circuit 3, the PIN diode 31 can be regarded as equivalently through and the PIN diode circuit 3 can be regarded as short-circuited. In this case, in the coupling circuit 4, there is no influence of coupling on the coupling output terminal 4c side with respect to the connection portion of the PIN diode 31, and the electrical length of the entire coupling circuit 4 is shortened. As a result, the amount of coupling changes, and the power to the branch terminal 4b side of the coupling circuit 4 is reduced.

  As described above, according to the second embodiment, it is possible to change not only the effect of reflection by the PIN diode circuit 3 but also the electrical length of the coupling circuit 4 in accordance with the input signal level. In addition to the effect that the input signal level to the detection circuit 7 according to the first mode can be lowered as the signal level increases, the PIN diode circuit connected between the coupling input terminal 4a and the coupling output terminal 4c of the coupling circuit 4 The position of 3 makes it possible to adjust the input signal level to the detection circuit 7.

  In the first and second embodiments described above, the case where the high-frequency signal line 32 is used as the DC return line has been described. However, the same effect can be obtained even when the high-frequency signal line 32 is used instead of an inductor or a resistor. Obtainable.

Embodiment 3 FIG.
A limiter circuit according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 4 is a diagram showing a configuration of a limiter circuit according to Embodiment 3 of the present invention.

  In FIG. 4, the coupling circuit 4 is connected between the input terminal 1 and the output terminal 9. The capacitor 2 is connected between the input terminal 1 and the coupling input terminal 4 a of the coupling circuit 4, and the capacitor 8 is connected between the output terminal 9 and the coupling output terminal 4 c of the coupling circuit 4.

  The PIN diode 31 has an anode connected between the capacitor 2 and the coupling input terminal 4a of the coupling circuit 4, and a cathode connected to the ground. The PIN diode 61 has an anode connected between the coupling output terminal 4c of the coupling circuit 4 and the capacitor 8, and a cathode connected to the ground.

  The detection circuit 7 has an input side connected to the branch terminal 4 b of the coupling circuit 4 and an output side connected between the capacitor 8 and the coupling output terminal 4 c of the coupling circuit 4. A positive bias current is supplied between the capacitor 2 and the capacitor 8 in accordance with the signal level of the signal.

  Next, the operation of the limiter circuit according to the third embodiment will be described with reference to the drawings.

  In the limiter circuit according to the third embodiment, the impedances of both the PIN diodes 31 and 61 are changed by the positive bias current supplied from the detection circuit 7. When the signal level of the high-frequency signal input from the input terminal 1 is sufficiently low, no positive bias current is supplied from the detection circuit 7, and both the PIN diodes 31 and 61 can be regarded as equivalently open. Therefore, the PIN diode circuits 3 and 6 can be regarded as through, and most of the input signals are output to the output terminal 9.

  On the other hand, when the signal level of the high-frequency signal input from the input terminal 1 is sufficiently high, current flows through the PIN diodes 31 and 61 due to the positive bias current output from the detection circuit 7 and is equivalently through. Thereby, the PIN diodes 31 and 61 can be regarded as a short circuit. Therefore, the input signal is reflected at each ground. Therefore, most of the input signal is returned to the input terminal 1 side. Thus, this limiter circuit is unnecessary because the bias current corresponding to the input signal level flows through the two PIN diodes 31 and 61. It operates as a limiter circuit that reduces high frequency signals.

  Here, in the limiter circuit according to the third embodiment, the PIN diode 31 closer to the input terminal 1 side is connected to the input terminal 1 side than the coupling circuit 4. Since the PIN diode 31 is instantaneously through when a high-frequency signal is input, a part of the input signal is reflected and returned to the input terminal 1 side. Therefore, the signal level input to the subsequent coupling circuit 4 is lower than the input signal, and the input power to the detection circuit 7 is also reduced. Furthermore, since the above effect becomes more significant as the input signal level increases, it is possible to obtain the same effect as increasing the power resistance of the detection circuit 7.

Embodiment 4 FIG.
A limiter circuit according to Embodiment 4 of the present invention will be described with reference to FIG. 5 is a diagram showing a configuration of a limiter circuit according to Embodiment 4 of the present invention.

  In FIG. 5, a PIN diode circuit 3 composed of a diode 31 is connected to an arbitrary position on the main line between the coupling input terminal 4a and the coupling output terminal 4c of the coupling circuit 4. A PIN diode circuit 6 is connected between the connection point between the coupling output terminal 4 c of the coupling circuit 4 and the output terminal of the detection circuit 7 and the capacitor 8. Other configurations are the same as those in the third embodiment.

  Next, the operation of the limiter circuit according to the fourth embodiment will be described with reference to the drawings.

  When the signal level of the high-frequency signal input from the input terminal 1 is sufficiently low, the positive bias current is not supplied from the detection circuit 7, and the PIN diodes 31 and 61 can be regarded as being equivalently open. Therefore, the PIN diode circuits 3 and 6 can be regarded as through, and most of the input signals are output to the output terminal 9.

  On the other hand, when the signal level of the high-frequency signal input from the input terminal 1 is sufficiently high, a current flows through the PIN diodes 31 and 61 due to the positive bias current output from the detection circuit 7. Thereby, the PIN diodes 31 and 61 are equivalently through, and the PIN diode circuits 3 and 6 can be regarded as short-circuits. Therefore, since the input signal is reflected at each ground, most of the input signal is returned to the input terminal 1 side. In this way, the limiter circuit operates as a limiter circuit that reduces unnecessary high-frequency signals when a bias current corresponding to the input signal level flows through the two PIN diodes 31 and 61.

  Here, in the configuration of the limiter circuit according to the fourth embodiment, as in the effect of the third embodiment, a part of the input signal is reflected by the PIN diode circuit 3 and input to the coupling circuit 4 at the subsequent stage. The signal level is lower than that of the input signal, and there is an effect that the input power to the detection circuit 7 is reduced.

  Furthermore, in the configuration of the limiter circuit according to the fourth embodiment, the PIN diode circuit 3 is connected between the coupling input terminal 4a and the coupling output terminal 4c of the coupling circuit 4. When a current flows through the PIN diode 31 of the PIN diode circuit 3, the PIN diode 31 can be regarded as equivalently through and the PIN diode circuit 3 can be regarded as short-circuited. In this case, in the coupling circuit 4, there is no influence of coupling on the coupling output terminal 4c side with respect to the connection portion of the PIN diode 31, and the electrical length of the entire coupling circuit 4 is shortened. As a result, the amount of coupling changes, and the input signal level to the branch terminal 4b side of the coupling circuit 4 is reduced.

  As described above, according to the fourth embodiment, not only the reflection effect by the PIN diode circuit 3 but also the electrical length of the coupling circuit 4 can be changed according to the input signal level. In addition to the effect that the input power to the detection circuit 7 according to the form 3 can be lowered as the signal level increases, the PIN diode circuit 3 connected between the coupling input terminal 4a and the coupling output terminal 4c of the coupling circuit 4 The position of the input signal to the detection circuit 7 can be adjusted depending on the position.

  In Embodiment 1-4 described above, the use of PIN diodes 31 and 61 has been described. However, a Schottky diode or a field effect transistor can provide the same effect instead of the PIN diode.

  Moreover, in Embodiment 1-4 mentioned above, even when the circuit which takes out some signals, such as a divider and a splitter, is used for the coupling circuit 4 for branching an input signal, an equivalent effect can be acquired. .

  In the first to fourth embodiments described above, the PIN diode circuit 3 may further include one or a plurality of PIN diodes connected in parallel to the PIN diode 31. The PIN diode circuit 6 may further include one or a plurality of PIN diodes connected in parallel to the PIN diode 61.

  In the first to fourth embodiments described above, the PIN diodes 31 and 61 have the cathode connected to the line between the input and output terminals, the anode connected to the ground, and the detection circuit 7 is connected to the branch terminal 4b of the coupling circuit 4. Alternatively, a negative bias current corresponding to the signal level of the high-frequency signal input from may be supplied.

  In the first to fourth embodiments described above, a nonlinear signal such as the PIN diode circuit 3 is provided between the branch terminal 4b of the coupling circuit 4 and the detection circuit 7 with respect to the input signal to the detection circuit 7, for example. A circuit showing pass characteristics may be connected.

  Furthermore, the limiter circuits may be connected in cascade by the same limiter circuit or a combination of different limiter circuits among the limiter circuits of the above-described first to fourth embodiments and the above-described modifications.

  1 input terminal, 2 capacitor, 3 PIN diode circuit, 4 coupling circuit, 4a coupling input terminal, 4b branching terminal, 4c coupling output terminal, 5 capacitor, 6 PIN diode circuit, 7 detection circuit, 8 capacitor, 9 output terminal, 31 PIN diode, 32 high frequency signal line, 61 PIN diode.

Claims (10)

A first PIN diode circuit connected between the input terminal and ground;
A coupling input terminal; a branch terminal; and a coupling output terminal. The coupling input terminal is connected in series to the first PIN diode circuit, and a high-frequency signal input from the input terminal via the coupling input terminal is the branch terminal. A coupling circuit branching from
A capacitor having one end connected to the coupling output terminal of the coupling circuit and the other end connected to the output terminal;
A second PIN diode circuit connected between the other end of the capacitor and ground;
A detection circuit that supplies a bias current according to a signal level of a high-frequency signal input from a branch terminal of the coupling circuit between the capacitor and the output terminal;
The first PIN diode circuit is:
A first PIN diode connected between the input terminal and ground;
A DC return line connected between the input terminal and the ground and having an electrical length of ¼ wavelength at a required center frequency;
The second PIN diode circuit is:
A limiter circuit comprising: a second PIN diode connected between the other end of the capacitor and the ground. A coupling circuit having a coupling input terminal, a branch terminal, and a coupling output terminal, wherein the coupling input terminal is connected in series to the input terminal, and a high-frequency signal input from the input terminal via the coupling input terminal is branched from the branch terminal. When,
A first PIN diode circuit connected between a coupling input terminal and a coupling output terminal of the coupling circuit and a ground;
A capacitor having one end connected to the coupling output terminal of the coupling circuit and the other end connected to the output terminal;
A second PIN diode circuit connected between the other end of the capacitor and ground;
A detection circuit that supplies a bias current according to a signal level of a high-frequency signal input from a branch terminal of the coupling circuit between the capacitor and the output terminal;
The first PIN diode circuit is:
A first PIN diode connected between the coupling input terminal and coupling output terminal of the coupling circuit and between ground;
A DC return line connected between the coupling input terminal and the coupling output terminal of the coupling circuit and between the ground and the ground, and having an electrical length of ¼ wavelength at a required center frequency;
The second PIN diode circuit is:
A limiter circuit comprising: a second PIN diode connected between the other end of the capacitor and the ground. A first PIN diode circuit connected between the input terminal and ground;
A coupling input terminal; a branch terminal; and a coupling output terminal. The coupling input terminal is connected in series to the first PIN diode circuit, and a high-frequency signal input from the input terminal via the coupling input terminal is the branch terminal. A coupling circuit branching from
A second PIN diode circuit connected between the coupled output terminal of the coupling circuit and the output terminal and ground;
A detection circuit that supplies a bias current according to a signal level of a high-frequency signal input from a branch terminal of the coupling circuit between the input terminal and the output terminal;
The first PIN diode circuit is:
A first PIN diode connected between the input terminal and ground;
The second PIN diode circuit is:
A limiter circuit, comprising: a coupling output terminal of the coupling circuit; and a second PIN diode connected between the output terminal and the ground. A coupling circuit having a coupling input terminal, a branch terminal, and a coupling output terminal, wherein the coupling input terminal is connected in series to the input terminal, and a high-frequency signal input from the input terminal via the coupling input terminal is branched from the branch terminal. When,
A first PIN diode circuit connected between a coupling input terminal and a coupling output terminal of the coupling circuit and a ground;
A second PIN diode circuit connected between the coupled output terminal of the coupling circuit and the output terminal and ground;
A detection circuit that supplies a bias current according to a signal level of a high-frequency signal input from a branch terminal of the coupling circuit between the input terminal and the output terminal;
The first PIN diode circuit is:
A first PIN diode connected between a coupling input terminal and a coupling output terminal of the coupling circuit and between ground;
The second PIN diode circuit is:
A limiter circuit, comprising: a coupling output terminal of the coupling circuit; and a second PIN diode connected between the output terminal and the ground. The first PIN diode circuit is:
The limiter circuit according to claim 1, further comprising a third PIN diode connected in parallel to the first PIN diode. The second PIN diode circuit is:
The limiter circuit according to claim 1, further comprising a fourth PIN diode connected in parallel to the second PIN diode. The first and second PIN diodes have an anode connected to a line between input and output terminals, a cathode connected to the ground,
The limiter according to claim 1, wherein the detection circuit supplies a positive bias current corresponding to a signal level of a high-frequency signal input from a branch terminal of the coupling circuit. circuit. The first and second PIN diodes have a cathode connected to a line between input and output terminals, an anode connected to the ground,
The limiter according to claim 1, wherein the detection circuit supplies a negative bias current corresponding to a signal level of a high-frequency signal input from a branch terminal of the coupling circuit. circuit. The circuit which shows a non-linear passage characteristic with respect to the input signal to the detection circuit is connected between the branch terminal of the coupling circuit and the detection circuit. The limiter circuit according to any one of the above. The limiter circuit according to any one of claims 1 to 9, wherein each limiter circuit is connected in cascade by a combination of the same limiter circuit or different limiter circuits.

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