JP2012128445A - Light emitting device and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce influence of capacitance parasitic on each part of a light emitting device.SOLUTION: A unit element P comprises: a light emitting element E in which a light emitting layer 23 intervenes between a first electrode 21 and a second electrode 22; a driving transistor Tdr for controlling the amount of electric current supplied to the light emitting element E; a capacitance element C1 electrically connected to a gate electrode of the driving transistor Tdr; a selection transistor Tsl for setting potential of the gate electrode of the driving transistor Tdr in accordance with data signals; and an initializing transistor Tint for controlling connection between the gate electrode of the driving transistor Tdr and a drain electrode. The first electrode 21 overlaps the capacitance element C1 and, on the one hand, the first electrode 21 does not overlap the selection transistor Tsl or the initializing transistor Tint.

Description

  The present invention relates to a structure of a light emitting device using a light emitting material such as an organic EL (ElectroLuminescent) material.

  An active matrix light-emitting device in which a transistor for controlling the amount of current supplied to the light-emitting element is provided for each light-emitting element has been proposed (for example, Patent Document 1). In this type of light-emitting device, for example, in order to improve the aperture ratio (the ratio of the region where light emitted from each light-emitting element is actually emitted out of the region where the light-emitting elements are arranged) , Wirings for electrically connecting each of them are stacked on the substrate.

JP 2004-119219 A

  However, in the configuration in which the elements are stacked as described above, the elements adjacent to each other are capacitively coupled (that is, capacitance is parasitic between the elements). For example, when the waveforms of various signals become dull due to the parasitic capacitance of each part, high-precision control of the light-emitting element may be hindered. In the background as described above, one embodiment of the present invention aims to solve the problem of reducing the influence of capacitance parasitic on each part of a light emitting device.

According to a first aspect of the present invention, there is provided a light emitting element having a light emitting layer interposed between a first electrode and a second electrode, a drive transistor for controlling an amount of current supplied to the light emitting element, and a gate of the drive transistor. And a capacitive element electrically connected to the electrode (for example, the capacitive element C1 of FIG. 2 or the capacitive element C2 of FIG. 21 or FIG. 32), wherein the first electrode overlaps the capacitive element. .
In this aspect, since the first electrode is formed so as to overlap with the capacitor element, the first electrode can be formed without forming the first electrode so as to overlap with various switching elements used for controlling the light emitting element. The area is easily secured. Therefore, it is possible to reduce the parasitic capacitance between the first electrode and the switching element (and prevent delay of the switching operation due to the parasitic capacitance) while sufficiently securing the area of the first electrode. .

For example, a selection transistor (for example, the selection transistor Ts1 in FIGS. 2 and 21) that is turned on or off according to a selection signal is provided, and the gate electrode of the drive transistor is connected to the selection transistor that is turned on. In the configuration in which the potential is set according to the data signal supplied from the data line, the first electrode is formed so as not to overlap with the selection transistor. According to this aspect, since the parasitic capacitance between the first electrode and the selection transistor is reduced, the selection transistor can be operated quickly (that is, without causing a delay due to the parasitic capacitance). .
Further, an initialization transistor (for example, the initialization transistor Tint in FIG. 2) that is turned on or off in response to the initialization signal is provided, and the gate electrode and the drain of the driving transistor are turned on. In the configuration in which the first electrodes are formed so as not to overlap with the initialization transistor, the first electrode is formed so as to be electrically connected via the initialization transistor. According to this aspect, since the parasitic capacitance between the first electrode and the initialization transistor is reduced, the initialization transistor can be operated quickly. Note that the gate electrode of the driving transistor electrically connected via the initialization transistor is set to a potential corresponding to the threshold voltage of the driving transistor. Therefore, it is possible to compensate for an error in the threshold voltage of the driving transistor.

  Note that the capacitor element is typically used for setting or holding the potential of the gate electrode of the driving transistor. For example, the capacitive element (for example, the capacitive element C1 in FIG. 2) in one embodiment is interposed between the gate electrode of the driving transistor and the data line. In this configuration, the gate electrode of the drive transistor is set to a potential corresponding to the amount of variation in the potential of the data line by capacitive coupling in the capacitive element. Further, the capacitive element (for example, the capacitive element C2 in FIGS. 21 and 32) in other modes is interposed between the gate electrode of the driving transistor and a wiring (for example, a power supply line) to which a constant potential is supplied. In this configuration, the potential supplied from the data line to the gate electrode of the driving transistor is held in the capacitor element.

The second aspect of the present invention is a light emitting device in which a light emitting layer is interposed between a power supply line (for example, the power supply line 15 in FIG. 2 or FIG. 21) to which a predetermined potential is supplied and a first electrode and a second electrode. And a drive transistor for controlling the amount of current supplied from the power supply line to the light emitting element, wherein the power supply line includes a portion interposed between the first electrode and the drive transistor. And A typical example of the power supply line is a power supply line for supplying a power supply potential.
According to this aspect, since the power supply line is interposed between the first electrode and the driving transistor, the capacitive coupling between the first electrode and the driving transistor is compared with the configuration in which no conductor is interposed between the first electrode and the driving transistor. Is suppressed. Therefore, it is possible to reduce the influence of the potential fluctuation in one of the first electrode and the driving transistor on the other potential.

According to a third aspect of the present invention, a data line to which a data signal is supplied, a power supply line to which a predetermined potential is supplied, a light emitting element in which a light emitting layer is interposed between the first electrode and the second electrode, A drive transistor that controls the amount of current supplied from the power supply line to the light emitting element according to a data signal, and the power supply line includes a portion interposed between the first electrode and the data line. .
According to this aspect, since the power supply line is interposed between the first electrode and the data line, the capacitive capacity of both is compared with the configuration in which the conductor is not interposed between the first electrode and the data line. Binding is suppressed. Therefore, it is possible to reduce the influence of the potential fluctuation in one of the first electrode and the data line on the other potential.

According to a fourth aspect of the present invention, a data line to which a data signal is supplied, a light emitting element in which a light emitting layer is interposed between the first electrode and the second electrode, and an amount of current supplied to the light emitting element are stored. And the first electrode is formed on a surface of an insulating layer (for example, the first insulating layer L1 or the second insulating layer L2 in FIG. 11) that covers the data line. The light reflecting electrode is characterized in that its outer peripheral edge overlaps the data line.
According to this aspect, the inclined surface (for example, the inclined surface 211 in FIG. 11) is formed in the vicinity of the outer peripheral edge of the first electrode by forming a step reflecting the thickness of the data line on the surface of the insulating layer. Can do. The light utilization efficiency can be improved by reflecting the light emitted from the light emitting layer on the inclined surface.

According to a fifth aspect of the present invention, there is provided a light emitting element having a light emitting layer interposed between a first electrode and a second electrode, a driving transistor for controlling an amount of current supplied to the light emitting element, and a gate of the driving transistor. A capacitive element electrically connected to the electrode and an auxiliary wiring formed of a material having a lower resistivity than the second electrode and conducting to the second electrode (for example, the auxiliary wiring 27 in FIGS. 3, 12, and 22) ), And the auxiliary wiring does not overlap the driving transistor and the capacitor.
According to this aspect, since the auxiliary wiring is formed so as not to overlap the driving transistor and the capacitive element, the parasitic capacitance between the auxiliary wiring and the driving transistor and between the auxiliary wiring and the capacitive element is reduced. The Therefore, it is possible to reduce the influence of the potential fluctuation in one of the auxiliary wiring and the driving transistor (or the capacitor) on the other potential.

In the light emitting device according to the fifth aspect, for example, an insulation in which a selection transistor that is turned on or off in response to a selection signal and an opening (opening 251 in FIG. 4) that overlaps the selection transistor and is formed are formed. And a driving transistor controls the amount of current to the light emitting element according to a data signal supplied from a data line through the selection transistor that is turned on. . In this aspect, a configuration in which the auxiliary wiring is formed above the insulating layer is also preferable. According to this aspect, since the insulating layer is interposed between the auxiliary wiring and the selection transistor, capacitive coupling between the selection transistor and the auxiliary wiring can be suppressed. In order to secure a wide area for arranging an opening for emitting light from the light emitting element and a power supply line, the selection transistor desirably overlaps with the auxiliary wiring.
Further, for example, even in a configuration in which an initialization transistor that is turned on or off in response to an initialization signal and an insulating layer that overlaps with the initialization transistor and has an opening are provided, the auxiliary wiring is insulated. It can be formed above the layer. According to this aspect, capacitive coupling between the auxiliary wiring and the initialization transistor can be suppressed. In order to secure a wide area for arranging an opening for emitting light from the light emitting element and a power supply line, the initialization transistor preferably overlaps with the auxiliary wiring.

The light emitting device according to the sixth aspect of the present invention is different from the first direction in a plurality of control lines extending in a first direction (for example, the X direction in FIGS. 18 to 20 and FIGS. 28 to 30). A data line that extends in a second direction (for example, the Y direction in FIGS. 18 to 20 and FIGS. 28 to 30) and intersects the plurality of control lines, and intersects the plurality of control lines and the data lines. And a plurality of unit elements arranged in corresponding directions and arranged in the second direction.
Each of the plurality of unit elements has a light emitting element in which a light emitting layer is interposed between a first electrode and a second electrode, and a potential of a gate electrode is set according to a signal supplied to the data line. A drive transistor that controls the amount of current supplied to the light emitting element, and whether or not a predetermined potential can be supplied to the gate electrode of the drive transistor or whether or not current can be supplied to the light emitting element among the plurality of control lines. And a control transistor that controls in accordance with a signal supplied to a control line corresponding to the unit element. The control transistor that controls whether or not a predetermined potential can be supplied to the gate electrode of the driving transistor is, for example, the selection transistor Ts1 or the initialization transistor Tint in FIG. Further, the control transistor that controls whether or not current can be supplied to the light emitting element is, for example, the light emission control transistor Tcnt of FIG. Therefore, the control line in this aspect corresponds to, for example, the selection line 11 and the initialization line 12 in FIG. 2, or the light emission control line 14 in FIG.
With the above configuration, in the first unit element (for example, the unit element P in the i-th row in FIGS. 18 to 20 and FIGS. 28 to 30) among the plurality of unit elements, The control line is located on one side in the second direction when viewed from the driving transistor, and is adjacent to the first unit element on one side in the second direction among the plurality of unit elements. Unit elements (for example, unit element P in the (i−1) th row) and a third unit element (for example, (i + 1) th) adjacent to the first unit element on the other side in the second direction. In each of the unit elements P) in the row, the control transistor and the control line are located on the other side in the second direction as viewed from the drive transistor. The data lines are formed on a surface of a plurality of first data line portions formed in the same layer as the plurality of control lines and arranged in the second direction, and an insulating layer covering the plurality of control lines. A second data line portion electrically connecting each of the first data line portions, the first data line portion being continuous over the first unit element and the third unit element, The second data line portion intersects the control line corresponding to the first unit element and the control line corresponding to the second unit element.

  According to this aspect, since the first data line portion is formed so as to be continuous over the first unit element and the third unit element, the gap between the first unit element and the third unit element is formed in the gap. There is no need to form the second data line portion. In the present invention, a plurality of elements are “formed from the same layer” means that a plurality of elements are formed by selective removal of a common film body (whether it is a single layer or a plurality of layers). It means that it is formed in the same process, and it does not matter whether each element is separated from each other or continuous. Specific examples of the sixth aspect described above will be described later as a third embodiment and a fifth embodiment.

In the light emitting device according to the sixth aspect, for example, a power supply line to which a predetermined potential is supplied is installed, and the drive transistor controls the amount of current supplied from the power supply line to the light emitting element, and The electric wire is formed from the same layer as the second data line portion of the data line, and a portion of the first data line portion located in the gap between the first unit element and the third unit element (for example, FIG. 29 connecting portions 153). According to this aspect, since the portion located in the gap between the first unit element and the third unit element is included, the resistance of the feeder line can be reduced.
In a more preferred aspect, an auxiliary wiring formed of a material having a lower resistivity than the second electrode and connected to the second electrode is provided, and the auxiliary wiring is the control transistor of the first unit element. The control line is formed so as to overlap the control transistor and the control line of the second unit element, and is not formed in the gap between the first unit element and the third unit element. According to this aspect, the line width of the auxiliary wiring formed between the first unit element and the second unit element is increased as compared with the configuration in which the auxiliary wiring is formed independently for each unit element. It is possible. In this configuration, since high accuracy is not required for forming the auxiliary wiring, the auxiliary wiring can be formed by an inexpensive method. In addition, since the number of auxiliary wirings formed in the light-emitting device is small, a margin area provided between each auxiliary wiring and another component can be reduced when forming the auxiliary wiring. Therefore, a region for forming the auxiliary wiring or a region where the light emitting element emits light can be widened.

  The light emitting device according to the present invention is used in various electronic devices. A typical example of this electronic device is a device that uses a light emitting device as a display device. Examples of this type of electronic device include a personal computer and a mobile phone. However, the use of the light emitting device according to the present invention is not limited to image display. For example, an exposure device (exposure head) for forming a latent image on an image carrier such as a photosensitive drum by irradiation of light, a device (backlight) that is arranged on the back side of the liquid crystal device and illuminates it, or The light emitting device of the present invention can be applied to various uses such as various illumination devices such as a device that illuminates a document by being mounted on an image reading device such as a scanner.

The block diagram which shows the arrangement | sequence of the several unit element in the light-emitting device of 1st Embodiment. The circuit diagram which shows the electric constitution of each unit element. The top view which shows the structure of the unit element in 1st Embodiment. Sectional drawing seen from the IV-IV line in FIG. The top view which shows the step in which the gate insulating layer was formed. The top view which shows the step in which the 1st insulating layer was formed. The top view which shows the step in which the 2nd insulating layer was formed. The top view which shows the several unit element in the step in which the 1st insulating layer was formed. The top view which shows the several unit element in the step in which the 2nd insulating layer was formed. The top view which shows the several unit element in the step in which the 2nd electrode was formed. Sectional drawing seen from the XI-XI line in FIG. The top view which shows the structure of the unit element in 2nd Embodiment. The top view which shows the step in which the gate insulating layer was formed. The top view which shows the step in which the 1st insulating layer was formed. The top view which shows the step in which the 2nd insulating layer was formed. The top view which shows the several unit element in the step in which the 2nd insulating layer was formed. The top view which shows the several unit element in the step in which the 2nd electrode was formed. The top view which shows the several unit element of the step in which the 1st insulating layer was formed in 3rd Embodiment. The top view which shows the unit element of the step in which the 2nd insulating layer was formed. The top view which shows the unit element of the step in which the 2nd electrode was formed. The circuit diagram which shows the electric constitution of each unit element in 4th Embodiment. The top view which shows the structure of one unit element. The top view which shows the step in which the gate insulating layer was formed. The top view which shows the step in which the 1st insulating layer was formed. The top view which shows the step in which the 2nd insulating layer was formed. The top view which shows the several unit element in the step in which the 2nd insulating layer was formed. The top view which shows the several unit element in the step in which the 2nd electrode was formed. The top view which shows the several unit element of the step in which the 1st insulating layer was formed in 5th Embodiment. The top view which shows the several unit element of the step in which the 2nd insulating layer was formed. The top view which shows the several unit element of the step in which the 2nd electrode was formed. The circuit diagram which shows the structure of the unit element which concerns on a modification. The circuit diagram which shows the structure of the unit element which concerns on a modification. 1 is a perspective view of a personal computer that is a specific example of an electronic apparatus according to the invention. FIG. 10 is a perspective view of a mobile phone that is a specific example of the electronic apparatus according to the invention. FIG. 14 is a perspective view of a portable information terminal that is a specific example of the electronic apparatus according to the invention.

<A: First Embodiment>
<A-1: Electrical configuration of light emitting device>
FIG. 1 is a block diagram showing an electrical configuration of a light emitting device D according to the first embodiment of the present invention. As shown in the figure, the light emitting device D includes a plurality of selection lines 11, a plurality of initialization lines 12, and a plurality of data lines 13. Each selection line 11 and each initialization line 12 extend in the X direction. Each data line 13 extends in the Y direction orthogonal to the X direction. A unit element (pixel) P is disposed at each intersection of each pair of the selection line 11 and the initialization line 12 and the data line 13. Therefore, these unit elements P are arranged in a matrix form in the X direction and the Y direction. One unit element P is an element which becomes a minimum unit of light emission. Each unit element P is supplied with a high-potential power supply potential Vdd via a power supply line 15.

  FIG. 2 is a circuit diagram showing a configuration of each unit element P. As shown in the figure, the light emitting element E and the drive transistor Tdr are arranged on the path from the power supply line 15 to the ground line (ground potential Gnd). The light emitting element E is an element in which a light emitting layer 23 made of an organic EL material is interposed between a first electrode 21 (anode) and a second electrode 22 (cathode). The first electrodes 21 are formed so as to be separated from each other for each unit element P. The second electrode 22 is continuously formed over the plurality of unit elements P and grounded (Gnd). The light emitting layer 23 emits light with a light amount corresponding to the amount of current flowing from the first electrode 21 to the second electrode 22.

  The drive transistor Tdr is a p-channel thin film transistor for controlling the amount of current supplied to the light emitting element E according to the potential of the gate electrode (hereinafter referred to as “gate potential”) Vg. The source electrode (S) of the driving transistor Tdr is connected to the power supply line 15, and the drain electrode (D) thereof is connected to the first electrode 21 of the light emitting element E.

  Between the gate electrode and the drain electrode of the drive transistor Tdr (the first electrode 21 of the light-emitting element E), an n-channel transistor (hereinafter referred to as “initialization transistor”) for controlling the electrical connection between the two. ) Tint intervenes. The gate electrode of the initialization transistor Tint is connected to the initialization line 12. An initialization signal Sb is supplied to the initialization line 12 from a drive circuit (not shown). When the initialization signal Sb becomes active level and the initialization transistor Tint is turned on, the gate electrode and the drain electrode of the drive transistor Tdr are electrically connected (diode connection). Hereinafter, a state in which the gate electrode and the drain electrode of the drive transistor Tdr are electrically connected via the initialization transistor Tint that is turned on is referred to as a state in which the drive transistor Tdr is diode-connected. There is also.

  As shown in FIG. 2, the unit element P includes a capacitive element C1 composed of an electrode E1 and an electrode E2. The electrode E1 is connected to the gate electrode of the drive transistor Tdr. Between the electrode E2 and the data line 13, an n-channel transistor (hereinafter referred to as “selection transistor”) Ts1 for controlling the electrical connection between the electrodes E2 and the data line 13 is interposed. The gate electrode of the selection transistor Ts1 is connected to the selection line 11. A selection signal Sa is supplied to the selection line 11 from a drive circuit (not shown). Note that the conductivity types of the drive transistor Tdr, the selection transistor Ts1, and the initialization transistor Tint are appropriately changed from the example of FIG.

  Next, the operation of one unit element P will be described by dividing it into an initialization period, a writing period, and a driving period. First, in the initialization period, a predetermined potential Vref is supplied to the data line 13 from a drive circuit (not shown), and the selection signal Sa of the selection line 11 and the initialization signal Sb of the initialization line 12 are active levels ( High level). Therefore, the potential Vref is supplied from the data line 13 to the electrode E2 of the capacitive element C1 via the selection transistor Ts1. Further, when the initialization transistor Tint is turned on, the drive transistor Tdr is diode-connected. Therefore, the gate potential Vg of the drive transistor Tdr converges to a difference value (Vg = Vdd−Vth) between the power supply potential Vdd supplied to the power supply line 15 and the threshold voltage Vth of the drive transistor Tdr.

  Next, in the writing period after the lapse of the initialization period, the initialization signal Sb changes to the inactive level (low level). Accordingly, the initialization transistor Tint changes to the off state, and the diode connection of the drive transistor Tdr is released. Further, the potential Vref supplied from the data line 13 to the electrode E2 is changed to the data potential Vdata while the selection transistor Ts1 is maintained in the on state. The data potential Vdata is a potential corresponding to the gradation specified for the unit element P.

Since the impedance of the gate electrode of the driving transistor Tdr is sufficiently high, when the electrode E2 varies by the change amount ΔV (= Vref−Vdata) from the potential Vref to the data potential Vdata, the potential of the electrode E1 is capacitively coupled in the capacitive element C1. As a result, the potential changes from the potential Vg (= Vdd−Vth) set in the initialization period. The amount of change in the potential of the electrode E1 at this time is determined according to the capacitance ratio between the capacitive element C1 and other parasitic capacitance (for example, the gate capacitance of the driving transistor Tdr or the capacitance parasitic on other wiring). More specifically, when the capacitance value of the capacitive element C1 is “C” and the capacitance value of the parasitic capacitance is “Cs”, the amount of change in the potential of the electrode E1 is expressed as “ΔV · C / (C + Cs)”. . Therefore, the gate potential Vg of the drive transistor Tdr is set to the level of the following formula (1) at the end of the writing period.
Vg = Vdd−Vth−k · ΔV (1)
However, k = C / (C + Cs)

  Next, in the driving period after the writing period has elapsed, the selection signal Sa transitions to an inactive level and the selection transistor Ts1 changes to an off state. Then, a current corresponding to the gate potential Vg of the drive transistor Tdr is supplied from the power supply line 15 to the light emitting element E via the source electrode and the drain electrode of the drive transistor Tdr. By supplying this current, the light emitting element E emits light with a light amount corresponding to the data potential Vdata.

Assuming that the driving transistor Tdr operates in the saturation region, the amount of current I supplied to the light emitting element E in the driving period is expressed by the following equation (2). In Equation (2), “β” is the gain coefficient of the drive transistor Tdr, and “Vgs” is the gate-source voltage of the drive transistor Tdr.
I = (β / 2) (Vgs−Vth) ² (2)
= (Β / 2) (Vdd−Vg−Vth) ²
By substituting equation (1), equation (2) is transformed as follows.
I = (β / 2) (k · ΔV) ²
That is, the amount of current I supplied to the light emitting element E does not depend on the threshold voltage Vth of the drive transistor Tdr. Therefore, according to the present embodiment, the error in the light amount of the light emitting element E (due to the variation in the threshold voltage Vth of each driving transistor Tdr (difference from the design value or the driving transistor Tdr of another unit element P)) ( (Unevenness in brightness) can be suppressed.

<A-2: Structure of unit element P>
Next, a specific structure of the unit element P will be described. 3 is a plan view showing a configuration of one unit element P, and FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. Although FIG. 3 is a plan view, elements that are the same as those in FIG. 4 are appropriately hatched in the same manner as in FIG. The same applies to other plan views referred to below. In the drawings referred to below, the dimensions and ratios of the elements are appropriately changed from actual devices for the convenience of explanation.

  As shown in FIG. 4, each element of FIG. 2 such as the drive transistor Tdr and the light emitting element E is formed on the surface of the substrate 10. The substrate 10 is a plate-like member made of at least various insulating materials such as glass and plastic. Each element of the unit element P may be formed on the surface of the substrate 10 with an insulating film covering the substrate 10 (for example, a film of silicon oxide or silicon nitride) as a base. Further, the light emitting device D of the present embodiment is a top emission type. Therefore, the substrate 10 is not required to have optical transparency.

  5 to 7 are plan views showing a state on the surface of the substrate 10 at each stage where the unit element P is formed. 5 to 7, the region A in which the first electrode 21 shown in FIG. 3 is to be formed is also indicated by a two-dot chain line.

  As shown in FIGS. 4 and 5, a semiconductor layer 31 and a semiconductor layer 41 are formed of a semiconductor material such as silicon on the surface of the substrate 10. The semiconductor layer 31 and the semiconductor layer 41 are collectively formed in the same process by patterning a film body formed continuously over the entire area of the substrate 10. As in the relationship between the semiconductor layer 31 and the semiconductor layer 41, a plurality of elements can be removed in the same process by selectively removing a common film body (whether it is a single layer or a plurality of layers). Hereinafter, the formation is simply referred to as “formed from the same layer”. Naturally, each element formed from the same layer is made of the same material, and the film thicknesses thereof are substantially the same. According to the configuration in which a plurality of elements are formed from the same layer, there is an advantage that the manufacturing process can be simplified and the manufacturing cost can be reduced as compared with a configuration in which each of the elements is formed from another layer.

  As shown in FIGS. 4 and 5, the semiconductor layer 31 includes a first element unit 311 and a second element unit 312. The first element portion 311 is a substantially rectangular portion that functions as a semiconductor layer of the drive transistor Tdr. The second element portion 312 functions as a semiconductor layer of the initialization transistor Tint. The second element portion 312 extends from the first element portion 311 to the negative side in the Y direction and extends from the portion 312a to the positive side in the X direction. And a portion 312c extending from the portion 312b to the positive side in the Y direction.

  The semiconductor layer 41 is a portion arranged on the positive side in the Y direction when viewed from the semiconductor layer 31, and extends from the electrode E2 to the positive side in the Y direction, and the substantially rectangular electrode E2 constituting the capacitive element C1 in FIG. Existing element portion 411. The element portion 411 is a portion that functions as a semiconductor layer of the selection transistor Ts1.

  As shown in FIG. 4, the surface of the substrate 10 on which the semiconductor layer 31 and the semiconductor layer 41 are formed is covered with the gate insulating layer L0 over the entire area. As shown in FIGS. 4 and 6, on the surface of the gate insulating layer L0, the selection line 11, the initialization line 12, the intermediate conductor 51, and the first data line portion 131 are formed from the same layer by a conductive material. Is done.

  The selection line 11 extends in the X direction over the plurality of unit elements P and overlaps the element portion 411 of the semiconductor layer 41. A region facing the selection line 11 across the gate insulating layer L0 in the element portion 411 is a channel region of the selection transistor Ts1. The initialization line 12 extends in the X direction across the plurality of unit elements P and overlaps the second element portion 312 of the semiconductor layer 31. Of each of the portion 312a and the portion 312c of the second element portion 312, the region facing the initialization line 12 with the gate insulating layer L0 interposed therebetween is the channel region of the initialization transistor Tint. That is, the initialization transistor Tint in this embodiment is a dual gate transistor.

  The intermediate conductor 51 is a portion formed in the gap between the selection line 11 and the initialization line 12 and includes an electrode E1, a gate electrode 511, and a connecting portion 513. The electrode E <b> 1 is a substantially rectangular portion that overlaps with the electrode E <b> 2 of the semiconductor layer 41 when viewed from the direction perpendicular to the substrate 10. As shown in FIGS. 4 and 6, the electrode C1 and the electrode E2 face each other with the gate insulating layer L0 (dielectric) interposed therebetween, so that the capacitive element C1 shown in FIG.

  As shown in FIG. 6, the connecting portion 513 extends from the upper right portion of the electrode E1 to the negative side in the Y direction. The gate electrode 511 is a portion that extends from the connecting portion 513 to the negative side in the X direction with a gap from the electrode E1, and the first element portion 311 extends over substantially the entire width (dimension in the X direction) of the first element portion 311. overlap. As shown in FIG. 4, the region facing the gate electrode 511 across the gate insulating layer L0 in the first element portion 311 is a channel region 311c of the drive transistor Tdr. Further, a region of the first element portion 311 closer to the electrode E2 than the channel region 311c (that is, a region located in the gap between the gate electrode 511 and the electrode E1 as viewed from the direction perpendicular to the substrate 10 as shown in FIG. 6). It is a source region 311s, and the opposite region is a drain region 311d.

  The first data line part 131 is a part constituting the data line 13 of FIG. The first data line portion 131 is disposed in a negative region in the X direction when viewed from the intermediate conductor 51, and extends in the Y direction at a gap between the selection line 11 and the initialization line 12.

  FIG. 8 is a plan view showing a state where the four unit elements P in the stage of FIG. 6 are arranged in the X direction and the Y direction. As shown in FIGS. 6 and 8, in each unit element P, the second element portion 312 (initializing transistor Tint) formed at the peripheral edge on the negative side in the Y direction is located on the positive side in the X direction, and is in the Y direction. The element part 411 (selection transistor Ts1) formed on the peripheral edge on the positive side is located on the negative side in the X direction.

  Now, a configuration is assumed in which the second element unit 312 and the element unit 411 are arranged on the same side in the X direction in each unit element P. In this configuration, in order to ensure the separation between the second element portion 312 and the element portion 411, a gap region (a region corresponding to the region B in FIG. 8) between the unit elements P adjacent in the Y direction is sufficiently provided. Since it is necessary to ensure, there is a problem that high definition of the unit element P is hindered. On the other hand, in the present embodiment, since the positions of the second element portion 312 and the element portion 411 in the X direction are different, the second element portion 312 and the element portion 411 are in the region B as shown in FIG. Are alternately arranged along the X direction. According to this configuration, even when the region B is narrowed, the second element portion 312 and the element portion 411 are surely separated from each other, so that there is an advantage that the high definition of the unit element P is easy.

  As shown in FIG. 4, the surface of the gate insulating layer L0 on which the intermediate conductor 51 and the first data line portion 131 are formed is covered with the first insulating layer L1 over the entire area. As shown in FIGS. 4 and 7, the connecting portion 61, the conducting portion 71, the power supply line 15, and the second data line portion 132 are formed from the same layer on the surface of the first insulating layer L1 by a conductive material. The

  When viewed from the direction perpendicular to the substrate 10 as shown in FIG. 7, the connecting portion 61 overlaps the portion 312 c of the second element portion 312 and the intermediate conductor 51 (gate electrode 511). The connecting portion 61 is electrically connected to the portion 312c through the contact hole Ha1 that penetrates the first insulating layer L1 and the gate insulating layer L0, and is intermediately conductive through the contact hole Ha2 that penetrates the first insulating layer L1. Conducted to the body 51. That is, the gate electrode 511 of the drive transistor Tdr (the electrode E1 of the capacitor C1) and the channel region of the initialization transistor Tint are electrically connected via the connection portion 61. Note that the contact hole in this specification is a portion for electrically connecting an element located on one side of the insulating layer and an element located on the other side of the insulating layer, more specifically. A portion (hole or hole) that penetrates the insulating layer in the thickness direction. The planar shape of the contact hole is arbitrary.

  The conducting portion 71 is a portion that is interposed between the driving transistor Tdr and the light emitting element E and electrically connects them. When viewed from a direction perpendicular to the substrate 10, the conducting portion 71 sandwiches the driving transistor Tdr and the capacitive element C1. Are arranged in the opposite region (that is, the negative region in the Y direction with respect to the drive transistor Tdr). The conductive portion 71 of this embodiment has a shape in which a portion 711 that overlaps the drain region 311d of the first element portion 311 and a portion 712 that is located on the opposite side of the portion 711 across the initialization line 12 are continuous.

  A plurality of contact holes Ha3 penetrating the first insulating layer L1 and the gate insulating layer L0 are formed in a region overlapping the drain region 311d in the first insulating layer L1 when viewed from the direction perpendicular to the substrate 10. These contact holes Ha3 are arranged in the X direction (that is, the channel width direction of the driving transistor Tdr) in which the gate electrode 511 extends. The portion 711 of the conducting portion 71 is conducted to the drain region 311d through each contact hole Ha3.

  Next, FIG. 9 is a plan view showing a state in which the unit elements P in the stage of FIG. 7 are arranged. As shown in FIGS. 7 and 9, the power supply line 15 is a strip-like wiring extending in the X direction along the arrangement of the plurality of unit elements P. The power supply line 15 overlaps both the capacitor element C1 of each unit element P and the source region 311s of the drive transistor Tdr when viewed from the direction perpendicular to the substrate 10. As shown in FIGS. 6 and 7, a plurality of contact holes Ha4 penetrating the first insulating layer L1 and the gate insulating layer L0 are formed in a region overlapping the source region 311s in the first insulating layer L1. These contact holes Ha4 are arranged in the X direction in which the gate electrode 511 extends. The power supply line 15 is electrically connected to the source region 311s of the drive transistor Tdr through each contact hole Ha4. The power supply line 15 of the present embodiment overlaps the selection transistor Ts1 (element unit 411), the selection line 11, the initialization transistor Tint (second element unit 312), and the initialization line 12 when viewed from the direction perpendicular to the substrate 10. The shape and dimensions are selected so that they do not match. In the present embodiment, the power supply line 15 extends in parallel with the selection line 11 and the initialization line 12.

  The second data line portion 132 is a portion that constitutes the data line 13 together with the first data line portion 131, and extends in the Y direction at the gap between the power supply lines 15 as shown in FIGS. As shown in FIG. 7, the positive end (lower) end 132a in the Y direction of the second data line portion 132 is the negative end (upper) end 131a (in the Y direction of the first data line portion 131). (See FIG. 6). The end portion 132a and the end portion 131a are electrically connected to each other through a contact hole Ha5 that penetrates the first insulating layer L1. Similarly, the negative end 132b in the Y direction of the second data line portion 132 and the positive end 131b in the Y direction of the first data line portion 131 (see FIG. 6) are connected via the contact hole Ha6. Conducts with each other. As described above, the first data line portions 131 and the second data line portions 132 that are alternately arranged along the Y direction are electrically connected to each other, whereby the data lines 13 extending linearly in the Y direction. Is configured.

  As shown in FIG. 7, a branch portion 134 is connected to the second data line portion 132. The branch part 134 is a part located on the opposite side of the capacitive element C1 across the selection line 11, extends in the X direction, and overlaps the element part 411 of the semiconductor layer 41. The branch portion 134 is electrically connected to the element portion 411 through a contact hole Ha7 that penetrates the first insulating layer L1 and the gate insulating layer L0. That is, the selection transistor Ts1 and the data line 13 are electrically connected via the branch part 134.

  As shown in FIG. 4, the surface of the first insulating layer L1 on which the second data line portion 132 and the power supply line 15 are formed is covered with the second insulating layer L2 over the entire area. As shown in FIGS. 3 and 4, the first electrode 21 is formed on the surface of the second insulating layer L2. The first electrode 21 is formed of, for example, a light-reflective conductive material such as a metal such as aluminum or silver or an alloy containing these metals as a main component, and via a contact hole Ha8 penetrating the second insulating layer L2. It conducts to the portion 712 of the conducting portion 71. In other words, the drain region 311 d of the drive transistor Tdr and the first electrode 21 of the light emitting element E are electrically connected via the conducting portion 71. Further, when the second insulating layer L2 is formed of an acrylic or polyimide resin, in the process of curing the resin by heat, heat is uniformly transmitted to the resin through the power supply line having high thermal conductivity. Melt. Thereby, the surface of the second insulating layer L2 is further flattened, so that the unevenness of the first electrode 21 formed thereon can be reduced.

  As shown in FIGS. 3 and 4, the first electrode 21 overlaps with the conductive portion 71, the drive transistor Tdr, and the capacitive element C <b> 1 when viewed from the direction perpendicular to the substrate 10. As shown in FIGS. 6 and 7, since the area occupied by the drive transistor Tdr and the capacitive element C1 is large in the region where the unit element P is arranged, according to the present embodiment, the first electrode 21 is formed over a wide range. It is possible. Therefore, in the present embodiment, a high aperture ratio is realized as compared with the configuration in which the first electrode 21 is formed so as to overlap only the selection transistor Tsl and the initialization transistor Tint. In addition, a step reflecting the outer shape of these transistors may appear on the surface of the region of the second insulating layer L2 that overlaps with the selection transistor Tsl and the initialization transistor Tint. In the present embodiment, since the first electrode 21 is formed on a wide flat surface that overlaps the drive transistor Tdr and the capacitive element C1 in the second insulating layer L2, the first electrode caused by the step of the second insulating layer L2 is formed. Thus, it is possible to effectively prevent 21 defects (for example, disconnection) and the light emitting layer 23.

  Since the power supply line 15 overlaps the capacitive element C1 and the source region 311s of the driving transistor Tdr, as shown in FIGS. 4 and 7, the first electrode 21 and the source region 311s of the driving transistor Tdr (and further the capacitive element C1). ) Is interposed between the power line 15. According to this configuration, capacitive coupling between the first electrode 21 and the drive transistor Tdr is suppressed compared to a configuration in which the power supply line 15 is not interposed between the first electrode 21 and the drive transistor Tdr. Therefore, the influence of a change in potential on one of the first electrode 21 and the driving transistor Tdr on the other potential is reduced, and thereby, each light emitting element E can be accurately controlled. Further, since the power supply line 15 is formed so as to cover the drive transistor Tdr and the capacitor C1 in the region where the first electrode 21 is formed, the surface on which the first electrode 21 is formed can be planarized.

  Further, as shown in FIG. 3, the first electrode 21 overlaps the first data line portion 131 of the data line 13 when viewed from the direction perpendicular to the substrate 10. Since the power supply line 15 overlaps with the first data line portion 131, the power supply line 15 is interposed between the first electrode 21 and the first data line portion 131 as shown in FIGS. 3 and 7. According to this configuration, the first electrode 21 and the data line 13 (first data line portion 131) are compared with the configuration in which the power supply line 15 is not interposed between the first electrode 21 and the first data line portion 131. The capacitive coupling of is suppressed. Therefore, the influence of the change in the potential on one of the first electrode 21 and the data line 13 on the other potential is reduced, thereby enabling accurate control of each light emitting element E.

  A partition wall 25 is formed of an insulating material on the surface of the second insulating layer L2 on which the first electrode 21 is formed. The partition wall 25 is an insulating film body in which an opening 251 is formed for each unit element P in accordance with the first electrode 21, and serves to electrically insulate the adjacent first electrodes 21 (that is, the first electrodes). It plays a role of enabling individual control of the potential of 21).

  The light emitting layer 23 is continuously formed over the plurality of unit elements P so as to cover the entire area of the second insulating layer L2 where the partition walls 25 are formed. That is, the light emitting layer 23 includes a portion that enters the inside of the opening 251 and contacts the first electrode 21 (that is, a portion that actually emits light) and a portion that is located on the surface of the partition wall 25. In addition, since the 1st electrode 21 is formed separately for every light emitting element E, even if it says that the light emitting layer 23 continues over several light emitting elements E, the light quantity of the light emitting layer 23 is controlled separately for every light emitting element E. Is done. In addition, various functional layers (a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, a hole block layer, and an electron block layer) for promoting or increasing the efficiency of light emission by the light emitting layer 23 are light emitting layers. 23 may be laminated.

  11 is a cross-sectional view taken along line XI-XI in FIG. As shown in FIG. 11, each element (first insulating layer L1, power supply line 15, and second insulating layer L2) covering the first data line portion 131 of the data line 13 has a film thickness of the first data line portion 131. A step that reflects Since the first electrode 21 is formed in a thin film on the surface of the second insulating layer L2 where such a step is formed, the portion of the first electrode 21 that overlaps the data line 13 is the first data line portion 131. The inclined surface 211 reflects the shape. According to this configuration, as indicated by an arrow L in FIG. 11, the light emitted from the light emitting layer 23 in the direction parallel to the substrate 10 is reflected by the inclined surface 211 and emitted to the opposite side (observation side) from the substrate 10. Can be made. Therefore, compared with the configuration in which the entire area of the first electrode 21 is a flat surface (that is, the configuration in which the emitted light in the direction parallel to the substrate 10 is not emitted from the light emitting layer 23 to the observation side), the emitted light from the light emitting layer 23. It is possible to improve the utilization efficiency.

  As shown in FIG. 4, the second electrode 22 is an electrode that is formed continuously over the plurality of unit elements P and covers the light emitting layer 23 and the partition walls 25. Therefore, the partition wall 25 electrically insulates the first electrode 21 and the second electrode 22 in the gap region between the light emitting elements E. In other words, the partition wall 25 defines a region where current flows between the first electrode 21 and the second electrode 22 (that is, a region that actually emits light). The second electrode 22 is formed of a light transmissive conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Therefore, the light emitted from the light emitting layer 23 to the opposite side of the substrate 10 and the light emitted from the light emitting layer 23 toward the substrate 10 and reflected by the surface of the first electrode 21 are transmitted through the second electrode 22 and emitted. . That is, the light emitting device D of this embodiment is a top emission type.

  By the way, since many of the light-transmitting conductive materials have high resistivity, the second electrode 22 formed of this kind of material has a high resistance, and the voltage drop in the surface becomes remarkable. Accordingly, the potential supplied to each light emitting element E differs depending on the position in the plane of the second electrode 22, and as a result, unevenness in the amount of light (luminance or gradation unevenness) in the light emitting region may occur. .

  In order to suppress this variation in the amount of light, in the present embodiment, an auxiliary wiring 27 for assisting the conductivity of the second electrode 22 is formed. The auxiliary wiring 27 is a wiring that is formed of a conductive material having a lower resistivity than the second electrode 22 and is electrically connected to the second electrode 22. In FIG. 3, only the outer shape of the auxiliary wiring 27 is shown by a two-dot chain line for convenience. FIG. 10 is a plan view showing a state in which the four unit elements P in the stage of FIG. 3 are arranged in the X direction and the Y direction. As shown in FIG. 3 and FIG. 10, the auxiliary wiring 27 in the present embodiment is a unit adjacent to the Y direction on the surface (part other than the opening 251) of the partition wall 25 when viewed from the direction perpendicular to the substrate 10. It extends in the X direction in the gap region of the element P, and does not overlap the first electrode 21. Further, as shown in FIG. 4, the auxiliary wiring 27 is interposed between the light emitting layer 23 and the second electrode 22 and is in contact with both. According to the above configuration, most of the current flows through the low-resistance auxiliary wiring 27, so that the voltage drop in the second electrode 22 is suppressed. Therefore, the potential supplied to each unit element P is made uniform, and as a result, unevenness in the amount of light of each light emitting element E due to the voltage drop can be effectively suppressed. Although many of the low-resistance conductive materials such as the auxiliary wiring 27 have a light shielding property (or light reflectivity), the auxiliary wiring 27 is formed so as not to overlap the first electrode 21 in this embodiment. Therefore, the aperture ratio is not lowered by the formation of the auxiliary wiring 27.

  Further, since the auxiliary wiring 27 does not overlap with the driving transistor Tdr and the capacitive element C1, capacitive coupling between them is suppressed. Therefore, the influence of the fluctuation of one potential of the auxiliary wiring 27, the driving transistor Tdr, and the capacitive element C1 on the other is suppressed, and as a result, the luminance of the light emitting element E can be controlled with high accuracy. On the other hand, when viewed from the direction perpendicular to the substrate 10, the auxiliary wiring 27 overlaps with the selection transistor Tsl and the initialization transistor Tint as shown in FIGS. 3 and 10. However, in the present embodiment, the partition wall 25 is interposed between the auxiliary wiring 27 and the selection transistor Tsl or the initialization transistor Tint (and also the selection line 11 and the initialization line 12). Compared with the configuration that does not, the capacitive coupling between the auxiliary wiring 27 and the selection transistor Tsl or the initialization transistor Tint is suppressed. Therefore, according to the present embodiment, although the auxiliary wiring 27 overlaps the selection transistor Tsl and the initialization transistor Tint, the waveform of the selection signal Sa and the initialization signal Sb is suppressed and the selection transistor Tsl and the initial value are suppressed. The transistor Tint can be operated at high speed. In the above description, the auxiliary wiring 27 is interposed between the light emitting layer 23 and the second electrode 22. However, the auxiliary wiring 27 is formed on the surface of the second electrode (the surface opposite to the light emitting layer 23). It may be formed.

<B: Second Embodiment>
Next, a specific configuration of the unit element P according to the second embodiment of the present invention will be described. The electrical configuration of the light emitting device D in the present embodiment is the same as that in the first embodiment (FIGS. 1 and 2). In each form shown below, the same code | symbol is attached | subjected to the element which is common in 1st Embodiment, and the description is abbreviate | omitted suitably.

  FIG. 12 is a plan view showing the configuration of the unit element P in the present embodiment, and FIGS. 13 to 15 are plan views showing states on the surface of the substrate 10 at each stage where the unit element P of FIG. 12 is formed. FIG. As shown in FIG. 13, the semiconductor layer 32, the semiconductor layer 42, and the semiconductor layer 45 are formed from the same layer on the surface of the substrate 10 by a semiconductor material. The semiconductor layer 32 is a substantially rectangular portion constituting the drive transistor Tdr. The semiconductor layer 42 is a portion formed on the positive side in the Y direction when viewed from the semiconductor layer 32, and includes a substantially rectangular electrode E2 and an element portion 421 extending in the X direction from the lower left portion of the electrode E2. The element portion 421 is a portion that functions as a semiconductor layer of the selection transistor Tsl. The semiconductor layer 45 is a part constituting the initialization transistor Tint, and extends in the X direction in a region opposite to the semiconductor layer 32 with the semiconductor layer 42 interposed therebetween.

  As shown in FIG. 14, the first data line 131, the selection line 11, the initialization line 12, the intermediate conductor 52, and the first relay wiring portion 171 are formed on the surface of the gate insulating layer L0 that covers the above elements. Are formed from the same layer. The first data line part 131 is a part constituting the data line 13 as in the first embodiment, and extends in the Y direction in the positive region in the X direction when viewed from the intermediate conductor 52.

  The initialization line 12 includes a first gate electrode 121 and a second gate electrode 122 that branch from the portion extending in the X direction to the negative side in the Y direction and overlap the semiconductor layer 45. A portion of the semiconductor layer 45 that overlaps each of the first gate electrode 121 and the second gate electrode 122 is a channel region of the initialization transistor Tint. Similarly, the selection line 11 includes a first gate electrode 111 and a second gate electrode 112 that branch from the portion extending in the X direction to the negative side in the Y direction and overlap the element portion 421 of the semiconductor layer 42. The first gate electrode 111 and the second gate electrode 112 are adjacent to each other in the X direction with a space therebetween. A portion of the element portion 421 that overlaps each of the first gate electrode 111 and the second gate electrode 112 across the gate insulating layer L0 is a channel region of the selection transistor Tsl. As described above, the selection transistor Tsl and the initialization transistor Tint of this embodiment are thin film transistors having a dual gate structure.

  The intermediate conductor 52 includes an electrode E1 that forms the capacitive element C1 facing the electrode E2, a connecting portion 525 that extends from the upper left portion of the electrode E1 to the negative side in the Y direction, and an X direction from the connecting portion 525. It includes a gate electrode 521 that extends to the positive side and overlaps the semiconductor layer 32, and a connection portion 523 that protrudes from the approximate center in the X direction to the positive side in the Y direction of the electrode E1. The gate electrode 521 extends in the X direction so as to overlap the semiconductor layer 32 over the entire dimension of the semiconductor layer 32 in the X direction. As shown in FIG. 14, in the semiconductor layer 32, a region facing the gate electrode 521 across the gate insulating layer L0 is a channel region 32c of the drive transistor Tdr. A region on the electrode E1 side with the channel region 32c interposed therebetween is a source region 32s, and a region on the opposite side is a drain region 32d.

  The first relay wiring portion 171 is a portion constituting a wiring (hereinafter referred to as “relay wiring”) for electrically connecting the initialization transistor Tint and the drain region 32d of the driving transistor Tdr. As a result, it extends in the Y direction in the negative region in the X direction. That is, the intermediate conductor 52 in the present embodiment is disposed in the gap between the first data line part 131 and the first relay wiring part 171.

  As shown in FIG. 15, on the surface of the first insulating layer L1 covering each of the above elements, the second data line portion 132, the connecting portion 62, and the second relay wiring are formed on the surface of the first insulating layer L1. The part 172, the conduction part 72, and the power supply line 15 are formed from the same layer.

  Similar to the first embodiment, the second data line part 132 is a wiring that forms the data line 13 together with the first data line part 131. That is, the second data line portion 132 extends in the Y direction from the end portion 132a that conducts to the upper end portion 131a (see FIG. 14) of the first data line portion 131 through the contact hole Hb1. It reaches the end 132b. The end portion 132b is electrically connected to the end portion 131b (see FIG. 14) below the drawing surface of the first data line portion 131 through the contact hole Hb2. In addition, the second data line portion 132 of this embodiment is electrically connected to the end portion of the element portion 421 through a contact hole Hb3 penetrating the first insulating layer L1 and the gate insulating layer L0. That is, the data line 13 and the selection transistor Tsl are electrically connected via the contact hole Hb3.

  As shown in FIGS. 14 and 15, the connecting portion 62 extends in the Y direction so as to overlap the connecting portion 523 of the intermediate conductor 52 and the positive end portion 451 in the X direction of the semiconductor layer 45. The connection part 62 is electrically connected to the connection part 523 (electrode E1 or gate electrode 521) through a contact hole Hb4 that penetrates the first insulating layer L1, and penetrates the first insulating layer L1 and the gate insulating layer L0. It conducts to the end 451 of the semiconductor layer 45 through the contact hole Hb5. That is, the electrode E1 of the capacitive element C1 (and the gate electrode 521 of the drive transistor Tdr) and the initialization transistor Tint are electrically connected via the connection portion 62.

  The conducting portion 72 is conducted to the first relay wiring portion 171 through a contact hole Hb6 that penetrates the first insulating layer L1. The conduction portion 72 is a portion that electrically connects the drain electrode of the drive transistor Tdr and the first electrode 21 of the light emitting element E, similarly to the conduction portion 71 of the first embodiment. A plurality (two in this case) of contact holes Hb7 penetrating the first insulating layer L1 and the gate insulating layer L0 are formed in a region overlapping the drain region 32d in the first insulating layer L1. These contact holes Hb7 are arranged in the X direction (that is, the channel width direction of the driving transistor Tdr) in which the gate electrode 521 extends. The conducting portion 72 is conducted to the drain region 32d through each contact hole Hb7.

  As shown in FIGS. 14 and 15, the second relay wiring portion 172 is a wiring extending in the Y direction so as to overlap the negative end portion 452 in the X direction and the first relay wiring portion 171 in the semiconductor layer 45. It is. The second relay wiring portion 172 is electrically connected to the end 452 through a contact hole Hb8 that passes through the first insulating layer L1 and the gate insulating layer L0, and via a contact hole Hb9 that passes through the first insulating layer L1. To the first relay wiring portion 171. As described above, the initialization transistor Tint and the drain region 32d (and the conduction portion 72) of the drive transistor Tdr are connected via the relay wiring 17 including the first relay wiring portion 171 and the second relay wiring portion 172. Are electrically connected.

  FIG. 16 is a plan view showing a state in which four unit elements P in the stage of FIG. 15 are arranged. As shown in FIGS. 15 and 16, in the first insulating layer L1, a plurality of regions penetrating the first insulating layer L1 and the gate insulating layer L0 are overlapped with the source region 32s (see FIG. 14) of the semiconductor layer 32. (Here, three) contact holes Hb10 are formed. These contact holes Hb10 are arranged in the X direction in which the gate electrode 521 extends. The power supply line 15 is electrically connected to the source region 32s through each contact hole Hb10.

  The power supply line 15 in the present embodiment has a shape (lattice) in which a first portion 151 extending in the X direction across a plurality of unit elements P and a second portion 152 extending in the Y direction across the plurality of unit elements P intersect. Wiring). The first portion 151 extends in the X direction so as to pass through the gap region between the second data line portions 132 and the gap region between the second relay wiring portion 172 and the conduction portion 72 (portion 721). Therefore, when viewed from the direction perpendicular to the substrate 10 as shown in FIGS. 15 and 16, the first portion 151 overlaps the first data line portion 131, the first relay wiring portion 171 and the capacitive element C1. Further, the second portion 152 passes in the Y direction so as to pass through the region of the gap between the conducting portion 72 (portion 722) and the second data line portion 132 and the region of the gap between the connecting portion 62 and the second data line portion 132. Extend to. On the other hand, as shown in FIGS. 15 and 16, the power supply line 15 does not overlap the selection transistor Tsl or the initialization transistor Tint.

  The first electrode 21 in FIG. 12 is formed on the surface of the second insulating layer L2 that covers the above elements, and is electrically connected to the conduction portion 72 (and further to the drain region 32d of the driving transistor Tdr) through the contact hole Hb11. Connected to. FIG. 17 is a plan view showing a state in which the unit elements P at the stage of FIG. 12 are arranged. As shown in FIGS. 12 and 17, the first electrode 21 is formed so as to overlap the drive transistor Tdr, the capacitive element C1, and the data line 13 (first data line portion 131). In this configuration, the power supply line 15 is interposed between the first electrode 21 and the drive transistor Tdr and the capacitive element C1 and between the first electrode 21 and the first data line portion 131 of the data line 13. Therefore, also in the present embodiment, the capacitive coupling between the first electrode 21 and each element is suppressed as in the first embodiment.

  Further, when viewed from the direction perpendicular to the substrate 10 as shown in FIG. 12, the first electrode 21 of the present embodiment overlaps with the selection transistor Tsl and the initialization transistor Tint (and also the selection line 11 and the initialization line 12). Absent. On the other hand, as shown in FIGS. 12 and 17, the auxiliary wiring 27 is formed in the gap region between the first electrodes 21 on the surface of the partition wall 25 formed on the surface of the second insulating layer L <b> 2. It extends in the X direction so as to overlap Tsl and the initialization transistor Tint (and also the selection line 11 and the initialization line 12). Since the partition wall 25 is interposed between the auxiliary wiring 27 and the selection transistor Tsl or initialization transistor Tint, capacitive coupling between the auxiliary wiring 27 and the selection transistor Tsl or initialization transistor Tint is the same as in the first embodiment. Is suppressed. In addition, the aspect of the 2nd electrode 22 is the same as that of 1st Embodiment.

  By the way, from the viewpoint of reducing the resistance of the power supply line 15 and the first electrode 21 and improving the aperture ratio, the power supply overlaps not only the drive transistor Tdr and the capacitive element C1, but also the selection transistor Tsl and the initialization transistor Tint. A configuration in which the line 15 and the first electrode 21 are formed (hereinafter referred to as “proportional”) is also employed. However, in this comparison, the selection transistor Tsl and the selection line 11 are capacitively coupled to the power supply line 15 and the first electrode 21 (that is, a capacitance is parasitic between both), and the selection signal Sa is caused by this capacitance. In some cases, the waveform becomes dull. Similarly, the capacitance associated between the initialization transistor Tint and the initialization line 12 and the power supply line 15 and the first electrode 21 can cause the waveform of the initialization signal Sb to become dull. Therefore, in contrast, for example, there is a problem that switching of the selection transistor Tsl and the initialization transistor Tint is delayed.

  On the other hand, in the present embodiment, the power supply line 15 and the first electrode 21 are formed so as not to overlap the selection transistor Tsl, the selection line 11, and the initialization transistor Tint or the initialization line 12. 15 and the parasitic capacitance between the first electrode 21 and other elements are reduced as compared with the proportionality. Therefore, according to the present embodiment, it is possible to operate the selection transistor Tsl and the initialization transistor Tint at high speed while suppressing the dullness of the waveform of the selection signal Sa and the initialization signal Sb.

<C: Third Embodiment>
Next, a specific configuration of the light emitting device D according to the third embodiment of the present invention will be described.
In each of the above embodiments, the configuration in which all the unit elements P are arranged on the surface of the substrate 10 in the same manner is illustrated. On the other hand, in the present embodiment, the mode (layout) of one unit element P is different from the mode of the unit element P adjacent thereto. The configuration of one unit element P in the present embodiment is the same as that in the second embodiment. Therefore, description of the specific configuration of each unit element P will be omitted as appropriate.

  In FIG. 18, nine unit elements P in a stage where the first data line portion 131, the selection line 11, and the initialization line 12 are formed on the surface of the gate insulating layer L0 are arranged in the X direction and the Y direction. It is a top view which shows a mode. 18 and later-described FIG. 19 and FIG. 20 illustrate unit elements P for three columns belonging to each row from the (i−1) th row to the (i + 1) th row. The i-th row is an odd-numbered row, and the (i−1) -th row and the (i + 1) -th row are even-numbered rows. As shown in the figure, in the present embodiment, in each unit element P in the odd-numbered row (i-th row) and each unit element P in the even-numbered row ((i-1) th row and (i + 1) th row). The arrangement in the Y direction of each element constituting each is reversed.

  In each of the unit elements P in the even-numbered rows (the (i−1) th row and the (i + 1) th row), positive in the Y direction as viewed from the drive transistor Tdr (and the capacitive element C1 located on the positive side in the Y direction). The selection transistor Tsl and the selection line 11 are arranged in the region on the side, and the initialization transistor Tint and the initialization line 12 are arranged in the region on the positive side in the Y direction when viewed from the selection line 11. On the other hand, in each unit element P in the odd-numbered row (i-th row), the selection transistor is located in the negative side region in the Y direction as viewed from the drive transistor Tdr (and the capacitive element C1 located on the negative side in the Y direction). Tsl and the selection line 11 are arranged, and an initialization transistor Tint and an initialization line 12 are arranged in a negative region in the Y direction when viewed from the selection line 11. Accordingly, as shown in FIG. 18, the gap between each unit element P in the even-numbered row ((i-1) th row) and each unit element P in the odd-numbered row (i-th row) adjacent to the positive side in the Y direction. There are two pairs of selection lines 11 and initialization lines 12 corresponding to each, whereas each unit element P in the odd-numbered row (i-th row) and the even-numbered row (the first row) adjacent to the positive side in the Y direction. Neither the selection line 11 nor the initialization line 12 exists in the gap between each unit element P in (i + 1) row).

  The first data line portion 131 formed from the same layer as the selection line 11 and the initialization line 12 among the data lines 13 includes each unit element P in the odd-numbered row (i-th row) and its Y as shown in FIG. It is formed continuously in a straight line over the unit elements P in even-numbered rows ((i + 1) th row) adjacent to the positive side in the direction. In other words, each first data line portion 131 is connected to the selection line 11 and the initialization line 12 of the even-numbered row ((i-1) th row) and the odd-numbered row (i-th row) adjacent to the positive side in the Y direction. The selection line 11 and the initialization line 12 are divided in the Y direction.

  Next, FIG. 19 is a plan view showing a state of each unit element P in a stage where each element (second data line portion 132 or power supply line 15) is formed on the surface of the first insulating layer L1. As shown in the figure, the second data line section 132 includes the selection lines 11 in the even-numbered rows (i-th row) and the odd-numbered rows (i-th row) located on the positive side in the Y direction. The data lines 13 are configured by connecting the first data line portions 131 that are formed so as to intersect the initialization line 12 and that are adjacent to each other in the Y direction. As shown in FIG. 19, the second data line portion 132 extends in the Y direction adjacent to the second portion 152 of the power supply line 15 formed from the same layer.

  On the other hand, since the first data line portion 131 is continuous over the odd-numbered rows (i-th row) and the even-numbered rows ((i + 1) -th row) adjacent to the positive side in the Y direction, the second data is inserted in the gap between these rows. The line part 132 is not formed. Therefore, in the present embodiment, the second portion 152 of the power supply line 15 is widened by the amount that the second data line portion 132 is not formed. That is, the width dimension Wa of the second portion 152 extending across the odd-numbered row (i-th row) and the even-numbered row ((i + 1) -th row) adjacent to the positive side in the Y direction is the even-numbered row (i-th (i−)). 1) The width dimension Wb of the second portion 152 extending across the row) and the odd-numbered row (i-th row) adjacent to the positive side in the Y direction is larger (Wa> Wb).

  FIG. 20 is a plan view showing a state in which each element (the first electrode 21 and the auxiliary wiring 27) is formed on the surface of the second insulating layer L2. As shown in the figure, the auxiliary wiring 27 formed on the surface of the partition wall 25 includes the first electrodes 21 in the even-numbered rows ((i-1) th row) and the odd-numbered rows adjacent to the positive side in the Y direction. It extends in the X direction in the gap with each first electrode 21 in the (i-th row) and overlaps the selection line 11 and the initialization line 12. On the other hand, each first electrode 21 in the odd-numbered row (i-th row) and each first electrode 21 in the even-numbered row ((i + 1) -th row) adjacent to the positive side in the Y direction are arranged close to each other, The auxiliary wiring 27 is not formed in the gap between the two. That is, in the second embodiment, the configuration in which one auxiliary wiring 27 is formed for each row of the unit elements P is exemplified. However, in this embodiment, one auxiliary wiring 27 is provided for every two rows of the unit elements P. A wiring 27 is formed.

  As described above, according to the present embodiment, the total number of locations (contact holes Hb1, Hb2) where the first data line portion 131 and the second data line portion 132 are conducted is compared with that of the second embodiment. Can be reduced to about half. Therefore, there is an advantage that the possibility of the disconnection of the data line 13 (the conduction failure between the first data line part 131 and the second data line part 132) can be reduced. Further, since the line width of the second portion 152 of the power supply line 15 is increased at a location where the second data line portion 132 is not necessary, the resistance of the power supply line 15 is reduced as compared with the second embodiment. Can do. Furthermore, since the auxiliary wiring 27 is formed wide so as to overlap the selection lines 11 and the initialization lines 12 for two rows, the dimensional accuracy required for the auxiliary wiring 27 is lower than that of the second embodiment. Therefore, the auxiliary wiring 27 can be easily formed by an inexpensive technique such as vapor deposition through a mask.

<D: Fourth Embodiment>
<D-1: Electrical configuration of light emitting device>
Next, a light emitting device according to a fourth embodiment of the invention will be described. FIG. 21 is a circuit diagram showing an electrical configuration of one unit element P in the present embodiment. As shown in the figure, in this unit element P, the capacitive element C1 and the initialization transistor Tint (initialization line 12) in each of the above forms are not formed, and the gate electrode of the drive transistor Tdr and the data line 13 are not connected. The electrical connection is controlled by the selection transistor Tsl. In addition, the capacitive element C2 is interposed between the gate electrode and the source electrode (power supply line 15) of the driving transistor Tdr.

  In this configuration, when the selection transistor Tsl is turned on, the data potential Vdata corresponding to the gradation designated for the light emitting element E is supplied from the data line 13 to the gate electrode of the drive transistor Tdr via the selection transistor Tsl. . At this time, charges corresponding to the data potential Vdata are accumulated in the capacitor C2, so that the gate potential Vg of the drive transistor Tdr is maintained at the data potential Vdata even when the selection transistor Tsl is turned off. Therefore, a current corresponding to the gate potential Vg of the driving transistor Tdr (current corresponding to the data potential Vdata) is continuously supplied to the light emitting element E. By supplying this current, the light emitting element E emits light with a luminance corresponding to the data potential Vdata.

<D-2: Structure of unit element P>
Next, a specific structure of the unit element P according to the present embodiment will be described. FIG. 22 is a plan view showing a configuration of one unit element P, and FIGS. 23 to 25 are plan views showing states on the surface of the substrate 10 at each stage where the unit element P is formed. 23 to 25, the region A where the first electrode 21 shown in FIG. 22 is formed is also shown by a two-dot chain line.

  As shown in FIG. 23, a semiconductor layer 34 and a semiconductor layer 44 are formed from the same layer on the surface of the substrate 10 by a semiconductor material. The semiconductor layer 34 is a substantially rectangular portion constituting the driving transistor Tdr and the capacitive element C2. The semiconductor layer 44 extends in the X direction in a region on the positive side in the Y direction when viewed from the semiconductor layer 34.

  As shown in FIG. 24, on the surface of the gate insulating layer L0 covering the semiconductor layer 34 and the semiconductor layer 44, the selection line 11, the first data line portion 131, and the intermediate conductor 54 are formed from the same layer. . The selection line 11 has two gate electrodes 114 that branch from the portion extending in the X direction to the negative side in the Y direction and overlap the semiconductor layer 44. A portion where each gate electrode 114 and the semiconductor layer 44 face each other with the gate insulating layer L0 interposed therebetween functions as a selection transistor Tsl having a dual gate structure. The first data line portion 131 is a portion constituting the data line 13 in FIG. 21, and is arranged in the Y direction in the gap region (region on the negative side in the X direction as viewed from the intermediate conductor 54) of the selection line 11 in each row. Extend.

  The intermediate conductor 54 has a substantially rectangular electrode part F, a connecting part 545 extending from the upper left part of the electrode part F to the negative side in the Y direction, and extending from the connecting part 545 to the positive side in the X direction. A gate electrode 541 that overlaps the semiconductor layer 34. A portion where the electrode portion F and the semiconductor layer 34 face each other with the gate insulating layer L0 interposed therebetween functions as the capacitor C2. In addition, a region of the semiconductor layer 34 that faces the gate electrode 541 with the gate insulating layer L0 interposed therebetween is a channel region 34c of the driving transistor Tdr. Further, in the semiconductor layer 34, a region on the electrode part F side with the channel region 34c interposed therebetween is a source region 34s, and a region on the opposite side is a drain region 34d.

  On the surface of the first insulating layer L1 covering the above elements, as shown in FIG. 25, the second data line portion 132, the connection portion 64, the conduction portion 74, and the power supply line 15 are formed from the same layer. . The second data line part 132 is a wiring that constitutes the data line 13 together with the first data line part 131, and is electrically connected to the first data line part 131 of each row through the contact hole Hc1, and on the negative side in the Y direction. Is electrically connected to the first data line portion 131 in the adjacent row through the contact hole Hc2. The second data line portion 132 is electrically connected to the semiconductor layer 44 through a contact hole Hc3 that penetrates the first insulating layer L1 and the gate insulating layer L0.

  The connection part 64 is a part for electrically connecting the selection transistor Tsl and the capacitive element C2. In other words, the connection portion 64 is electrically connected to the electrode portion F of the intermediate conductor 54 through the contact hole Hc4 that penetrates the first insulating layer L1, and is a contact hole that penetrates the first insulating layer L1 and the gate insulating layer L0. It conducts to the semiconductor layer 44 through Hc5. The conduction portion 74 is a portion that electrically connects the drive transistor Tdr and the light emitting element E, and is a drain region of the semiconductor layer 34 via a plurality of contact holes Hc6 arranged in the X direction along the gate electrode 541. Conducted to 34d.

  FIG. 26 is a plan view showing a state in which the four unit elements P at the stage of FIG. 25 are arranged. As shown in FIGS. 25 and 26, the power supply line 15 of the present embodiment extends in the X direction in the region of the gap between the second data line portions 132 adjacent in the Y direction. The power supply line 15 is electrically connected to the source region 34s of the semiconductor layer 34 through a plurality of contact holes Hc7 penetrating the first insulating layer L1 and the gate insulating layer L0.

  The first electrode 21 of FIG. 22 is formed on the surface of the second insulating layer L2 covering the above elements and is electrically connected to the conductive portion 74 through the contact hole Hc8. FIG. 27 is a plan view showing a state in which four unit elements P in the stage of FIG. 22 are arranged. As shown in FIGS. 22 and 27, the first electrode 21 is formed so as to overlap the drive transistor Tdr, the capacitive element C2, and the data line 13. In this configuration, since the power supply line 15 is interposed between the first electrode 21 and the drive transistor Tdr and the data line 13, the capacitive coupling between the first electrode 21 and each element is the same as in the first embodiment. Is suppressed. Further, since the first electrode 21 does not overlap the selection transistor Tsl, capacitive coupling between the first electrode 21 and the selection transistor Tsl can be suppressed. The contact holes Hc1, Hc8, Hc6 are arranged in a straight line in the X direction. The contact holes Hc2 and Hc4 are arranged in a straight line in the X direction. The semiconductor layer 44 constituting the selection transistor Tsl extends in the X direction. Therefore, the power supply line 15 can be extended widely in the X direction.

  On the other hand, as shown in FIGS. 22 and 27, the auxiliary wiring 27 is formed in the region of the gap between the first electrodes 21 on the surface of the partition wall 25 formed on the surface of the second insulating layer L2, and is selected transistor. It extends in the X direction so as to overlap with Tsl and the selection line 11. Thus, since the partition wall 25 is interposed between the auxiliary wiring 27 and the selection transistor Tsl, capacitive coupling between the auxiliary wiring 27 and the selection transistor Tsl is suppressed as in the first embodiment. In addition, the aspect of the 2nd electrode 22 is the same as that of 1st Embodiment.

<E: Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described. In the present embodiment, the mode (layout) of one unit element P is different from the mode of each unit element P adjacent in the X and Y directions. The structure of each unit element P is the same as that of the fourth embodiment. Therefore, description of the specific configuration of each unit element P will be omitted as appropriate.

  FIG. 28 is a plan view showing a state in which a plurality of unit elements P at the stage where the first data line portion 131, the selection line 11, and the intermediate conductor 54 are formed from the same layer are arranged in the X direction and the Y direction. is there. The i-th row in the figure is an odd-numbered row, and the (i-1) -th row and the (i + 1) -th row are even-numbered rows.

  In the configuration of FIG. 28, as in the third embodiment, the arrangement of the elements constituting the plurality of unit elements P in the Y direction is an odd row (i-th row) and an even-numbered row ((i-1) -th row). The layout is reversed with respect to the (i + 1) th line. That is, in the unit element P belonging to the odd row (i-th row), the selection transistor Tsl and the selection line 11 are arranged on the positive side in the Y direction when viewed from the drive transistor Tdr. On the other hand, in each unit element P belonging to the even-numbered rows (the (i−1) th row and the (i + 1) th row), the selection transistor Tsl and the selection line 11 are arranged on the negative side in the Y direction as viewed from the drive transistor Tdr. Is done. The first data line portion 131 is continuous over the unit elements P in the even-numbered rows ((i−1) -th row) and the unit elements P in the odd-numbered rows (i-th row) located on the positive side in the Y direction. It is formed into a shape.

  Further, in the present embodiment, the layout of the elements constituting the unit element P in the X direction is reversed between the jth column and the (j + 1) th column adjacent to the X direction. That is, each unit element P belonging to the j-th column belongs to the (j + 1) -th column while the first data line portion 131 is arranged on the positive side in the X direction when viewed from the drive transistor Tdr and the capacitive element C2. In each unit element P, the first data line portion 131 is arranged on the negative side in the X direction when viewed from the drive transistor Tdr and the capacitive element C2. Therefore, the drive transistor Tdr and the capacitor C2 do not exist in the gap between the first data line portion 131 in the j-th column and the first data line portion 131 in the (j + 1) -th column.

  Next, FIG. 29 is a plan view showing a state in which each element (second data line part 132 and power supply line 15) is formed on the surface of the first insulating layer L1. As shown in the figure, the second data line unit 132 includes an odd-numbered row (i-th row) selection line 11 and an even-numbered row ((i + 1) -th row) selection line 11 adjacent to the positive side in the Y direction. Intersect. On the other hand, the second data line portion 132 is not formed in the gap between the even-numbered row ((i-1) th row) and the odd-numbered row (i-th row) adjacent to the positive side in the Y direction.

  The power supply line 15 according to the present embodiment includes a connecting portion 153 that connects these parts to each other in addition to the part extending in the X direction so as to overlap the capacitive element C2 of each unit element P. The connecting portion 153 is a gap between the even-numbered row (i-th row) and the odd-numbered row (i-th row) adjacent to the positive side in the Y direction, and each of the j-th column and the (j + 1) -th column. It is formed in a region overlapping with the first data line portion 131 (that is, a region where the second data line portion 132 is not formed). As described above, according to the present embodiment, the area of the power supply line 15 is increased by the amount of the connecting portion 153 as compared with the fourth embodiment. Variations in Vdd can be suppressed.

  FIG. 30 is a plan view showing a state in which each element (the first electrode 21 and the auxiliary wiring 27) is formed on the surface of the second insulating layer L2. As shown in the drawing, the auxiliary wiring 27 formed on the surface of the partition wall 25 includes the odd-numbered (i-th) first electrode 21 and the even-numbered (i + 1) -th row adjacent to the positive side in the Y direction. The row extends in the X direction with a gap from the first electrode 21 and overlaps the selection line 11 and the selection transistor Tsl belonging to each row. On the other hand, auxiliary wiring is provided in the gap between the even-numbered row ((i-1) th row) and the odd-numbered row (i-th row) adjacent to the positive side in the Y direction (that is, the region where the selection line 11 and the selection transistor Tsl are not formed). 27 is not formed. According to this embodiment, the same operations and effects as those of the third embodiment are achieved.

<F: Modification>
Various modifications are added to the above embodiment. An example of a specific modification is as follows. In addition, you may combine each following aspect suitably.

<F-1: Modification 1>
The electrical configuration of the unit element P in each of the above embodiments is appropriately changed. Specific embodiments of the unit element P applied to the present invention are exemplified below.

  (1) As shown in FIG. 31, a transistor (hereinafter referred to as “light emission control transistor”) Tcnt may be interposed between the drive transistor Tdr and the light emitting element E. The light emission control transistor Tcnt is a switching element that controls the electrical connection between the drain electrode of the drive transistor Tdr and the first electrode 21 of the light emitting element E according to the light emission control signal Sc supplied to the light emission control line 14. is there. When the light emission control transistor Tcnt changes to the on state, a current path from the power supply line 15 to the light emitting element E is formed and light emission of the light emitting element E is permitted. When the light emission control transistor Tcnt changes to the off state, this path is blocked. Accordingly, the light emission of the light emitting element E is prohibited. Therefore, according to this configuration, the period during which the light emitting element E actually emits light, such as when the light emitting control transistor Tcnt is turned on and the light emitting element E emits light only in the driving period excluding the initialization period and the writing period, is set. Can be accurately defined. Note that the light emission control transistor Tcnt may be added to the unit element P having the configuration illustrated in FIG.

  For the light emission control transistor Tcnt and the light emission control line 14 in the above configuration, the same mode as the selection transistor Tsl and the selection line 11 (or the initialization transistor Tint and the initialization line 12) exemplified in the above embodiments is employed. .

  (2) As shown in FIG. 32, the unit element P illustrated in FIG. 2 may be configured such that the capacitive element C2 is interposed between the gate electrode and the source electrode (power supply line 15) of the drive transistor Tdr. . According to this configuration, there is an advantage that the gate potential Vg of the driving transistor Tdr set in the writing period can be held in the capacitive element C2 in the driving period. However, in the configuration in which the area of the gate electrode (channel area) of the drive transistor Tdr is sufficiently secured, the gate potential Vg is held by the gate capacitance of the drive transistor Tdr. Therefore, the gate potential Vg can be held in the driving period even when the capacitor C2 is not disposed as in the first to third embodiments.

  As described above, the capacitive element connected to the gate electrode of the drive transistor Tdr may be the capacitive element C1 for setting the gate potential Vg of the drive transistor Tdr by capacitive coupling, or the gate of the drive transistor Tdr. It may be a capacitive element C2 for holding the potential of the electrode.

<F-2: Modification 2>
In the above embodiment, the configuration in which the first electrode 21 is formed of a light-reflective material has been illustrated. However, the light emitted from the light emitting layer 23 toward the substrate 10 is reflected by the reflective layer separate from the first electrode 21. It is good also as a structure reflected on the opposite side. In this configuration, a reflective layer is formed on the surface of the first insulating layer L1 with a light reflective material, and the first electrode 21 is formed so as to cover the reflective layer. The first electrode 21 is formed of a light-transmitting conductive material such as ITO or IZO. In the above embodiment, the configuration in which the second electrode 22 is formed of a light-transmitting material is exemplified. However, an electrode formed by sufficiently thinning a light-blocking or light-reflecting conductive material is the second electrode 22. The emitted light from the light emitting layer 23 can be transmitted also by the configuration.

  However, the present invention is also applied to a bottom emission type light emitting device in which light emitted from the light emitting layer 23 passes through the substrate 10 and is emitted. In this configuration, for example, the second electrode 22 is formed of a light-reflective conductive material, and the first electrode 21 is formed of a light-transmissive conductive material. The light emitted from the light emitting layer 23 toward the substrate 10 and the light emitted from the light emitting layer 23 to the opposite side of the substrate 10 and reflected by the surface of the second electrode 22 are the first electrode 21 and the substrate 10. Is transmitted through.

<F-3: Modification 3>
In the above configuration, the configuration in which the light emitting layer 23 is formed so as to be continuous over a plurality of unit elements P is illustrated, but the configuration in which the light emitting layer 23 is separated for each unit element P (for example, the light emitting layer 23 is the partition wall 25). The configuration formed only inside the opening of the above is also employed. Moreover, the partition 25 is abbreviate | omitted suitably.

<F-4: Modification 4>
In each of the above embodiments, the light emitting element E including the light emitting layer 23 made of at least an organic EL material is exemplified, but the light emitting element in the present invention is not limited to this. For example, various light emitting elements such as a light emitting element including a light emitting layer made of an inorganic EL material and an LED (Light Emitting Diode) element can be employed. The light-emitting element in the present invention may be an element that emits light by supplying electric energy (typically supplying current), and its specific structure and material are not limited.

<G: Application example>
Next, specific modes of electronic devices using the light-emitting device according to the present invention will be described. FIG. 33 is a perspective view showing the configuration of a mobile personal computer that employs the light-emitting device D according to any one of the embodiments described above as a display device. The personal computer 2000 includes a light emitting device D as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the light emitting device D uses the light emitting layer 23 of the organic EL material for the light emitting element E, it is possible to display an easy-to-see screen with a wide viewing angle.

  FIG. 34 shows a configuration of a mobile phone to which the light emitting device D according to each embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a light emitting device D as a display device. By operating the scroll button 3002, the screen displayed on the light emitting device D is scrolled.

  FIG. 35 shows a configuration of a personal digital assistant (PDA) to which the light emitting device D according to each embodiment is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a light emitting device D as a display device. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the light emitting device D.

  Electronic devices to which the light emitting device according to the present invention is applied include those shown in FIGS. 33 to 35, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic papers, calculators. , Word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like. Further, the use of the light emitting device according to the present invention is not limited to the display of images. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, a writing head that exposes a photosensitive member according to an image to be formed on a recording material such as paper is used. The light emitting device of the present invention can also be used.

  D ... light emitting device, P ... unit element, E ... light emitting element, 10 ... substrate, 11 ... select line, 12 ... initialization line, 13 ... data line, 14 ... light emission control line, 15 ... power supply line, 21 ... first Electrode, 22 ... second electrode, 23 ... light emitting layer, Tdr ... drive transistor, Tsl ... selection transistor, Tint ... initialization transistor, Tcnt ... light emission control transistor, C1, C2 ... capacitive element, E1, E2 ... electrode, L0 ... Gate insulating layer, L1 ... first insulating layer, L2 ... second insulating layer.

Claims (15)

A power supply line to which a predetermined potential is supplied;
A light emitting device in which a light emitting layer is interposed between the first electrode and the second electrode;
A drive transistor for controlling the amount of current supplied from the power supply line to the light emitting element;
The light-emitting device, wherein the power supply line includes a portion interposed between the first electrode and the driving transistor. A capacitive element electrically connected to the gate electrode of the driving transistor;
The light emitting device according to claim 1, wherein the first electrode overlaps the capacitor. A data line to which a data signal is supplied,
The drive transistor controls the amount of current according to the data signal,
The light-emitting device according to claim 1, wherein the power supply line includes a portion interposed between the first electrode and the data line. A data line to which a data signal is supplied;
4. The first electrode according to claim 1, wherein the first electrode is a light-reflective electrode formed on a surface of an insulating layer covering the data line, and an outer peripheral edge thereof overlaps with the data line. The light emitting device according to any one of the above. A selection transistor that is turned on or off in response to a selection signal;
The gate electrode of the driving transistor is set to a potential according to a data signal supplied from a data line through the selection transistor that is turned on,
5. The light emitting device according to claim 1, wherein the first electrode is formed so as not to overlap the selection transistor. 6. An initialization transistor that is turned on or off according to an initialization signal; and the gate electrode and the drain of the drive transistor are electrically connected via the initialization transistor that is turned on,
The light emitting device according to claim 1, wherein the first electrode is formed so as not to overlap the initialization transistor. A light emitting device in which a light emitting layer is interposed between the first electrode and the second electrode;
A drive transistor for controlling the amount of current supplied to the light emitting element;
A capacitive element electrically connected to the gate electrode of the driving transistor;
An auxiliary wiring formed of a material having a lower resistivity than the second electrode and conducting to the second electrode;
The light-emitting device, wherein the auxiliary wiring does not overlap the driving transistor and the capacitor. A selection transistor that is turned on or off in response to a selection signal; and
An insulating layer overlapping the selection transistor and having an opening formed therein;
A light emitting element in which the first electrode and the second electrode covering the insulating layer are opposed to each other with the light emitting layer sandwiched at least inside the opening;
A driving transistor that controls the amount of current supplied to the light emitting element in response to a data signal supplied from a data line via the selection transistor that is turned on;
A light emitting device comprising: an auxiliary wiring which is formed on a surface of the insulating layer with a material having a lower resistivity than the second electrode and is electrically connected to the second electrode.   The light emitting device according to claim 8, wherein the selection transistor overlaps with the auxiliary wiring. An initialization transistor that is turned on or off in response to an initialization signal;
An insulating layer overlapping the initialization transistor and having an opening formed therein;
A light emitting element in which the first electrode and the second electrode covering the insulating layer are opposed to each other with the light emitting layer sandwiched at least inside the opening;
A driving transistor that controls the amount of current supplied to the light-emitting element and electrically connects a gate electrode and a drain via the initialization transistor that is turned on;
A light emitting device comprising: an auxiliary wiring which is formed on a surface of the insulating layer with a material having a lower resistivity than the second electrode and is electrically connected to the second electrode.   The light emitting device according to claim 10, wherein the initialization transistor overlaps with the auxiliary wiring. A plurality of control lines extending in a first direction;
A data line extending in a second direction different from the first direction and intersecting the plurality of control lines;
A plurality of unit elements that are arranged at positions corresponding to the intersections of the plurality of control lines and the data lines and arranged in the second direction;
Each of the plurality of unit elements is
A light emitting device in which a light emitting layer is interposed between the first electrode and the second electrode;
A driving transistor that controls the amount of current supplied to the light emitting element by setting the potential of the gate electrode in accordance with a signal supplied to the data line;
Whether to supply a predetermined potential to the gate electrode of the driving transistor or whether to supply a current to the light emitting element is controlled according to a signal supplied to a control line corresponding to the unit element among the plurality of control lines. And a control transistor that
In the first unit element of the plurality of unit elements, the control transistor and the control line are located on one side in the second direction when viewed from the drive transistor,
Among the plurality of unit elements, a second unit element adjacent to the first unit element on one side in the second direction and a first unit element on the other side in the second direction. In each of the adjacent third unit elements, the control transistor and the control line are located on the other side in the second direction as viewed from the drive transistor,
The data lines are formed on a surface of a plurality of first data line portions formed in the same layer as the plurality of control lines and arranged in the second direction, and an insulating layer covering the plurality of control lines. A second data line portion that electrically connects each of the first data line portions,
The first data line unit is continuous over the first unit element and the third unit element, and the second data line unit includes the control line corresponding to the first unit element and the second unit element. The light emitting device crosses the control line corresponding to the unit element. A power supply line to which a predetermined potential is supplied;
The drive transistor controls the amount of current supplied from the feeder line to the light emitting element,
The feeder line is formed in the same layer as the second data line portion of the data line, and a portion of the first data line portion located in the gap between the first unit element and the third unit element is formed. The light emitting device according to claim 10, further comprising: An auxiliary wiring formed of a material having a lower resistivity than the second electrode and conducting to the second electrode;
The auxiliary wiring is formed to overlap the control transistor and the control line of the first unit element and the control transistor and the control line of the second unit element, and the first unit element and the control line 14. The light emitting device according to claim 12, wherein the light emitting device is not formed in a gap with the third unit element.   An electronic apparatus comprising the light emitting device according to claim 1.

Images