JP2012125433A - Light presentation system, and pachinko game machine including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light presentation system and a Pachinko game machine including the light presentation system allowing light to be recognized in a pseudo manner as if it is rotary light emission over the whole circumference of light emitting elements based on the selective light emission of each light emitting element even if the arranged region of each light emitting element is minimized by devising improvements on the light emitting form of a plurality of light emitting elements.SOLUTION: The light emitted from LEDs 1-5 is sequentially reflected by a curved reflecting plate 47b as the light emission points of maximum brightness sequentially with a period τ and then sequentially darkened with a period τ between the LEDs 1, 2, between the LEDs 2, 3, between the LEDs 3, 4 and between the LEDs 4, 5 and reflected as dark points by the curved reflecting plate 47b.

Description

  The present invention relates to a light effect device that performs an effect by light by blinking a plurality of light emitting elements, and a gaming machine such as a pachinko gaming machine including the light effect device.

  Conventionally, in a light effect system for a gaming machine, for example, a rotary light emitting device for a gaming machine described in Patent Document 1 below has been proposed. This rotary light emitting device includes a substantially circular substrate, five light emitter systems, and a conical reflector. Each of the five light emitter systems is composed of three light emitting diodes, and is radially arranged on the substantially semicircular portion of the substantially circular substrate at equal angular intervals in the semicircular direction. Yes. Further, the conical reflector is provided in an upside down conical shape above the substrate so as to face the central portion of the substantially circular substrate at the top.

JP 2002-239093 A

  By the way, in the rotary light emitting device configured as described above, when each light emitter system is caused to emit light sequentially and intermittently with each light emitting diode, the light from each light emitter system is a semi-conical portion of the conical reflector. The reflected light is sequentially reflected as reflected light, so that the reflected light is visually recognized as pseudo-rotating light such as rotation of a rotating lamp.

  However, when the light from each light emitter system is reflected as reflected light sequentially by the reflecting surface of the semi-conical part of the conical reflector, the reflected light is pseudo-rotated over the semi-conical part of the conical reflector. It is only visible as you do. In other words, the reflected light cannot be visually recognized so as to rotate over the entire circumference of the conical portion of the conical reflector, and the rotation extension by the light is still insufficient.

  Therefore, in order to deal with the above, the present invention has been devised for the light emission form of a plurality of light emitting elements, and based on the light emission control of each light emitting element even if the arrangement area of each light emitting element is minimized. An object of the present invention is to provide a light effect system that makes a pseudo-recognition like rotating light emission over the circumference and a pachinko gaming machine equipped with this light effect system.

In solving the above-mentioned problems, the light effect system according to the present invention is as described in claim 1.
A reflective surface portion (47b) that curves in a convex shape toward the player side, a disposition surface portion (47c) that extends forward of the reflective surface portion, and one end side to the other end in the bending direction of the reflective surface portion A light-emitting / reflecting unit (47) having a plurality of light-emitting elements (L1 to L5) disposed at intervals on the arrangement surface portion along the curved direction toward the side;
A plurality of light emitting elements emit light at a predetermined light emission intensity in a predetermined light emission mode from the light emitting element (L1) on the one end side of the reflecting surface portion to the light emitting element (L5) on the other end side,
After light emission at the predetermined light emission intensity of the light emitting element (L5) on the other end side, at least one light emitting element having a light emission intensity of zero among a plurality of light emitting elements is selected as both light emitting elements on the one end side and the other end side ( L1 and L5) are sequentially shifted from one light emitting element to the other light emitting element, and the at least one light emitting element having the light emission intensity of zero is transferred with the transition of the at least one light emitting element having the light emission intensity of zero. Each light emitting element that is separated from the light emitting element emits light with a light emission intensity that sequentially increases in a range lower than the predetermined light emission intensity.

  According to this, the plurality of light emitting elements are arranged on the player side at intervals on the arrangement surface portion along the bending direction of the reflecting surface portion from one end side to the other end side of the reflecting surface portion of the light emitting and reflecting unit. It is arranged in a convex curved shape.

  Then, under such an arrangement, a plurality of light emitting elements have a predetermined light emission mode from the light emitting element on one end side in the bending direction to the light emitting element on the other end side in the bending direction. Emits light with a predetermined emission intensity.

  After such light emission, at least one light emitting element having a light emission intensity of zero among a plurality of light emitting elements extends from one light emitting element to the other light emitting element on both the one end side and the other end side in the bending direction. In accordance with the transition of both the light emitting elements, the light emitting elements that emit light sequentially increase in a range lower than the predetermined light emission intensity for each of the light emitting elements separated from each other.

  In other words, each light emission of the plurality of light emitting elements sequentially moves as a light emitting point having a predetermined brightness from the light emitting element on one end side in the bending direction of the reflecting surface portion to the light emitting element on the other end side in the bending direction. While being reflected by the reflecting surface portion and visually recognized, the position of at least one light-emitting element having a light emission intensity of zero or the vicinity thereof among the plurality of light-emitting elements is each of the one end side and the other end side in the bending direction. From both light emitting elements of both light emitting elements to between the other light emitting elements, the light emitting elements are sequentially moved as a dark spot and visually recognized.

  As a result, even if a plurality of light emitting elements are arranged only on the front side of the reflective surface portion on the arrangement surface portion, the light on the entire front side and rear side of the reflective surface portion can be obtained by moving the light emitting point and the dark spot. It can be visually recognized as if it is performing.

  Here, along with the transition of each of the at least one light emitting element in which the light emission intensity is zero as described above, the light emitting elements that are separated from the at least one light emitting element are sequentially increased in a range lower than the predetermined light emission intensity. Since the light is emitted at the light emission intensity, the dark spot near or at the position of each at least one light-emitting element having a light emission intensity of zero is formed more satisfactorily. For this reason, in the light effect mentioned above, the effect by movement of a dark spot becomes still clearer.

Moreover, according to the description of claim 2, the present invention provides the light effect system according to claim 1,
Of each of the plurality of light emitting elements, each light emitting element is close to the light emitting element (L5) on the other end side among the light emitting elements adjacent to the one light emitting element in accordance with the light emission with the predetermined light emission intensity of the one light emitting element. The light emitting element emits light at a first low light emission intensity lower than the predetermined light emission intensity, and among the two adjacent light emitting elements, a light emitting element close to the light emitting element (L1) on the one end side is lower than the first low light emission intensity. Emits light at the second low emission intensity,
Both light emitting elements adjacent to the at least one light emitting element each time the at least one light emitting element transitions to zero light emission intensity after the light emitting element (L5) on the other end side emits light with the predetermined light emission intensity. At the same low light emission intensity, and the light emitting element (L5) on the other end side emits light so that the light emission intensity decreases sequentially from the second low light emission intensity, and the light emitting element on the one end side is Light emission is performed such that the light emission intensity is sequentially increased from the same light emission intensity in a range lower than the predetermined light emission intensity.

  According to this, since the brightness of each light emitting element adjacent to each of the plurality of light emitting elements that emit light with the predetermined brightness is made darker than the predetermined brightness, the plurality of light emitting elements that emit light with the predetermined brightness are provided. Since each light emitting point becomes clearer and light is emitted so that both light emitting elements adjacent to each at least one light emitting element having the light emission intensity of zero emit the same darkness, each of the above dark spots is further increased. Become clear. As a result, the function and effect of the invention of claim 1 can be further improved.

  Moreover, you may comprise the light production system which concerns on this invention as follows.

That is, the light effect system includes a reflective surface portion (47b) that curves in a convex shape toward the player, a disposition surface portion (47c) that extends forward of the reflective surface portion, and the reflective surface portion. A light-emitting / reflecting unit (47) having a plurality of light-emitting elements (L1 to L5) arranged at intervals on the arrangement surface portion along the bending direction from one end side to the other end side in the bending direction;
The first to fifth light emitting elements are sequentially applied from the first light emitting element which is the light emitting element (L1) on the one end side of the reflecting surface portion to the fifth light emitting element which is the light emitting element (L5) on the other end side. Emits light at a predetermined emission intensity,
After the fifth light emitting element (L5) emits light with the predetermined light emission intensity, at least one light emitting element having a light emission intensity of zero among the first to fifth light emitting elements is designated as the first and fifth light emitting elements (L1, L5). ) Are sequentially shifted from one light emitting element to the other light emitting element, and are separated from at least one light emitting element having the light emission intensity of zero with the transition of the at least one light emitting element having the light emission intensity of zero. You may make it light-emit by the light emission intensity which becomes high sequentially in the range lower than the said predetermined light emission intensity for both light emitting elements.

  Thus, by providing five light emitting elements, the effect of the invention of claim 1 can be achieved more specifically.

Here, the second light emitting element (L2) emits light with a first low light emission intensity lower than the predetermined light emission intensity in accordance with the light emission with the predetermined light emission intensity of the first light emitting element (L1),
Of each of the second to fourth light emitting elements (L2 to L4), the fifth light emitting element among the two adjacent light emitting elements of the one light emitting element is adapted to emit light with the predetermined light emission intensity of the one light emitting element. A light emitting element close to the element (L5) emits light at the first low light emission intensity and a light emitting element close to the first light emitting element (L1) among the two adjacent light emitting elements is a second lighter than the first low light emission intensity. Emits light at low emission intensity,
The fourth light emitting element (L4) emits light with the second low light emission intensity in accordance with the light emission with the predetermined light emission intensity of the fifth light emitting element,
After light emission with the predetermined light emission intensity of the fifth light emitting element (L5), at least one light emitting element transitioning to zero light emission intensity, both light emitting elements adjacent to the at least one light emitting element have the same low light emission. The fifth light emitting element (L5) emits light at an intensity, and the first light emitting element (L1) is emitted at the light emission intensity and gradually decreases from the second low light emission intensity. You may make it light-emit so that it may become high sequentially from the said same low light emission intensity in the range lower than predetermined light emission intensity.

  Furthermore, after the light emission with the predetermined light emission intensity of the fifth light emitting element (L5), when both the light emitting elements are the first and second light emitting elements every time the light emitting elements shift to zero. The fifth light emitting element (L5) emits light at the second low light emission intensity, and when both light emitting elements are the second and third light emitting elements (L2, L3), the fifth light emitting element (L5) is the second light emitting element (L5). Light is emitted at a third low emission intensity lower than the low emission intensity, and the fourth and first light emitting elements emit light at the same low emission intensity, and both the light emitting elements are the third and fourth light emitting elements. When the first light emitting element (L1) emits light with the third low light emission intensity, the fifth and second light emitting elements (L5, L2) emit light with the same low light emission intensity. 1st light emitting element (L1) when it is the 4th and 5th light emitting element (L4, L5) The second light emitting element (L2) and the third light emitting element (L3), respectively the second low emission intensity may be emitting at the third low emission intensity and the same low emission intensity.

  According to this, for each transition of both light emitting elements having a light emission intensity of zero, out of the respective light emitting elements excluding the both light emitting elements, the fifth and first light emitting elements are sequentially darkened toward the both light emitting elements. Thus, each dark spot becomes more specific.

Moreover, according to the description of claim 3, the light effect system according to the present invention is
A reflective surface portion (47b) that curves in a convex shape toward the player side, an arrangement surface portion (47c) that extends forward of the reflective surface portion, and one end side to the other end side of the reflective surface portion in the bending direction A light-emitting / reflecting unit (47) having first to m-th light-emitting elements (L1 to L5) disposed at intervals on the arrangement surface along the bending direction,
1st to mth light emission modes having a predetermined duty ratio required for light emission of the 1st to mth light emitting elements, and at least one of the first to mth light emitting elements having a duty ratio required for light emission of zero. Transition of the at least one light emitting element in which the light emitting element is sequentially shifted from one light emitting element to the other light emitting element of the light emitting elements (L1, L5) on the one end side and the other end side, and the duty ratio is zero. Accordingly, (m + 1) to (m + 2) having a low duty ratio that sequentially increases in a range lower than the predetermined duty ratio for each of the light emitting elements that are separated from the at least one light emitting element having the duty ratio of zero. Storage means for storing the light-emission mode of) as light-emission mode data;
The first to mth light emitting elements emit light based on the first to mth light emission modes of the light emission mode data, and then the (m + 1) to (m + 2) th of the light emission mode data. Drive control means (310-320, 322) that drives and controls the light emitting elements other than the at least one light emitting element to emit light in accordance with the transition of the at least one light emitting element that sets the duty ratio to zero based on the light emission mode. -340, 360-370, 390-400, 420-430, 450-460, 480-490, 510-520, 540-550, 200, 210-250, 210A-250A, 200A).

  As described above, the first to mth light emitting elements emit light based on the first to mth light emission modes of the light emission mode data, and then the (m + 1) th to mth of the light emission mode data. Based on the light emission mode of (m + 2), the drive control is performed so that the light emitting elements other than the at least one light emitting element emit light with the transition of the at least one light emitting element having the duty ratio of zero. The effect similar to that of the invention described in 1 can be achieved. In addition, in Claim 3, the code | symbol m is an integer.

According to a fourth aspect of the present invention, in the light effect system according to the third aspect,
In the light emission mode data, the first to mth light emission modes are respectively on the mth light emitting element side of both adjacent light emitting elements of the one light emitting element for each light emitting element of the first to mth light emitting elements. The duty ratio required for light emission of the light emitting element near the light emitting element is also the first low duty ratio lower than the predetermined duty ratio, and the duty required for light emission of the light emitting element near the first light emitting element among the two adjacent light emitting elements. The ratio is also set to be a second low duty ratio lower than the first low duty ratio,
Each of the (m + 1) to (m + 2) light emission modes has a duty required for light emission of both light emitting elements adjacent to the at least one light emitting element every time the at least one light emitting element has a duty ratio of zero. The duty ratio required for light emission of the mth light emitting element is also sequentially decreased from the second low duty ratio, and the duty ratio required for light emission of the first light emitting element is also equal to the predetermined duty ratio. Is set so as to increase the duty ratio sequentially from the lowest duty ratio in a lower range,
The drive control means emits light from the first to mth light emitting elements and the both adjacent light emitting elements based on the first to mth light emitting modes, and based on the (m + 1) th to (m + 2) light emitting modes. The drive control is performed so that the light emitting elements other than the at least one light emitting element emit light with the transition of the at least one light emitting element having the duty ratio of zero.

  Thereby, the duty ratio corresponds to the light emission intensity, so that the substantially same effect as that of the invention of claim 2 can be achieved.

  Moreover, according to the description of claim 5, the present invention provides a pachinko machine equipped with a game board, wherein the light effect system according to any one of claims 1 to 4 is the light effect device, It is provided in a part of the game board.

  Accordingly, it is possible to provide a pachinko gaming machine that can achieve the operational effects of the invention according to any one of claims 1 to 4.

  According to the present invention, even if a plurality of light emitting elements are disposed only on the front surface of the reflecting surface portion on the disposing surface portion, the entire front side and rear side of the reflecting surface portion can be obtained by moving the light emitting point and the dark spot. It can be visually recognized as if the light effect is performed over the period.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows a corresponding relationship with the specific means as described in embodiment mentioned later.

1 is a perspective view showing a first embodiment of a pachinko gaming machine to which the present invention is applied in a state where a front door is opened. FIG. 2 is a perspective view showing the light effect device shown in FIG. 1 in a state separated from a pachinko gaming machine. FIG. 3 is an enlarged perspective view of the light effect device of FIG. 2 as viewed from the front side. FIG. 3 is an enlarged perspective view of the light effect device of FIG. 2 as viewed from the rear side. FIG. 3 is an enlarged perspective view of the light effect device of FIG. 2 as viewed obliquely from below. FIG. 3 is an enlarged bottom view of the light effect device of FIG. 2. FIG. 3 is an enlarged exploded perspective view of the light effect device of FIG. 2. It is a top view of the light-emitting plate member of FIG. It is a perspective view which shows the state which assembled | attached the left sphere discharge cylinder member and the right sphere discharge cylinder member to the effect member of FIG. 7 in the state seen from the rear side of the effect member. It is a perspective view which shows the state which assembled | attached the left sphere discharge cylinder member and the right sphere discharge cylinder member with the production | presentation member of FIG. 7 in the state seen from diagonally lower back of the production member. It is a perspective view which shows the state which assembled | attached the left sphere discharge cylinder member and the right sphere discharge cylinder member with the production | presentation member of FIG. It is a longitudinal cross-sectional view of the principal part of the pachinko gaming machine of FIG. It is a block circuit diagram for controlling the light effect device in the first embodiment. It is a graph which shows the light emission mode data which specify the relationship between the light emission mode in the said 1st Embodiment, and the duty ratio required for light emission of each light emitting diode. It is a circuit diagram which shows the detailed circuit structure of the light emission drive circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a part of flowchart which shows the effect | action of the microcomputer which is an effect control circuit of FIG. It is a timing chart which shows the light emission mode of each light emitting diode in the said 1st Embodiment by the relationship between the arrangement position and phase angle of each said light emitting diode. It is a detailed circuit diagram which shows the principal part of 2nd Embodiment of this invention.

Hereinafter, each embodiment of the present invention will be described with reference to the drawings.
(First embodiment)
1 and 2 show a first embodiment of a light effect system according to the present invention applied to a pachinko gaming machine. The pachinko gaming machine is erected on an island in the pachinko hall, and the pachinko gaming machine includes a machine frame PF, a gaming machine main body B, and a front door FD. The front door FD includes a front frame FD1 and a window glass FD2 assembled in a hollow portion of the front frame FD1, and the front door FD is a gaming machine at the left edge of the front frame FD1. Via the left edge part of the main body B, it is supported by the left edge part of the machine frame PF so that opening and closing is possible in the front-back direction. In FIG. 1, the up, down, left, and right directions in the figure correspond to the up, down, left, and right directions when the pachinko gaming machine is viewed from the front, and the front and back directions in the figure correspond to the front and rear direction of the pachinko gaming machine.

  The gaming machine main body B includes a frame BF, and the frame BF is supported at the left edge thereof so as to be rotatable in the front-rear direction on the left edge of the machine frame PF. A ball launcher 10 is disposed at the lower right portion of the frame BF.

  In addition, the gaming machine main body B includes a gaming board 20, and the gaming board 20 is fitted in the hollow portion of the frame body BF.

  A guide rail 22 including an outer rail 22 a and an inner rail 22 b is attached to the board surface 21 of the game board 20. The guide rail 22 forms a game area 23 defined on the board surface 21 of the game board 20 on the inner peripheral side thereof. In addition, the guide rail 22 allows game balls to be launched from the ball launcher 10 by rotating an operation handle (not shown) provided at the lower right front of the front door FD to the outer rail 22a and the inner rail 22b. It guides in the game area 23 through.

  Although not shown in the present embodiment, the game board 20 has a center decoration member, an image display, a game nail group, a start chucker, an attacker, an electric tulip, a through gate, A windmill, a plurality of ordinary prize opening devices, etc. are provided. The winning of the game ball into the winning opening of the electric tulip is detected by an electric chew winning opening sensor (not shown). Further, when the detection by the electric chew winning mouth sensor is performed in this way, a main board circuit described later generates a specific gaming state that becomes a gaming state advantageous to the player based on the detection result of the electric chew winning mouth sensor. A lottery lottery on whether or not.

  As shown in FIG. 1 or FIG. 2, the light effect system includes a light effect device 40 and a light emission control device E for controlling the light effect device 40 to emit light.

  As shown in FIG. 1, the light effect device 40 is assembled to the game board 20 from the board surface 21 side along the lower end portion of the inner rail 22b and into the out port 30 (see FIG. 2). In the present embodiment, as shown in FIG. 2, the out port 30 is formed in the game board 20 so as to be opened immediately above the lower end portion of the inner rail 22 b.

  The light effect device 40 includes a casing 40a as shown in any of FIGS. The casing 40a includes an annular member 41, a translucent plate 42, an effect member 43, and a lid member 44. The casing 40a projects the effect member 43 forward from the board surface 21 of the game board 20. The annular member 41, the translucent plate 42 and the lid member 44 are assembled to the game board 20 so as to be fitted into the out port 30.

  As shown in FIG. 7, the annular member 41 is formed in an annular shape with an upper wall 41a, a left side wall 41b, a lower wall 41c, and a right side wall 41d. Here, a concave passage portion 41e is formed in a semi-cylindrical shape that is concave upward along the front-rear direction at the central portion in the left-right direction of the upper wall 41a. The concave passage portion 41e will be described later. Construct a midway path for the winning ball path.

  The translucent plate 42 includes a substantially square plate-like transparent plate portion 42a, and both attachment portions 42b and 42b that protrude in opposite directions from the center left and right ends of the transparent plate portion 42a. The translucent plate 42 is sandwiched between the annular member 41 and the effect member 43 by the transparent plate portion 42a by fastening a plurality of screws, and both mounting portions 42b and 42b of the translucent plate 42 are provided. Is screwed to the outer periphery of the out port 30 from the board surface 21 side of the game board 20.

  The effect member 43 includes a transparent effect wall 43a, an upper wall 43b extending rearward from the upper end of the effect wall 43a, a winning mouth 43c provided at the center in the left-right direction of the upper wall 43b, and an effect. Left and right both side walls 43d and 43e that extend rearward from the left and right upper end portions of the wall 43a and constitute a U-shaped wall together with the upper wall 43b, and left and right both-side out ball entry paths provided at the left and right lower ends of the effect wall 43a 43f and 43g.

  Here, the effect wall 43a transmits the light incident from behind, and optically exhibits the effect with the English letters “RUSH”. The winning opening 43c is fitted in the left and right central notch of the upper wall 43b at the bottom wall, and the winning opening 43c is opened in the left-right direction so as to open upward and rearward. It has a U-shaped cross section and an L-shaped cross section in the front-rear direction.

  Out of the left and right out ball entry paths 43f and 43g, the left out ball entry path 43f has a U-shaped cross section that opens in the upper and left and right directions together with the left lower end portion behind the left lower end portion of the effect wall 43a. It is comprised so that it may become a passage. The left out ball entry path 43f is located in front of the board surface 21 of the game board 20 and along the upper surface of the inner rail 22b. The left out ball entry path 43f is formed at the entrance 43h of the inner rail. It opens toward the left side part of 22b. Thereby, the game ball rolling downward along the upper surface of the left side portion of the inner rail 22b enters the left out ball entry path 43f from the entrance portion 43h.

  The right-out ball entry path 43g is configured to be a U-shaped passage that opens in the upper and left and right directions together with the right lower end at the rear side of the right lower end of the effect wall 43a. The right-out ball entry path 43g is located in front of the board surface 21 of the game board 20 and along the upper surface of the inner rail 22b. The right-out ball entry path 43g is connected to the inner rail at the entrance 43i. It opens toward the right side part of 22b. As a result, a game ball that rolls downward along the upper surface of the right portion of the inner rail 22b enters the right out ball entry path 43f from its entrance 43i.

  The winning opening 43c constitutes a winning opening of a start chucker (not shown) of the pachinko gaming machine at the upper opening thereof, and the winning of the game ball from the upper opening with respect to the winning opening 43c is made. At this time, a main board circuit (not shown) arranged on a main board (not shown) mounted on the game board 21 detects a winning of a game ball with respect to the winning opening of the start chucker by a start winning mouth sensor, Based on the detection result, a big win lottery is performed as to whether or not to generate a specific gaming state that is advantageous to the player. The start winning opening sensor is provided in the winning opening of the start chucker, and the starting winning opening sensor detects the winning of a game ball with respect to the winning opening of the start chucker.

  As shown in any of FIGS. 4 to 11, the light effect device 40 includes a left sphere discharge cylinder member 45 and a right sphere discharge cylinder member 46. As shown in FIG. 5, the left sphere discharge cylinder member 45 is assembled to the lower wall 41 c of the annular member 41 from the lower surface side. Specifically, the left sphere discharge cylinder member 45 is assembled to the lower wall 41c of the annular member 41 by fastening of each screw by both stays at an intermediate portion in the longitudinal direction of the outer peripheral wall (see FIG. 5). .

  The left sphere discharge cylinder member 45 is configured to extend from the inside of the left out sphere entry path 43f in a curved shape substantially horizontally to the rear right and then bend downward and extend. The member 45 extends into the out port 30 and opens at the extended end opening 45a. Thereby, the left sphere discharge cylinder member 45 introduces a game ball that rolls downward along the upper surface of the left side portion of the inner rail 22b, and the rear of the game board 20 from the extended end opening 45a through the out port 30. To discharge.

  The right sphere discharge cylinder member 46 is assembled from the rear surface side to the middle lower portion in the left-right direction of the effect wall 43a. Specifically, the right sphere discharge cylinder member 46 is assembled by fastening of each screw to the middle lower portion of the effect wall 43a by both stays (see FIG. 9).

  The right sphere discharge cylinder member 46 is configured to extend in a curved shape from the inside of the right-out sphere inlet path 43g to the rear and slightly downward, and the right sphere discharge cylinder member 46 has an extended end opening. At 46a, it extends into the outlet 30 and opens. As a result, the right sphere discharge cylinder member 46 introduces a game ball that rolls downward along the upper surface of the right portion of the inner rail 22b, and the rear of the game board 20 from the extended end opening 46a via the out port 30. To discharge. In the present embodiment, the extension opening 46 a of the right sphere discharge cylinder member 46, together with the extension opening 45 a of the left sphere discharge cylinder member 45, is located behind the extension opening 45 a in the out port 30. It is extended. In place of this, the extension opening 46a of the right sphere discharge cylinder member 46, together with the extension opening 45a of the left sphere discharge cylinder member 45, is located on the front side of the extension opening 45a. You may make it extend to.

  The lid member 44 is assembled by fastening its outer peripheral portion to the annular member 41 with a screw from behind.

  The light emitting / reflecting unit 47 is housed in the annular member 41 by being assembled to the front surface of the lid member 44, and the light emitting / reflecting unit 47 includes a light emitting plate member 47a and a curved reflecting plate 47b. (See FIG. 7).

  The light emitting plate member 47a includes a disposing plate portion 47c extending forward from an intermediate portion in the vertical direction of the curved reflecting plate 47b, and a predetermined number (for example, five) of light emitting diodes disposed on the disposing plate portion 47c. L1 to L5. Here, as shown in FIG. 8, the arrangement plate portion 47c has a semicircular shape, and the arrangement plate portion 47c is an intermediate portion in the vertical direction of the curved reflection plate 47b at its linear base portion. And is extended in a semicircular shape toward the front of the curved reflector 47b. For this reason, the said arrangement | positioning board part 47c is formed in the semicircle circular arc shape which protrudes ahead in the extension outer periphery part. In the present embodiment, the light emitting diode is hereinafter also referred to as an LED.

  Moreover, each LEDL1-L5 is arrange | positioned from LEDL1 to LEDL5 at the predetermined | prescribed angular space | interval (30 degree space | interval) along the circular arc direction in the extension outer periphery part of the arrangement | positioning board part 47c.

  Here, as shown in FIG. 8, the arrangement plate portion 47c has an angular position of 15 ° counterclockwise from the left base line a (hereinafter referred to as the left 15 ° position) and 15 ° clockwise from the right base line b. The LED L1 is disposed at the angular position of the left 15 ° position when it is partitioned at intervals of 37.5 ° in the arc direction between the angular position of ° (hereinafter referred to as the right 15 ° position).

  LED 2 is disposed at an angular position of 52.5 ° from the left base line a, LED 3 is disposed at an angular position of 90 ° from the left base line a, and LED 4 is 127.5 ° from the left base line a. The LED 5 is disposed at an angular position, and the LED 5 is disposed at an angular position of 165 ° from the left base line a (15 ° from the right base line b).

  Accordingly, each of the light emitting diodes L1 to L5 is driven to emit light as described later, and emits light radially upward. Each of the light emitting diodes L1 to L5 is a light emitting diode of the same specification.

  The curved reflecting plate 47b is divided into upper and lower side portions 47d and 47e with the arrangement plate portion 47c as a boundary, and the upper portion 47d functions as a reflecting portion (hereinafter also referred to as a reflecting portion 47d). Thus, the curved reflecting plate 47b reflects the light from each of the light emitting diodes L1 to L5 toward the light transmitting plate 42 at the reflecting portion 47d.

  Further, the light effect device 40 includes an upper winning ball path member 48 and a lower winning ball path member 49, and the upper winning ball path member 48 and the lower winning ball path member 49 are awarded to the effect member 43. Together with the mouth 43c and the concave passage portion 41e of the annular member 41, a winning ball passage is constituted. Accordingly, the upper winning ball passage member 48 extends downward along the center of the rear surface of the lid member 44 in the left-right direction so as to open from the rear to the concave passage portion 41e at the upper end opening. In the present embodiment, the winning prize opening device is configured by the winning ball passage and the starting prize opening sensor 50.

  The lower winning ball passage member 49 is communicated with the extended opening of the upper winning ball passage member 48 through the sensor casing 51 for the start winning mouth sensor 50 at the upper end opening thereof. It extends downward along the center of the rear surface in the left-right direction.

  The start winning opening sensor 50 is housed in the sensor casing 51 and detects a game ball falling from the inside of the upper winning ball passage member 48 into the lower winning ball passage member 49 as a winning ball. The sensor casing 51 extends rearward from the rear surface of the lid member 44. Further, the detected game ball is discharged from the lower end opening 49 a of the lower winning ball passage member 49 to the back side of the game board 20.

  As shown in FIG. 13, the light emission control device E includes an effect control circuit 100 connected to the above-described start winning port sensor 50 and an electric chew winning port sensor (hereinafter also referred to as an electric chew winning port sensor 60), and this effect control. A light emission driving circuit 200 connected between the circuit 100 and the light emitting diodes L1 to L5 is provided.

  The electric chew winning port sensor 60 is provided in the electric tulip winning port (electric chew winning port) provided in the game board 20 immediately below the start winning port device. A game ball that wins the above-mentioned electric chew winning port is detected, and a big hit lottery is performed together with the start winning port sensor 50.

  The effect control circuit 100 is composed of a microcomputer, and the effect control circuit 100 executes a computer program according to the flowcharts shown in FIGS. During this execution, the effect control circuit 100 performs each of the light emission drive circuits 200 by the light emission drive circuit 200 at the time of a big hit based on the detection output of the start winning port sensor 50 or the electric chew winning port sensor 60 and the light emission mode data (see FIG. 14). An effect process required for the light emission drive control of the LEDs L1 to L5 is performed. The computer program is stored in advance in the ROM of the effect control circuit 100 so as to be readable together with the light emission mode data.

  The light emission mode data is data representing the relationship between the first to ninth light emission modes and the duty ratios D1 to D5 of the LEDs L1 to L5, as shown in FIG. The ROM of the effect control circuit 100 is stored in a readable manner in advance. In the present embodiment, the duty ratios D1, D2, D3, D4 and D5 are duty ratios for driving the LEDs L1 to L5 to emit light. In the first embodiment, when a duty signal to be described later is formed by a high level period and a low level period subsequent thereto over the period, the duty ratio is (high level period / period). Specified.

  In the first to ninth light emission modes described above, as shown in FIG. 14, the light emission mode 1 includes the duty ratio D1 of LED L1, D1 = 100 (%), the duty ratio D2 of LEDL2, D2 = 50 (%), and the duty ratio of LED L3. It is specified by D3 = 0 (%), LEDL4 duty ratio D4 = 0 (%), and LEDL5 duty ratio D5 = 0 (%).

  The light emission mode 2 is specified by D1 = 20 (%), D2 = 100 (%), D3 = 50 (%) and D4 = D5 = 0 (%) as shown in FIG. , D1 = 0 (%), D2 = 20 (%), D3 = 100 (%), D4 = 50 (%) and D5 = 0 (%), and the light emission mode 4 is D1 = D2 = 0 (%), D3 = 20 (%), D4 = 100 (%) and D5 = 50 (%).

  As shown in FIG. 14, the light emission mode 5 is specified by D1 = D2 = D3 = 0 (%) D4 = 20 (%) and D5 = 100 (%), and the light emission mode 6 is D1 = D2 = 0. (%), D3 = 5 (%), D4 = 10 (%) and D5 = 20 (%), and the light emission mode 7 is D1 = 5 (%), D2 = D3 = 0 (%), D4 = 5 (%) and D5 = 10 (%) are specified, and the light emission mode 8 is D1 = 10 (%), D2 = 5 (%), D3 = D4 = 0 (%) and D5 = 5 ( The light emission mode 9 is specified with D1 = 20 (%), D2 = 10 (%), D3 = 5 (%), and D4 = D5 = 0 (%).

  As shown in FIG. 16, the light emission drive circuit 200 is configured with the switching circuits 210 to 250. The switching circuit 210 includes a power transistor 211, a bias resistor 212, a collector resistor 213, and a field effect transistor 214. Hereinafter, the field effect transistor is also referred to as an FET.

  The power transistor 211 is connected to the output port P1 of the effect control circuit 100 via the bias resistor 212 at the gate 211a, and the collector 211b of the power transistor 211 is connected to a DC power source (illustrated) via the collector resistor 213. Not connected to the positive terminal. Note that the emitter of the power transistor 211 is grounded.

  Thus, the power transistor 211 has its collector 211b applied with the positive DC voltage + Vc from the DC power source via the resistor 213, and has its gate 211a through the bias resistor 212 and the effect control circuit 100. When any one of the first to first to ninth duty signals (described later) corresponding to the duty ratio D1 required for the light emission drive of the LED L1 is input via the output port P1, the power transistor 211 is The switching operation is performed according to the level of any of the first to first to ninth duty signals to turn it on or off, thereby generating a low-level or high-level collector voltage.

  The FET 214 is composed of a MOS type P-channel field effect transistor, and the FET 214 is connected to the collector 211b of the power transistor 211 at its gate 214a. The source 214b of the FET 214 is connected to the positive power source of the DC power source. Connected to the side terminal. Further, the drain 214c of the FET 214 is grounded via the LED1.

  Thus, the FET 214 receives a low-level or high-level collector voltage from the collector 211b of the power transistor 211 at the gate 214a in a state where the DC voltage + Vc is applied from the DC power source at the source 214b. It is applied and switches to turn on or off.

  Therefore, a direct current corresponding to the direct current voltage + Vc flows from the direct current power source into the LED 1 when the FET 214 is turned on, and the inflow of the direct current into the LED 1 is blocked when the FET 214 is turned off. This means that the LED 1 emits light based on the inflow of the direct current and stops emitting light based on the interruption of the inflow of the direct current. Here, the light emission duration time of the LED 1 corresponds to a high level time (described later) of any of the first to first to ninth duty signals, and the light emission stop time of the LED 1 is the first to first time. This corresponds to the low level time (described later) of any one of the duty signals 1-9.

  The switching circuit 220 includes a power transistor 221, a bias resistor 222, a collector resistor 223, and an FET 224.

  The power transistor 221 is connected to the output port P2 of the effect control circuit 100 via the bias resistor 222 at the gate 221a, and the collector 221b of the power transistor 221 is connected to the positive polarity of the DC power source via the collector resistor 223. Connected to the side terminal. Note that the emitter of the power transistor 221 is grounded.

  Thus, the power transistor 221 has its collector controlled at the gate 221a through the bias resistor 222 in a state where a positive DC voltage + Vc is applied from the DC power source to the collector 221b through the resistor 223. When any one of 2-1 to 2-9 duty signals (to be described later) corresponding to the duty ratio D2 required for light emission driving of the LED L2 is input from the circuit 100 through the output port P2, the power transistor The switching operation 221 is turned on or off according to the level of any of the duty signals 2-1 to 2-9, and generates a low-level or high-level collector voltage.

  The FET 224 is composed of a MOS type P-channel field effect transistor, and the FET 224 is connected to the collector 221b of the power transistor 221 at the gate 224a, and the source 224b of the FET 224 is the positive side of the DC power supply. Connected to the terminal. The drain 224b of the FET 224 is grounded via the LED2.

  Thus, the FET 224 applies a low-level or high-level collector voltage from the collector 221b of the power transistor 221 at the gate 224a in a state where the DC voltage + Vc is applied from the DC power source at the source 214b. Then, the switching operation is performed to turn on or off. Therefore, a direct current corresponding to the direct current voltage + Vc flows from the direct current power source into the LED 2 when the FET 224 is turned on, and the inflow of the direct current into the LED 2 is interrupted when the FET 224 is turned off. This means that the LED 2 emits light based on the inflow of the direct current and stops emitting light based on the interruption of the inflow of the direct current. Here, the light emission continuation time of the LED 2 corresponds to a high level time (described later) of any of the 2-1 to 2-9 duty signals, and the light emission stop time of the LED 2 is 2-1 to the second. This corresponds to a low level time (described later) of any of the 2-9 duty signals.

  The switching circuit 230 includes a power transistor 231, a bias resistor 232, a collector resistor 233, and an FET 234.

  The power transistor 231 is connected to the output port P3 of the effect control circuit 100 via the bias resistor 232 at the gate 231a. The collector 231b of the power transistor 231 is connected to the positive power source of the DC power source via the collector resistor 233. Connected to the side terminal. The emitter of the power transistor 231 is grounded.

  Accordingly, the power transistor 231 is connected to the collector 231b from the effect control circuit 100 through the bias resistor 232 at the gate 231a in a state where the positive DC voltage + Vc is applied from the DC power source via the collector resistor 233. When any one of 3-1 to 3-9 duty signals (to be described later) corresponding to the duty ratio D3 required for light emission driving of the LED L3 is input via the output port P3, the power transistor 231 The switching operation is performed according to the level of any one of the duty signals of 3-1 to 3-9 to turn on or off to generate a low-level or high-level collector voltage.

  The FET 234 is composed of a MOS type P-channel field effect transistor, and the FET 234 is connected to the collector 231b of the power transistor 231 at the gate 234a. The source 234a of the FET 234 is connected to the positive side of the DC power supply. Connected to the terminal. The drain 234c of the FET 234 is grounded via the LED 3.

  Thus, the FET 234 applies a low-level or high-level collector voltage from the collector 231b of the power transistor 231 at the gate 234a in a state where the DC voltage + Vc is applied from the DC power source at the source 234a. Then, the switching operation is performed to turn on or off. Therefore, a DC current corresponding to the DC voltage + Vc flows from the DC power source into the LED 3 when the FET 234 is turned on, and the DC current flowing into the LED 3 is blocked when the FET 234 is turned off. This means that the LED 3 emits light based on the inflow of the DC current and stops emitting light based on the interruption of the inflow of the DC current. Here, the light emission continuation time of the LED 3 corresponds to a high level time (described later) of any of the 3-1 to 3-9 duty signals, and the light emission stop time of the LED 3 is 3-1 to 1st. This corresponds to the low level time (described later) of any of the duty signals 3-9.

  The switching circuit 240 includes a power transistor 241, a bias resistor 242, a collector resistor 243, and an FET 244.

  The power transistor 241 is connected to the output port P4 of the effect control circuit 100 via the bias resistor 242 at the gate 241a. The collector 241b of the power transistor 241 is connected to the positive polarity of the DC power source via the collector resistor 243. Connected to the side terminal. The emitter of the power transistor 241 is grounded.

  Accordingly, the power transistor 241 is applied from the effect control circuit 100 through the bias resistor 242 at the gate 241a in a state where the positive DC voltage + Vc is applied from the DC power source through the collector resistor 243 at the collector 241b. When any one of the 4-1 to 4-9 duty signals (described later) corresponding to the duty ratio D4 required for the light emission drive of the LED L4 is input via the output port P4, the power transistor 241 Switching operation is performed according to the level of any one of the 4-1 to 4-9 duty signals to turn it on or off, and a low-level or high-level collector voltage is generated.

  The FET 244 is composed of a MOS type P-channel field effect transistor, and the FET 244 is connected to the collector 241b of the power transistor 241 at its gate 244a, and the source 244b of the FET 244 is connected to the positive terminal of the DC power source. Connected to the side terminal. The drain 244c of the FET 244 is grounded via the LED 4.

  Thus, the FET 244 applies a low-level or high-level collector voltage from the collector 241b of the power transistor 241 at the gate 244a in a state where the DC voltage + Vc is applied from the DC power source at the source 244b. Then, the switching operation is performed to turn on or off. Therefore, a direct current corresponding to the direct current voltage + Vc flows from the direct current power source into the LED 4 when the FET 244 is turned on, and the inflow of the direct current into the LED 4 is interrupted when the FET 244 is turned off. This means that the LED 4 emits light based on the inflow of the DC current and stops emitting light based on the interruption of the inflow of the DC current. Here, the light emission continuation time of the LED 4 corresponds to a high level time (described later) of any of the 4-1 to 4-9 duty signals, and the light emission stop time of the LED 4 is 4-1 to 1st. This corresponds to the low level time (described later) of any of the duty signals 4-9.

  The switching circuit 250 includes a power transistor 251, a bias resistor 252, a collector resistor 253, and an FET 254.

  The power transistor 251 is connected to the output port P5 of the effect control circuit 100 via a bias resistor 252 at the gate 251a, and the collector 251b of the power transistor 251 is connected to the positive polarity of the DC power supply via the collector resistor 253. Connected to the side terminal.

  Thus, the power transistor 251 is connected to the collector 251b of the power transistor 251 through the collector resistor 253 and the positive DC voltage + Vc from the DC power source, and the gate 251a of the power transistor 251 is connected to the bias resistor 252. When any one of 5-1 to 5-9 duty signals (described later) corresponding to the duty ratio D5 required for the light emission drive of the LED L5 is input from the effect control circuit 100 through the output port P5, The power transistor 251 is switched on or off according to the level of any of the duty signals of the 5-1 to 5-9, and generates a low-level or high-level collector voltage.

  The FET 254 is composed of a MOS type P-channel field effect transistor, and the FET 254 is connected to the collector 251b of the power transistor 251 at the gate 254a. The source 254b of the FET 254 is the positive side of the DC power supply. Connected to the terminal. The drain 254c of the FET 254 is grounded via the LED 5.

  Thus, the FET 254 receives a low-level or high-level collector voltage from the collector 251b of the power transistor 251 at the gate 254a in a state where the DC voltage + Vc is applied from the DC power source at the source 254b. It is applied and switches to turn on or off. For this reason, a direct current corresponding to the direct current voltage + Vc flows from the direct current power source into the LED 5 when the FET 254 is turned on, and the inflow of the direct current into the LED 5 is interrupted when the FET 254 is turned off. This means that the LED 5 emits light based on the inflow of the direct current and stops emitting light based on the interruption of the inflow of the direct current. Here, the light emission continuation time of the LED 5 corresponds to a high level time (described later) of any of the 5-1 to 5-9 duty signals, and the light emission stop time of the LED 5 is 5-1 to This corresponds to a low level time (described later) of any of the duty signals 5-9. In the present embodiment, the periods of the first to fifth duty signals described above are both equal to τ.

  In the first embodiment configured as described above, when the effect control circuit 100 enters an operating state in which power is supplied from a power source (not shown), the effect control circuit 100 executes the computer program according to FIGS. Start running at the start step.

  In addition, the game balls that are sequentially guided through the space between the outer rail 22a and the inner rail 22b of the guide rail 22 into the game area 23 of the game board 20 of the pachinko gaming machine are moved downward along the board surface 21 of the game board 20. It rolls.

  Here, as shown in FIG. 12, when the game ball rolling in this way enters the winning opening 43c of the light effect device 40 from its upper opening, the game ball is recessed in the annular member 41. The portion 41e, the upper winning ball passage member 48 and the lower winning ball passage member 49 are discharged.

  In such a discharging process, when the game ball rolls from the inside of the upper prize ball passage member 48 to the inside of the lower prize ball passage member 49, the game ball is detected as a prize ball by the start prize port sensor 50. The

  In addition, when the game ball that rolls as described above wins the electric tulip winning opening of the electric tulip of the game board 20 instead of the winning opening 43c of the light effect device 40, the gaming ball is The winning prize sensor 60 detects the winning ball.

  Accordingly, in accordance with the detection of the game ball winning by the start winning mouth sensor 50 or the electric chew winning mouth sensor 60 as described above, a lottery lottery is performed under predetermined conditions in the main board circuit.

  Further, when the computer program proceeds to step 300 in accordance with the execution of the program of the computer program by the effect control circuit 100 described above, in step 300, it is determined whether or not the variable n = 1. Here, the variable n represents the number of the light emission mode shown in FIG. For example, n = 1 specifies the light emission mode 1.

  Therefore, at the present stage, if n = 1 is not satisfied, the determination in step 300 is NO, and in step 301, n = 1 is set. Accordingly, YES is determined in step 300.

  Then, in the first light emission mode data reading process in the next step 310, the light emission mode 1 in FIG. 14 is read from the ROM as the first light emission mode data. Here, the first light emitting mode data includes the LED 1 duty ratio D1 = 100 (%), the LED 2 duty ratio D2 = 50 (%), the LED 3 duty ratio D3 = 0 (%), and the LED 4 duty ratio D4 = It is specified by 0 (%) and the duty ratio D5 = 0 (%) of the LED 5 (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 311, D1 = 100 (%), D2 = 50 (%), D3 = 0 (%), D4 = 0 (%) of the first light emission mode data in step 310. ) And D5 = 0 (%) are formed as the first to 5-1th duty signals, respectively.

  Here, the 1-1st duty signal is formed at a high level over the period based on the duty ratio D1 = 100 (%), and the 2-1st duty signal is the duty ratio D1 = 50. Based on (%), the first half and the second half of the period are formed at a high level and a low level, respectively.

  The 3-1 duty signal is formed at a low level over the cycle based on the duty ratio D3 = 0 (%), and the 4-1 duty signal is the duty ratio D4 = 0 (%). The 5-1th duty signal is formed at a low level over the period based on the duty ratio D5 = 0 (%).

  As described above, when the duty signal forming process is performed in step 311, the duty signal output process in the next step 312 receives the first to 5-1 duty signals in step 312 from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-1 duty signal is at a high level over the period, the power transistor 211 is turned on over the period based on the 1-1 duty signal, and the FET 214 is turned on. The transistor is turned on based on a low-level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source to the LED L1 through the FET 214. Here, the inflow of the direct current continues over the period of the 1-1st duty signal. For this reason, LEDL1 emits light over the period of the 1-1st duty signal. This means that the light emission intensity of the LED L1 becomes the maximum value.

  In the switching circuit 220, since the 2-1 duty signal is at the high level and the low level in the first half and the second half of the cycle, the power transistor 221 is based on the 2-1 duty signal. It turns on over the first half of the cycle, and then turns off over the second half of the cycle based on the 2-1 duty signal.

  Therefore, the FET 224 is turned on based on the low-level collector voltage generated from the power transistor 221, and then turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a DC current based on the DC voltage + Vc from the DC power source flows into the LED L2 through the FET 224 while the FET 224 is on, and then stops flowing into the LED L2 while the FET 224 is off.

  Here, since the inflow of the direct current continues over the first half of the cycle of the 2-1 duty signal as described above, the LED L2 emits light over the first half of the cycle of the 2-1 duty signal. Thereafter, light emission is stopped during the second half of the cycle of the (2-1) duty signal. This means that the light emission intensity of LED L2 is one half of the maximum value of the light emission intensity of LED L1.

  In the switching circuit 230, since the 3-1 duty signal is at a low level over the period, the power transistor 231 is turned off over the period based on the 3-1 duty signal, and the FET 234 The transistor is turned off based on the high level collector voltage generated from the transistor 231. For this reason, a direct current based on the direct current voltage + Vc from the direct current power source is cut off from the FET 234. Accordingly, the LED L3 stops light emission over the period of the 3-1 duty signal. This means that the light emission intensity of the LED L3 becomes zero.

  In the switching circuit 240, since the 4-1th duty signal is at a low level over the period, the power transistor 241 is turned off over the period based on the 4-1 duty signal, and the FET 244 The transistor is turned off based on the high-level collector voltage generated from the transistor 241. For this reason, the DC current based on the DC voltage + Vc from the DC power supply is cut off from the FET 244. Accordingly, the LED L4 stops light emission over the period of the 4-1th duty signal. This means that the light emission intensity of the LED L4 becomes zero.

  In the switching circuit 250, since the 5-1 duty signal is at a low level over the period, the power transistor 251 is turned off over the period based on the 5-1 duty signal, and the FET 254 is turned on. The transistor is turned off based on the high-level collector voltage generated from the power transistor 251. For this reason, the DC current based on the DC voltage + Vc from the DC power supply is cut off from the FET 254. Accordingly, the LED L5 stops light emission over the period of the 5-1 duty signal. This means that the light emission intensity of the LED L5 becomes zero.

  Since the duty signals 1-1 to 5-1 described above are simultaneously output from the effect control circuit 100 in step 312, in the light emission drive circuit 200, the LEDs 1 to LED5 are simultaneously placed in the light emission drive state. For this reason, LED1 and LED2 emit light simultaneously in the light emission stop state of each LED3 to LED5, and continue to emit light during each period (same period) of the duty signals 1-1 and 2-1. (See light emission mode 1 in FIG. 25). However, since LED1 emits light with a light emission intensity twice that of LED2, the brightness of LED2 is half that of LED1.

  After the processing in step 312 described above, in the next step 313, the soft timer built in the microcomputer that is the effect control circuit 100 is reset and started to start timing.

  Thus, when the period τ elapses after the LEDs 1 to 5 are simultaneously in the light emission driving state, the determination in step 320 is YES. In addition, LED1 and LED2 stop light emission with progress of the period (tau).

  With the determination of YES in step 320, in the next step 330, it is determined whether or not the variable n = 2. At this stage, since n = 1 is maintained, NO is determined in step 330, and then, in step 331, the variable n = 2 is set. Accordingly, YES is determined in step 330.

  When the computer program proceeds to step 332 in FIG. 17 after this determination, the light emission mode 2 in FIG. 14 is read from the ROM as the second light emission mode data in the second light emission mode data reading process in step 332. Here, the second light emission mode data includes the duty ratio D1 = 20 (%), the duty ratio D2 = 100 (%), the duty ratio D3 = 50 (%), the duty ratio D4 = 0 (%), and the duty ratio D5. = 0 (%) (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 333, the duty ratio D1 = 20 (%), the duty ratio D2 = 100 (%), and the duty ratio D3 = 50 (%) of the second light emission mode data in step 332 , The duty ratio D4 = 0 (%) and the duty ratio D5 = 0 (%) are formed as the first to second to 5-2 duty signals, respectively.

  Here, the 1-2 duty signal is formed at a high level and a low level over the front 1/5 portion and the rear 4/5 portion of the cycle based on the duty ratio D1 = 20 (%), respectively. The 2-2 duty signal is formed at a high level over the period based on the duty ratio D1 = 100 (%).

  The 3-2 duty signal is formed at a high level and a low level over the first half and the second half of the cycle based on the duty ratio D3 = 50 (%), respectively. The signal is formed at a low level over the period based on the duty ratio D4 = 0 (%), and the duty signal 5-2 is based on the duty ratio D5 = 0 (%). It is formed at a low level.

  As described above, when the duty signal forming process is performed in step 333, in the next duty signal output process in step 334, the 2-1st to 5-2th duty signals in step 333 are transmitted from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-2 duty signal is at the high level and the low level over the front 1/5 portion and the rear 4/5 portion of the cycle, the power transistor 211 Based on the duty signal of 1-2, the signal is turned on for the first 1/5 portion of the cycle, and thereafter, turned off for the rear 4/5 portion of the cycle based on the first-second duty signal.

  For this reason, the FET 214 is turned on based on the low-level collector voltage generated from the power transistor 211, and thereafter is turned off based on the high-level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source passes through the FET 214 while the FET 214 is on and then flows into the LED L1, and then stops flowing into the LED L1 while the FET 214 is off.

  Here, the inflow of the direct current is limited to the front 1/5 portion of the period of the 1-2 duty signal. Therefore, the LED L1 is in the front 1/5 part of the period of the 1-2 duty signal. As long as it emits light. This means that the emission intensity of the LED L1 is reduced to 1/5 of its maximum value.

  In the switching circuit 220, since the 2-2nd duty signal is at a high level over the period, the power transistor 221 is turned on over the period based on the 2-2 duty signal.

  Therefore, the FET 224 is turned on based on the low level collector voltage generated from the power transistor 221. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source to the LED L2 through the FET 224. Here, since the inflow of the direct current continues over the period of the 2-2nd duty signal as described above, the LED L2 emits light over the period of the 2-2th duty signal. This means that the light emission intensity of the LED L2 is at the maximum value of the light emission intensity.

  In the switching circuit 230, since the 3-2 duty signal is at the low level and the high level over the first half and the second half of the period, the power transistor 231 is changed to the 3-2 duty signal. Based on the first half of the cycle, the signal is turned on, and based on the duty signal of the 3-2, the signal is turned off over the second half of the cycle.

  Therefore, the FET 234 is turned on based on the high level collector voltage generated from the power transistor 231, and then turned off based on the low level collector voltage generated from the power transistor 231. For this reason, a direct current based on the direct current voltage + Vc from the direct current power source flows into the LED 3 through the FET 234 while the FET 234 is turned on, and is then cut off from the LED 3 by the FET 234 while the FET 234 is turned off. Accordingly, the LED L3 emits light only in the first half of the period of the 3-2 duty signal. This means that the emission intensity of the LED L3 is reduced to ½ of its maximum value.

  In the switching circuit 240, since the 4-2 duty signal is at the low level over the period, the power transistor 241 is turned off over the period based on the 4-2 duty signal, and the FET 244 The transistor is turned off based on the high-level collector voltage generated from the transistor 241. For this reason, a direct current based on the direct current voltage + Vc from the direct current power source is blocked from the LED 4 by the FET 244. Accordingly, the LED L4 stops light emission over the period of the 4-2th duty signal. This means that the light emission intensity of the LED L4 decreases to zero.

  In the switching circuit 250, since the 5-2 duty signal is at a low level over the period, the power transistor 251 is turned off over the period based on the 5-2 duty signal, and the FET 254 is turned on. The transistor is turned off based on the high-level collector voltage generated from the power transistor 251. For this reason, a direct current based on the direct current voltage + Vc from the direct current power source is blocked from the LED 5 by the FET 254. Accordingly, the LED L5 stops light emission over the period of the 5-2th duty signal. This means that the light emission intensity of the LED L5 decreases to zero.

  Since the above-described duty signals 1-2 to 5-2 are simultaneously output from the effect control circuit 100 in step 334, in the light emission drive circuit 200, the LEDs 1 to LED5 are simultaneously placed in the light emission drive state. For this reason, LED1, LED2, and LED3 emit light simultaneously in the light emission stop state of LED4 and LED5. The LED 1 continuously emits light only during the front 1/5 portion of the period of the duty signal of 1-2, the LED 2 emits light continuously over the period of the duty signal of 2-2, and the LED 3 The light is continuously emitted only in the front part of the cycle of the duty signal 3-2 (see FIG. 25). However, since LED1 emits light with an emission intensity that is 1/5 that of LED2, the brightness of LED1 is 1/5 that of LED2, and LED3 emits light with an emission intensity that is 1/2 that of LED2. The brightness of LED3 is 1/2 of the brightness of LED2 and 2.5 times the brightness of LED1.

  After the processing in step 334 described above, in the next step 335, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are simultaneously in the light emission driving state, the determination in step 340 is YES. Note that the LED 2 stops emitting light as the period τ elapses.

  With the determination of YES in step 340, in the next step 350, it is determined whether or not the variable n = 3. At this stage, since n = 2 remains, it is determined NO in step 350, and then, in step 351, the variable n = 3 is set. Accordingly, YES is determined in step 350.

  When the computer program proceeds to step 360 in FIG. 18 after this determination, the light emission mode 3 in FIG. 14 is read from the ROM as the third light emission mode data in the third light emission mode data reading process in step 360. Here, the third light emission mode data includes the duty ratio D1 = 0 (%), the duty ratio D2 = 20 (%), the duty ratio D3 = 100 (%), the duty ratio D4 = 50 (%), and the duty ratio D5. = 0 (%) (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 361, the duty ratio D1 = 0 (%), the duty ratio D2 = 20 (%), and the duty ratio D3 = 100 (%) of the third light emission mode data in step 360. , Duty ratio D4 = 50 (%) and duty ratio D5 = 0 (%) are formed as the first to third to fifth-3 duty signals, respectively.

  Here, the first to third duty signals are formed at a high level over the cycle based on the duty ratio D1 = 0 (%), and the second to third duty signals are duty ratio D2 = 20 (%). The third and third duty signals have a duty ratio D3 = 100 (%), respectively, at a high level and a low level over the front 1/5 portion and the rear 4/5 portion of the cycle. Based on this, it is formed at a high level over the period.

  The 4-3rd duty signal is formed at a high level and a low level over the first half and the second half of the cycle based on the duty ratio D4 = 50 (%), respectively, and the 5-3 The duty signal is formed at a low level over the period based on the duty ratio D5 = 0 (%).

  As described above, when the duty signal forming process is performed in step 361, the 1st to 3rd to 3rd duty signals in step 362 are output from the effect control circuit 100 in the next duty signal output process in step 362. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the first to third duty signals are at a high level over the period, the power transistor 211 is turned off over the period based on the first to third duty signals. For this reason, the FET 214 is turned off based on the high-level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source is cut off from the LED L1 when the FET 214 is turned off.

  In the switching circuit 220, since the 2-3 duty signal is at the high level and the low level over the front 1/5 portion and the rear 4/5 portion of the cycle, the power transistor 221 Based on the duty signal of 2-3, it is turned on for the front 1/5 portion of the cycle, and thereafter, it is turned off for the rear 4/5 portion of the cycle based on the duty signal 3-3.

  For this reason, the FET 224 is turned on based on the low-level collector voltage generated from the power transistor 221, and then turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source passes through the FET 224 while the FET 224 is on and flows into the LED L2, and then stops flowing into the LED L2 while the FET 224 is off.

  Here, since the inflow of the direct current is limited to the front 1/5 portion of the period of the 2-3 duty signal, the LED L2 is in the front 1/5 part of the period of the 2-3 duty signal. As long as it emits light. This means that the light emission intensity of the LED L2 is reduced to 1/5 of its maximum value.

  In the switching circuit 230, since the first to third duty signals are at a high level over the period, the power transistor 231 is turned on over the period based on the first to third duty signals.

  For this reason, the FET 234 is turned on based on the low-level collector voltage generated from the power transistor 231. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source to the LED L3 through the FET 234. Here, since the inflow of the direct current continues over the period of the first to third duty signals as described above, the LED L3 emits light over the period of the first to third duty signals. This means that the light emission intensity of the LED L3 is at the maximum value of the light emission intensity.

  In the switching circuit 240, since the 4-3rd duty signal is at the low level and the high level over the first half and the second half of the period, the power transistor 241 changes to the 4-3 duty signal. Based on the first half of the cycle, the signal is turned on, and based on the fourth to third duty signal, the signal is turned off over the second half of the cycle.

  For this reason, the FET 244 is turned on based on the high level collector voltage generated from the power transistor 241, and then turned off based on the low level collector voltage generated from the power transistor 241. For this reason, a DC current based on the DC voltage + Vc from the DC power source flows into the LED 4 through the FET 244 while the FET 244 is on, and is then cut off from the LED 4 by the FET 244 while the FET 244 is off. Accordingly, the LED L4 emits light only in the first half of the period of the 4-3rd duty signal. This means that the emission intensity of the LED L4 is reduced to ½ of its maximum value.

  In the switching circuit 250, since the 5-3rd duty signal is at a low level over the period, the power transistor 251 is turned off over the period based on the 5-3 duty signal, and the FET 254 is turned on. The transistor is turned off based on the high-level collector voltage generated from the power transistor 251. For this reason, a direct current based on the direct current voltage + Vc from the direct current power source is blocked from the LED 5 by the FET 254. Therefore, LEDL5 stops light emission over the period of the 5-3rd duty signal. This means that the light emission intensity of the LED L5 decreases to zero.

  Since the above-described duty signals 1-3 to 5-3 are simultaneously output from the effect control circuit 100 in step 362, in the light emission drive circuit 200, the LEDs 1 to LED 5 are simultaneously placed in the light emission drive state. For this reason, LED2, LED3, and LED4 emit light simultaneously in the light emission stop state of LED1 and LED5. The LED 2 continuously emits light only during the front 1/5 portion of the cycle of the duty signal 2-3, the LED 3 emits light continuously over the cycle of the duty signal 3-3, and the LED 4 , 4-3, light is continuously emitted only in the front part of the cycle of the duty signal (see FIG. 25). However, since the LED 2 emits light with an emission intensity that is 1/5 that of the LED 3, the brightness of the LED 2 is 1/5 that of the LED 3, and the LED 4 emits light with an emission intensity that is 1/2 that of the LED 3. The brightness of the LED 4 is 1/2 the brightness of the LED 3 and 2.5 times the brightness of the LED 2.

  After the processing in step 362 described above, in the next step 363, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are simultaneously in the light emission driving state, the determination in step 370 becomes YES. Note that the LED 3 stops emitting light as the period τ elapses.

  With the determination of YES in step 370, in the next step 380, it is determined whether or not the variable n = 4. At this stage, since n = 3 remains, it is determined NO in Step 380, and then, in Step 381, the variable n = 4 is set. Accordingly, YES is determined in step 380.

  After this determination, when the computer program proceeds to step 390 in FIG. 19, in the fourth light emission mode data reading process in step 390, the light emission mode 4 in FIG. 14 is read from the ROM as the fourth light emission mode data. Here, the fourth light emission mode data includes the duty ratio D1 = 0 (%), the duty ratio D2 = 0 (%), the duty ratio D3 = 20 (%), the duty ratio D4 = 100 (%), and the duty ratio D5. = 50 (%) (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 391, the duty ratio D1 = 0 (%), the duty ratio D2 = 0 (%), and the duty ratio D3 = 20 (%) of the fourth light emission mode data in step 390. , Duty ratio D4 = 100 (%) and duty ratio D5 = 50 (%) are formed as the first to fourth to fifth-4 duty signals, respectively.

  Here, the first to fourth duty signals are formed at a high level over the cycle based on the duty ratio D1 = 0 (%), and the second to fourth duty signals are also set to the duty ratio D2 = 0 (%). Similarly, the third to fourth duty signals are formed at the high level over the period, and the third to fourth duty signals are based on the duty ratio D3 = 20 (%), and the front 1/5 portion and the rear 4/5 portion of the cycle. Are formed at a high level and a low level, respectively.

  Also, the 4th-4th duty signal is formed at a high level over the cycle based on the duty ratio D4 = 100 (%), and the 5th-4th duty signal has a duty ratio D5 = 50 ( %), The first half and the second half of the period are formed at a high level and a low level, respectively.

  As described above, when the duty signal forming process is performed in step 391, in the next duty signal output process in step 392, the 1-4th to 4th-4 duty signals in step 391 are output from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-4th duty signal is at the high level over the period, the power transistor 211 is turned off over the period based on the 1-4th duty signal. For this reason, the FET 214 is turned off based on the high-level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source is cut off from the LED L1 when the FET 214 is turned off.

  In the switching circuit 220, the 2-4 duty signal is also at a high level over the period, so that the power transistor 221 is turned off over the period based on the 2-4 duty signal. It becomes. For this reason, the FET 224 is turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a direct current based on the direct-current voltage + Vc from the direct-current power supply is cut off from the LED L2 when the FET 224 is turned off.

  In the switching circuit 230, since the 3-4th duty signal is at the high level and the low level over the front 1/5 portion and the rear 4/5 portion of the cycle, the power transistor 231 Based on the duty signal of 3-4, it is turned on for the front 1/5 portion of the cycle, and thereafter, it is turned off for the rear 4/5 portion of the cycle based on the 3-4 duty signal.

  For this reason, the FET 234 is turned on based on the low-level collector voltage generated from the power transistor 231, and then turned off based on the high-level collector voltage generated from the power transistor 231. Accordingly, a DC current based on the DC voltage + Vc from the DC power supply passes through the FET 234 while the FET 234 is on and then flows into the LED L3, and then stops flowing into the LED L3 while the FET 234 is off.

  Here, since the inflow of the direct current is limited to the front 1/5 portion of the cycle of the 3-4 duty signal, the LED L3 is in the front 1/5 portion of the cycle of the 3-4 duty signal. As long as it emits light. This means that the emission intensity of the LED L3 is reduced to 1/5 of its maximum value.

  In the switching circuit 240, since the 4th-4th duty signal is at a high level over the period, the power transistor 241 is turned on over the period based on the 4th-4th duty signal.

  For this reason, the FET 244 is turned on based on the low-level collector voltage generated from the power transistor 241. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source to the LED L4 through the FET 244. Here, since the inflow of the direct current continues over the cycle of the 4th-4th duty signal as described above, the LED L4 emits light over the cycle of the 4th-4th duty signal. This means that the light emission intensity of the LED L4 is at the maximum value of the light emission intensity.

  In the switching circuit 250, since the 5-4th duty signal is at the low level and the high level over the first half and the second half of the cycle, the power transistor 251 is changed to the 5-4th duty signal. Based on the first half of the cycle, the signal is turned on, and based on the fifth to fourth duty signal, the signal is turned off over the latter half of the cycle.

  Therefore, the FET 254 is turned on based on the high level collector voltage generated from the power transistor 251, and then turned off based on the low level collector voltage generated from the power transistor 251. For this reason, a DC current based on the DC voltage + Vc from the DC power source flows into the LED 5 through the FET 254 while the FET 254 is on, and is then cut off from the LED 5 by the FET 254 while the FET 254 is off. Accordingly, the LED L5 emits light only in the first half of the cycle of the 5th-4th duty signal. This means that the light emission intensity of the LED L5 is reduced to ½ of its maximum value.

  Since the duty signals of 1-4 to 5-4 described above are simultaneously output from the effect control circuit 100 in step 392, in the light emission drive circuit 200, the LEDs 1 to LED5 are simultaneously placed in the light emission drive state. For this reason, LED3, LED4, and LED5 emit light simultaneously in the light emission stop state of LED1 and LED2. The LED 3 continuously emits light only during the front 1/5 portion of the 3-4 duty signal cycle, the LED 4 emits light continuously over the 4-4 duty signal cycle, and the LED 5 The light is continuously emitted only in the front half of the cycle of the 5-4 duty signal (see FIG. 25). However, since the LED 3 emits light with an emission intensity that is 1/5 that of the LED 4, the brightness of the LED 3 is 1/5 that of the LED 4, and the LED 5 emits light with an emission intensity that is 1/2 that of the LED 4. The brightness of the LED 5 is ½ the brightness of the LED 3 and 2.5 times the brightness of the LED 2.

  After the processing in step 392 described above, in the next step 393, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are placed in the light emission driving state at the same time, the determination in step 400 is YES. In addition, LED4 stops light emission with progress of period (tau).

  With the determination of YES in step 400, in the next step 410, it is determined whether or not the variable n = 5. At this stage, since n = 4, NO is determined in step 410, and thereafter, in step 411, the variable n = 5 is set. Accordingly, YES is determined in step 410.

  After the determination, when the computer program proceeds to step 420 in FIG. 20, in the fifth light emission mode data read process in step 420, the light emission mode 5 in FIG. 14 is read from the ROM as the fifth light emission mode data. Here, the fifth light emission mode data is specified by each duty ratio D1 = D2 = D3 = 0 (%), duty ratio D4 = 20 (%), and duty ratio D5 = 100 (%) (FIG. 14).

  Thereafter, in the duty signal forming process in the next step 421, each duty ratio D1 = D2 = D3 = 0 (%), duty ratio D4 = 20 (%) and duty ratio D5 of the fifth light emission mode data in step 420. = 100 (%) is formed as the 1-5th to 5th-5th duty signals, respectively.

  Here, each of the first to fifth to fifth duty signals is formed at a high level over the period based on each duty ratio D1 = D2 = D3 = 0 (%).

  The fourth to fifth duty signals are formed at a high level and a low level over the front 1/5 portion and the rear 4/5 portion of the cycle based on the duty ratio D4 = 20 (%), respectively. The fifth to fifth duty signals are formed at a high level over the cycle based on the duty ratio D5 = 100 (%).

  As described above, when the duty signal forming process is performed in step 421, the duty signal output process in the next step 422 causes the 1st-5th to 5th-5th duty signals in step 421 to be output from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-5th duty signal is at a high level over the period, the power transistor 211 is turned off over the period based on the 1-5th duty signal. For this reason, the FET 214 is turned off based on the high-level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source is cut off from the LED L1 when the FET 214 is turned off.

  In the switching circuit 220, since the 2-5th duty signal is also at a high level over the period, the power transistor 221 is turned off over the period based on the 2-5th duty signal. It becomes. For this reason, the FET 224 is turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a direct current based on the direct-current voltage + Vc from the direct-current power supply is cut off from the LED L2 when the FET 224 is turned off.

  In the switching circuit 230, since the 3-5th duty signal is also at a high level over the period, the power transistor 231 is turned off over the period based on the 3-5th duty signal. It becomes. Therefore, the FET 234 is turned off based on the high-level collector voltage generated from the power transistor 231. Accordingly, a DC current based on the DC voltage + Vc is cut off from the LED L3 by turning off the FET 234.

  In the switching circuit 240, since the 4-5th duty signal is at the high level and the low level over the front 1/5 portion and the rear 4/5 portion of the cycle, the power transistor 241 Based on the duty signal of 4-5, the signal is turned on for the front 1/5 portion of the cycle, and thereafter, turned off for the rear 4/5 portion of the cycle based on the 4-5th duty signal.

  Therefore, the FET 244 is turned on based on the low level collector voltage generated from the power transistor 241, and then turned off based on the high level collector voltage generated from the power transistor 241. Along with this, a DC current based on the DC voltage + Vc from the DC power source flows into the LED L4 through the FET 244 while the FET 244 is on, and then stops flowing into the LED L4 while the FET 244 is off.

  Here, since the inflow of the direct current is limited to the front 1/5 portion of the cycle of the 4-5th duty signal, the LED L4 is in the front 1/5 portion of the cycle of the 4-5th duty signal. As long as it emits light. This means that the emission intensity of the LED L4 is reduced to 1/5 of its maximum value.

  In the switching circuit 250, since the 5th-5th duty signal is at a high level over the period, the power transistor 251 is turned on over the period based on the 5th-5th duty signal.

  Therefore, the FET 254 is turned on based on the low level collector voltage generated from the power transistor 251. Accordingly, a DC current based on the DC voltage + Vc flows from the DC power source through the FET 254 to the LED L5. Here, since the inflow of the direct current continues over the cycle of the fifth to fifth duty signals as described above, the LED L5 emits light over the cycle of the fifth to fifth duty signals. This means that the light emission intensity of the LED L5 is at the maximum value of the light emission intensity.

  Since the duty signals 1-5 to 5-5 described above are simultaneously output from the effect control circuit 100 in step 422, in the light emission drive circuit 200, the LEDs 1 to LED5 are simultaneously placed in the light emission drive state. For this reason, LED4 and LED5 light-emit simultaneously in the light emission stop state of LED1-LED3. The LED 4 continuously emits light only during the front 1/5 portion of the cycle of the duty signal 4-5, and the LED 5 emits light continuously over the cycle of the duty signal 5-5 (see FIG. 25). . However, since the LED 4 emits light with a light emission intensity 1/5 that of the LED 5, the brightness of the LED 4 is 1/5 of the brightness of the LED 5.

  After the processing of step 422 described above, in the next step 423, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are placed in the light emission driving state at the same time, the determination in step 430 is YES. In addition, LED5 stops light emission with progress of period (tau).

  With the determination of YES in step 430, in the next step 440, it is determined whether or not the variable n = 6. At this stage, since n = 5, NO is determined in step 440, and then, in step 441, the variable n = 6 is set. Accordingly, YES is determined in step 440.

  After the determination, when the computer program proceeds to step 450 in FIG. 21, in the sixth light emission mode data reading process in step 450, the light emission mode 6 in FIG. 14 is read from the ROM as the sixth light emission mode. Here, the sixth light emission mode data includes the duty ratio D1 = D2 = 0 (%), the duty ratio D3 = 5 (%), the duty ratio D4 = 10 (%), and the duty ratio D5 = 20 (%). Therefore, it is specified (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 451, each duty ratio D1 = D2 = 0 (%), duty ratio D3 = 5 (%), and duty ratio D4 = 10 of the sixth light emission mode data in step 450. (%) And a duty ratio D5 = 20 (%) are formed as the 1-6th to 5-6th duty signals, respectively.

  Here, each of the first to sixth and second to sixth duty signals is formed at a high level over the period based on each duty ratio D1 = D2 = 0 (%). The third to sixth duty signals are formed at a high level and a low level over the front 1/20 portion and the rear 19/20 portion of the cycle based on the duty ratio D3 = 5 (%), respectively.

  The 4-6th duty signal is formed at a high level and a low level over the front 1/10 portion and the rear 9/10 portion of the cycle based on the duty ratio D4 = 10 (%), respectively. The fifth to sixth duty signals are formed at a high level and a low level over the front 1/5 portion and the rear 4/5 portion of the cycle based on the duty ratio D4 = 20 (%), respectively.

  As described above, when the duty signal forming process is performed in step 451, in the next duty signal output process in step 452, the 1-6th to 5-6th duty signals in step 451 are output from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-6th duty signal is at a high level over the period, the power transistor 211 is turned off over the period based on the 1-6th duty signal. For this reason, the FET 214 is turned off based on the high-level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source is cut off from the LED L1 when the FET 214 is turned off.

  In the switching circuit 220, since the 2-6th duty signal is also at a high level over the period, the power transistor 221 is turned off over the period based on the 2-6th duty signal. It becomes. For this reason, the FET 224 is turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a direct current based on the direct-current voltage + Vc from the direct-current power supply is cut off from the LED L2 when the FET 224 is turned off.

  In the switching circuit 230, the duty signal of the 3-6th is that the front side 1/20 portion and the rear side 19/20 portion of the cycle are at the high level and the low level, respectively. Based on the duty signal of 3-6, it is turned on for the front 1/20 portion of the cycle, and thereafter turned off for the rear 19/20 portion of the cycle based on the 3-6th duty signal.

  For this reason, the FET 234 is turned on based on the low-level collector voltage generated from the power transistor 231, and then turned off based on the high-level collector voltage generated from the power transistor 231. Along with this, a DC current based on the DC voltage + Vc from the DC power source flows into the LED 3 through the FET 234 while the FET 234 is on, and is then cut off from the LED L3 by the FET 234 while the FET 234 is off.

  In the switching circuit 240, since the 4-6th duty signal is at the high level and the low level over the front 1/10 portion and the rear 9/10 portion of the cycle, the power transistor 241 Based on the duty signal of 4-6, it is turned on for the front 1/10 portion of the cycle, and then turned off for the rear 9/10 portion of the cycle based on the 4-6th duty signal.

  Therefore, the FET 244 is turned on based on the low level collector voltage generated from the power transistor 241, and then turned off based on the high level collector voltage generated from the power transistor 241. Accordingly, a DC current based on the DC voltage + Vc from the DC power supply passes through the FET 244 while the FET 244 is turned on and flows into the LED L4, and then stops flowing into the LED L4 while the FET 244 is turned off.

  Here, since the inflow of the direct current is limited to the front 1/10 portion of the cycle of the 4-6th duty signal, the LED L4 is in the front 1/10 portion of the cycle of the 4-6th duty signal. As long as it emits light. This means that the emission intensity of the LED L4 is reduced to 1/10 of its maximum value.

  In the switching circuit 250, since the 5-6th duty signal is at the high level and the low level over the front 1/5 portion and the rear 4/5 portion of the cycle, the power transistor 251 Based on the duty signal of 5-6, it is turned on for the front 1/5 portion of the cycle, and thereafter, it is turned off for the rear 4/5 portion of the cycle based on the 5-6th duty signal.

  Therefore, the FET 254 is turned on based on the low-level collector voltage generated from the power transistor 251, and then turned off based on the high-level collector voltage generated from the power transistor 251. Along with this, a DC current based on the DC voltage + Vc from the DC power source flows into the LED L5 through the FET 254 while the FET 254 is turned on, and is then cut off from the LED 5 by the FET 254 while the FET 254 is turned off. Here, since the inflow of the direct current continues over the front 1/5 portion of the cycle of the 5-6th duty signal as described above, the LED L5 has the front side 1 of the cycle of the 5-6th duty signal. / 5 part only emits light. This means that the emission intensity of the LED L5 decreases to 1/5 of its maximum value.

  Since the duty signals 1-6 to 5-6 described above are simultaneously output from the effect control circuit 100 in step 452, in the light emission drive circuit 200, the LEDs 1 to LED5 are simultaneously placed in the light emission drive state. For this reason, LED3-LED5 light-emits simultaneously in the light emission stop state of LED1 and LED2. The LED 3 continuously emits light only during the front 1/20 portion of the cycle of the duty signal 3-6, and the LED 4 emits light continuously over the front 1/10 portion of the cycle of the duty signal 4-6. Moreover, the LED 5 continuously emits light only in the front 1/5 portion of the period of the duty signal of 5-6 (see FIG. 25). However, since the LED 3 emits light with a light emission intensity 1/2 that of the LED 4 (1/20 of the maximum value of the light emission intensity), the brightness of the LED 3 is 1/5 of the brightness of the LED 4. Further, since the light emission intensity of the LED 5 is 1/2 of the light emission intensity of the LED 4 (1/10 of the maximum value of the light emission intensity), the brightness of the LED 5 is 1/2 of the brightness of the LED 4 and the LED 3 Is four times as bright.

  After the processing in step 452 described above, in the next step 453, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are placed in the light emission driving state at the same time, the determination in step 460 becomes YES.

  With the determination of YES in step 460, in the next step 470, it is determined whether or not the variable n = 7. At this stage, since n = 6, it is determined NO in step 470, and then, in step 471, the variable n = 7 is set. Accordingly, YES is determined in step 470.

  When the computer program proceeds to step 480 in FIG. 22 after this determination, the light emission mode 7 in FIG. 14 is read from the ROM as the seventh light emission mode data in the seventh light emission mode data read process in step 480. Here, the seventh light emission mode data has a duty ratio D1 = 5 (%), a duty ratio D2 = D3 = 0 (%), a duty ratio D4 = 5 (%), and a duty ratio D5 = 10 (%). It has been identified (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 481, the duty ratio D1 = 5 (%), the duty ratio D2 = D3 = 0 (%), the duty ratio D4 = 5 (in the step 480) %) And duty ratio D5 = 10 (%) are formed as the 1-7th to 5-7th duty signals, respectively.

  Here, the first to seventh duty signals are formed at a high level and a low level over the front 1/20 portion and the rear 19/20 of the cycle based on the duty ratio D1 = 5 (%), respectively. . Each of the 2-7th and 3-7th duty signals is formed at a high level over the period based on each duty ratio D2 = D3 = 0 (%).

  The fourth to seventh duty signals are formed at a high level and a low level over the front 1/20 portion and the rear 19/20 of the cycle based on the duty ratio D4 = 5 (%), respectively. . The fifth to seventh duty signals are formed at a high level and a low level over the front 1/10 portion and the rear 9/10 portion of the cycle based on the duty ratio D5 = 10 (%), respectively.

  As described above, when the duty signal forming process is performed in step 481, in the next duty signal output process in step 482, the 1-7th to 5-7th duty signals in step 481 are output from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-7th duty signal is at the high level and the low level over the front 1/20 portion and the rear 19/20 portion of the cycle, the power transistor 211 Based on the duty signal of 1-7, it is turned on for the front 1/20 part of the period, and thereafter, it is turned off for the rear 19/20 part of the period based on the 1-7 duty signal.

  For this reason, the FET 214 is turned on based on the high level collector voltage generated from the power transistor 211, and then turned off based on the low level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source through the FET 214 to the LED L1 while the FET 214 is on, and is then cut off from the LED L1 by the FET 214 while the FET 214 is off.

  In the switching circuit 220, since the 2-7th duty signal is at a high level over the period, the power transistor 221 is turned off over the period based on the 2-7 duty signal. . For this reason, the FET 224 is turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a direct current based on the direct-current voltage + Vc from the direct-current power supply is cut off from the LED L2 when the FET 224 is turned off.

  Further, in the switching circuit 230, the 3-7th duty signal is also at a high level over the period, so that the power transistor 231 extends over the period based on the 3-7th duty signal. Turn off. Therefore, the FET 234 is turned off based on the high-level collector voltage generated from the power transistor 231. Accordingly, a DC current based on the DC voltage + Vc is cut off from the LED L3 by turning off the FET 234.

  In the switching circuit 240, the front 1/20 portion and the rear 19/20 portion of the period of the 4-7th duty signal are at the high level and the low level, respectively. Based on the 7th duty signal, it is turned on for the front 1/20 part of the cycle, and then turned off for the rear 19/20 part of the cycle based on the 4-7th duty signal. Therefore, the FET 244 is turned on based on the low level collector voltage generated from the power transistor 241, and then turned off based on the high level collector voltage generated from the power transistor 241. Along with this, a DC current based on the DC voltage + Vc from the DC power source flows into the LED 4 through the FET 244 while the FET 244 is on, and is then cut off from the LED L4 by the FET 244 while the FET 244 is off.

  In the switching circuit 250, since the 5-7th duty signal is at the high level and the low level over the front side 1/10 portion and the rear side 9/10 portion of the cycle, the power transistor 251 Based on the duty signal of 5-7, it is turned on for the front 1/10 portion of the cycle, and then turned off for the rear 9/10 portion of the cycle based on the 5-7th duty signal.

  Therefore, the FET 254 is turned on based on the low-level collector voltage generated from the power transistor 251, and then turned off based on the high-level collector voltage generated from the power transistor 251. Accordingly, a direct current based on the direct current voltage + Vc from the direct current power source passes through the FET 254 while the FET 254 is on and flows into the LED L5, and then stops flowing into the LED L5 while the FET 254 is off.

  Here, since the inflow of the direct current is limited to the front 1/10 portion of the cycle of the 5-7th duty signal, the LED L5 is set to the front 1/10 portion of the cycle of the 5-7th duty signal. As long as it emits light. This means that the emission intensity of the LED L5 is reduced to 1/10 of its maximum value.

  Since the duty signals 1-7 to 5-7 described above are simultaneously output from the effect control circuit 100 in step 482, in the light emission drive circuit 200, the LEDs 1 to LED5 are simultaneously placed in the light emission drive state. For this reason, LED1, LED4, and LED5 emit light simultaneously in the light emission stop state of LED2 and LED3. The LED 1 continuously emits light only during the front 1/20 portion of the 1-7 duty signal cycle, and the LED 4 emits light continuously over the front 1/20 portion of the 4-7 duty signal cycle. Further, the LED 5 continuously emits light only in the front 1/5 portion of the period of the duty signal of 5-7 (see FIG. 25). However, since the LED 1 emits light with the same light emission intensity as that of the LED 5, the brightness of the LED 1 is the same as that of the LED 5. Moreover, since the light emission intensity of the LED 5 is twice the light emission intensity of the LED 4, the brightness of the LED 5 is twice the brightness of the LED 4 and twice the brightness of the LED 1.

  After the processing in step 482 described above, in the next step 483, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are placed in the light emission driving state at the same time, the determination in step 490 becomes YES.

  With the determination of YES in step 490, in the next step 500, it is determined whether or not the variable n = 8. At this stage, since n = 7, NO is determined in step 500, and then, in step 501, variable n = 8 is set. Accordingly, YES is determined in step 500.

  After this determination, when the computer program proceeds to step 510 in FIG. 23, the light emission mode 8 in FIG. 14 is read from the ROM as the eighth light emission mode data in the eighth light emission mode data read processing in step 510. Here, the eighth light emission mode data has a duty ratio D1 = 10 (%), a duty ratio D2 = 5 (%), a duty ratio D3 = D4 = 0 (%), and a duty ratio D5 = 5 (%). It has been identified (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 511, the duty ratio D1 = 10 (%), the duty ratio D2 = 5 (%), and the duty ratio D3 = D4 = 0 (step 510). %) And duty ratio D5 = 5 (%) are formed as the 1-8th to 5-8th duty signals, respectively.

  Here, based on the duty ratio D1 = 10 (%), the 1-8th duty signal is formed at a high level and a low level over the front 1/10 portion and the rear 9/10 of the cycle, respectively. . The second to eighth duty signals are formed at a high level and a low level over the front 1/20 portion and the rear 19/20 of the cycle based on the duty ratio D2 = 5 (%), respectively. .

  Each of the 3-8th and 4-8th duty signals is formed at a high level over the period based on each duty ratio D3 = D4 = 0 (%). The fifth to eighth duty signals are formed at a high level and a low level over the front 1/20 portion and the rear 19/20 of the cycle based on the duty ratio D5 = 5 (%), respectively. .

  As described above, when the duty signal forming process is performed in step 511, in the next duty signal output process in step 512, the 1st to 8th to 8th duty signals in step 511 are output from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-8th duty signal is at the high level and the low level over the front side 1/10 portion and the rear side 9/10 portion of the cycle, the power transistor 211 Based on the 1-8 duty signal, it is turned on for the front 1/10 portion of the period, and thereafter, it is turned off for the rear 9/10 portion of the period based on the 1-8 duty signal. For this reason, the FET 214 is turned on based on the high level collector voltage generated from the power transistor 211, and then turned off based on the low level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source through the FET 214 to the LED L1 while the FET 214 is on, and is then cut off from the LED L1 by the FET 214 while the FET 214 is off.

  In the switching circuit 220, since the 2-8th duty signal is at the high level and the low level over the front 1/20 portion and the rear 19/20 portion of the cycle, respectively, the power transistor 221 Is turned on for the front 1/20 part of the period based on the 2-8th duty signal, and is then turned off for the rear 19/20 part of the period based on the 2-8 duty signal. Become. For this reason, the FET 224 is turned on based on the low-level collector voltage generated from the power transistor 221, and then turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a DC current based on the DC voltage + Vc from the DC power source flows through the FET 224 into the LED L2 while the FET 224 is on, and is then cut off from the LED L2 by the FET 224 while the FET 224 is off.

  In the switching circuit 230, since the 3-8th duty signal is at a high level over the period, the power transistor 231 is turned off over the period based on the 3-8 duty signal. . Therefore, the FET 234 is turned off based on the high-level collector voltage generated from the power transistor 231. Accordingly, a DC current based on the DC voltage + Vc is cut off from the LED L3 by turning off the FET 234.

  In the switching circuit 240, the 4-8th duty signal is also at a high level over the period, so that the power transistor 241 operates over the period based on the 8-4 duty signal. Turn off. Therefore, the FET 244 is turned off based on the high-level collector voltage generated from the power transistor 241. Accordingly, a direct current based on the direct current voltage + Vc is cut off from the LED L4 by turning off the FET 244 from the direct current power source.

  In the switching circuit 250, since the front 1/20 portion and the rear 19/20 portion of the cycle of the 5-8th duty signal are at the high level and the low level, respectively, the power transistor 251 Based on the 8th duty signal, the signal is turned on for the front 1/20 part of the cycle, and then turned off for the rear 19/20 part of the cycle based on the 5-8th duty signal. Therefore, the FET 254 is turned on based on the low-level collector voltage generated from the power transistor 251, and then turned off based on the high-level collector voltage generated from the power transistor 251. Along with this, a DC current based on the DC voltage + Vc from the DC power source flows into the LED 5 through the FET 254 while the FET 254 is on, and is then cut off from the LED L5 by the FET 254 while the FET 254 is off.

  Here, since the inflow of the direct current is limited to the front 1/10 portion of the cycle of the 5-8th duty signal, the LED L5 is set to the front 1/20 portion of the cycle of the 5-8th duty signal. As long as it emits light. This means that the light emission intensity of the LED L5 is reduced to 1/20 of its maximum value.

  Since the above-described duty signals 1-8 to 5-8 are simultaneously output from the effect control circuit 100 in step 512, the LED1 to LED5 are simultaneously placed in the light emission drive state in the light emission drive circuit 200. . For this reason, LED1, LED2, and LED5 emit light simultaneously in the light emission stop state of LED3 and LED4. Then, LED1 continues to emit light only during the front 1/10 portion of the cycle of the 1-8th duty signal, and LED2 continues over the front 1/20 portion of the cycle of the 2-8th duty signal. In addition, the LED 5 also emits light only during the front 1/5 portion of the cycle of the fifth to eighth duty signals (see FIG. 25). However, since the LED 1 emits light with a light emission intensity twice that of the LED 2, the brightness of the LED 1 is the same as that of the LED 2. Further, since the light emission intensity of the LED 5 is the same as the light emission intensity of the LED 2, the brightness of the LED 5 is the same as the brightness of the LED 2 and is ½ of the brightness of the LED 1.

  After the processing in step 512 described above, in the next step 513, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are simultaneously in the light emission driving state, the determination in step 520 is YES.

  With the determination of YES in step 520, in the next step 530, it is determined whether or not the variable n = 9. At this stage, since n = 8, NO is determined in Step 530, and then, in Step 531, the variable n = 9 is set. Accordingly, YES is determined in step 530.

  After this determination, when the computer program proceeds to step 540 in FIG. 24, the light emission mode 9 in FIG. 14 is read out from the ROM as the ninth light emission mode data in the ninth light emission mode data read processing in step 540. Here, the ninth light emission mode data includes a duty ratio D1 = 20 (%), a duty ratio D2 = 10 (%), a duty ratio D3 = 5 (%), and each duty ratio D4 = D5 = 0 (%). Therefore, it is specified (see FIG. 14).

  Thereafter, in the duty signal forming process in the next step 541, the duty ratio D1 = 20 (%), the duty ratio D2 = 10 (%), and the duty ratio D3 = 5 (%) of the ninth light emission mode data in step 540. Each duty ratio D4 = D5 = 0 (%) is formed as the 1-9th to 5th-9th duty signals, respectively.

  Here, the first to ninth duty signals are formed at a high level and a low level over the front 1/5 portion and the rear 4/5 of the cycle based on the duty ratio D1 = 20 (%), respectively. The The second to ninth duty signals are formed at a high level and a low level over the front side 1/10 portion and the rear side 9/10 of the cycle based on the duty ratio D2 = 10 (%), respectively. .

  The third to ninth duty signals are formed at a high level and a low level over the front 1/20 portion and the rear 19/20 of the cycle based on the duty ratio D3 = 5 (%), respectively. . Each of the 4th-9th and 5th-9th duty signals is formed at a high level over the period based on each duty ratio D4 = D5 = 0 (%).

  As described above, when the duty signal forming process is performed in step 541, in the next duty signal output process in step 542, the 1-9th to 5-9th duty signals in step 541 are output from the effect control circuit 100. The light is output to the switching circuits 210 to 250 of the light emission driving circuit 200 via the output ports P1 to P5.

  Then, in the switching circuit 210, since the 1-9th duty signal is at the high level and the low level over the front 1/5 portion and the rear 4/5 portion of the cycle, the power transistor 211 Based on the 1-9 duty signal, the signal is turned on for the first 1/5 portion of the cycle, and thereafter, turned off for the 4/5 portion of the cycle based on the 1-9 duty signal. For this reason, the FET 214 is turned on based on the high level collector voltage generated from the power transistor 211, and then turned off based on the low level collector voltage generated from the power transistor 211. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source through the FET 214 to the LED L1 while the FET 214 is on, and is then cut off from the LED L1 by the FET 214 while the FET 214 is off.

  In the switching circuit 220, since the 2-9th duty signal is at the high level and the low level over the front 1/10 portion and the rear 9/10 portion of the cycle, respectively, the power transistor 221 Is turned on over the front 1/10 portion of the cycle based on the 2-9th duty signal, and is then turned off over the back 9/10 portion of the cycle based on the 2-9 duty signal. Become. For this reason, the FET 224 is turned on based on the low-level collector voltage generated from the power transistor 221, and then turned off based on the high-level collector voltage generated from the power transistor 221. Accordingly, a DC current based on the DC voltage + Vc from the DC power source flows through the FET 224 into the LED L2 while the FET 224 is on, and is then cut off from the LED L2 by the FET 224 while the FET 224 is off.

  In the switching circuit 230, since the 3-9th duty signal is at the high level and the low level over the front 1/20 portion and the rear 19/20 portion of the cycle, respectively, the power transistor 231 Is turned on over the front 1/20 portion of the period based on the 3-9 duty signal, and is then turned off over the back 19/20 portion of the period based on the 3-9 duty signal. Become.

  For this reason, the FET 234 is turned on based on the low-level collector voltage generated from the power transistor 231, and then turned off based on the high-level collector voltage generated from the power transistor 231. Accordingly, a direct current based on the direct current voltage + Vc flows from the direct current power source through the FET 234 to the LED L3 while the FET 234 is on, and is then cut off from the LED L3 by the FET 234 while the FET 234 is off.

  In the switching circuit 240, since the 4th-9th duty signal is at a high level over the period, the power transistor 241 is turned off over the period based on the 4th-9th duty signal. . Therefore, the FET 244 is turned off based on the high-level collector voltage generated from the power transistor 241. Accordingly, a direct current based on the direct current voltage + Vc is cut off from the LED L4 by turning off the FET 244 from the direct current power source.

  Further, in the switching circuit 250, the 5-9th duty signal is also at a high level over the period, so that the power transistor 251 extends over the period based on the 5-9 duty signal. Turn off. For this reason, the FET 254 is turned off based on the high-level collector voltage generated from the power transistor 251. Accordingly, a direct current based on the direct current voltage + Vc is cut off from the LED L5 by turning off the FET 254 from the direct current power source.

  Since the 1-9th to 5th-9th duty signals described above are simultaneously output from the effect control circuit 100 in step 542, in the light emission drive circuit 200, the LEDs 1 to 5 are simultaneously placed in the light emission drive state. . For this reason, LED1, LED2, and LED3 emit light simultaneously in the light emission stop state of LED4 and LED5. The LED 1 continuously emits light only in the front 1/5 portion of the cycle of the 1-9th duty signal, and the LED 2 continues in the front 1/10 portion of the cycle of the 2-9 duty signal. Further, the LED 3 continuously emits light only in the front 1/20 portion of the period of the third to ninth duty signals (see FIG. 25). However, since the LED 1 emits light with a light emission intensity twice that of the LED 2, the brightness of the LED 1 is twice that of the LED 2. Moreover, since the light emission intensity of LED3 is 1/2 of the light emission intensity of LED2, the brightness of LED3 is 1/2 of the brightness of LED2.

  After the processing of step 542 described above, in the next step 543, the soft timer is reset and started to start timing.

  Therefore, when the period τ elapses after the LEDs 1 to 5 are placed in the light emission driving state at the same time, the determination in step 550 becomes YES. Thereafter, the computer program returns from the return step to the start step in FIG. 16, and the processing of the return step in steps 300 to 9 is repeated in the same manner as described above. Further, this process is repeated during the production time for the above jackpot lottery.

  As described above, the LEDs 1 to 5 emit light sequentially from the LED 1 to the LED 5 according to the first to fifth light emission modes at a duty ratio of 100 (%) sequentially from the LED 1 to the LED 5, and the duty ratio of the LED 1 is 100 (%). LED2 emits light with a duty ratio of 50 (%) according to the light emission by LED, LED3 emits light with a duty ratio of 50 (%) according to light emission with a duty ratio of 100 (%) of LED2, and LED1 has a duty ratio of 20 ( %), And LED4 emits light at a duty ratio of 50 (%) and LED2 emits light at a duty ratio of 20 (%), and the duty ratio of LED4. The LED 5 emits light at a duty ratio of 50% in accordance with the light emission by 100 (%) and the LED 3 Emitted by Ti ratio 20 (%), and the LED4 in accordance with the light emission by LED5 duty ratio of 100 (%) emits at a duty ratio of 20 (%).

  Further, the LEDs 1 to 5 emit light at respective duty ratios of 20 (%), 10 (%) and 5 (%) from LED5 to LED3 according to the light emission mode 6, and the LED5 is driven at a duty ratio of 10 (%) according to the light emission mode 7. LED3 and LED1 emit light with a duty ratio of 5 (%), LED1 emits light with a duty ratio of 20 (%) and LED5 and LED2 emit light with a duty ratio of 5 (%) In addition, light is emitted from the LED 1 to the LED 3 according to the light emission mode 9 at respective duty ratios of 20 (%), 10 (%), and 5 (%).

  Therefore, according to the light emission modes 1 to 5, the LEDs 1 to 5 emit light at the maximum light emission intensity (that is, the maximum brightness) every period τ. Then, the LED 2 emits light at half the maximum light emission intensity (that is, half the maximum brightness) in accordance with the light emission by the maximum light emission intensity of the LED 1, and the light emission at each maximum light emission intensity of the LED 2 to LED 4. LED3 to LED5 emit light at half of the maximum emission intensity (ie, half the maximum brightness) and LED1 to LED4 are 1/5 of the maximum emission intensity (ie, the maximum brightness). (1/5 brightness).

  Further, according to the light emission mode 6, from LED5 to LED3, 1/5 of the maximum emission intensity (that is, 1/5 of the maximum brightness), 1/10 (that is, 1/10 and 1/20 of the maximum brightness), respectively. (That is, 1/20 of the maximum brightness), and according to the light emission mode 7, the LED 5 emits light at 1/10 of the maximum emission intensity (that is, 1/10 of the maximum brightness) and the LED 3 and The LED 1 emits light at 1/20 of the maximum emission intensity (that is, 1/20 of the maximum brightness), and the LED 1 according to the light emission mode 8 is 1/5 of the maximum emission intensity (that is, the brightness of 1/5 of the maximum brightness). The LED 5 and the LED 2 emit light at 1/20 of the maximum emission intensity (that is, 1/20 of the maximum brightness), and the maximum emission intensity from the LED 1 to the LED 3 according to the emission mode 9 respectively. of / 5 (ie, 1/5 of the maximum brightness), 1/10 (ie, 1/10 of the maximum brightness) and 1/20 (ie, 1/20 of the maximum brightness) In other words, darkness is formed between LED1 and LED2, between LED2 and LED3, between LED3 and LED4, and between LED4 and LED5.

  According to the above, the emitted light from LED1 to LED5 is sequentially reflected by the curved reflecting plate 47b as a light emitting point having the maximum brightness sequentially every period τ, and then between LED1 and LED2, between LED2 and LED3, LED3 and LED4. And between LED4 and LED5, it becomes darker by the period τ.

  Accordingly, each light emission of LED1 to LED5 is sequentially reflected by the curved reflecting plate 47b and moves from the left end side toward the right end side along the outer peripheral edge of the arrangement plate portion 47c. As visible. In addition, the darkness formed between LED1 and LED2, between LED2 and LED3, between LED3 and LED4, and between LED4 and LED5 is sequentially reflected by the curved reflector 47b, so that the arrangement plate 47c It is visually recognized as a dark spot that moves from the left end side toward the right end side along the outer peripheral edge.

  As a result, even if five LEDs are arranged only on the semicircular outer peripheral edge of the arrangement plate portion 47c, the light effect is performed over the entire circumference by moving the light emitting point and the dark point. It can be visually recognized.

  Here, since the brightness of each LED adjacent to LED1 to LED5 that emits light at the maximum brightness is made darker than the maximum brightness, each light emitting point of LED1 to LED5 that emits light at the maximum brightness is more It becomes clearer.

  In addition, when following the light emission mode 6, it becomes darker sequentially from the LED5 to the LED3, when following the light emission mode 7, it becomes darker sequentially from the LED5 and the LED4, and the LED1 is made the same darkness as the LED4, and when following the light emission mode8, it becomes darker sequentially from the LED1 and the LED2. Since the LED 5 has the same darkness as that of the LED 2, and the light emission mode 9 is followed, the LED 5 is gradually darkened from the LED 1 to the LED 3, so that each dark spot is further clarified.

  As a result, the light effect over the entire circumference by the movement of the light emitting point and the dark spot is further clarified.

  On the other hand, each game ball rolling downward as described above rolls downward along the upper surface of the left portion and the upper portion of the right portion of the inner rail 22b without entering the winning opening 43c of the light effect device 40. When it moves, the game ball on the upper surface of the left portion of the inner rail 22b (hereinafter also referred to as the left sphere) runs along the upper surface of the left portion of the inner rail 22b, in other words, at the lower center of the inner rail 22b. On the other hand, the game ball on the upper surface of the right part of the inner rail 22b (hereinafter also referred to as the right sphere) moves along the upper surface of the right part of the inner rail 22b, and the center of the lower end of the inner rail 22b. In other words, it rolls from the right side toward the light effect device 40. This means that the left sphere and the right sphere roll in the direction of approaching and colliding with each other along the upper surfaces of the left and right portions of the inner rail 22b.

  However, the light effect device 40 is provided with the left sphere discharge cylinder member 45 and the right sphere discharge cylinder member 46 in the configuration as described above. Accordingly, the left sphere that reaches the center of the lower end of the inner rail 22b from the left side passes through the left sphere discharge cylinder member 45 and is discharged to the rear of the game board 20 through the out port 30, while The reaching right sphere passes through the right sphere discharge cylinder member 46 and is discharged to the rear of the game board 20 through the out port 30.

  Here, the left sphere discharge cylinder member 45 opens to the left from the center lower part of the inner rail 22b through the left out sphere entry path 43f, while the right sphere discharge cylinder member 46 passes through the right out sphere entry path 43g. It opens from the center lower part of 22b to the right side. Accordingly, the left sphere smoothly enters the left sphere discharge cylinder member 45 from the left portion of the inner rail 22b through the left out ball entry path 43f and is discharged to the rear of the game board 20 through the out port 30, while the right side The ball can smoothly enter the right ball discharge cylinder member 46 from the right portion of the inner rail 22b through the right out ball entry path 43g and be discharged to the rear of the game board 20 through the out port 30.

  Thus, the left sphere discharge cylinder member 45 serves as a passage exclusively for discharge to the rear of the game board 20 via the left sphere out port 30, while the right sphere discharge cylinder member 46 is Since it serves as a passage exclusively for discharge to the rear of the game board 20 through the out port 30, the left sphere and the right sphere collide from the left and right at the lower end central portion of the inner rail 22b, causing clogging of the ball. The occurrence of a situation can be prevented in advance.

  Here, the extension opening 46 a of the right sphere discharge cylinder member 46 extends into the out port 30 on the rear side of the extension opening 45 a together with the extension opening 45 a of the left sphere discharge cylinder member 45. Therefore, the above-described effect can be achieved more reliably. The extension opening 46a of the right sphere discharge cylinder member 46 and the extension opening 45a of the left sphere discharge cylinder member 45 extend into the out port 30 on the front side of the extension opening 45a. Even so, similar effects can be achieved.

As described above, according to the first embodiment, the light effect system is configured to be compact so that the light effect device 40 integrally includes the left sphere discharge cylinder member 45 and the right sphere discharge cylinder member 46. Therefore, both the effect described above and the effect of preventing ball clogging can be achieved with the above-described integrated compact configuration.
(Second Embodiment)
FIG. 26 shows a main part of the second embodiment of the present invention. In the second embodiment, a light emission drive circuit 200A is employed instead of the light emission drive circuit 200 described in the first embodiment.

  The light emission drive circuit 200 </ b> A includes switching circuits 210 </ b> A to 250 </ b> A corresponding to the switching circuits 210 to 250 of the light emission drive circuit 200, respectively.

  The switching circuit 210A is configured by adopting an FET 214A and an inverter 215 in place of the FET 214 in the switching circuit 210 described in the first embodiment, and the FET 214A has a MOS N-channel field effect. It is configured with a transistor.

  The FET 214A is connected at its gate 214d to the collector 211b of the power transistor 211 via the inverter 215, and the drain 214e of the FET 214A is connected to the positive terminal of the DC power source via the LED 1. The source 214f of the FET 214A is grounded.

  Here, the inverter 215 inverts the low-level or high-level collector voltage from the collector 211b of the power transistor 211 to generate a high-level or low-level inverted voltage.

  Accordingly, the FET 214A is turned on or off by performing a switching operation when an inverted voltage of a high level or a halo level is applied from the inverter 215. When the FET 214A is turned on, a direct current based on the direct current voltage + Vc from the direct current power source flows into the LED 1. Further, the FET 214A shuts off the direct current based on the direct current voltage + Vc from the direct current power source from the LED 1 by being turned off.

  This means that the LED 1 emits light based on the inflow of the direct current and stops emitting light based on the interruption of the inflow of the direct current. Here, the light emission duration of the LED 1 corresponds to the high level time of any of the first to 1-9 duty signals described in the first embodiment, and the light emission stop time of the LED 1 is This corresponds to the low level time of any of the 1-1 to 1-9th duty signals. The other configuration of the switching circuit 210A is the same as that of the switching circuit 210 described in the first embodiment.

  The switching circuit 220A is configured by adopting an FET 224A instead of the FET 224 in the switching circuit 220 described in the first embodiment, and the FET 224A is a MOS type N-channel field effect transistor. It is configured.

  The FET 224A is connected to the collector 221b of the power transistor 221 at its gate 224d, and the drain 224e of the FET 224A is connected to the positive terminal of the DC power supply via the LED 2. The source 224f of the FET 224A is grounded.

  Accordingly, the FET 224A is turned on or off by switching operation by applying a low-level or high-level collector voltage from the collector 221b of the power transistor 221. When the FET 224A is turned on, a direct current based on the direct current voltage + Vc from the direct current power source flows into the LED 2. The FET 224A shuts off the direct current based on the direct current voltage + Vc from the direct current power source from the LED 2 by turning off the FET 224A.

  This means that the LED 2 emits light based on the inflow of the direct current and stops emitting light based on the interruption of the inflow of the direct current. Here, the light emission duration of the LED 2 corresponds to the high level time of any of the 2-1 to 2-9 duty signals described in the first embodiment, and the light emission stop time of the LED 2 is This corresponds to the low level time of any of the 2-1 to 2-9 duty signals. The other configuration of the switching circuit 220A is the same as that of the switching circuit 220 described in the first embodiment.

  The switching circuit 230A is configured by adopting an FET 234A instead of the FET 234 in the switching circuit 230 described in the first embodiment, and the FET 234A is a MOS type N-channel field effect transistor. It is configured.

  The FET 234A is connected to the collector 231b of the power transistor 231 at its gate 234d, and the drain 234e of the FET 234A is connected to the positive terminal of the DC power supply via the LED 3. The source 234f of the FET 234A is grounded.

  Thus, the FET 234A is turned on or off by switching operation by applying a low-level or high-level collector voltage from the collector 231b of the power transistor 231. When the FET 234A is turned on, a direct current based on the direct current voltage + Vc from the direct current power source flows into the LED 3. Further, the FET 234A shuts off the direct current based on the direct current voltage + Vc from the direct current power source from the LED 3 by being turned off.

  This means that the LED 3 emits light based on the inflow of the DC current and stops emitting light based on the interruption of the inflow of the DC current. Here, the light emission continuation time of the LED 3 corresponds to the high level time of any of the 3-1 to 3-9 duty signals described in the first embodiment, and the light emission stop time of the LED 3 is This corresponds to the low level time of any one of the 3-1 to 3-9 duty signals. The other configuration of the switching circuit 230A is the same as that of the switching circuit 230 described in the first embodiment.

  The switching circuit 240A is configured by adopting an FET 244A instead of the FET 244 in the switching circuit 240 described in the first embodiment, and the FET 244A is a MOS type N-channel field effect transistor. It is configured.

  The FET 244A is connected to the collector 241b of the power transistor 241 at its gate 244d, and the drain 244e of the FET 244A is connected to the positive terminal of the DC power supply via the LED 4. The source 244f of the FET 244A is grounded.

  Thus, the FET 244A is turned on or off by switching operation by applying a low-level or high-level collector voltage from the collector 241b of the power transistor 241. When the FET 244A is turned on, a DC current based on the DC voltage + Vc from the DC power supply flows into the LED 4. Further, the FET 244A shuts off the direct current based on the direct current voltage + Vc from the direct current power source from the LED 4 by being turned off.

  This means that the LED 4 emits light based on the inflow of the DC current and stops emitting light based on the interruption of the inflow of the DC current. Here, the light emission continuation time of the LED 4 corresponds to the high level time of any of the 4-1 to 4-9 duty signals described in the first embodiment, and the light emission stop time of the LED 4 is This corresponds to the low level time of any of the 4-1 to 4-9 duty signals. The other configuration of the switching circuit 240A is the same as that of the switching circuit 240 described in the first embodiment.

  The switching circuit 250A is configured by adopting an FET 254A instead of the FET 254 in the switching circuit 250 described in the first embodiment, and the FET 254A is a MOS type N-channel field effect transistor. It is configured.

  The FET 254A is connected to the collector 251b of the power transistor 251 at its gate 254d, and the drain 254e of the FET 254A is connected to the positive terminal of the DC power supply via the LED 5. The source 254f of the FET 254A is grounded.

  Therefore, the FET 254A is turned on or off by switching operation by applying a low-level or high-level collector voltage from the collector 251b of the power transistor 251. When the FET 254A is turned on, a direct current based on the direct current voltage + Vc from the direct current power source flows into the LED 5. Further, the FET 254A shuts off the DC current from the LED 5 based on the DC voltage + Vc from the DC power supply.

  This means that the LED 5 emits light based on the inflow of the direct current and stops emitting light based on the interruption of the inflow of the direct current. Here, the light emission duration time of the LED 5 corresponds to the high level time of any of the duty signals 5-1 to 5-9 described in the first embodiment, and the light emission stop time of the LED 5 is This corresponds to the low level time of any of the duty signals 5-1 to 5-9. The other configuration of the switching circuit 250A is the same as that of the switching circuit 250 described in the first embodiment. Other configurations of the second embodiment are the same as those of the first embodiment.

  In the second embodiment configured as described above, unlike the first embodiment, each of the LEDs 1 to 5 is connected to the positive terminal of the DC power supply, and the switching circuit 210A of the light emission control circuit 200A. As described above, the inverter 215 and FET 214A of the switching circuit 220A, the inverter 225 and FET 224A of the switching circuit 220A, the inverter 235 and FET 234A of the switching circuit 230A, the inverter 245 and FET 244A of the switching circuit 240A, and the inverter 255 and FET 254A of the switching circuit 250A, respectively. The FET 214 of the switching circuit 210, the FET 224 of the switching circuit 220, the FET 234 of the switching circuit 230, and the switch of the light emission control circuit 200 described in the first embodiment. Since it has the same function as the FET254 the FET244 and switching circuit 250 of the grayed circuit 240, it is possible to achieve a dramatic effect similar to the above first embodiment. Other functions and effects are the same as those of the first embodiment.

In carrying out the present invention, the following various modifications are possible without being limited to the above embodiments.
(1) Needless to say, in implementing the present invention, the number of light emitting diodes is not limited to five.
(2) In implementing the present invention, the light emission drive circuit is not limited to the configuration described in each of the above embodiments, and may be any circuit as long as it has a similar function. For example, in each switching circuit of the light emission drive circuit 200A described in the second embodiment, the inverter may be connected in series to the gate of the power transistor.
(3) In carrying out the present invention, in each of the light emission modes 6 to 9 among the light emission modes 1 to 9, unlike the above-described embodiment, both the LEDs that make the light emission intensity zero (the duty ratio in FIG. 14). Unlike the above-described embodiment, each LED that is zero) may be at least one LED.

Here, when at least one LED is, for example, a single LED, the position of the single LED is a dark spot, and in the case of three LEDs, the position of the three LEDs is the same. The center LED position is a dark spot.
(4) In carrying out the present invention, among the light emitting modes 1 to 9, in each of the light emitting modes 6 to 9, both LEDs 5, 4, both LEDs 4, 3, both LEDs 3, 2, and both are opposite to the above embodiment. The light emission intensity may be set to zero in the order of the LEDs 2 and 1.
(5) In carrying out the present invention, each duty ratio may be a value different from the above embodiment.

47: Light-emitting reflection unit, 47a: Light-emitting plate member, 47b: Curved reflection plate,
47c ... Arrangement plate part, 200, 200A ... Light emission drive circuit,
210 to 250 ... switching circuit,
210A-250A ... switching circuit, L1-L5 ... light emitting diode.

Claims (5)

A reflective surface portion that curves in a convex shape toward the player side, a disposition surface portion that extends forward of the reflective surface portion, and the curved direction of the reflective surface portion from one end side to the other end side in the curved direction. A light-emitting / reflecting unit having a plurality of light-emitting elements disposed at intervals on the disposition surface portion, and
The plurality of light emitting elements emit light at a predetermined light emission intensity in a predetermined light emission mode from the light emitting element on the one end side to the light emitting element on the other end side of the reflective surface portion,
After light emission by the predetermined light emission intensity of the light emitting element on the other end side, at least one light emitting element having a light emission intensity of zero among the plurality of light emitting elements is set to one of the light emitting elements on both the one end side and the other end side. Both the light emitting elements that are sequentially shifted from the light emitting element to the other light emitting element and that are separated from the at least one light emitting element that has the light emission intensity of zero with the transition of the at least one light emitting element that has the light emission intensity of zero. A light production system in which light is emitted at a light emission intensity that gradually increases in a range lower than the predetermined light emission intensity for each element. A light emitting element close to the light emitting element on the other end side among the light emitting elements adjacent to the one light emitting element in accordance with the light emission by the predetermined light emission intensity of the one light emitting element for each of the plurality of light emitting elements. Is emitted at a first low emission intensity lower than the predetermined emission intensity, and a light emitting element close to the one end-side light emitting element among the two adjacent light emitting elements is a second low emission intensity lower than the first low emission intensity. Emits light,
After light emission with the predetermined light emission intensity of the light emitting element on the other end side, at least one light emitting element adjacent to the at least one light emitting element is set to the same low level every time the at least one light emitting element has the light emission intensity of zero. The light emitting element emits light at a light emission intensity, and the light emitting element on the other end side emits light so that the light emission intensity sequentially decreases from the second low light emission intensity. 2. The light effect system according to claim 1, wherein light is emitted so as to increase sequentially from the same light emission intensity in a range lower than a predetermined light emission intensity. A reflective surface portion that curves in a convex shape toward the player side, a disposition surface portion that extends forward of the reflective surface portion, and the curved direction of the reflective surface portion from one end side to the other end side along the curved direction. A light-emitting / reflecting unit having first to m-th light-emitting elements disposed at intervals on the arrangement surface portion;
1st to mth light emission modes having a predetermined duty ratio required for light emission of the first to mth light emitting elements, and at least a duty ratio required for light emission of the first to mth light emitting elements is zero. With the transition of the at least one light emitting element in which one light emitting element is sequentially shifted from one light emitting element to the other light emitting element of the one end side and the other end side, and the duty ratio is zero, The (m + 1) th to (m + 2) light emission having a low duty ratio that sequentially increases in a range lower than the predetermined duty ratio for each of the light emitting elements that are separated from the at least one light emitting element having the duty ratio of zero. Storage means for storing the mode as light emission mode data;
The first to mth light emitting elements emit light based on the first to mth light emission modes of the light emission mode data, and then the (m + 1) th to (m + 2) th of the light emission mode data. And a drive control means for drivingly controlling the light emitting elements other than the at least one light emitting element to emit light in accordance with the transition of the at least one light emitting element having the duty ratio of zero. system. In the light emission mode data, the first to mth light emission modes are the mth light emitting element among the adjacent light emitting elements of the one light emitting element for each one light emitting element of the first to mth light emitting elements. The duty ratio required for light emission of the light emitting element close to the light emitting element on the side is also set to the first low duty ratio lower than the predetermined duty ratio, and the light emitting element near the first light emitting element among the two adjacent light emitting elements emits light. The required duty ratio is also set to be a second low duty ratio lower than the first low duty ratio,
Each of the (m + 1) to (m + 2) light emission modes is required for light emission of both light emitting elements adjacent to the at least one light emitting element for each transition of the at least one light emitting element having the duty ratio of zero. The duty ratio is also set to the same low light emission intensity, and the duty ratio required for light emission of the mth light emitting element is also sequentially decreased from the second low duty ratio, and the duty ratio required for light emission of the first light emitting element is also increased. It is set to be a duty ratio that is sequentially increased from the lowest duty ratio in a range lower than a predetermined duty ratio,
The drive control unit emits light from the first to mth light emitting elements and the adjacent light emitting elements based on the first to mth light emitting modes, and the (m + 1) th to (m + 2) light emitting modes. The drive control is performed so that the light emitting elements other than the at least one light emitting element emit light in accordance with the transition of the at least one light emitting element that sets the duty ratio to zero. Light production system described in 1.   A pachinko gaming machine provided with a game board, wherein the light effect system according to any one of claims 1 to 4 is provided in a part of the game board by the light effect device.

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