JP2012122854A - Test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize power supply voltage V, when testing a DUT changing an operation state without depending on a test pattern.SOLUTION: A DUT 1 is equipped with a notification circuit 50 which produces a notification signal S4 for notifying an event to the outside, before the generation of the event which generates changes in an operation current I. A main power supply 10 supplies electric power to a power supply terminal P1 of the DUT 1. A power supply compensation circuit 20 has a switch element which is controlled according to a control signal S, and produces a compensation pulse current according to an on/off state of the switch element. A compensation control circuit 52 receives the notification signal S4 from the DUT 1, and outputs the control signal Swhich is a signal for controlling the switch element and based on at least the notification signal S4 to the power supply compensation circuit 20.

Description

  The present invention relates to a power supply stabilization technique.

  When testing a semiconductor integrated circuit (hereinafter referred to as DUT) such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), and memory using CMOS (Complementary Metal Oxide Semiconductor) technology, flip-flops and latches in the DUT are When the clock is supplied, a current flows, and when the clock is stopped, the circuit becomes static and the current decreases. Therefore, the total operating current (load current) of the DUT varies from moment to moment depending on the contents of the test.

  A power supply circuit that supplies power to the DUT is configured using, for example, a regulator, and can ideally supply constant power regardless of the load current. However, an actual power supply circuit has an output impedance that cannot be ignored, and an impedance component that cannot be ignored exists between the power supply circuit and the DUT, so that the power supply voltage fluctuates due to load fluctuations.

  The fluctuation of the power supply voltage seriously affects the test margin of the DUT. In addition, fluctuations in the power supply voltage affect the operation of other circuit blocks in the test apparatus, such as a pattern generator that generates a pattern to be supplied to the DUT, and a timing generator that controls the pattern transition timing. Deteriorating accuracy.

  In the technique described in Patent Document 2, in addition to a main power supply that supplies a power supply voltage to a device under test, a compensation circuit including a switch that is controlled to be turned on and off by an output of a driver is provided. Then, a compensation control pattern for the switch element is defined in association with the test pattern so as to cancel the fluctuation of the power supply voltage that may occur according to the test pattern supplied to the device under test. During the actual test, the power supply voltage can be kept constant by switching the switch of the compensation circuit according to the control pattern while supplying the test pattern to the device under test.

JP 2007-205813 A International Publication No. 10 / 029709A1 Pamphlet

  The technique described in Patent Document 2 is based on the assumption that the operating current of the DUT can be predicted based on the test pattern. However, in a high function IC (Integrated Circuit) such as SoC (System On Chip), the operation state can be changed regardless of the test pattern.

  SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and one of the exemplary purposes of one aspect thereof is to supply power voltage when testing a device under test whose operating state can change without depending on a test pattern. Is to provide technology to stabilize

One embodiment of the present invention relates to a test apparatus for testing a device under test. Prior to the occurrence of an event that causes a change in the operating current, the device under test includes a notification circuit that generates a notification signal for notifying the event to the outside. The test apparatus includes a main power supply that supplies power to the power supply terminal of the device under test, a power supply compensation circuit, and a compensation control circuit.
The power supply compensation circuit includes at least one of a source compensation circuit and a sink compensation circuit. The source compensation circuit has a switch element that is controlled according to a control signal, generates a compensation pulse current according to the ON / OFF state of the switch element, and supplies the compensation pulse current from a power supply terminal through a path different from the main power supply. Configured to inject. The sink compensation circuit has a switch element controlled according to the control signal, generates a compensation pulse current according to the ON / OFF state of the switch element, and compensates from the power supply current flowing from the main power supply to the device under test. The pulse current is configured to be drawn in a different path from the device under test. The compensation control circuit receives a notification signal indicating the operation state from the device under test, and outputs a control signal for controlling the switch element, and at least a control signal based on the notification signal to the switch element.

  According to this aspect, even in a situation where the device under test operates autonomously without depending on the test pattern, the operation current waveform of the device under test is predicted based on the notification signal, and according to the predicted operation current waveform By generating the compensation current in the power supply compensation circuit, fluctuations in the power supply voltage can be suppressed or an intentional power supply voltage can be caused.

The device under test includes a plurality of cores, and the event may be switching of the number of active cores.
The device under test is configured such that its operating frequency is variable, and the event may be switching of the operating frequency of the device under test.

  The device under test includes a clock gating circuit, and the event may be switching the clock gating circuit on or off.

  The device under test includes a power gating circuit, and the event may be an on / off switching of power gating by the power gating circuit.

  The device under test may be an analog circuit device or an SoC (System On Chip) including an analog circuit, and the event may be switching of the operation mode of the analog circuit.

  The device under test may be an analog circuit device or an SoC including an analog circuit, and the event may be a setting change of the analog circuit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to an aspect of the present invention, a power supply voltage can be stabilized when testing a device under test whose operating state can change without depending on a test pattern.

It is a circuit diagram which shows the structure of the test apparatus which concerns on embodiment. It is a flowchart which shows an example of the method of calculating a control pattern. It is a wave form diagram which shows an example of operating current _IOP , power supply current _IDD , source compensation current _ICMP, and source pulse current _ISRC . 4A and 4B are circuit diagrams illustrating a configuration example of the power supply compensation circuit. FIGS. 5A to 5C are circuit diagrams illustrating another configuration example of the power supply compensation circuit. It is a block diagram which shows the structure of the test apparatus which concerns on embodiment. It is a time chart which shows operation | movement of the test apparatus of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram showing a configuration of a test apparatus 2 according to the embodiment. FIG. 1 shows a semiconductor device (hereinafter referred to as DUT) 1 to be tested in addition to a test apparatus 2.

The DUT 1 includes a plurality of pins, at least one of which is a power supply terminal P1 for receiving the power supply voltage V _DD , and at least one other is a ground terminal P2. A plurality of input / output (I / O) terminals P3 are provided to receive data from the outside or to output data to the outside, and at the time of testing, test signals (tests) output from the test apparatus 2 Pattern) S _TEST is received or data corresponding to the test signal S _TEST is output to the test apparatus 2. FIG. 1 shows a configuration for giving a test signal to the DUT 1 among the configurations of the test apparatus 2, and a configuration for evaluating a signal from the DUT 1 is omitted.

  The test apparatus 2 includes a main power supply 10, a pattern generator PG, a plurality of timing generators TG and a waveform shaper FC, a plurality of drivers DR, and a power supply compensation circuit 20.

  The test apparatus 2 includes a plurality of n channels CH1 to CHn, some of which (CH1 to CH4) are allocated to the plurality of I / O terminals P3 of the DUT1. Although FIG. 1 shows a case where n = 6, the actual number of channels of the test apparatus 2 is on the order of hundreds to thousands.

The main power supply 10 generates a power supply voltage V _DD to be supplied to the power supply terminal P1 of the DUT 1. For example, the main power supply 10 is composed of a linear regulator, a switching regulator, and the like, and feedback-controls the power supply voltage V _DD supplied to the power supply terminal P1 so as to coincide with the target value. The capacitor Cs is provided to smooth the power supply voltage V _DD . The main power supply 10 generates a power supply voltage for other blocks inside the test apparatus 2 in addition to a power supply voltage for the DUT 1. The output current from the main power supply 10 to the power terminal P1 of DUT1, referred to as the power supply current _{I DD.}

The main power supply 10 are the voltage and current source having a response speed of the finite, there is a case where the load current, i.e. can not follow the abrupt change in the operating current I _OP of DUT1. For example, when the operating current I _OP changes stepwise, the power supply voltage V _DD may overshoot or undershoot, or be accompanied by subsequent ringing. Variations in the power supply voltage V _DD prevent accurate testing of DUT 1. This is because when an error is detected in DUT 1, it cannot be distinguished whether it is due to defective manufacturing of DUT 1 or due to fluctuations in power supply voltage V _DD .

The power supply compensation circuit 20 is provided to compensate for the response speed of the main power supply 10. The designer of the DUT 1 can estimate the time transition such as the operation rate of the internal circuit of the DUT 1 in a state where a certain known test signal S _TEST (test pattern S _PTN ) is supplied, so the operating current I _{OP of the} DUT 1 The time waveform can be accurately predicted. Here, the prediction includes calculation using computer simulation, actual measurement for devices having the same configuration, and the method is not particularly limited.

On the other hand, if the response speed (gain, feedback band) of the main power source 10 is known, the power source current I _DD generated by the main power source 10 in response to the predicted operating current I _OP can also be predicted. Then, the power supply voltage V _DD can be stabilized by making up the difference between the predicted operating current I _OP and the power supply current I _DD by the power supply compensation circuit 20.
A differential or integral relationship is established between the power supply voltage V _DD ′ and the power supply current I _DD . Specifically, depending on whether the impedance of the main power supply 10 and the path from the main power supply 10 to the power supply terminal P1 is dominant, capacitive, inductive, or resistive, the relationship between voltage and current differentiation and integration Is determined.

The power supply compensation circuit 20 includes a source compensation circuit 20a and a sink compensation circuit 20b. The source compensation circuit 20a can be switched on and off according to the control signal _SCNTa . When the source compensation circuit 20a is turned on in response to the control signal _SCNTa , a compensation pulse current (also referred to as a source pulse current) I _SRC is generated. The power supply compensation circuit 20 injects the source pulse current I _SRC into the power supply terminal P1 from a different path from the main power supply 10.

Similarly, the sink compensation circuit 20b can be switched on and off in accordance with the control signal _SCNTb . When sync compensation circuit 20b is turned on in response to the control signal _{S CNTb,} the compensation pulse current _{I SINK} (also referred to as a sink pulse current) is generated. Power compensation circuit 20 draws from the power supply current _{I DD} flowing into the power source terminal P1, the sync pulse current _{I SINK,} a separate path from the DUT1.

Between the operating current I _OP flowing into the power supply terminal P1 of the DUT 1, the power supply current I _DD output from the main power supply 10, and the compensation current _ICMP output from the power supply compensation circuit 20, Formula (1), (2) holds.
I _OP = I _DD + I _CMP (1)
_{I CMP = I SRC -I SINK ...} (2)
That is, the positive component of the compensation current _{I CMP} is supplied from the source compensation circuit 20a as the source pulse current _{I SRC,} negative components of the compensation current _{I CMP} is supplied from the sink compensation circuit 20b as a sink pulse current _{I SINK} .

Of the driver _DR 1 _{~DR 6,} the driver DR ₆ is assigned to the source compensation circuit 20a, the driver DR ₅ are assigned to the sink compensation circuit 20b. The other at least one driver DR _{1 to} DR ₄ is assigned to at least one I / O terminal P 3 of the DUT 1. The pattern generator PG, the drivers DR ₅ and DR ₆ , and the interface circuits 4 ₅ and 4 ₆ can be understood as control circuits that control the power supply compensation circuit 20.

The waveform shaper FC and the timing generator TG are collectively referred to as an interface circuit 4. The plurality of 4 ₁ to 4 ₆ are provided for each of the channels CH _{1 to} CH ₆ , in other words, for each of the drivers DR ₁ to DR ₆ . The i-th (1 ≦ i ≦ 6) interface circuit 4 _{i shapes the} input pattern signal S _PTNi into a signal format suitable for the driver DR, and outputs it to the corresponding driver DR _i .

The pattern generator PG generates a pattern signal _SPTN for the interface circuits 4 ₁ to 4 ₆ based on the test program. Specifically, for the drivers DR _{1 to} DR ₄ assigned to the I / O terminal P3 of the DUT 1, the pattern generator PG describes a test pattern S _PTNi that describes the test signal S _TESTi that each driver DR _i should generate. Is output to the interface circuit 4 _i corresponding to the driver DR _i . The test pattern S _PTNi includes data indicating the level in each cycle (unit interval) of the test signal S _TESTi and data describing the timing at which the signal level transitions.

The pattern generator PG generates the control patterns _{S PTN_CMP} for compensation which is determined according to the required compensation current _{I CMP.} Control pattern _{S PTN_CMP} includes a control pattern _{S PTN_CMPa} describing a control signal _{S CNTa} be generated driver DR ₆ which is assigned to the source compensation circuit 20a is, sink compensation circuit 20b to the assigned driver DR ₅ is controlled to be generated A control pattern S _{PTN_CMPb} describing the signal S _CNTb is included. The control patterns S _{PTN_CMPa} and S _{PTN_CMPb} include data designating the on / off state of the source compensation circuit 20a and the sink compensation circuit 20b in each cycle, and data describing the timing for switching on / off.

The pattern generator PG generates control patterns S _{PTN_CMPa} and S _{PTN_CMPb} that can compensate for the test patterns S _{PTN1 to} S _PTN4 , that is, according to the variation of the operating current of the DUT 1, and the corresponding interface circuit 4 _6. 4 and ₅ are output.

As described above, if the test patterns S _{PTN1 to} S _PTN4 are known, the time waveform of the operating current I _OP of the DUT 1 can be predicted, and the compensation current I _CMP to be generated in order to keep the power supply voltage V _DD constant, that is, The time waveforms of I _SRC and I _SINK can be calculated.
When the predicted operating current I _OP is larger than the power supply current I _DD , the power supply compensation circuit 20 generates the source compensation current I _SRC to compensate for the insufficient current. Since the current waveform required for the source compensation current I _SRC can be predicted, the source compensation circuit 20a is controlled so that it can be appropriately obtained. For example, the source compensation circuit 20a may be controlled by pulse width modulation. Alternatively, pulse amplitude modulation, ΔΣ modulation, pulse density modulation, pulse frequency modulation, or the like may be used.

FIG. 2 is a flowchart illustrating an example of a method for calculating a control pattern. Based on the test pattern and circuit information input to the DUT 1, the operating current I _{OP of the} DUT 1 is estimated (S100). Further, when the DUT 1 is connected to the main power source 10 as a load, when the event occurs in the DUT 1, the power source current I _DD output from the main power source 10 is calculated (S102). Then, when it is desired to achieve an ideal power is the difference between the estimated operating current _{I OP} and the power supply current _{I DD,} the compensation current _{I CMP} to be generated by the power supply compensation circuit 20 (S104).

Then, by applying ΔΣ modulation, PWM (pulse width modulation), PDM (pulse density modulation), PAM (pulse amplitude modulation), PFM (pulse frequency modulation), etc. to the waveform of the compensation current _ICMP to be generated, a bit is obtained. A stream control pattern _{SPTN_CMP} is generated (S106). For example, the compensation current _ICMP may be sampled every test cycle, and the sampled compensation current _ICMP may be pulse-modulated.

FIG. 3 is a waveform diagram showing an example of the operating current I _OP , the power supply current I _DD , the source compensation current _ICMP, and the source pulse current I _SRC . It is assumed that the operating current I _{OP of the} DUT 1 to which a certain test signal S _TEST is supplied increases stepwise. In response to this, the power supply current I _DD is supplied from the main power supply 10, but it does not become an ideal step waveform due to the limitation of the response speed, and the current to be supplied to the DUT 1 is insufficient. As a result, unless the compensation current I _SRC is supplied, the power supply voltage V _DD decreases as shown by a broken line.

The power supply compensation circuit 20 generates a source compensation current _ICMP corresponding to the difference between the operating current _IOP and the power supply current _IDD . The source compensation current I _CMP is given by the source pulse current I _SRC generated according to the control signal S _CNTa . The source compensation current _ICMP needs to be the maximum amount immediately after the change of the operating current _IOP , and then needs to be gradually reduced. Thus, for example, the necessary source compensation current _ICMP can be generated by reducing the on-time (duty ratio) of the source compensation circuit 20a with time using PWM (pulse width modulation).

When all the channels of the test apparatus 2 operate synchronously according to the test rate, the cycle of the control signal _{SCNTa is} the cycle of data supplied to the DUT 1 (unit interval), an integral multiple thereof, or an integral fraction. Equivalent to. For example, in the unit interval is 4ns system, the control signal if the _S period of the _CNTa is 4ns, each pulse of the ON period _{T ON} contained in the control signal _{S CNTa} can be adjusted between 0～4Ns. The response speed of the main power source 10 is on the order of a few hundred ns~ number .mu.s, the waveform of the compensation current I _CMP can be controlled by hundreds of pulses contained in the control signal S _CNTa. A method of deriving the control signal _SCNTa necessary for generating the source compensation current I _{SRC from} the waveform will be described later.

If the operating current _{I OP} to the opposite is smaller than the power supply current _{I DD,} the power supply compensation circuit 20 as the sink compensation current _{I CMP} is obtained by generating a sync pulse current _{I SINK,} pull the excessive current.

By providing the power supply compensation circuit 20, the lack of response speed of the main power supply 10 can be compensated, and the power supply voltage V _DD can be kept constant as shown by a solid line in FIG. 3. Further, as described above, since the power supply compensation circuit 20 can generate a pulse current having a stable amplitude, the power supply voltage can be compensated with high accuracy.

  The above is the description of the entire test apparatus 2.

Next, a specific configuration example of the power supply compensation circuit 20 will be described.
4A and 4B are circuit diagrams illustrating a configuration example of the power supply compensation circuit 20.
Reference is made to FIG. The source compensation circuit 20a includes a voltage source 22 that generates a voltage Vx higher than the power supply voltage V _DD and a source switch SW1. The source switch SW1 is provided between the output terminal of the voltage source 22 and the power supply terminal P1.
If the voltage Vx and the power supply voltage V _DD are constant, the amplitude of the source current I _SRC is as follows when the source switch SW1 is on.
I _SRC = (Vx−V _DD ) / R _ON1
Given in. R _ON1 is the ON resistance of the source switch SW1. 4A and 4B have an advantage that the power supply compensation circuit 20 can be configured to be small.

The sink compensation circuit 20b includes a sink switch SW2 provided between the power supply terminal P1 and the ground terminal. If the power supply voltage _{V DD} is constant, in a state where the sync switch SW2 is turned on, the amplitude of sink current _{I SINK} is
I _SINK = V _DD / R _ON2
Given in. R _ON2 is an on-resistance of the sink switch SW2.

Turning to FIG. The source compensation circuit 20a includes a source current source 24a and a source switch SW1. The source current source 24a generates a reference current that defines the amplitude of the source pulse current _ISRC . The source switch SW1 is provided on the path of the reference current from the source current source 24a.
The sink compensation circuit 20b includes a sink switch SW2 and a sink current source 24b. Sink current source 24b generates a reference current for defining the amplitude of the sync pulse current _{I SINK.} The sink switch SW2 is provided on the path of the reference current from the sink current source 24b.

Source pulse current _{I SRC,} the amplitude of the sync pulse current _{I SINK} may several A are required. In this case, the sizes of the source switch SW1 and the sink switch SW2 in FIGS. 4A and 4B are increased, and the gate capacitance is also increased. Due to this gate capacitance, the switching response speed of the source switch SW1 and sink switch SW2 may be reduced, and a desired current may not be generated.
The source switch SW1, or variations in the ON resistance _{R ON1, R ON2} sink switch SW2, the control signal _{S CNTa,} the amplitude of the _{S CNTb} varies, the degree of on of each switch varies, the pulse current _{I SRC,} I There is a possibility that the amplitude of _SINK may fluctuate.

When such a problem becomes significant, the following technique may be used to solve the problem. FIGS. 5A to 5C are circuit diagrams illustrating another configuration example of the power supply compensation circuit 20.
The source compensation circuit 20a in FIG. 5A includes a current D / A converter 26a, a first transistor M1a, a second transistor M2a, and a source switch SW1.

The current D / A converter 26a generates a reference current I _REF corresponding to the digital setting signal D _SET . The first transistor M1a and the second transistor M2a form a current mirror circuit, and generates a sync pulse current _{I SINK} of the reference current _{I REF} and multiplying a predetermined coefficient (mirror ratio K).

Specifically, the first transistor M1a is a P-channel MOSFET, and is provided on the path of the reference current _IREF . The second transistor M2 is also a P-channel MOSFET, and its gate is commonly connected to the gate and drain of the first transistor M1a.

In FIG. 5A, the source switch SW1 is provided between the gate of the first transistor M1a and the gate of the second transistor M2a. For example, the source switch SW1 may be configured with a transfer gate as shown in FIG. 5A, may be configured with only an N-channel MOSFET, or may be configured with only a P-channel MOSFET. The on / off state of the source switch SW1 is switched according to the control signal _SCNTa .

  In FIG. 5A, the drain N2 of the first transistor M1a is connected to the terminal N1 on the gate side of the first transistor M1a of the source switch SW1.

While the control signal _SCNTa is at a high level, the source switch SW1 is turned on. Then, the source pulse current I _SRC proportional to the reference current I _REF is discharged from the output terminal P4 of the source compensation circuit 20a. While the control signal _SCNTa is at a low level, the source switch SW1 is turned off and the current mirror circuit does not operate, so that the source pulse current I _SRC becomes zero.

As described above, according to the source compensation circuit 20a of FIG. 5A, the source pulse current I _SRC that is switched in accordance with the control signal _SCNTa can be generated.
According to the source compensation circuit 20a of FIG. 5A, the stability of the amplitude of the source pulse current I _SRC can be improved. Further, since the driver DR is driven not by a switch through which a large current flows but by a switch provided at the gate of the current mirror circuit, high-speed switching is possible.

Further, the source compensation circuit 20a of FIG. 5 (a), the source switch SW1 is also in the off state, the reference current _{I REF} continues to flow in the first transistor M1a, the bias state of the first transistor M1a is maintained. Therefore, there is an advantage that the switching response speed of the source compensation circuit 20a with respect to the switching of the source switch SW1 is high.

  The sink compensation circuit 20b can be configured by switching the conductivity of the transistor of the source compensation circuit 20a and inverting the top and bottom. FIG. 5A shows a configuration example of the sink compensation circuit 20b. The sink compensation circuit 20b includes a current D / A converter 26b, N-channel MOSFET transistors M1b and M2b, and a sink switch SW2. The sink compensation circuit 20b has the same advantages as the source compensation circuit 20a.

5B and 5C show only the configuration of the sink compensation circuit 20b, and the source compensation circuit 20a is omitted.
In FIG. 5B, the position of the sink switch SW2 is different from that in FIG. In FIG. 5B, the drain N2 of the first transistor M1b is connected to the terminal N3 on the gate side of the second transistor M2b of the sink switch SW2.
With this configuration, similarly to the configuration of FIG. 5 (a), it has a stable amplitude, can generate a sync pulse current I _SINK switching speed.
In FIG. 5B, the reference current _IREF is cut off when the sink switch SW2 is off. Therefore, there is an advantage that the current consumption of the circuit can be reduced.

In FIG. 5C, the sink switch SW2 is provided between a gate N4 commonly connected to the first transistor M1b and the second transistor M2b and a fixed voltage terminal such as a ground terminal. If the sink switch SW2 is turned on while the control signal _SCNTb # (# indicates logic inversion) is at a high level, the gate voltages of the first transistor M1 and the second transistor M2 become the ground voltage, so that the current mirror circuit is turned off. and sink pulse current _{I sINK} is interrupted. When the control signal _{S CNTb} # is low, when the sink switch SW2 is turned off, the current mirror circuit is turned on, flows sink pulse current _{I SINK.}

According to the configuration of FIG. 5 (c), the similar to FIG. 5 (a), (b) , it has a stable amplitude, can generate a sync pulse current _{I SINK} switching speed. Needless to say, the modifications of FIGS. 5B and 5C are also applicable to the source compensation circuit 20a.
Furthermore, the configuration shown in FIG. 5C may be combined with the configuration shown in FIG.

Further, the current flowing through the internal elements constituting the DUT 1, that is, the operating current I _OP varies due to process variations. That is, the waveform of the operating current of the DUT 1 to which a certain test pattern is supplied increases or decreases due to process variations. Therefore, prior to DUT1 testing process, by adjusting the amplitude of the compensation pulse current calibrate process, even as the operating current I _OP of DUT1 is varied by the process variations, to keep the power environment constant it can. This calibration can be realized by changing the value of the digital set value D _SET for the current D / A converters 26a and 26b.

  The above is the configuration example of the power supply compensation circuit 20.

In the above description, the operating current I _OP of DUT1 have assumed that it is predictable based on the test pattern. However, in a high function IC (Integrated Circuit) such as SoC (System On Chip), the operation state can be changed regardless of the test pattern. In particular, devices that will be developed in the future may operate more autonomously or unpredictably from the outside than current devices. Therefore, hereinafter, a test apparatus capable of stabilizing the power supply voltage V _DD when testing such a DUT 1 will be described.

FIG. 6 is a block diagram illustrating a configuration of the test apparatus 2 according to the embodiment. The DUT 1 includes a notification circuit 50 that issues a notification signal S4. The notification circuit 50, prior to the occurrence of an event causing a change in the operating current I _OP of DUT1 (also referred to as a characteristic point events), the notification signal S4 for notifying the occurrence of the event to the outside through a terminal P4 Output to the outside. The notification signal S4 may include data indicating information accompanying the event. The notification circuit 50 may be a circuit based on a so-called DFT (Design For Test) concept, or a circuit mounted for a purpose other than the test may be used for event detection during the test.

Examples of the DUT 1 and its feature point event are as follows.
1. The DUT 1 may be a multi-core processor including a plurality of cores. The DUT 1 changes the number of autonomously active cores. In the DUT 1, the number of active cores changes according to the amount of calculation, and the operating current I _{OP of the} DUT 1 changes according to the number. That is, the number of active cores can be a feature point event. In this case, the notification signal S4 may include data indicating the number of active cores after switching.

2. The DUT 1 may be configured such that its operating frequency is variable, and the operating frequency can be switched autonomously. The operating current I _OP of DUT1, because that can vary depending on the operating frequency f, switching the operating frequency f can be a feature point event. In this case, the notification signal S4 may include data indicating the operating frequency f before and after switching.

  3. The DUT 1 may include a clock gating circuit and / or a power gating circuit used to reduce power consumption. In this case, for example, the current consumption of the DUT 1 can fluctuate greatly at the timing when the clock gating circuit or the power gating circuit operates or does not operate. That is, switching the clock gating circuit and power gating circuit on and off can be a feature point event.

  4). For example, the DUT 1 may be an SoC (System on Chip) device including an analog circuit device or an analog circuit. For example, the characteristic point event of the analog circuit can be exemplified by changing the setting or switching the operation mode.

The test apparatus 2 includes a compensation control circuit 52. Compensation control circuit 52 receives the notification signal S4 from DUT1, the control signal _S CNTa for controlling the switching elements of the power supply compensation circuit 20 (SW1, _SW2), and generates an _{S CNTb.} The control signals S _CNTa and S _CNTb are based at least on the notification signal S4. Of course, the operating current I _{OP of the} DUT 1 may correspond to _{SPTN in} the test pattern. In this case, the compensation control circuit 52, in addition to the notification signal S4, the control signal _S CNTa corresponding to the test pattern _{S PTN,} generates an _{S CNTb.}

The compensation control circuit 52 includes interface circuits 4 ₅ and 4 ₆ assigned to the source switch SW1 and the sink switch SW2, drivers DR ₅ and DR _6, and a part of the pattern generator PG (referred to as a control pattern generation unit 54). May be.

The control pattern generation unit 54 detects a feature point event that will occur in the DUT 1 based on the notification signal S4. DUT1 designer (i.e. the test apparatus 2 user), the variation of the operating current I _OP generated in DUT1 by each feature point event, can be known in advance by simulation or actual measurement other means. The designer is able to calculate the compensation current I _CMP required to cancel the variation of the operating current I _OP. Control pattern generation unit 54, for each feature point events that may occur in the DUT1, control pattern _{S PTN_CMPa} capable of canceling the change in the operating current _{I OP} with it, generating configured to allow _{S PTN_CMPb.} For example, the control pattern generation unit 54 may include a pattern memory that holds the control patterns S _{PTN_CMPa} and S _{PTN_CMPb,} and may read the control pattern each time a feature point event occurs. Alternatively, the control pattern may be generated by another method.

When the control pattern generation unit 54 generates the control patterns S _{PTN_CMPa} and S _{PTN_CMPb} , the corresponding control signals S _CNTa and S _CNTb are supplied to the power supply compensation circuit 20 to compensate the fluctuation of the operating current I _{OP. CMP} is generated.

  The above is the configuration of the test apparatus 2. Next, the operation will be described. FIG. 7 is a time chart showing the operation of the test apparatus 2 of FIG. Here, it is assumed that DUT1 is a multi-core processor and the feature point event is a switch of the number of active cores.

In the initial state, M cores are active, and a certain amount of operating current I _OP (M) flows through DUT 1. At time t2, when the number of cores in which DUT 1 is autonomously switched to N, the operating current I _OP changes. At time t1 prior to time t2, the DUT 1 issues a notification signal S4 to notify the test apparatus 2 of switching of the number of cores. Further, the notification signal S4 may include timing data D3 indicating the timing t2 at which the number of cores is actually switched in the DUT 1. The timing data D3 may be data indicating a waiting time (delay time) from the issue timing t1 of the notification signal S4 to the core switching timing t2.

The compensation control circuit 52 that has received the notification signal S4 generates a control signal _SCMPa corresponding to the feature point event indicated by the notification signal S4 at an appropriate timing. Thereby, change in the power supply voltage _{V DD} due to variations in the operating current _{I CMP} at time t2 is inhibited.

The amount of compensation current I _CMP to be generated depends on the difference between the operating current I _OP (M) before time t2 and the operating current I _OP (N) after time t2, and the operating current I _OP (M) And I _OP (N) may depend on the number of cores M and N, respectively. In this case, it is necessary to generate the compensation current _ICMP according to the number of cores M and N. Therefore, the notification signal S4 generated by the DUT 1 may include accompanying data D2 indicating the number M of cores before switching and the number N of cores after switching, in addition to the data D1 indicating switching of the number of cores. Good. Thus, the compensation control circuit 52 can generate an appropriate amount of compensation current _ICMP . Thus, the notification signal S4 may include ancillary data needed to predict the change in the operating current I _OP of DUT1.

Thus, according to the test apparatus 2 according to the embodiment, the operating current waveform of the DUT 1 is predicted and predicted based on the notification signal S4 even in a situation where the DUT 1 operates autonomously without depending on the test pattern. By causing the power supply compensation circuit 20 to generate the compensation current _ICMP according to the operated current waveform, fluctuations in the power supply voltage V _DD can be suppressed.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

In addition to what has been described in the embodiment, examples of DUT 1 that operates autonomously and its characteristic point events include the following, and DUT 1 that targets these is also included in the present invention.
For example, DUT 1 may include a PLL (Phase Locked Loop) circuit. Depending on the DUT, a certain operation may be started after the PLL circuit is locked, so that the PLL circuit can be locked as a feature point event.

Alternatively, the DUT 1 may include a flash memory. The flash memory is in a busy state until the writing is completed after instructing writing (or erasing), and the timing of completing the writing does not depend on the test pattern. That is, at the timing when writing is completed in the DUT 1, the operating current I _OP can be reduced, so that writing completion or erasing completion can be a feature point event. Since the current flash memory generates a flag signal (R / B signal) indicating a ready / busy state after writing is completed, if a control signal is generated based on the R / B signal, the response is not in time. . Therefore, if the DUT 1 is configured so that the R / B signal is generated immediately before the completion of writing, a compensation current can be generated at an appropriate timing.

In the embodiment, a case has been described in which the compensation current _ICMP realizes an ideal power supply environment in which the fluctuation of the power supply voltage is zero, that is, the output impedance is zero. However, the present invention is not limited thereto. In other words, to calculate the waveform of a compensation current I _CMP to cause deliberate supply voltage variation, it may have been prescribed to control patterns S _{PTN_CMP} as its compensation current waveform is obtained. In this case, an arbitrary power supply environment can be emulated according to the control pattern _{SPTN_CMP} .

  In the embodiment, the case where the power supply compensation circuit 20 includes the source compensation circuit 20a and the sink compensation circuit 20b has been described. However, the present invention is not limited to this, and only one of the configurations may be employed.

If the source compensation circuit 20a provided only may generate a constant current I _DC to the source compensation circuit 20a. When the power supply current I _DD is insufficient with respect to the operating current I _OP , the current I _SRC generated by the source compensation circuit 20a may be relatively increased from the steady current I _DC . On the other hand, when the power supply current I _DD is excessive with respect to the operating current I _OP , the current I _SRC generated by the source compensation circuit 20a may be relatively decreased from the steady current I _DC .
When the sink compensation circuit 20b is provided only it may generate a constant current I _DC to the sink compensation circuit 20b. When the power supply current _{I DD} is insufficient relative to the operating current _{I OP} is the current _{I SINK} sink compensation circuit 20b is generated, may be relatively decreased from constant current _{I DC.} Conversely, when the power supply current _{I DD} is excessive relative to the operating current _{I OP} is the current _{I SINK} sink compensation circuit 20b is generated, may be relatively increased from a steady current _{I DC.}
Thus, the current consumption of the entire test device is increased steady current I _DC component therewith in exchange for, only a single switch, the compensation current I _SRC, it is possible to generate I _SINK.

DESCRIPTION OF SYMBOLS 1 ... DUT, 2 ... Test apparatus, PG ... Pattern generator, TG ... Timing generator, FC ... Waveform shaper, 4 ... Interface circuit, DR ... Driver, 10 ... Main power supply, 20 ... Power supply compensation circuit, 20a ... Source Compensation circuit, 20b ... sink compensation circuit, P1 ... power supply terminal, P2 ... ground terminal, P3 ... I / O terminal, SW1 ... source switch, SW2 ... sink switch, 22 ... voltage source, 24a ... source current source, 24b ... sink Current source, 26 ... current D / A converter, M1 ... first transistor, M2 ... second transistor, 50 ... notification circuit, 52 ... compensation control circuit, 54 ... control pattern generator, S4 ... notification signal.

Claims (7)

A test apparatus for testing a device under test,
The device under test includes a notification circuit that generates a notification signal for notifying the outside of the event prior to the occurrence of an event that causes a change in the operating current,
The test apparatus comprises:
A main power supply for supplying power to the power supply terminal of the device under test;
A switching element controlled in accordance with a control signal; generates a compensation pulse current according to an on / off state of the switching element; and injects the compensation pulse current into the power supply terminal from a path different from the main power supply A source compensation circuit configured to control and a switch element controlled according to a control signal, generating a compensation pulse current according to an on / off state of the switch element, and generating the compensation pulse current from the main power source A power compensation circuit including at least one of a sink compensation circuit configured to draw the compensation pulse current to a path different from the device under test from a power supply current flowing to the device;
A compensation control circuit that receives the notification signal from the device under test and controls the switch element, and outputs a control signal based on at least the notification signal to the switch element;
A test apparatus comprising:   The test apparatus according to claim 1, wherein the device under test includes a plurality of cores, and the event is switching of the number of active cores.   The test apparatus according to claim 1, wherein the device under test is configured such that an operating frequency thereof is variable, and the event is switching of the operating frequency of the device under test. The device under test includes a clock gating circuit,
The test apparatus according to claim 1, wherein the event is an on / off switching of the clock gating circuit. The device under test includes a power gating circuit,
The test apparatus according to claim 1, wherein the event is switching of power gating on and off by the power gating circuit. The device under test is an analog circuit device or a SoC (System On Chip) including an analog circuit,
The test apparatus according to claim 1, wherein the event is switching of an operation mode of the analog circuit. The device under test is an analog circuit device or a SoC including an analog circuit,
The test apparatus according to claim 1, wherein the event is a setting change of the analog circuit.

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