JP2012098183A - Power supply apparatus and testing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a testing apparatus capable of keeping a power supply voltage constant by a simple configuration.SOLUTION: A power supply apparatus is provided to supply a power supply voltage to a semiconductor device. A main power supply 10 supplies power to a power supply terminal P1 of the semiconductor device. A source switch 12b of a power supply compensation circuit 12 is provided between the power supply terminal P1 and a ground terminal. The power compensation circuit 12 generates a current Iwith a source switch 12b being set to normally-on, and injects the amount of change in the current at the time when the source switch 12b is turned off by switching, as a source compensation current I, to the power supply terminal P1 of the semiconductor device.

Description

  The present invention relates to a power supply stabilization technique.

  When testing a semiconductor integrated circuit (hereinafter referred to as DUT) such as a CPU (Central Processing Unit), DSP (Digital Signal Processor), and memory using CMOS (Complementary Metal Oxide Semiconductor) technology, flip-flops and latches in the DUT are When the clock is supplied, a current flows, and when the clock is stopped, the circuit becomes static and the current decreases. Therefore, the total operating current (load current) of the DUT varies from moment to moment depending on the contents of the test.

  A power supply circuit that supplies power to the DUT is configured using, for example, a regulator, and can ideally supply constant power regardless of the load current. However, an actual power supply circuit has an output impedance that cannot be ignored, and an impedance component that cannot be ignored exists between the power supply circuit and the DUT, so that the power supply voltage fluctuates due to load fluctuations.

  The fluctuation of the power supply voltage seriously affects the test margin of the DUT. In addition, fluctuations in the power supply voltage affect the operation of other circuit blocks in the test apparatus, such as a pattern generator that generates a pattern to be supplied to the DUT, and a timing generator that controls the pattern transition timing. Deteriorating accuracy.

  In the technique described in Patent Document 2, in addition to a main power supply that supplies a power supply voltage to a device under test, a compensation circuit including a switch that is controlled to be turned on and off by an output of a driver is provided. Then, a compensation control pattern for the switch element is defined in association with the test pattern so as to cancel the fluctuation of the power supply voltage that may occur according to the test pattern supplied to the device under test. During the actual test, the power supply voltage can be kept constant by switching the switch of the compensation circuit according to the control pattern while supplying the test pattern to the device under test.

JP 2007-205813 A International Publication No. 10 / 029709A1 Pamphlet

In the configuration of FIG. 1 of Patent Document 2, a power source that generates a voltage higher than that is required in addition to the main power source that generates the power source voltage V _DD to be supplied to the DUT. The addition of such an auxiliary power source complicates the system.

  An aspect of the present invention has been made in view of such a situation, and one of exemplary purposes of the aspect is to provide a test apparatus capable of keeping a power supply voltage constant with a single power supply. is there.

  One embodiment of the present invention relates to a power supply apparatus that supplies a power supply voltage to a semiconductor device. The power supply apparatus is a power supply apparatus that supplies a power supply voltage to a semiconductor device, and includes a main power supply that supplies power to a power supply terminal of the semiconductor device, and a source switch provided between the power supply terminal and the ground terminal, A power supply compensation circuit that generates a current when the switch is normally turned on and injects a change amount of the current when the source switch is turned off by switching into a power supply terminal of the semiconductor device as a source compensation current.

  Another aspect of the present invention relates to a test apparatus for testing a device under test. This test apparatus includes a main power supply that supplies power to the power supply terminal of the device under test, and a source switch provided between the power supply terminal and the ground terminal. A power compensation circuit that injects the amount of change in current when the switch is turned off as a source compensation current to the power supply terminal of the device under test, one of which is assigned to the source switch, and at least one of the other is at least one of the devices under test A plurality of drivers assigned to one input / output terminal and a plurality of interface circuits each provided for each driver, each of which shapes the input pattern signal and outputs it to the corresponding driver Assigned to the I / O terminal of the device under test A test pattern describing a test signal to be output by a given driver is output to the interface circuit corresponding to the driver, and a control pattern determined according to the test pattern is output to the driver assigned to the source switch. A pattern generator for outputting to a corresponding interface circuit.

  According to these aspects, a simple system that does not use a power supply in addition to the main power supply can inject auxiliary current into the power supply terminal of the semiconductor device to suppress fluctuations in the power supply voltage.

In one embodiment, the source switch may be an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
In this case, since the source potential of the source switch becomes the ground voltage, the gate-source voltage is not easily affected by fluctuations in the power supply voltage. As a result, a stable compensation current can be generated.

  The power supply compensation circuit further includes a sink switch provided between the power supply terminal and the ground terminal. The sink switch is normally off, and the current that flows when the sink switch is turned on by switching is drawn to a path different from that of the semiconductor device. But you can.

  Yet another embodiment of the present invention is also a power supply device. The power supply apparatus includes a main power supply that supplies power to a power supply terminal of a semiconductor device, an auxiliary power supply that generates a voltage higher than an output voltage of the main power supply, a capacitor connected to the output terminal of the auxiliary power supply, and a power supply for the semiconductor device. A power supply compensation that includes a source switch of a P-channel MOSFET provided between the terminal and the output terminal of the auxiliary power supply, and injects a current that flows when the source switch is turned on by switching to the power supply terminal of the semiconductor device as a source compensation current A circuit.

  According to this aspect, the capacitor is connected to the output of the auxiliary power supply, the output voltage is stabilized, and the source of the P-channel MOSFET that is the source switch is connected to the output terminal of the auxiliary power supply, whereby the on-resistance of the source switch Fluctuation can be suppressed, and accurate compensation becomes possible.

  A test apparatus according to still another aspect of the present invention is connected to a main power supply that supplies power to a power supply terminal of a device under test, an auxiliary power supply that generates a voltage higher than the output voltage of the main power supply, and an output terminal of the auxiliary power supply. And a source switch of a P-channel MOSFET provided between the power supply terminal of the device under test and the output terminal of the auxiliary power supply, and a current flowing when the source switch is turned on by switching is measured as a source compensation current. A power supply compensation circuit that injects into the power supply terminal of the test device, one of which is assigned to the source switch, and at least one of the other is assigned to at least one input / output terminal of the device under test. A plurality of interface circuits provided for each, each of which is input A test pattern that describes the test signals that should be output by the driver assigned to the input / output terminals of the device under test, and multiple interface circuits that shape the output pattern signal and output it to the corresponding driver And a pattern generator for outputting a control pattern determined according to the test pattern to the interface circuit corresponding to the driver assigned to the source switch.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other between methods and apparatuses are also effective as an aspect of the present invention.

  According to an aspect of the present invention, fluctuations in power supply voltage can be suppressed with a simple system.

1 is a circuit diagram showing a configuration of a test apparatus according to a first embodiment. It is a wave form diagram which shows the compensation pulse current produced | generated by a source switch. It is a flowchart which shows an example of the method of calculating a control pattern. It is a wave form diagram which shows an example of an operating current, a power supply current, a source compensation current, and a source pulse current. It is a wave form diagram which shows the control method for reducing power consumption. It is a block diagram which shows the structure of the test apparatus which concerns on 2nd Embodiment.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a test apparatus 2 according to the first embodiment. FIG. 1 shows a semiconductor device (hereinafter referred to as DUT) 1 to be tested in addition to a test apparatus 2.

The DUT 1 includes a plurality of pins, at least one of which is a power supply terminal P1 for receiving the power supply voltage V _DD , and at least one other is a ground terminal P2. A plurality of input / output (I / O) terminals P3 are provided to receive data from the outside or to output data to the outside, and at the time of testing, test signals (tests) output from the test apparatus 2 Pattern) S _TEST is received or data corresponding to the test signal S _TEST is output to the test apparatus 2. FIG. 1 shows a configuration for giving a test signal to the DUT 1 among the configurations of the test apparatus 2, and a configuration for evaluating a signal from the DUT 1 is omitted.

  The test apparatus 2 includes a main power supply 10, a pattern generator PG, a plurality of timing generators TG and a waveform shaper FC, a plurality of drivers DR, and a power supply compensation circuit 12.

  The test apparatus 2 includes a plurality of n channels CH1 to CHn, some of which (CH1 to CH4) are allocated to the plurality of I / O terminals P3 of the DUT1. Although FIG. 1 shows a case where n = 6, the actual number of channels of the test apparatus 2 is on the order of hundreds to thousands.

The main power supply 10 generates a power supply voltage V _DD to be supplied to the power supply terminal P1 of the DUT 1. For example, the main power supply 10 is composed of a linear regulator, a switching regulator, and the like, and feedback-controls the power supply voltage V _DD supplied to the power supply terminal P1 so as to coincide with the target value. The capacitor Cs is provided to smooth the power supply voltage V _DD . The main power supply 10 generates a power supply voltage for other blocks inside the test apparatus 2 in addition to a power supply voltage for the DUT 1. The output current from the main power supply 10 to the power terminal P1 of DUT1, referred to as the power supply current _{I DD.}

The main power supply 10 are the voltage and current source having a response speed of the finite, there is a case where the load current, i.e. can not follow the abrupt change in the operating current I _OP of DUT1. For example, when the operating current I _OP changes stepwise, the power supply voltage V _DD may overshoot or undershoot, or be accompanied by subsequent ringing. Variations in the power supply voltage V _DD prevent accurate testing of DUT 1. This is because when an error is detected in DUT 1, it cannot be distinguished whether it is due to defective manufacturing of DUT 1 or due to fluctuations in power supply voltage V _DD .

The power supply compensation circuit 12 is provided to compensate for the response speed of the main power supply 10. DUT1 designers, in a state with a known test signal _{S TEST} (test pattern _{S PTN)} is supplied, because it is possible to estimate the temporal transition of the operation rate of the internal circuit of DUT1, the operating current _{I OP} of DUT1 The time waveform can be accurately predicted. Here, the prediction includes calculation using computer simulation, actual measurement for devices having the same configuration, and the method is not particularly limited.

On the other hand, if the response speed (gain, feedback band) of the main power source 10 is known, the power source current I _DD generated by the main power source 10 in response to the predicted operating current I _OP can also be predicted. Then, the power supply voltage V _DD can be stabilized by compensating the predicted difference between the operating current I _OP and the power supply current I _DD by the power supply compensation circuit 12.
A differential or integral relationship is established between the power supply voltage V _DD ′ and the power supply current I _DD . Specifically, depending on whether the impedance of the main power supply 10 and the path from the main power supply 10 to the power supply terminal P1 is dominant, capacitive, inductive, or resistive, the relationship between voltage and current differentiation and integration Is determined.

The power supply compensation circuit 12 includes a source switch 12b and a sink switch 12c. Each of the source switch 12b and the sink switch 12c is a switch using an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is controlled in accordance with control signals _SCNT1 and _SCNT2 .

The source switch 12b has a power component of the DUT 1 as a compensation pulse current I _SRC (source pulse current) with a current component that the power source current I _DD is insufficient with respect to the operating current I _OP in order to suppress a decrease in the power source voltage V _DD. Inject into P1. The source switch 12b is provided between the output terminal of the main power supply 10a and the ground terminal, and a control signal _SCNT1 is input to its gate. The source switch 12b is normally to generate a current of a predetermined level I _DC in steady ON state.
That is, the output current I _DD of the main power supply 10 is constantly given by the following equation.
I _DD = I _OP + I _DC

When the source switch 12b is turned off in response to the control signal _SCNT1 , the current Is flowing through the source switch 12b suddenly becomes zero. Since the response of the main power supply 10 cannot follow the switching of the source switch 12b, the reduced amount of the current Is flowing through the source switch 12b is injected into the DUT 1 as the compensation pulse current I _SRC .

FIG. 2 is a waveform diagram showing the compensation pulse current I _SRC (I _CMP ) generated by the source switch 12b. The source switch 12b is turned on when the control signal _SCNT1 is at a high level and turned off when the control signal _SCNT1 is at a low level. The power supply compensation circuit 12 injects the source pulse current I _SRC into the power supply terminal P1 from a different path from the main power supply 10. The waveform of the effective compensation current _ICMP is given by the time average of the compensation pulse current _ICMP .

On the other hand, the sync switch 12c draws in order to suppress the increase of the power supply voltage _{V DD,} the excess power supply current _{I DD} for an operating current _{I OP} to another route as DUT1. Similarly to the source switch 12b, the sink switch 12c is provided between the output terminal and the ground terminal of the main power supply 10a, and the control signal _SCNT2 is input to the gate thereof. The sink switch 12c is normally off. When the sync switch 12c is turned on in response to the control signal _{S CNT2,} the compensation pulse current _{I SINK} (also referred to as a sink pulse current) is generated. The main power supply 10, can not follow the rapid off of the sink switch 12c, the power supply current _{I DD} flowing into the power source terminal P1, the sync pulse current _{I SINK} is drawn toward the other path and DUT1.

Between the operating current I _OP flowing into the power terminal P 1 of the DUT 1, the power source current I _DD output from the main power source 10, and the compensation current I _CMP output from the power source compensation circuit 12, from the current conservation law, (2) holds.
I _OP = I _DD + I _CMP (1)
_{I CMP = I SRC -I SINK ...} (2)

That is, the positive component of the compensation current _{I CMP} is supplied from the source switch 12b as a source pulse current _{I SRC,} negative components of the compensation current _{I CMP} is supplied from the sink switch 12c as a sink pulse current _{I SINK.}

Of the driver _DR 1 _{~DR 6,} the driver DR ₆ is assigned to the source switch 12b, the driver DR ₅ are assigned to the sink switch 12c. The other at least one driver DR _{1 to} DR ₄ is assigned to at least one I / O terminal P 3 of the DUT 1.

The waveform shaper FC and the timing generator TG are collectively referred to as an interface circuit 4. The plurality of 4 ₁ to 4 ₆ are provided for each of the channels CH _{1 to} CH ₆ , in other words, for each of the drivers DR ₁ to DR ₆ . The i-th (1 ≦ i ≦ 6) interface circuit 4 _{i shapes the} input pattern signal S _PTNi into a signal format suitable for the driver DR, and outputs it to the corresponding driver DR _i .

The pattern generator PG generates a pattern signal _SPTN for the interface circuits 4 ₁ to 4 ₆ based on the test program. Specifically, for the drivers DR _{1 to} DR ₄ assigned to the I / O terminal P3 of the DUT 1, the pattern generator PG describes a test pattern S _PTNi that describes the test signal S _TESTi that each driver DR _i should generate. Is output to the interface circuit 4 _i corresponding to the driver DR _i . The test pattern S _PTNi includes data indicating the level in each cycle (unit interval) of the test signal S _TESTi and data describing the timing at which the signal level transitions.

The pattern generator PG generates the control patterns _{S PTN_CMP} for compensation which is determined according to the required compensation current _{I CMP.} Control pattern _{S PTN_CMP} includes a control signal _{S CNT1} describing control pattern _{S PTN_CMP1} to be generated driver DR ₆ which is assigned to the source switch 12b is, the control signal S to be generated by the driver DR ₅ assigned to the sync switch 12c _It includes a control pattern _{SPTN_CMP2} that describes _CNT2 . Each of the control patterns S _{PTN_CMP1} and S _{PTN_CMP2} includes data designating the on / off state of the source switch 12b and the sink switch 12c in each cycle, and data describing the timing for switching on / off.

The pattern generator PG generates control patterns S _{PTN_CMP1} and S _{PTN_CMP2} that can compensate for the test patterns S _{PTN1 to} S _PTN4 , that is, according to fluctuations in the operating current of the DUT 1, and corresponding interface circuits 4 _6. 4 and ₅ are output.

As described above, if the test patterns S _{PTN1 to} S _PTN4 are known, the time waveform of the operating current I _OP of the DUT 1 can be predicted, and the compensation current I _CMP to be generated in order to keep the power supply voltage V _DD constant, that is, The time waveforms of I _SRC and I _SINK can be calculated.
If the predicted operating current I _OP is larger than the power supply current I _DD , the power supply compensation circuit 12 generates a source compensation current I _SRC to compensate for the insufficient current. Since the current waveform required for the source compensation current I _SRC can be predicted, the source switch 12b is controlled so that it can be appropriately obtained. For example, the source switch 12b may be controlled by pulse width modulation. Alternatively, pulse amplitude modulation, ΔΣ modulation, pulse density modulation, pulse frequency modulation, or the like may be used.

FIG. 3 is a flowchart illustrating an example of a method for calculating a control pattern. Based on the test pattern and circuit information given to the DUT 1, the operating current I _{OP of the} DUT 1 is estimated (S100). Further, when the DUT 1 is connected to the main power source 10 as a load, when the event occurs in the DUT 1, the power source current I _DD output from the main power source 10 is calculated (S102). Then, when it is desired to achieve an ideal power is the difference between the estimated operating current _{I OP} and the power supply current _{I DD,} the compensation current _{I CMP} to be generated by the power supply compensation circuit 12 (S104).

Then, by applying ΔΣ modulation, PWM (pulse width modulation), PDM (pulse density modulation), PAM (pulse amplitude modulation), PFM (pulse frequency modulation), etc. to the waveform of the compensation current _ICMP to be generated, a bit is obtained. A stream control pattern _{SPTN_CMP} is generated (S106). For example, the compensation current _ICMP may be sampled every test cycle, and the sampled compensation current _ICMP may be pulse-modulated.

The above is the configuration of the test apparatus 2. Next, the operation will be described.
In FIG. 4, ignores the effects of constant current I _DC source switch 12b is produced. FIG. 4 is a waveform diagram showing an example of the operating current I _OP , the power supply current I _DD , the source compensation current I _SRC and the source pulse current I _SRC . It is assumed that the operating current I _{OP of the} DUT 1 to which a certain test signal S _TEST is supplied increases stepwise. In response to this, the power supply current I _DD is supplied from the main power supply 10, but it does not become an ideal step waveform due to the limitation of the response speed, and the current to be supplied to the DUT 1 is insufficient. As a result, unless the compensation current I _SRC is supplied, the power supply voltage V _DD decreases as shown by a broken line.

The power supply compensation circuit 12 generates a source compensation current _ICMP corresponding to the difference between the operating current _IOP and the power supply current _IDD . The source compensation current I _CMP is given by the source pulse current I _SRC generated according to the control signal S _CNT1 . The source compensation current _ICMP needs to be the maximum amount immediately after the change of the operating current _IOP , and then needs to be gradually reduced. Therefore, for example, the necessary source compensation current _ICMP can be generated by reducing the on-time (duty ratio) of the source switch 12b with time using PWM (pulse width modulation).

When all the channels of the test apparatus 2 operate synchronously according to the test rate, the cycle of the control signal _{SCNT1 is} the cycle of data supplied to the DUT 1 (unit interval), an integral multiple thereof, or a fraction of an integer. Equivalent to. For example, in the unit interval is 4ns system control if the period of the signal _{S CNT1} is 4ns, each pulse of the ON period _{T ON} contained in the control signal _{S CNT1} is, can be adjusted between 0～4Ns. The response speed of the main power source 10 is on the order of a few hundred ns~ number .mu.s, the waveform of the compensation current I _CMP can be controlled by hundreds of pulses contained in the control signal S _CNT1. A method of deriving the control signal _SCNT1 necessary for generating the source compensation current I _{SRC from} the waveform will be described later.

If the operating current _{I OP} to the opposite is smaller than the power supply current _{I DD,} the power supply compensation circuit 12 as the sink compensation current _{I CMP} is obtained by generating a sync pulse current _{I SINK,} pull the excessive current.

The above is the operation of the test apparatus 2.
Thus, by providing the power supply compensation circuit 12, the shortage of the response speed of the main power supply 10 can be compensated, and the power supply voltage V _DD can be kept constant as shown by the solid line in FIG. This test apparatus 2 has the following advantages.

  First, in the test apparatus 2 of FIG. 1, a single main power supply 10 can be used to generate both sink and source compensation currents. That is, since a power supply different from the main power supply 10 is not required, the system is simplified and the cost can be reduced.

The source switch 12b and the sink switch 12c are composed of N-channel MOSFETs, and their sources are grounded. Therefore, the gate-source voltage V _GS of the MOSFET matches the voltage of the control signal S _CNT and is not easily affected by fluctuations in the power supply voltage V _DD . That is, the on-resistance of the MOSFET is not easily affected by fluctuations in the power supply voltage V _DD . If the on-resistance of the MOSFET fluctuates, the designed compensation current _ICMP cannot be generated, which causes further fluctuations in the power supply voltage V _DD . On the other hand, according to the test apparatus 2 of FIG. 1, even if the power supply voltage V _DD fluctuates, fluctuations in the compensation current _ICMP can be prevented.

  The N-channel MOSFET has an advantage that the power supply compensation circuit 12 can be downsized because the on-resistance is lower than that of the P-channel MOSFET of the same size.

Incidentally, in the power supply compensation circuit 12 in FIG. 1, constant current I _DC flowing through the source switch 12b is a useless current, there is a problem of increasing the power consumption of the main power supply 10. This problem can be reduced by the following processing.
FIG. 5 is a waveform diagram showing a control method for reducing power consumption. In the initial state, the currents Is, I _OP , and I _DD are all zero. At time t1, when it is known that the operating current of DUT1 changes, from the pattern generator PG time t0 preceding it, gradually increasing the duty ratio of the control signal _{S CNT1,} a current Is flowing through the source switch 12b the main power source 10 at possible tracking speed is increased from zero to a predetermined current I _DC. Along with this, also it increases the output current _{I DD} of the main power source 10. During this time, the compensation current _ICMP is zero.

The operation between times t1 and t2 is as described with reference to FIG. When the compensation operation is completed at time t2, the current _{I DC} flowing through the source switch 12b is wasted. Therefore, the pattern generator PG gradually decreases the duty ratio of the control signal _SCNT1 , and reduces the current Is flowing through the source switch 12b to zero at a speed that the main power supply 10 can follow.
If the control of FIG. 5 is performed, useless current (hatching) can be reduced.

(Second Embodiment)
FIG. 6 is a block diagram showing the configuration of the test apparatus 2a according to the second embodiment. Differences from the first embodiment will be described.
The power supply compensation circuit 12 includes an auxiliary power supply 12a, a capacitor Cs2 source switch 12b, and a sink switch 12c. The auxiliary power supply 12 a generates an auxiliary voltage Vx that is higher than that of the main power supply 10. In order to suppress the fluctuation of the auxiliary voltage Vx, the output terminal is provided with a smoothing capacitor Cs2. The source switch 12b is composed of a P-channel MOSFET, and is provided between the output terminal of the auxiliary power supply 12a and the power supply terminal P1 of the DUT1. The source switch 12b is turned on when a low level control signal _SCNT1 is input to its gate, and generates a pulsed source compensation current I _SRC .

The above is the configuration of the test apparatus 2a. The operation of the test apparatus 2a is the same as that of the test apparatus 2 of FIG. 1, and can suppress fluctuations in the power supply voltage V _DD .

The test apparatus 2a uses a P-channel MOSFET as the source switch 12b. This advantage becomes clear by comparison with the case where the source switch 12b is configured by an N-channel MOSFET. When the source switch 12b is composed of N channels, the power supply voltage V _DD is applied to the source of the transistor. Therefore, when the power supply voltage V _DD varies, the gate-source voltage V _GS is affected. When the gate-source voltage V _GS fluctuates, the compensation current I _SRC fluctuates and the compensation accuracy decreases, causing further fluctuation of the power supply voltage V _DD .

Here, the source current I _SRC to be supplied by the combination of the auxiliary power source 12a and the source switch 12b is smaller than the operating current I _OP to be supplied by the combination of the main power source 10 and the capacitor Cs. Therefore, if the capacitance of the capacitor Cs2 connected to the output terminal of the auxiliary power supply 12a is appropriately designed, the fluctuation of the output voltage Vx of the auxiliary power supply 12a can be made smaller than the fluctuation of the power supply voltage _VDD . When a P-channel MOSFET is used for the source switch 12b, the gate-source voltage V _GS is not easily affected by the power supply voltage V _DD , so that a stable compensation current I _SRC can be generated.

  Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and changes in the arrangement are allowed within the range not to be performed.

In the embodiment, a case has been described in which the compensation current _ICMP realizes an ideal power supply environment in which the fluctuation of the power supply voltage is zero, that is, the output impedance is zero. However, the present invention is not limited thereto. In other words, to calculate the waveform of a compensation current I _CMP to cause deliberate supply voltage variation, it may have been prescribed to control patterns S _{PTN_CMP} as its compensation current waveform is obtained. In this case, an arbitrary power supply environment can be emulated according to the control pattern _{SPTN_CMP} .

DESCRIPTION OF SYMBOLS 1 ... DUT, 2 ... Test apparatus, PG ... Pattern generator, TG ... Timing generator, FC ... Waveform shaper, 4 ... Interface circuit, DR ... Driver, 10 ... Main power supply, 12 ... Power supply compensation circuit, 12a ... Auxiliary Power supply, 12b ... source switch, 12c ... sink switch, P1 ... power supply terminal, P2 ... ground terminal, P3 ... I / O terminal.

Claims (10)

A power supply device for supplying a power supply voltage to a semiconductor device,
A main power supply for supplying power to the power supply terminal of the semiconductor device;
A source switch provided between the power supply terminal and the ground terminal, generating a current with the source switch being normally on, and a change amount of the current when the source switch is turned off by switching as the source compensation current A power compensation circuit for injecting into the power terminal of the semiconductor device;
A power supply apparatus comprising:   2. The power supply device according to claim 1, wherein the source switch is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power supply compensation circuit is:
A sink switch provided between the power supply terminal and the ground terminal; wherein the sink switch is normally off, and a current that flows when the sink switch is turned on by switching is drawn to a path different from the semiconductor device The power supply device according to claim 1, wherein: A test apparatus for testing a device under test,
A main power supply for supplying power to the power supply terminal of the device under test;
A source switch provided between the power supply terminal and the ground terminal, generating a current with the source switch being normally on, and a change amount of the current when the source switch is turned off by switching as the source compensation current A power compensation circuit that is injected into the power terminal of the device under test;
A plurality of drivers, one of which is assigned to the source switch and at least one of which is assigned to at least one input / output terminal of the device under test;
A plurality of interface circuits each provided for each of the drivers, and each of the plurality of interface circuits for shaping and outputting the input pattern signal to a corresponding driver;
A test pattern describing a test signal to be output by the driver assigned to the input / output terminal of the device under test is output to the interface circuit corresponding to the driver, and determined according to the test pattern. A pattern generator for outputting the control pattern to the interface circuit corresponding to the driver assigned to the source switch;
A test apparatus comprising:   5. The test apparatus according to claim 4, wherein the source switch is an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The power supply compensation circuit is:
It further includes a sink switch provided between the power supply terminal and the ground terminal. The sink switch is normally off, and the current that flows when the sink switch is turned on by switching is drawn to a path different from that of the device under test. The test apparatus according to claim 4, wherein the test apparatus is configured to be configured to be configured to be A power supply device for supplying a power supply voltage to a semiconductor device,
A main power supply for supplying power to the power supply terminal of the semiconductor device;
An auxiliary power source that generates a voltage higher than the output voltage of the main power source;
A capacitor connected to the output terminal of the auxiliary power source;
A source switch of a P-channel MOSFET provided between the power supply terminal of the semiconductor device and the output terminal of the auxiliary power supply, and a current flowing when the source switch is turned on by switching is defined as a source compensation current A power compensation circuit that injects into the power terminal of the device;
A power supply apparatus comprising: The power supply compensation circuit is:
8. The method according to claim 7, further comprising a sink switch provided between the power supply terminal and the ground terminal, wherein a current flowing when the sink switch is turned on by switching is drawn to a path different from the semiconductor device. The power supply device described in 1. A test apparatus for testing a device under test,
A main power supply for supplying power to the power supply terminal of the device under test;
An auxiliary power source that generates a voltage higher than the output voltage of the main power source;
A capacitor connected to the output terminal of the auxiliary power source;
A source switch of a P-channel MOSFET provided between the power supply terminal of the device under test and the output terminal of the auxiliary power supply, and a current that flows when the source switch is turned on by switching as the source compensation current A power compensation circuit that is injected into the power terminal of the device under test;
A plurality of drivers, one of which is assigned to the source switch and at least one of which is assigned to at least one input / output terminal of the device under test;
A plurality of interface circuits each provided for each of the drivers, and each of the plurality of interface circuits for shaping and outputting the input pattern signal to a corresponding driver;
A test pattern describing a test signal to be output by the driver assigned to the input / output terminal of the device under test is output to the interface circuit corresponding to the driver, and determined according to the test pattern. A pattern generator for outputting the control pattern to the interface circuit corresponding to the driver assigned to the source switch;
A test apparatus comprising: The power supply compensation circuit is:
A sink switch provided between the power supply terminal and the ground terminal is further included, and a current that flows when the sink switch is turned on by switching is drawn into a path different from the device under test. 9. The test apparatus according to 9.

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