JP2012114203A - Insulation substrate, manufacturing method thereof, and power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device using an insulation substrate which maintains service life with reliability of a heat cycle even if temperature change conditions of a heat cycle test makes the transition to more strict conditions.SOLUTION: An insulation substrate according to this invention includes a ceramic base material 202, a rear surface pattern 203a formed on a rear surface of the ceramic base material 202, and a heat sink 3 joined to the rear surface pattern 203a through solder 5 serving as a joining member. The rear surface pattern 203a has dimples 204 on a surface contacting with the solder 5.

Description

  The present invention relates to an insulating substrate, a manufacturing method thereof, and a power semiconductor device.

  As a reliability evaluation for thermal stress in a conventional power semiconductor device using an insulating substrate for general industry, for example, the power semiconductor element is not energized, the ambient environment temperature is changed, and the fatigue resistance of the solder under the insulating substrate There is a heat cycle test to confirm characteristics.

  Conventionally, in this heat cycle test, the temperature change condition was set to -40 ° C to 125 ° C, but the temperature change condition was -40 ° C to -40 ° C to cope with recent miniaturization of power semiconductor devices and adoption of high heat resistance elements. It is shifting from -40 ° C to 150 ° C from what was 125 ° C. In power semiconductor devices used in high-temperature environments, there is a problem that cracks occur early in the solder joints of power semiconductor elements and insulating substrates, preventing the required reliability life from being obtained. It was.

  Conventionally, as a measure for improving the heat cycle resistance of the solder material under the insulating substrate, the examination of the solder alloy composition excellent in maintaining the strength at high temperature and the solder for suppressing the solder crack by reducing the amount of distortion generated in the solder. Techniques such as thickening of thickness or “set patterning” as disclosed in Patent Document 1 have been adopted. However, further improvement in heat cycle resistance has been required for use in a high temperature environment.

Japanese Patent No. 3953442

  A conventional power semiconductor device includes a ceramic substrate made of AlN having a thickness of 0.3 to 0.635 mm, for example, and a surface pattern made of Cu having a thickness of 0.2 to 0.6 mm, for example, formed on the surface of the ceramic substrate. A power semiconductor element disposed on the surface pattern via solder, and further formed on the back surface of the ceramic substrate, for example, a back surface pattern made of Cu having a thickness of 0.2 to 0.6 mm, and a back surface pattern, A heat sink made of Cu having a thickness of 4 mm, for example, connected via solder, a resin case connected via a heat sink and an adhesive, and a silicone gel (or epoxy resin) filled in the resin case. .

  Here, the ceramic substrate, the surface pattern formed on the surface thereof, and the back surface pattern formed on the back surface thereof are used as the insulating substrate.

  The ceramic substrate, the front surface pattern, and the back surface pattern are bonded in advance with an Ag, Cu, Ti-based active metal brazing material, or the like.

  Since the conventional power semiconductor device is configured as described above, when the power semiconductor device is subjected to a heat cycle load, for example, the apparent linear expansion coefficient α of the insulating substrate α = 7 ppm and the linear expansion coefficient of the heat sink made of Cu material Due to the mismatch with α = 17 ppm, the solder under the substrate is distorted. As the heat cycle load is repeated, microcracks are generated in the solder under the substrate. As the crack progresses, heat dissipation of the power semiconductor element is hindered, and eventually the element is destroyed.

  Also, for the insulating substrate, in the case of the above-described high temperature load condition, for example, the linear expansion coefficient α = 4.5 ppm of the aluminum nitride (AlN) ceramic base material and the linear expansion coefficient α = 17 ppm of the Cu material of the back surface pattern. The stress concentrated on the joining end portion is further increased by the unmatching, and cracks are easily generated in the ceramic base material at the joining end portion.

  In the conventional power semiconductor device, the structural design has been made so as to satisfy the reliability guaranteed life cycle in which the temperature change condition setting of the heat cycle test is set to −40 to 125 ° C. However, as described above, the temperature change condition of the heat cycle test has been changed to −40 ° C. to 150 ° C. in order to cope with downsizing of the power semiconductor device and adoption of a high heat resistance element.

  According to the analysis, in the conventional power semiconductor device, the solder strain under the substrate under this condition increases by about 45%, and the reliability life becomes about 1/10 or less in actual evaluation as the strain increases. It turned out to be reduced.

  As described above, in the power semiconductor device using the conventional insulating substrate, there is a problem that the reliability life of the device is greatly lowered when used under a higher temperature load condition.

  The present invention has been made to solve the above problems, and an insulating substrate that can maintain the reliability life of the heat cycle even when the temperature change condition of the heat cycle test shifts to more severe conditions. An object is to provide a power semiconductor device used.

  The insulating substrate according to the present invention includes a ceramic base material, a back surface pattern formed on the back surface of the ceramic base material, the back surface pattern, and a heat sink joined via a joining member, Dimples are provided on the surface in contact with the joining member.

  In addition, a power semiconductor device according to the present invention includes the above insulating substrate, wherein the ceramic base material further includes a surface pattern facing the back surface pattern, and further includes a power semiconductor element mounted on the surface pattern. Prepare.

  Moreover, the 1st manufacturing method of the insulated substrate concerning this invention consists of (a) the process of forming a back surface pattern in the back surface of a ceramic base material, and (b) joining the said back surface pattern and a heat sink via a joining member. The step (a) includes a step of forming dimples by a pressure press method on the surface of the back surface pattern that contacts the joining member.

  Moreover, the 2nd manufacturing method of the insulated substrate concerning this invention consists of (a) the process of forming a back surface pattern in the back surface of a ceramic base material, and (b) joining the said back surface pattern and a heat sink via a joining member. The step (a) forms a dimple by forming a resist on the surface of the back surface pattern in contact with the bonding member, removing the resist after etching, and performing etching again to chamfer. Process.

  According to the insulating substrate of the present invention, the back surface pattern includes a ceramic base material, a back surface pattern formed on the back surface of the ceramic base material, the back surface pattern, and a heat sink joined via a joining member. In the surface in contact with the bonding member, by having dimples, when receiving a thermal history such as a heat cycle, the generation of cracks in the bonding member under the substrate can be suppressed, and the propagation speed of the cracks can be delayed. As a result, reliability and lifetime can be improved.

  Moreover, according to the power semiconductor device of the present invention, the power semiconductor element including the insulating substrate, the ceramic base material further including a surface pattern facing the back surface pattern, and mounted on the surface pattern In addition, when receiving a thermal history such as a heat cycle, the generation of cracks in the bonding member under the substrate can be suppressed, and the reliability and life of the power semiconductor device can be reduced by delaying the propagation speed of the cracks. Improvements can be realized.

  Moreover, according to the 1st manufacturing method of the insulated substrate concerning this invention, (a) The process of forming a back surface pattern in the back surface of a ceramic base material, (b) The said back surface pattern and a heat sink via a joining member, The step (a) includes a step of forming dimples by a pressure press method on the surface of the back surface pattern that contacts the bonding member, so that the dimple formation is performed simultaneously with the pattern punching. This makes it possible to provide an insulating substrate with extremely high mass productivity.

  Moreover, according to the 2nd manufacturing method of the insulated substrate concerning this invention, (a) The process of forming a back surface pattern in the back surface of a ceramic base material, (b) The said back surface pattern and a heat sink via a joining member, In the step (a), a dimple is formed by forming a resist on a surface of the back surface pattern in contact with the bonding member, removing the resist after etching, chamfering by performing etching again. By including the forming step, since the etching step is a normal flow, an insulating substrate that can withstand severe temperature change conditions can be obtained without the need for an additional etching apparatus.

1 is a partially cutaway cross-sectional view of an insulating substrate according to a first exemplary embodiment. 1 is a plan view of an insulating substrate according to a first embodiment. 1A is a cross-sectional view and a plan view of an insulating substrate according to a first exemplary embodiment; 1A is a cross-sectional view and a plan view of an insulating substrate according to a first exemplary embodiment; 1 is a plan view of an insulating substrate according to a first embodiment. 1A is a cross-sectional view and a plan view of an insulating substrate according to a first exemplary embodiment; 1A is a cross-sectional view and a plan view of an insulating substrate according to a first exemplary embodiment; It is a figure which shows the relationship used as the basis which performs numerical value limitation of the dimple concerning Embodiment 1. FIG. It is a figure which shows the comparison figure with a premise technique concerning Embodiment 1, and a comparison graph. 1 is a cross-sectional view of a power semiconductor device configured using an insulating substrate according to a first embodiment. 2A and 2B are a plan view and a cross-sectional view of the insulating substrate according to the first embodiment. 3 is a manufacturing flowchart in chemical etching of an insulating substrate according to the first exemplary embodiment; FIG. 3 is a cross-sectional view showing the production of the back surface pattern of the insulating substrate according to the first embodiment by a pressure press. It is sectional drawing of the power semiconductor device comprised using the insulating substrate as a premise technique. It is the top view and sectional view of an insulating substrate as a base technology.

<A. Embodiment 1>
As shown in FIG. 14, the power semiconductor device as a prerequisite technology includes, for example, a ceramic substrate 202 made of AlN having a thickness of 0.3 to 0.635 mm, a surface pattern 201 a and a surface pattern 201 b formed on the surface of the ceramic substrate 202. The surface pattern 201c, the power semiconductor element 1a disposed on the surface pattern 201a via the solder 4a, and disposed on the surface pattern 201a via the solder 4b and connected to the power semiconductor element 1a via the aluminum wire 11b Power semiconductor element 1b, electrode terminal 7 disposed on surface pattern 201b via solder 10, signal terminal 8b connected to surface pattern 201c via aluminum wire 11c, power semiconductor element 1a, And a signal terminal 8a connected via an aluminum wire 11a.

  Further, the back surface pattern 203 made of Cu having a thickness of 0.2 to 0.6 mm, for example, formed on the back surface of the ceramic substrate 202, and made of Cu having a thickness of 4 mm, for example, connected to the back surface pattern 203 via the solder 5. A heat sink 3, a resin case 6 connected to the heat sink 3 via an adhesive 9, and a silicone gel 12 (which may be an epoxy resin) filled in the resin case 6 are provided.

  Here, the ceramic substrate 202, the surface pattern 201a, the surface pattern 201b, the surface pattern 201c formed on the surface thereof, and the back surface pattern 203 formed on the back surface thereof are used as the insulating substrate 2.

  The ceramic substrate 202 and the front surface pattern 201a, the front surface pattern 201b, the front surface pattern 201c, and the back surface pattern 203 are bonded in advance with an Ag, Cu, Ti-based active metal brazing material or the like.

  Further, a control board on which electronic components for electrically controlling the power semiconductor device according to the present invention is not shown in FIG.

  FIG. 15 shows a front view (FIG. 15A), a back view (FIG. 15B), and a cross-sectional view (FIG. 15C) of an insulating substrate as a prerequisite technology.

  A surface pattern 201a and a surface pattern 201b are arranged on the ceramic substrate 202 as shown in FIG. 15A, and a back pattern 203 is arranged below the ceramic substrate 202 as shown in FIG. 15B. Looking at the cross section, the positional relationship is as shown in FIG. 15C, and the insulating substrate 2 is formed as a whole.

  Since the power semiconductor device as the base technology is configured as described above, when the power semiconductor device receives a heat cycle load, for example, the apparent linear expansion coefficient α of the insulating substrate 2 is 7 ppm, and the heat sink 3 made of a Cu material. Due to the mismatch with the linear expansion coefficient α = 17 ppm, the solder 5 under the substrate is distorted. As the repeated heat cycle load progresses, minute cracks are generated in the solder 5 under the substrate. As the crack progresses, the heat dissipation of the power semiconductor element 1a and the power semiconductor element 1b is hindered, and eventually the element is destroyed.

  For the insulating substrate 2 also, in the case of the above-described high temperature load condition, for example, the ceramic base material 202 has a linear expansion coefficient α = 4.5 ppm of aluminum nitride (AlN), and the back surface pattern 203 has a linear expansion coefficient of Cu material. By unmatching with α = 17 ppm, the stress concentrated on the joint end portion 202a further increases, and cracks are likely to occur in the ceramic substrate 202 at the joint end portion.

  Note that when the pattern material is Al, the solder strain generated in the solder 5 under the insulating substrate 2 is not much different from that when the pattern material is Cu, but the stress concentrated on the joint end portion 202a is the same when the pattern material is Cu. Compared to the case, the ceramic substrate 202 does not have to be cracked.

  In the power semiconductor device as the base technology, the structural design has been made so as to satisfy the reliability guaranteed life cycle in which the temperature change condition setting of the heat cycle test is set to −40 to 125 ° C. However, the temperature change condition of the heat cycle test has been changed from −40 ° C. to 150 ° C. in order to cope with downsizing of the power semiconductor device and adoption of a high heat resistance element.

  According to the analysis, in the power semiconductor device as the premise technology, the solder strain under the substrate under this condition is increased by about 45%, and the reliability life is about 1/10 in actual evaluation as the strain increases. It turned out that it falls below.

  As described above, a power semiconductor device using an insulating substrate as a prerequisite technology has a problem that the reliability life of the device is significantly reduced when used under a higher temperature load condition.

  In Embodiment 1 shown below, an insulating substrate and a power semiconductor device that solve the above problems are shown, and even if the temperature change condition of the heat cycle test shifts to more severe conditions, the reliability life of the heat cycle is improved. It is an object of the present invention to provide a sustainable insulating substrate and a power semiconductor device.

<A-1. Configuration>
As shown in FIG. 1, a power semiconductor device using an insulating substrate according to the present invention is formed on a ceramic substrate 202 made of, for example, AlN, Al ₂ O ₃ , or Si ₃ N _4, and on the surface of the ceramic substrate 202. And a surface pattern 201 made of, for example, Cu or Al. The surface treatment of the pattern is omitted in FIG. Here, as for the thickness of the ceramic base material 202, 0.25-1.0 mm is desirable, for example.

  Furthermore, a back surface pattern 203a made of, for example, Cu or Al, formed on the back surface of the ceramic substrate 202, and a heat sink 3 connected to the back surface pattern 203a via solder 5 as a joining member are provided. As the solder 5, lead-free or lead-containing solder can be used.

  Here, the ceramic substrate 202, the surface pattern 201 formed on the surface thereof, and the back surface pattern 203a formed on the back surface thereof are referred to as an insulating substrate 2a.

  The ceramic substrate 202, the front surface pattern 201, and the back surface pattern 203a are bonded in advance with an Ag, Cu, Ti-based active metal brazing material, or the like.

A dimple 204 having a curved surface 204d with a radius r is formed on the surface of the back pattern 203a that contacts the solder 5. Here, the dimple 204 has a back surface pattern thickness t (mm), for example,
Diameter φD = (3/5) t to (4/5) t (mm),
Radius r ≧ (3/10) t to (4/10) t (mm),
And
Depth h = (3/5) t to (4/5) t (mm),
Is ideal. This is because the analysis results shown in FIG. 8, the restriction from the difficulty of solder crack development shown in “dimple h / r and crack progress difficulty”, and the valley of the dimple 204 do not reach the ceramic substrate 202. Depending on the regulations to be.

  As shown in FIG. 8, it can be seen that as h / r (horizontal axis) of the dimple increases, the crack progress difficulty (vertical axis) becomes more difficult, and the generation of cracks can be suppressed. However, if the valley of the dimple 204 reaches the ceramic substrate 202, the solder 5 will not be joined to the valley, resulting in poor adhesion and a decrease in reliability.

  2A and 2B show the ceramic substrate 202 from the back side when the dimples 204 are intensively arranged at the four corner portions of the back pattern 203a. FIG. 2A is an enlarged view of one corner portion in FIG.

  FIGS. 3 and 4 are diagrams showing a form of forming the dimples 204 when the dimples 204 shown in FIG. 2 are intensively arranged at the four corners of the back surface pattern 203a. 3 (a) and 4 (a) are sectional views in that case, and FIGS. 3 (b) and 4 (b) are plan views in that case. As shown in FIG. 3, the dimples 204 in each corner portion may be formed in a line along the outer periphery of the back surface pattern 203a. As shown in FIG. 4, the dimples 204 in each corner portion are A plurality of rows may be formed along the outer periphery of the back pattern 203a.

  5A and 5B show ceramics in the case where the dimples 204 are intensively arranged at the four corners of the back surface pattern 203a, and the dimples 204 are also arranged at the entire outer periphery of the back surface pattern 203a. The base material 202 is shown from the back side. FIG. 5A is an enlarged view of one corner portion in FIG.

  FIGS. 6 and 7 show the case where the dimples 204 shown in FIG. 5 are intensively arranged at the four corners of the back surface pattern 203a, and the dimples 204 are also arranged at the entire outer periphery of the back surface pattern 203a. FIG. 4 is a view showing a formation mode of dimples 204. 6 (a) and 7 (a) are cross-sectional views in that case, and FIGS. 6 (b) and 7 (b) are plan views in that case. As shown in FIG. 6, the dimples 204 may be formed in one row along the outer periphery of the back surface pattern 203a. As shown in FIG. 7, the dimples 204 have a plurality of rows along the outer periphery of the back surface pattern 203a. May be formed.

<A-2. Operation>
FIG. 9 is a diagram showing a comparison (analysis result) of the solder strain under the substrate and the crack propagation path between the power semiconductor device as the prerequisite technology and the power semiconductor device according to the present invention.

  FIG. 9A shows a surface pattern 201 formed on the surface of the ceramic substrate 202, a back surface pattern 203 formed on the back surface, and the heat sink 3 connected to the back surface pattern 203 via the solder 5. ing.

  As shown in FIG. 9A, in the case of a power semiconductor device using an insulating substrate as a prerequisite technology, if the heat history of the heat cycle acts, the solder 5 near the pattern edge portion 202b of the back surface pattern 203 Solder distortion occurs intensively. Therefore, a solder crack is generated at the location by repeating the heat cycle, and the solder crack is likely to progress almost linearly along the vicinity of the back surface pattern 203. In addition, the propagation path of a crack is shown with a dotted line.

  On the other hand, in the case of the power semiconductor device using the insulating substrate of the present invention shown in FIG. 9B, the curved surface in the back surface pattern 203a by the dimple 204, the mass amount at the end, the partial increase in the solder thickness, Therefore, the solder distortion generated in the solder 5 near the back surface pattern 203a is alleviated. In addition, the propagation path of a crack is shown with a dotted line. In FIG. 9B, dimples 204 are formed in a region where a crack propagation path is formed.

  Therefore, in FIG. 9C, the peak of the solder strain is halved and the solder life is extended by about 4 times, as indicated by the solid line in the case of the base technology and the two-dot chain line in the case of the present invention.

  In addition, since the solder crack propagates along the unevenness of the dimple 204, the propagation speed of the crack is delayed, and for example, the life from the corner portion of the back surface pattern 203a to the projected portion of the power semiconductor element is extended. .

  When one insulating substrate 2 is used for the heat sink 3, solder distortion tends to be concentrated on the solder 5 at the corner portion of the back surface pattern 203 of the insulating substrate 2. In the case of using a plurality of sheets, the solder distortion of the solder 5 under the substrate on the side adjacent to the insulating substrate 2 may increase intensively due to the influence of the warp of the heat sink 3 due to repeated heat cycles. In this case, as shown in FIG. 5, the dimples 204 are intensively arranged at the four corners of the back pattern 203a, and the dimples 204 are also arranged at the entire outer periphery of the back pattern 203a. desirable.

  FIG. 10 is an overall view of a power semiconductor device using an insulating substrate according to the present invention. Although FIG. 10 shows the case where it is formed at the four corners of the back surface pattern 203a, it may be formed over the entire outer periphery.

  The power semiconductor device shown in FIG. 10 has the same structure and configuration as the power semiconductor device of FIG. 14 described above except that the insulating substrate 2a has a back surface pattern 203a on which the dimples 204 are formed. Description is omitted. In addition, the material of the back surface pattern 203a on which the front surface pattern 201a, the front surface pattern 201b, the front surface pattern 201c, and the dimple 204 are formed is the same as the Cu material or the Al material, and suppresses cracking of the solder 5 under the substrate and propagation of cracks. The effect of speed delay is obtained similarly.

  FIG. 11 shows a front view (FIG. 11A), a back view (FIG. 11B), and a cross-sectional view (FIG. 11C) of a power semiconductor device using an insulating substrate according to the present invention. Is.

  A surface pattern 201a and a surface pattern 201b are arranged on the ceramic substrate 202 as shown in FIG. 11A, and a back surface pattern 203a is arranged under the ceramic substrate 202 as shown in FIG. 11B. Looking at the cross section, the positional relationship is as shown in FIG. 11C, and the insulating substrate 2a is formed as a whole. A difference from the case shown in FIG. 15 is that dimples 204 are formed on the back surface pattern 203a.

<A-3. Manufacturing method>
FIG. 12 is a flowchart for explaining a chemical etching method for forming the dimples 204 on the back surface pattern of the insulating substrate in the power semiconductor device according to the present invention.

  In FIG. 12A, first, a front surface pattern 201 is formed on the surface of the ceramic substrate 202, and a back surface pattern 203 is formed on the back surface.

  In FIG. 12B, the resist 13 is formed in predetermined ranges of the front surface pattern 201 and the back surface pattern 203, respectively. In the resist 13, a resist opening hole 13 a is provided in advance in a portion where the dimple 204 is formed.

  In FIG. 12C, the etching process is performed in the state covered with the resist 13 described above.

  In FIG. 12D, the above-described resist 13 is removed to expose the curved surface 204c, and chemical polishing is performed.

  In FIG. 12E, the side on which the back surface pattern is formed is selected and soft etching is performed to perform chamfering (entire edge chamfering). A curved surface 204d is formed.

  The diameter φD of the dimple 204 shown in FIG. 1 is substantially determined by the resist opening hole 13a at the time of manufacture, but the radius r and depth h of the curved surface 204d are adjusted according to the conditions of chemical etching.

  After chamfering the edge portion, electroless Ni—P plating of 2 to 4 μm is applied as a surface treatment (not shown). When the material of the front surface pattern 201 and the back surface pattern 203a is Cu, it is possible to maintain the bondability between the Cu material and the solder material by inactivating the solder bonding atmosphere and reducing the pressure. There is no need for electroless Ni-P plating.

  FIG. 13 shows an example in which the dimples 204 formed on the back surface pattern 203a are formed by press working. In FIG. 13, the punch 14, the die 15, and the back surface pattern 203a having the curved surface 204d of the dimple 204 are shown.

  A back surface pattern is formed on the back surface of the ceramic substrate 202, and press working is performed using the punch 14 and the die 15. The dimple 204 is formed by this processing, and the back surface pattern and the heat sink 3 are further joined via the solder 5 (not shown).

<A-4. Effect>
According to the first embodiment of the present invention, in the insulating substrate, the ceramic base material 202, the back surface pattern 203a formed on the back surface of the ceramic base material 202, the back surface pattern 203a, and the solder 5 as the joining member are interposed. The back surface pattern 203a has dimples 204 on the surface in contact with the solder 5 so as to suppress the occurrence of cracks in the solder 5 under the substrate when receiving a thermal history such as a heat cycle. In addition, the reliability and life can be improved by delaying the propagation speed of cracks.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the back surface pattern 203a has a thickness of t = 0.2 to 0.6 mm, and the dimple 204 has a diameter of φD = (3/5). t to (4/5) tmm, depth h = (3/5) t to (4/5) tmm, and r ≧ (3/10) t to (4/10) t at the edge portion The occurrence of cracks in the solder 5 under the substrate can be further suppressed.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the dimples 204 are formed at each corner portion of the back surface pattern 203a, so that the dimple 204 is generated intensively particularly on the solder 5 below the corner portion of the substrate. It is possible to reduce the distortion and suppress the occurrence of solder cracks.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the dimple 204 is formed on the outer peripheral portion of the back surface pattern 203a, so that in addition to the distortion generated in the solder 5 below the corner portion of the substrate, the substrate The distortion which generate | occur | produces in the solder 5 under the outer peripheral part can also be reduced, and it can aim at suppression of the solder crack generation | occurrence | production from an outer peripheral part.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the back surface pattern 203a is made of Cu or Al, so that the stress generated in the ceramic base material 202 can be reduced by forming the dimple 204, The crack suppression effect of the ceramic base material 202 arises.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the back surface pattern 203a is plated on the surface in contact with the solder 5 as the bonding member, thereby improving the bondability with the solder 5 and the solder. The generation of cracks can be suppressed and the propagation speed of cracks can be delayed. Moreover, when the material of the back surface pattern 203a is Cu, plating work such as electroless Ni—P is not necessarily required by inactivating the solder bonding atmosphere and reducing the pressure.

Further, according to the first embodiment of the present invention, in the insulating substrate, the ceramic base 202 is made of AlN, Al ₂ O ₃ , or Si ₃ N ₄ , and thus receives a thermal history such as a heat cycle. In this case, the occurrence of cracks in the solder 5 under the substrate can be suppressed, and the reliability and life can be improved by delaying the propagation speed of the cracks.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the ceramic base material 202 has a thickness of 0.25 to 1.0 mm. The occurrence of cracks in the solder 5 can be suppressed, and the reliability and life can be improved by delaying the propagation speed of cracks.

  Further, according to the first embodiment of the present invention, in the insulating substrate, the solder 5 as the joining member is a lead-free or lead-containing solder material, so that cracking and crack propagation of the solder 5 under the substrate are suppressed. Longer life can be realized by speed reduction.

  Further, according to the first embodiment of the present invention, the power semiconductor device includes the above-described insulating substrate, and the ceramic base material 202 further includes a surface pattern 201 facing the back surface pattern 203a, and is provided on the surface pattern 201. By further including the mounted power semiconductor element 1a and power semiconductor element 1b, when receiving a thermal history such as a heat cycle, the occurrence of cracks in the solder 5 under the substrate can be suppressed, and the propagation speed of the cracks can be delayed. Thus, the reliability and life of the power semiconductor device can be improved.

  Further, according to the first embodiment of the present invention, in the method for manufacturing an insulating substrate, (a) a step of forming the back surface pattern 203a on the back surface of the ceramic substrate 202, and (b) the solder 5 as a joining member. A step of joining the back surface pattern 203a and the heat sink 3 to each other, and the step (a) includes a step of forming the dimples 204 by a pressure press method on the surface of the back surface pattern 203a in contact with the solder 5. The dimple 204 can be formed simultaneously with the pattern punching, and an insulating substrate with extremely high mass productivity can be provided.

  Further, according to the first embodiment of the present invention, in the method for manufacturing an insulating substrate, (a) a step of forming the back surface pattern 203a on the back surface of the ceramic substrate 202, and (b) the solder 5 as a joining member. A step of joining the back surface pattern 203a and the heat sink 3 to each other. In the step (a), a resist is formed on the surface of the back surface pattern 203a in contact with the solder 5, the resist is removed after etching, and etching is performed again. By including the step of forming the dimple 204 by chamfering, since the etching step is a normal flow, an insulating substrate that can withstand severe temperature change conditions can be obtained without adding an etching apparatus.

  In the embodiment of the present invention, the material, material, conditions for implementation, etc. of each component are also described, but these are examples and are not limited to those described.

  1a, 1b Power semiconductor element, 2, 2a Insulating substrate, 3 Heat sink, 5 Solder, 6 Resin case, 7 Electrode terminal, 8a, 8b Signal terminal, 9 Adhesive, 11a-11c Aluminum wire, 12 Silicone gel, 13 Resist, 13a Resist opening hole, 14 punches, 15 dies, 201, 201a to 201c surface pattern, 202 ceramic substrate, 202a bonding end, 202b pattern edge, 203, 203a back pattern, 204 dimple, 204c, 204d curved surface.

Claims (12)

A ceramic substrate;
A back surface pattern formed on the back surface of the ceramic substrate;
The back surface pattern, and a heat sink joined via a joining member,
The back surface pattern has dimples on the surface in contact with the joining member.
Insulating substrate. The back surface pattern has a thickness t = 0.2 to 0.6 mm,
The dimple has a diameter of φD = (3/5) t to (4/5) tmm, a depth of h = (3/5) t to (4/5) tmm, and r ≧ at the edge portion (3/10) t to (4/10) t curved surface,
The insulating substrate according to claim 1. The dimples are formed at each corner portion of the back pattern,
The insulating substrate according to claim 1 or 2. The dimple is formed on the outer periphery of the back surface pattern.
The insulating substrate according to claim 1. The back surface pattern is made of Cu or Al.
The insulating substrate according to claim 1. The back surface pattern is plated on the surface in contact with the joining member.
The insulating substrate according to claim 1. The ceramic substrate is made of AlN, Al ₂ O ₃ , or Si ₃ N ₄ .
The insulating substrate according to claim 1. The ceramic substrate has a thickness of 0.25 to 1.0 mm.
The insulating substrate according to claim 1. The joining member is a lead-free or lead-containing solder material,
The insulating substrate according to claim 1. Comprising the insulating substrate according to any one of claims 1 to 9,
The ceramic substrate further comprises a surface pattern facing the back surface pattern,
A power semiconductor element mounted on the surface pattern;
Power semiconductor device. (A) forming a back surface pattern on the back surface of the ceramic substrate;
(B) a step of bonding the back surface pattern and the heat sink via a bonding member;
The step (a) includes a step of forming dimples by a pressure press method on a surface of the back surface pattern that contacts the joining member.
Insulating substrate manufacturing method. (A) forming a back surface pattern on the back surface of the ceramic substrate;
(B) a step of bonding the back surface pattern and the heat sink via a bonding member;
The step (a) includes a step of forming a dimple by forming a resist on a surface of the back surface pattern in contact with the bonding member, removing the resist after etching, performing etching again, and chamfering.
Insulating substrate manufacturing method.

Images