JP2012110099A - Main circuit structure for power converter - Google Patents

Main circuit structure for power converter Download PDF

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JP2012110099A
JP2012110099A JP2010255895A JP2010255895A JP2012110099A JP 2012110099 A JP2012110099 A JP 2012110099A JP 2010255895 A JP2010255895 A JP 2010255895A JP 2010255895 A JP2010255895 A JP 2010255895A JP 2012110099 A JP2012110099 A JP 2012110099A
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power semiconductor
parallel
semiconductor modules
capacitors
power
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JP5678597B2 (en
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Akitake Takizawa
聡毅 滝沢
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Fuji Electric Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To laterally lengthen a stack constituting a power converter, to increase the capacity of electrolytic capacitors, to unbalance a generation loss between parallel-connected power semiconductor modules, and to reduce a surge voltage at the time of turning off.SOLUTION: By devising an arrangement of electrolytic capacitors 1-6 constituting a DC circuit part and power semiconductor modules 11-16 constituting a power conversion part as shown in a figure, the wiring inductance between the electrolytic capacitors 1, 2, and 3 and the power semiconductor modules 11, 13, and 15 and the wiring inductance between the electrolytic capacitors 4, 5, and 6 and the power semiconductor modules 12, 14, and 16, for example, are controlled to be substantially the same as each other.

Description

この発明は、直流から交流、または交流から直流に変換する電力変換器、特に直流部の大容量コンデンサと電力変換部のパワー半導体モジュールとの配置構造に関する。   The present invention relates to a power converter that converts direct current to alternating current or from alternating current to direct current, and more particularly to an arrangement structure of a large-capacity capacitor in a direct current section and a power semiconductor module in the power conversion section.

図5にこの種の一般的な例として、インバータの回路例を示す。
符号1〜6が直流回路部に設けられたコンデンサで、正側電位をPc,負側電位をNcとして、通常動作時は直流変動のない平滑化された電圧となる。一般に、本直流回路部を交流電源から構成する場合は、図示されないダイオード整流回路を介して形成することができる。ここでは、大容量化のため6並列接続の例が示され、コンデンサ1〜6には電解コンデンサが用いられることが多い。
FIG. 5 shows a circuit example of an inverter as a general example of this type.
Reference numerals 1 to 6 denote capacitors provided in the DC circuit unit, where the positive side potential is Pc and the negative side potential is Nc, which is a smoothed voltage without DC fluctuation during normal operation. In general, when the direct current circuit unit is composed of an alternating current power source, it can be formed via a diode rectifier circuit (not shown). Here, an example of six parallel connections is shown for increasing the capacity, and electrolytic capacitors are often used for the capacitors 1 to 6.

7,8は正側電位Pcに接続されたIGBTとダイオード、9,10は負側電位Ncに接続されたIGBTとダイオードで、これらが1組で1相分のパワー半導体モジュールを構成し、3台使用することで3相分の直流−交流変換回路を構成することができる。図5では大容量化のため1相分を2並列構成としているため、パワー半導体モジュールは11と12,13と14,15と16の6台で構成されている。17は3相交流負荷で、モータ(交流電動機)が代表的である。   Reference numerals 7 and 8 denote IGBTs and diodes connected to the positive potential Pc, and reference numerals 9 and 10 denote IGBTs and diodes connected to the negative potential Nc. By using the stand, a DC-AC conversion circuit for three phases can be configured. In FIG. 5, since one phase has two parallel configurations for increasing the capacity, the power semiconductor modules are composed of six units 11, 12, 13, 14, 15 and 16. Reference numeral 17 denotes a three-phase AC load, typically a motor (AC motor).

図6には、図5に対してさらに大容量化のために、パワー半導体モジュールを1相分あたり6並列構成とした回路(1相分のみ図示)を示す。
図7には、パワー半導体モジュールの外観例を示す。Pc電位に接続されるC1端子18、Nc電位に接続されるE2端子19、および交流出力に接続されるU端子(交流出力端子)20などが図示されている。
FIG. 6 shows a circuit (only one phase is shown) in which power semiconductor modules are configured in parallel for one phase in order to further increase the capacity compared to FIG.
In FIG. 7, the external appearance example of a power semiconductor module is shown. A C1 terminal 18 connected to the Pc potential, an E2 terminal 19 connected to the Nc potential, a U terminal (AC output terminal) 20 connected to the AC output, and the like are illustrated.

電解コンデンサ6台とパワー半導体モジュール6台の設置例を図8,図9に上面図として示す。
図8には6台の電解コンデンサおよびパワー半導体モジュールを、ともに横一列に並べた例を、また、図9には6台の電解コンデンサおよびパワー半導体モジュールを、2×3の配置で縦,横方向に配置した例を示す。
Examples of installation of six electrolytic capacitors and six power semiconductor modules are shown as top views in FIGS.
FIG. 8 shows an example in which six electrolytic capacitors and power semiconductor modules are arranged in a horizontal row, and FIG. 9 shows six electrolytic capacitors and power semiconductor modules in a 2 × 3 arrangement in the vertical and horizontal directions. An example of arrangement in the direction is shown.

また、図10,図11に図8,図9に対応する側面図を示す。
21,22はパワー半導体モジュール冷却用の放熱器、23,24は負側電位Ncの配線導体、25,26は正側電位Pcの配線導体をそれぞれ示す。
このような電解コンデンサとパワー半導体モジュールの設置または配置については、例えば特許文献1等に示されている。
Moreover, the side view corresponding to FIG. 8, FIG. 9 is shown to FIG. 10, FIG.
Reference numerals 21 and 22 denote power semiconductor module cooling radiators, reference numerals 23 and 24 denote negative-side potential Nc wiring conductors, and reference numerals 25 and 26 denote positive-side potential Pc wiring conductors, respectively.
The installation or arrangement of such an electrolytic capacitor and a power semiconductor module is disclosed in, for example, Patent Document 1 and the like.

特開2006−042406号公報JP 2006-042406 A

図8の構成で、パワー半導体モジュール1相分あたり6並列接続し、3相分構成した例を図12(a)に示す。図示のように18台のパワー半導体モジュールが横一列に並ぶため、横方向に極めて長くなり、これらのスタックを盤内に収容しようとすると、盤自体が非常に大型化するという問題がある。なお、図8の構成で3相分を一列に設置せずに、相毎に分けて盤内に設置すれば、盤自体を大きくせずに収容可能であるが、この場合、電解コンデンサには相毎の交流分の電流が流れるため、図12(a)のような3相一括とする方式に比べ、電解コンデンサ容量が大きくなるという問題が生じる。   FIG. 12 (a) shows an example in which the configuration of FIG. 8 is connected in parallel for 6 phases per phase of the power semiconductor module and configured for 3 phases. As shown in the figure, 18 power semiconductor modules are arranged in a horizontal row, so that they become extremely long in the horizontal direction, and there is a problem that if the stack is accommodated in the board, the board itself becomes very large. In the configuration of FIG. 8, if the three phases are not installed in a row but are installed in the board separately for each phase, the board itself can be accommodated without increasing the size. Since an alternating current for each phase flows, there arises a problem that the capacity of the electrolytic capacitor is increased as compared with the three-phase batch method as shown in FIG.

一方、図9の構成では、図12(b)のように3相一括とした場合でも、スタックが横に広がるのを回避することができるが、図14のような配線インダクタンスを考慮した等価回路図にも示されるように、電解コンデンサに近い側のパワー半導体モジュール11,13および15と、遠い側の12,14および16とでは、電解コンデンサとの物理的な距離の違いにより、両者間の配線インダクタンス値に差(L1とL1+L2)が生じることになる。なお、図8の構成では、配線インダクタンス値は全パワー半導体モジュール間でほぼ等しくL1となる。この場合の等価回路図を、図13に示す。   On the other hand, in the configuration of FIG. 9, it is possible to avoid the stack from spreading laterally even in the case of a three-phase package as shown in FIG. 12B, but an equivalent circuit taking into account the wiring inductance as shown in FIG. As shown in the figure, the power semiconductor modules 11, 13, and 15 on the side closer to the electrolytic capacitor and the terminals 12, 14, and 16 on the far side have a difference in physical distance from the electrolytic capacitor. A difference (L1 and L1 + L2) occurs in the wiring inductance value. In the configuration of FIG. 8, the wiring inductance value is almost equal L1 among all power semiconductor modules. An equivalent circuit diagram in this case is shown in FIG.

図16に、配線インダクタンス値に差がある場合の、並列接続されているパワー半導体モジュール各々の、IGBTのターンオン時の波形例を示す。なお、この場合のパワー半導体モジュールは、例えば図17のように、2並列構成であるとする。
一般に、IGBTがターンオンする際のコレクタ電流の変化率di/dtは、パワー半導体モジュールと電解コンデンサ間の配線インダクタンス値に依存する。すなわち、配線インダクタンス値の大きい方(L1+L2)のパワー半導体モジュールはdi/dtが小さくなり(図17ではIc2側)、配線インダクタンス値の小さい方(L1)のパワー半導体モジュールはdi/dtが大きくなる(図17ではIc1側)。
FIG. 16 shows a waveform example when the IGBT is turned on for each of the power semiconductor modules connected in parallel when there is a difference in the wiring inductance value. It is assumed that the power semiconductor module in this case has a two-parallel configuration as shown in FIG.
In general, the change rate di / dt of the collector current when the IGBT is turned on depends on the wiring inductance value between the power semiconductor module and the electrolytic capacitor. That is, the power semiconductor module having the larger wiring inductance value (L1 + L2) has a smaller di / dt (Ic2 side in FIG. 17), and the power semiconductor module having the smaller wiring inductance value (L1) has a larger di / dt. (Ic1 side in FIG. 17).

その結果、特に電流波形は図16のように大きく相違し、ターンオン損失(Eon=∫Vce・Icdt)にも両者間に大きな差異が発生する。また、電解コンデンサから遠い側のパワー半導体モジュールと、電解コンデンサ間は距離があるため、その配線インダクタンス値の絶対値(L1+L2)も大きくなり、ターンオフ時のサージ電圧も高くなる。
これに対し、図8の構成では、並列接続されているパワー半導体モジュール間で配線インダクタンス値はほぼ等しく、また、その値も小さい(L1)ため、ターンオン時の波形は図15のようになり、ターンオン損失はほぼ等しくなり、ターンオフ時のサージ電圧の高圧化も抑制される。
As a result, the current waveforms are particularly different as shown in FIG. 16, and there is a large difference in turn-on loss (Eon = ∫Vce · Ictt). Further, since there is a distance between the power semiconductor module far from the electrolytic capacitor and the electrolytic capacitor, the absolute value (L1 + L2) of the wiring inductance value also increases, and the surge voltage at turn-off also increases.
On the other hand, in the configuration of FIG. 8, the wiring inductance values are almost equal between the power semiconductor modules connected in parallel, and the value is small (L1), so the waveform at turn-on is as shown in FIG. The turn-on loss is substantially equal, and the surge voltage at turn-off is prevented from being increased.

以上のことから、図9の構成で、放熱器設計やIGBTのジャンクション温度設計を実施する場合は、発生損失やサージ電圧が大きくなる側のパワー半導体モジュール基準で実施する必要があるため、全体として見た場合、高い放熱能力や低熱抵抗のものが必要となり、装置の大型化やコストアップの一因ともなっている。
従って、この発明の課題は、電解コンデンサとパワー半導体モジュールとの配置に工夫を凝らすことにより、スタックの横長化,電解コンデンサの大容量化,並列接続されるパワー半導体モジュール間の発生損失のアンバランス化,ターンオフ時のサージ電圧の低圧化を図ることにある。
From the above, when implementing the radiator design and IGBT junction temperature design with the configuration of FIG. 9, it is necessary to implement on the basis of the power semiconductor module on the side where the generated loss and surge voltage increase, so as a whole When viewed, a high heat dissipation capability and a low thermal resistance are required, which contributes to an increase in size and cost of the device.
Accordingly, an object of the present invention is to devise the arrangement of the electrolytic capacitor and the power semiconductor module, thereby making the stack longer, increasing the capacity of the electrolytic capacitor, and imbalance of the generated loss between the power semiconductor modules connected in parallel. The aim is to reduce the surge voltage during turn-off and turn-off.

このような課題を解決するため、請求項1の発明では、直流回路部には大容量化のためにコンデンサを複数台並列接続するとともに、電力変換部には大容量化のためにパワー半導体素子モジュールを複数台並列接続し、直流から交流または交流から直流に変換する電力変換器において、
複数台並列接続されるコンデンサを2つに分けて対向配置し、この対向配置された各コンデンサ間に、前記パワー半導体素子モジュールを少なくとも2台対向配置し、コンデンサとパワー半導体モジュール間をそれぞれ配線することを特徴とする。
In order to solve such a problem, according to the first aspect of the present invention, a plurality of capacitors are connected in parallel to the DC circuit section for increasing the capacity, and a power semiconductor element is connected to the power conversion section for increasing the capacity. In a power converter that connects multiple modules in parallel and converts DC to AC or AC to DC,
A plurality of capacitors connected in parallel are divided and arranged opposite to each other, and at least two of the power semiconductor element modules are arranged opposite to each other between the opposed capacitors, and wiring between the capacitors and the power semiconductor modules is performed. It is characterized by that.

上記請求項1の発明においては、前記コンデンサとパワー半導体モジュールの配置を、並列接続されるパワー半導体モジュール間を対称軸として、線対称となるように配置することができ(請求項2の発明)、この請求項2の発明においては、前記パワー半導体モジュールは、その交流出力端子側が前記線対称軸に最も近くなるように配置することができる(請求項3の発明)。   In the first aspect of the invention, the capacitor and the power semiconductor module can be arranged so as to be line symmetric with respect to the power semiconductor modules connected in parallel as the axis of symmetry (invention of claim 2). In the invention of claim 2, the power semiconductor module can be arranged so that the AC output terminal side is closest to the line symmetry axis (invention of claim 3).

この発明によれば、直流部のコンデンサやパワー半導体モジュールをそれぞれ複数並列接続して大容量化を図る電力変換システムでは、スタックの横長化,電解コンデンサの大容量化,並列接続されるパワー半導体モジュール間の発生損失のアンバランス化およびターンオフサージ電圧の高圧化などを防止することができる。その結果、小型で安価な電力変換システムを構築することができる。なお、パワー半導体モジュールが2並列,6並列の場合について説明したが、4並列,8並列でも同様の効果が得られることは勿論である。   According to the present invention, in a power conversion system for increasing the capacity by connecting a plurality of capacitors and power semiconductor modules in a direct current section in parallel, the power semiconductor module is configured to have a longer stack, a larger electrolytic capacitor, and a parallel connection. It is possible to prevent unbalance of generated loss and increase of turn-off surge voltage. As a result, a small and inexpensive power conversion system can be constructed. In addition, although the case where the power semiconductor module is 2 parallel and 6 parallel was demonstrated, of course, the same effect is acquired even if it is 4 parallel and 8 parallel.

この発明の実施形態を示す構成図。The block diagram which shows embodiment of this invention. 図1に対応する等価回路図。FIG. 2 is an equivalent circuit diagram corresponding to FIG. 1. この発明の別の実施の形態を示す上面図。The top view which shows another embodiment of this invention. この発明のさらに別の実施の形態を示す上面図。The top view which shows another embodiment of this invention. 一般的なインバータ主回路の一例を示す回路図。The circuit diagram which shows an example of a general inverter main circuit. 一般的なインバータ主回路の別の例を示す回路図。The circuit diagram which shows another example of a general inverter main circuit. 一般的なパワー半導体モジュールの一例を示す外観図。The external view which shows an example of a general power semiconductor module. パワー半導体モジュールと電解コンデンサの配置例を示す上面図。The top view which shows the example of arrangement | positioning of a power semiconductor module and an electrolytic capacitor. パワー半導体モジュールと電解コンデンサの別の配置例を示す上面図。The top view which shows another example of arrangement | positioning of a power semiconductor module and an electrolytic capacitor. 図8の側面図。The side view of FIG. 図9の側面図。The side view of FIG. 図8,図9と図1との相違を対比して示す上面図。FIG. 10 is a top view showing the difference between FIG. 8 and FIG. 9 and FIG. 図8の場合の主回路等価図。The main circuit equivalent diagram in the case of FIG. 図9の場合の主回路等価図。FIG. 10 is a main circuit equivalent diagram in the case of FIG. 9. 図8の場合のターンオン波形図。FIG. 9 is a turn-on waveform diagram in the case of FIG. 8. 図9の場合のターンオン波形図。FIG. 10 is a turn-on waveform diagram in the case of FIG. 9. 図9の場合の等価回路図。The equivalent circuit diagram in the case of FIG.

図1はこの発明の実施の形態を示す構成図である。
図示のように、電解コンデンサ1,2,3と電解コンデンサ4,5,6を対向配置するとともに、各電解コンデンサに対しパワー半導体モジュール11〜16をそれぞれ対向配置して構成する。パワー半導体モジュールを6並列とする場合は、パワー半導体モジュール11〜16が図2(b)のように全て並列接続され、1相分を構成する。また、2並列とする場合は、パワー半導体モジュール11と12,13と14,15と16が図2(a)のように並列接続され(13と14,15と16は省略)、3相分を構成する。いずれの場合も、図1(a)にXで示す対称軸で対称配置される。
FIG. 1 is a block diagram showing an embodiment of the present invention.
As shown in the figure, the electrolytic capacitors 1, 2, 3 and the electrolytic capacitors 4, 5, 6 are arranged to face each other, and the power semiconductor modules 11 to 16 are arranged to face each electrolytic capacitor. When six power semiconductor modules are arranged in parallel, the power semiconductor modules 11 to 16 are all connected in parallel as shown in FIG. When two parallel circuits are used, the power semiconductor modules 11 and 12, 13 and 14, 15 and 16 are connected in parallel as shown in FIG. Configure. In either case, they are symmetrically arranged with the symmetry axis indicated by X in FIG.

図1の構成では、電解コンデンサ1,2,3とパワー半導体モジュール11,13,15間、電解コンデンサ4,5,6とパワー半導体モジュール12,14,16間の配線インダクタンス27および28がほぼ等しく(L1)なるため、各IGBTのターンオン波形は図15のように、全パワー半導体モジュールでほぼ等しくなる。また、電解コンデンサとパワー半導体モジュール間の距離も、全パワー半導体モジュールでほぼ等しくなり、図9の場合のパワー半導体モジュール12,14,16についても、低配線インダクタンス化が実現できる。さらに、図1のように構成した場合を図8や図9の場合と対比させて示す図12においては、図12(c)のように体積的にも図12(b)の場合とほぼ等しくなり、現実的な構成となる。   In the configuration of FIG. 1, the wiring inductances 27 and 28 between the electrolytic capacitors 1, 2, 3 and the power semiconductor modules 11, 13, 15 and between the electrolytic capacitors 4, 5, 6 and the power semiconductor modules 12, 14, 16 are substantially equal. Since (L1), the turn-on waveform of each IGBT is substantially equal in all power semiconductor modules as shown in FIG. Further, the distance between the electrolytic capacitor and the power semiconductor module is almost the same for all the power semiconductor modules, and a low wiring inductance can also be realized for the power semiconductor modules 12, 14, and 16 in the case of FIG. Further, in FIG. 12 showing the case of the configuration as shown in FIG. 1 in contrast with the cases of FIG. 8 and FIG. 9, the volume is almost equal to the case of FIG. 12B as in FIG. It becomes a realistic configuration.

図3,図4に別の実施の形態を示す。
図3がパワー半導体モジュール2並列構成の場合、図4が6並列構成の場合である。これらは、交流出力端子(U端子;29〜31(図3),32(図4))が中央に来るように、パワー半導体モジュールを配置したものである。これにより、並列接続されるパワー半導体モジュールの交流出力端子が互いに接近するため、配線が容易となる。
3 and 4 show another embodiment.
FIG. 3 shows the case of the power semiconductor module 2 parallel configuration, and FIG. 4 shows the case of the 6 parallel configuration. In these, the power semiconductor modules are arranged so that the AC output terminals (U terminals; 29 to 31 (FIG. 3), 32 (FIG. 4)) are in the center. Thereby, since the AC output terminals of the power semiconductor modules connected in parallel approach each other, wiring becomes easy.

以上では、電解コンデンサとパワー半導体モジュールとの配置を、中心軸に対して線対称としたが、厳密な線対称にしなくても(例えば、電解コンデンサの電極位置を図1とは反対(逆)にするなど)、対向配置される電解コンデンサ間にパワー半導体モジュールを2台以上設置する構造であれば、概ね同様の効果を得ることができる。   In the above, the arrangement of the electrolytic capacitor and the power semiconductor module is line-symmetric with respect to the central axis, but it is not necessary to be strictly line-symmetric (for example, the electrode position of the electrolytic capacitor is opposite (reverse) to FIG. 1). If the structure is such that two or more power semiconductor modules are installed between the electrolytic capacitors disposed opposite to each other, substantially the same effect can be obtained.

1〜6…電解コンデンサ、7,9…IGBT、8,10…ダイオード、11〜16…パワー半導体モジュール、17…3相負荷(モータ)、18…C1端子、19…E2端子、20…U端子、21,22…放熱器、23〜26…配線導体、27,28(L1)…配線インダクタンス、29〜32…交流出力端子。   DESCRIPTION OF SYMBOLS 1-6 ... Electrolytic capacitor, 7, 9 ... IGBT, 8, 10 ... Diode, 11-16 ... Power semiconductor module, 17 ... Three-phase load (motor), 18 ... C1 terminal, 19 ... E2 terminal, 20 ... U terminal 21, 22 ... radiator, 23 to 26 ... wiring conductor, 27 and 28 (L1) ... wiring inductance, 29 to 32 ... AC output terminal.

Claims (3)

直流回路部には大容量化のためにコンデンサを複数台並列接続するとともに、電力変換部には大容量化のためにパワー半導体素子モジュールを複数台並列接続し、直流から交流または交流から直流に変換する電力変換器において、
複数台並列接続されるコンデンサを2つに分けて対向配置し、この対向配置された各コンデンサ間に、前記パワー半導体素子モジュールを少なくとも2台対向配置し、コンデンサとパワー半導体モジュール間をそれぞれ配線することを特徴とする電力変換器の主回路構造。
A plurality of capacitors are connected in parallel to the DC circuit section to increase the capacity, and a plurality of power semiconductor element modules are connected in parallel to the power converter section to increase the capacity, from DC to AC or from AC to DC. In the power converter to convert,
A plurality of capacitors connected in parallel are divided and arranged opposite to each other, and at least two of the power semiconductor element modules are arranged opposite to each other between the opposed capacitors, and wiring between the capacitors and the power semiconductor modules is performed. The main circuit structure of the power converter characterized by the above.
前記コンデンサとパワー半導体モジュールの配置を、並列接続されるパワー半導体モジュール間を対称軸として、線対称となるように配置することを特徴とする請求項1に記載の電力変換器の主回路構造。   2. The main circuit structure of the power converter according to claim 1, wherein the capacitors and the power semiconductor modules are arranged so as to be line symmetric with respect to a power semiconductor module connected in parallel as an axis of symmetry. 前記パワー半導体モジュールは、その交流出力端子側が前記線対称軸に最も近くなるように配置することを特徴とする請求項2に記載の電力変換器の主回路構造。   The main circuit structure of the power converter according to claim 2, wherein the power semiconductor module is arranged so that the AC output terminal side is closest to the line symmetry axis.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103856068A (en) * 2012-12-04 2014-06-11 三星电子株式会社 Power conversion apparatus
EP3203625A1 (en) 2016-02-05 2017-08-09 Hitachi Ltd. Electric power conversion apparatus
JP2018198498A (en) * 2017-05-24 2018-12-13 三菱電機株式会社 Switching device
DE102019132702A1 (en) 2019-01-30 2020-07-30 Fuji Electric Co., Ltd. LIMITATION DEVICE AND POWER IMPLEMENTATION DEVICE

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001031771A1 (en) * 1999-10-27 2001-05-03 Hitachi, Ltd. Electric power converter
US20020034089A1 (en) * 2000-09-06 2002-03-21 Hitachi, Ltd. Semiconductor electric power conversion device
JP2004135444A (en) * 2002-10-11 2004-04-30 Fuji Electric Fa Components & Systems Co Ltd Stack structure of power converter
JP2006042406A (en) * 2004-07-22 2006-02-09 Fuji Electric Fa Components & Systems Co Ltd Stack structure of power converter
WO2006103721A1 (en) * 2005-03-25 2006-10-05 Mitsubishi Denki Kabushiki Kaisha Power converter cooling structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001031771A1 (en) * 1999-10-27 2001-05-03 Hitachi, Ltd. Electric power converter
US20020034089A1 (en) * 2000-09-06 2002-03-21 Hitachi, Ltd. Semiconductor electric power conversion device
JP2002084766A (en) * 2000-09-06 2002-03-22 Hitachi Ltd Semiconductor power converter
JP2004135444A (en) * 2002-10-11 2004-04-30 Fuji Electric Fa Components & Systems Co Ltd Stack structure of power converter
JP2006042406A (en) * 2004-07-22 2006-02-09 Fuji Electric Fa Components & Systems Co Ltd Stack structure of power converter
WO2006103721A1 (en) * 2005-03-25 2006-10-05 Mitsubishi Denki Kabushiki Kaisha Power converter cooling structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103856068A (en) * 2012-12-04 2014-06-11 三星电子株式会社 Power conversion apparatus
CN103856068B (en) * 2012-12-04 2018-04-13 三星电子株式会社 Power-converting device
EP3203625A1 (en) 2016-02-05 2017-08-09 Hitachi Ltd. Electric power conversion apparatus
JP2017139915A (en) * 2016-02-05 2017-08-10 株式会社日立製作所 Power conversion device
JP2018198498A (en) * 2017-05-24 2018-12-13 三菱電機株式会社 Switching device
DE102019132702A1 (en) 2019-01-30 2020-07-30 Fuji Electric Co., Ltd. LIMITATION DEVICE AND POWER IMPLEMENTATION DEVICE
US11165333B2 (en) 2019-01-30 2021-11-02 Fuji Electric Co., Ltd. Snubber device and power conversion apparatus

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