JP2012109489A - Manufacturing method of compound semiconductor optical element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a compound semiconductor optical element capable of providing excellent etching controllability.SOLUTION: A manufacturing method of a compound semiconductor optical element includes: a semiconductor layer formation step of forming a contact layer 105 containing Ga as a constituent atom on a semiconductor substrate 101 composed of a group III-V compound semiconductor, forming an etching monitor layer 106 not containing Ga as the constituent atom on the contact layer 105, and forming a cover layer 107 containing Ga as the constituent atom on the etching monitor layer; and an etching step of continuously etching the cover layer 107 and the etching monitor layer 106 via dry etching which uses a chlorine gas. The etching step controls a timing of stopping dry etching by observing whether a wavelength component of a Ga luminescence plasma is present or absent.

Description

  The present invention relates to a method for manufacturing a compound semiconductor optical device such as an optical modulator.

  Patent Document 1 describes a technique related to a method for manufacturing a semiconductor laser element. In this manufacturing method, after the mesa is covered with an insulating film, the top of the mesa is removed by dry etching. Then, the contact layer is exposed, and an electrode is formed thereon.

Patent Document 2 describes a technique related to a method for manufacturing a semiconductor device. In this manufacturing method, the insulating resin is removed by dry etching using a CF-based gas. Here, in reactive ion etching (RIE) using an F-based gas, AlF ₃ is easily generated when Al is exposed to the F-based gas. Therefore, by continuously performing RIE using a Cl-based gas, the Al fluoride is sublimated in the form of AlCl ₃ to remove impurities generated on the surface of Al.

Patent Document 3 describes a technique related to a method of manufacturing a compound semiconductor optical device. In this method, a film forming gas containing an organosilane source material and an oxygen source material is supplied, and a dielectric mask film made of a silicon compound is deposited on the compound semiconductor region by inductively coupled plasma-chemical vapor deposition. And forming a dielectric mask by forming a pattern on the dielectric mask film, and forming a mesa-shaped compound semiconductor region by performing dry etching of the compound semiconductor region using the dielectric mask. . The thickness of the dielectric mask is 1 micrometer or more. Further, a mixed gas of CH ₄ and H ₂ is supplied, and the semiconductor layer is etched by electron cyclotron resonance type reactive ion etching (ECR-RIE).

JP 2004-104073 A JP 2010-16233 A JP 2007-208134 A

  In the technique described above, the electrode is formed on the contact layer after the insulating film on the mesa is removed by dry etching. Due to this dry etching, a damaged portion is formed on the surface of the contact layer. A crystal defect is formed in the damaged portion, which causes a problem in device characteristics and reliability. Therefore, a method of removing the damaged contact layer surface portion by wet etching or chlorine dry etching has been considered.

  However, in wet etching, it is difficult to control the etching depth and the like because the etching rate varies greatly. For this reason, the thickness of the contact layer after etching becomes non-uniform for each element. Further, in wet etching, side etching proceeds, and the mesa side below the interface from the insulating film may be etched. On the other hand, even in chlorine-based dry etching, the etching rate varies greatly. Moreover, since the etching rate in chlorine-based dry etching is affected by the opening width of the insulating film, it is more difficult to accurately control the etching depth.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method of manufacturing a compound semiconductor optical device that can provide good etching controllability.

  In order to solve the above-described problem, a method for manufacturing a compound semiconductor optical device according to the present invention forms a first semiconductor layer containing Ga as a constituent atom on a semiconductor substrate made of a III-V compound semiconductor. Forming a second semiconductor layer that does not contain Ga as a constituent atom on the semiconductor layer, and forming a third semiconductor layer containing Ga as a constituent atom on the second semiconductor layer; An etching step of continuously etching the third semiconductor layer and the second semiconductor layer by dry etching using a gas, and in the etching step, by confirming the presence or absence of a wavelength component of Ga light emission plasma The timing for stopping the dry etching is controlled.

  According to this method, when the third semiconductor layer containing Ga as a constituent atom is removed, a signal component of 850 nanometers which is a wavelength component of Ga light emission plasma is confirmed, and Ga is not contained as a constituent atom. When the second semiconductor layer is removed, a signal component of 850 nanometers is not confirmed. By confirming the presence or absence of the wavelength component of the Ga light emission plasma, it is possible to accurately control the timing at which dry etching is stopped, thereby providing good controllability of etching.

  The first semiconductor layer may be made of InGaAs, the second semiconductor layer may be made of InP, and the third semiconductor layer may be made of InGaAs.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the compound semiconductor optical element which can provide the controllability of favorable etching can be provided.

It is a flowchart which shows the manufacturing method of a compound semiconductor optical element. FIG. 2A is a cross-sectional view showing one step of the method of manufacturing a compound semiconductor optical device, and FIG. 2B is a cross-sectional view showing the next step of FIG. 3A is a cross-sectional view showing the next step of FIG. 2B, and FIG. 3B is a cross-sectional view showing the next step of FIG. 4A is a cross-sectional view showing the next step of FIG. 3B, and FIG. 4B is a cross-sectional view showing the next step of FIG. FIG. 5A is a cross-sectional view showing the next step of FIG. 4B, and FIG. 5B is a cross-sectional view showing the next step of FIG. FIG. 6 is a cross-sectional view showing the next step of FIG.

  Hereinafter, embodiments of a method for producing a compound semiconductor optical device according to the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Examples of the compound semiconductor optical device manufactured by the manufacturing method of the present invention include a semiconductor laser device and an optical modulator.

A method for manufacturing a compound semiconductor optical device according to this embodiment will be described with reference to FIGS. FIG. 1 is a flowchart showing a method of manufacturing a compound semiconductor optical device according to this embodiment. 2 to 6 are cross-sectional views illustrating one step of the method for manufacturing the compound semiconductor optical device according to the present embodiment.
(Semiconductor layer formation process)

  First, as shown in FIG. 2A, a semiconductor substrate 101 for forming a plurality of semiconductor layers is prepared. As the semiconductor substrate 101, for example, an n-type InP substrate which is a III-V group compound semiconductor is used. Next, the lower cladding layer 102, the active layer 103 including a multiple quantum well structure (MQW), the upper cladding layer 104, the contact layer 105, the etching monitor layer 106, and the cover layer 107 are sequentially formed on the semiconductor substrate 101 (S11). ). In this manufacturing method, each semiconductor layer is formed by, for example, a metal organic chemical vapor deposition apparatus (OMVPE).

  Here, an n-type InP layer having a thickness of 0.3 μm, for example, is used for the lower cladding layer 102, and a semiconductor layer having a thickness of 0.3 μm made of, for example, AlGaInAs and AlInAs is used for the active layer 103. For example, a p-type InP layer having a thickness of 0.3 μm is used for the upper cladding layer 104. Further, a p-type InGaAs layer having a thickness of 0.2 μm, for example, is used for the contact layer 105, and a p-type InP having a thickness of, for example, 0.1 μm is used for the etching monitor layer 106. For example, a p-type InGaAs layer having a thickness of 0.2 μm is used for 107. Note that the contact layer 105 corresponds to a first semiconductor layer, the etching monitor layer 106 corresponds to a second semiconductor layer, and the cover layer 107 corresponds to a third semiconductor layer.

Next, as shown in FIG. 2B, a first insulating film 108 is formed using a chemical vapor deposition (CVD) apparatus (S13). For example, a SiN film, a SiO ₂ film, and a SiON film are used for the first insulating film 108. Further, the thickness of the first insulating film 108 is, for example, 0.3 micrometers. Then, a photoresist 109 is formed by photolithography. This photoresist 109 has a pattern shape corresponding to the planar shape of the mesa. Further, the thickness of the photoresist 109 is, for example, 0.5 micrometers.

Next, as shown in FIG. 3A, a part of the first insulating film 108 is removed by dry etching using CF ₄ gas (S15). This etching is performed until the etching rate is set to, for example, 0.1 micrometers per minute and the cover layer 107 is exposed. The etching time is about 3 minutes. Then, when the photoresist 109 is removed using an organic solvent, a first insulating film 108 patterned into a mesa planar shape is obtained as shown in FIG.

  Next, as shown in FIG. 4A, the mesa 51 is formed by dry etching using a chlorine-based gas using the first insulating film 108 as a mask (S17). This etching is stopped when the etching rate is set to, for example, 0.1 μm / min and the semiconductor substrate 101 is exposed. The height of the mesa 51 is, for example, 1.4 micrometers. 4A shows a state in which etching is stopped at the interface between the semiconductor substrate 101 and the lower cladding layer 102, the mesa 51 may be formed in the semiconductor substrate 101 by over-etching.

Next, the first insulating film 108 is removed by dry etching using CF ₄ gas (S18). Then, as shown in FIG. 4B, the second insulating film 110 is formed on the cover layer 107 and on the side surface of the mesa 51 using a CVD apparatus (S21). Here, for example, a SiN film, a SiO ₂ film, and a SiON film are used for the second insulating film 110. The thickness of the second insulating film 110 is, for example, 0.3 micrometers.

Next, as shown in FIG. 5A, a resist pattern 111 is formed on the second insulating film 110 by photolithography. An opening 52 is formed in a portion of the resist pattern 111 on the mesa 51. Moreover, the thickness of the resist pattern 111 is 0.5 micrometer, for example. Then, a part of the second insulating film 110 on the mesa 51 is removed by dry etching using CF ₄ gas using the resist pattern 111 as a mask (S23). In this etching, the etching rate is set to 0.1 micrometer per minute, for example. The etching time is about 5 minutes.
(Etching process)

  Next, the resist pattern 111 is removed using an organic solvent. Then, as shown in FIG. 5B, the cover layer 107, the etching monitor layer 106, and part of the contact layer 105 are formed by dry etching using a chlorine-based gas using the second insulating film 110 as a mask. It removes continuously (S25). In this etching, the etching rate is set to 0.1 micrometer per minute, for example. The etching time is about 3 minutes.

  During this etching, a device (not shown) for monitoring the luminescent plasma is used to monitor the wavelength component of Ga (wavelength 850 nm). First, since a p-type InGaAs layer is used for the cover layer 107, a signal of a Ga wavelength component can be confirmed while the cover layer 107 is being removed. Next, since the p-type InP layer is used for the etching monitor layer 106, the signal of the Ga wavelength component disappears while the etching monitor layer 106 is removed. Since the p-type InGaAs layer is used for the contact layer 105, when the contact layer 105 is exposed, the signal of the Ga wavelength component can be confirmed again. When the Ga wavelength component signal once disappears and reappears, the etching reaches the contact layer 105. Therefore, the etching is stopped when the signal of the Ga wavelength component appears again.

  Next, as shown in FIG. 6, a p-electrode 112 is formed on the second insulating film 110 by vapor deposition. The p-electrode 112 is made of, for example, an AuZn / Au alloy having a thickness of 0.1 μm. Then, the back surface of the semiconductor substrate 101 is polished to form an n-electrode 113. The n electrode 113 is made of, for example, an AuGe / Ni alloy having a thickness of 0.1 μm.

  The compound semiconductor optical device 1 is completed through the above steps. The above-described process can also be applied to the manufacture of a compound semiconductor optical device having a structure in which both sides of the mesa 51 are embedded with resin.

  Next, the effect of the manufacturing method of the compound semiconductor optical device according to the present embodiment will be described. The compound semiconductor optical device 1 manufactured according to the present embodiment does not contain Ga as a constituent atom between the contact layer 105, which is the first semiconductor layer containing Ga as a constituent atom, and the second insulating film 110. It has an etching monitor layer 106 that is a second semiconductor layer, and a cover layer 107 that is a third semiconductor layer containing Ga as a constituent atom. For this reason, when the wavelength component of the light-emitting plasma generated during dry etching is confirmed, the wavelength component of the Ga light-emitting plasma is confirmed when the cover layer 107 is removed. When the etching monitor layer 106 is removed, the wavelength component of the Ga light emission plasma is not confirmed. By confirming the presence or absence of the wavelength component of the Ga light emission plasma, it is possible to accurately know to what depth dry etching progresses in the order of the cover layer 107 and the etching monitor layer 106. This makes it possible to accurately detect that the dry etching interface has reached the contact layer 105. Therefore, according to the manufacturing method of the compound semiconductor optical device according to the present embodiment, it is possible to provide good controllability of etching.

  Further, in the dry etching (S25) when removing the cover layer 107 on which the damaged layer is formed, the timing for stopping the dry etching (S25) can be accurately controlled. Therefore, since the remaining thickness of the contact layer 105 can be controlled with high accuracy, variations in characteristics among elements can be suppressed.

  Furthermore, since it is possible to prevent an increase in element resistance due to over-etching of the contact layer 105, the element characteristics and reliability of the compound semiconductor optical element 1 can be improved.

DESCRIPTION OF SYMBOLS 1 ... Compound semiconductor optical element, 101 ... Semiconductor substrate, 105 ... Contact layer, 106 ... Etching monitor layer, 107 ... Cover layer, S11 ... Semiconductor layer formation process, S25 ... Etching process.

Claims (2)

A first semiconductor layer containing Ga as a constituent atom is formed on a semiconductor substrate made of a III-V group compound semiconductor, and a second semiconductor layer not containing Ga as a constituent atom is formed on the first semiconductor layer. A semiconductor layer forming step of forming a third semiconductor layer containing Ga as a constituent atom on the second semiconductor layer;
An etching step of continuously etching the third semiconductor layer and the second semiconductor layer by dry etching using a chlorine-based gas;
Including
In the etching step, the timing for stopping the dry etching is controlled by confirming the presence or absence of a wavelength component of Ga light emission plasma. 2. The compound semiconductor optical device according to claim 1, wherein the first semiconductor layer is made of InGaAs, the second semiconductor layer is made of InP, and the third semiconductor layer is made of InGaAs. Method.

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