JP2012104927A - Signal transmission circuit, skew correction method, and image reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal transmission circuit, a skew correction method, and an image reader, capable of adjusting a balance between the advancement and delay of skew that occurs in the data signal in various bit patterns.SOLUTION: A signal transmission circuit 100 includes a transmission part 110 and a reception part 120 which individually transmit/receive clock signal CLK and data signal DATA through a parallel signal line. The signal line through which the data signal DATA is transmitted is provided with a delay part 125 which is an extension of the signal line. The amount of delay of the delay part 125 is determined based on the average time difference between H/L toggle signal (the signal in which H and L are alternately repeated) HLT, having been received, and the clock signal CLK. By adjusting the delay amount of the delay part 125 in this manner, the balance between advancement and delay of skew that occurs in the data signal DATA of various bit patterns is adjusted, for suppressing skew correction amount as a whole.

Description

  The present invention relates to a signal transmission circuit, a skew correction method, and an image reading apparatus.

  2. Description of the Related Art In an image reading apparatus that processes high resolution image data obtained by reading an image of a document, an LVDS (Low Voltage Differential Signaling) type signal transmission circuit is provided on an internal bus or the like in order to transmit digital signals such as image data at high speed. It is used. In such a signal transmission circuit, there is a problem of an increase in skew in which the timings of the clock signal and the data signal are shifted as the data transmission rate is increased.

  In order to suppress a skew between bits of a data signal modulated into a serial signal by the LVDS method, for example, Patent Document 1 discloses a plurality of receiver circuits that perform different phase adjustments on transmitted data signals, and an input signal. There is disclosed an input buffer circuit including a pattern detection circuit that detects the length of a period during which the signal does not change, and a signal selection circuit that selects one of the outputs of the receiver circuit according to the detection result of the pattern detection circuit.

JP 2000-174609 A

  An object of the present invention is to provide a signal transmission circuit, a skew correction method, and an image reading apparatus that can adjust the balance between the advance and delay of skew generated in data signals having various bit patterns.

[1] A transmitting unit that individually transmits a clock signal and a data signal via parallel signal lines, a receiving unit that receives the clock signal and the data signal transmitted from the transmitting unit, the transmitting unit, A signal transmission circuit comprising: a delay unit capable of adjusting a delay amount provided in the signal line through which the data signal is transmitted to and from the reception unit.

[2] The signal transmission circuit according to [1], wherein the delay amount of the delay unit is determined based on an average time difference of the data signal with respect to the clock signal.

[3] The signal transmission circuit according to [1] or [2], wherein the delay unit includes an extension unit in which a length of the data signal is extended from the signal line to which the clock signal is transmitted. .

[4] A first step of measuring in advance a time difference between a clock signal and a data signal that are individually transmitted via a parallel signal line and received by a receiving unit, and the data signal based on the measured time difference A second step of adjusting a delay amount of a delay unit provided in the signal line to which a signal is transmitted, and a third step of synchronizing a clock signal received by the receiving unit and a data signal delayed through the delay unit And a skew correction method comprising:

[5] The skew according to [4], wherein in the first step, the reception unit measures the time difference by receiving a toggle signal in which a high potential and a low potential are alternately repeated as a temporary data signal. Correction method.

[6] An image reading unit that reads an image of a document, and an image reading control unit that controls the image reading unit and processes an image read by the image reading unit, and is provided in an internal bus of the image reading control unit. An image reading apparatus provided with the signal transmission circuit according to any one of [1] to [3].

  According to the first, second, fourth, and fifth aspects of the present invention, it is possible to adjust the balance between the advance and delay of the skew generated in the data signals having various bit patterns, and to suppress the skew correction amount.

  According to the third aspect of the present invention, in addition to the above effects, the delay unit can be realized with a simple configuration.

  According to the sixth aspect of the present invention, in the signal transmission circuit in the image reading control unit, it is possible to adjust the balance between the advance and delay of the skew generated in the data signals of various bit patterns, thereby suppressing the skew correction amount. be able to.

FIG. 1 is a block diagram showing a configuration of a signal transmission circuit according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a circuit configuration of the receiving unit shown in FIG. FIGS. 3A to 3D are time charts showing bit patterns of data signals in which phase lag or phase advance with respect to the clock signal is extremely generated. FIG. 4 is a diagram illustrating a waveform of the H / L toggle signal used for selecting the delay amount of the delay unit. FIG. 5A is a diagram illustrating a result of measuring the skew amount in a state where the delay amount of the delay unit is substantially zero. FIG. 5B is a diagram illustrating the result of the skew amount measured after adjusting the delay amount of the delay unit. FIG. 6 is a block diagram showing a circuit configuration of a receiving unit according to the second embodiment of the present invention. FIG. 7 is a block diagram showing a configuration of a signal transmission circuit according to the third embodiment of the present invention. FIG. 8 is a diagram showing a configuration example of an image reading apparatus according to the fourth embodiment of the present invention. FIG. 9 is a block diagram illustrating the configuration of the control system of the image reading apparatus shown in FIG.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In addition, in each figure, about the component which has the substantially same function, the same code | symbol is attached | subjected and the duplicate description is abbreviate | omitted.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a signal transmission circuit 100 according to the first embodiment of the present invention. The signal transmission circuit 100 includes a signal transmission unit 110 and a reception unit 120.

  The transmission unit 110 includes a clock source 111, a frequency division unit 112, a clock output buffer 113, a data modulation unit 114, and a data output buffer 115.

  The clock source 111 outputs a reference clock SCLK necessary for 1-bit signal transmission in one lane of the transmission line divided in parallel.

  The frequency dividing unit 112 divides the reference clock SCLK from the clock source 111 by 8 and outputs, for example, a 72 MHz clock signal CLK to the clock output buffer 113 and a shift signal obtained by shifting the phase of the reference clock SCLK for each clock. The data is output to the data modulation unit 114.

  The data modulation unit 114 sequentially assigns each bit of data to a time position obtained by shifting, for example, a 7-bit digital signal per lane by the reference clock SCLK in synchronization with the shift signal from the frequency division unit 112, thereby Is modulated into a serial data signal DATA. Then, the data modulation unit 114 outputs the modulated data signal DATA to the data output buffer 115. Here, the time length of the data signal DATA corresponds to one cycle of the clock signal CLK.

  The clock output buffer 113 differentially outputs the clock signal CLK to the clock line 131. The data output buffer 115 differentially outputs the data signal DATA to the data line 132.

  Next, the reception unit 120 includes a clock input buffer 121, a data input buffer 122, a synchronization adjustment unit 123, a data demodulation unit 124, and a delay unit 125. Here, FIG. 2 is a block diagram showing a circuit configuration of the receiving unit 120.

  The clock input buffer 121 receives the differential signal of the clock signal CLK transmitted via the clock line 131 and outputs it to the synchronization adjustment unit 123.

  The data input buffer 122 receives the data signal DATA transmitted through the data line 132 and outputs the data signal DATA to the delay unit 125.

  The synchronization adjustment unit 123 compares the phase difference between the clock signal CLK received by the clock input buffer 121 and the data signal DATA received by the data input buffer 122 and delayed through the delay unit 125, and latches based on the phase difference. The signal is output to the data demodulator 124. The data demodulator 124 forms a PLL (Phase Locked Loop) circuit together with the synchronization adjuster 123, and performs skew correction for synchronizing the clock signal CLK and the data signal DATA. Then, the data demodulator 124 demodulates, for example, 7-bit digital data by sequentially latching the bit data assigned to the time axis of the data signal DATA.

  As shown in FIG. 2, the delay unit 125 includes a data line extension including a wiring pattern meandering a plurality of times in the chip in which the receiving unit 120 is formed. The delay unit 125 is initially formed by short-circuiting (substantially the delay amount is zero), and can be adjusted in a direction in which the delay amount (delay time) increases by trimming of a laser or the like. That is, the line is trimmed longer than the clock line so that the data signal DATA is delayed by a delay amount selected by the method described below. By adjusting the delay amount of the delay unit 125, the balance between the delay and the advance phase generated in the data signal DATA of various bit patterns with respect to the clock signal CLK is adjusted, and the skew correction amount by the synchronization adjustment unit 123 is entirely suppressed. Is done.

(Adjustment method of delay amount in delay unit)
FIGS. 3A to 3D are time charts showing bit patterns in which a phase delay or a phase advance with respect to the clock signal CLK is extremely generated in the data signal DATA to which data is transmitted. In FIG. 3, a high signal position is a high potential H, and a low signal position is a low potential L (the same in FIG. 4).

  For example, FIG. 3A shows the bit pattern P1 of the data signal DATA in which the data to be latched at the rising edge of the clock signal CLK is H, and the L state continues at least 2 bits before that. The data signal DATA having such a bit pattern P1 is usually delayed from the clock signal CLK. Here, the delay time of the data signal DATA of the bit pattern P1 is Td1.

  FIG. 3B shows a bit pattern P2 of the data signal DATA in which the data to be latched at the rising edge of the clock signal CLK is L and only the previous 1 bit is H. The data signal DATA having such a bit pattern P2 usually falls faster than the clock signal CLK. Here, the advance time of the bit pattern P2 by the data signal DATA is Tl1.

  Further, FIG. 3C shows a bit pattern P3 of the data signal DATA in which the data to be latched at the rising edge of the clock signal CLK is L, and the H state lasts at least 2 bits before that. The data signal DATA having such a bit pattern P3 is usually delayed from the clock signal CLK. Here, the delay time of the bit pattern P3 due to the data signal DATA is Td2.

  FIG. 3D shows a bit pattern P4 of the data signal DATA in which the data to be latched at the rising edge of the clock signal CLK is H and only the previous 1 bit is L. The data signal DATA having such a bit pattern P4 normally rises faster than the clock signal CLK. Here, the advance time of the bit pattern P4 by the data signal DATA is Tl2.

  As described above, a time difference (phase delay or phase advance skew amount) of the data signal DATA with respect to the clock signal CLK occurs according to the bit pattern of the data signal DATA, and the amount is the bit of the data signal DATA actually sent. It depends on the pattern and transmission rate. Therefore, in the present embodiment, an average signal in the signal transmission circuit 100 is used by using the H / L toggle signal HLT having a waveform in which H and L are alternately repeated one bit at a time as shown in FIG. 4 as the dummy data signal DATA. The amount of skew (time difference) is measured in advance. Then, the delay amount in the delay unit 125 is selected based on the average skew amount.

FIG. 5A is an example of a result of measuring the skew amount in each bit pattern in a short-circuited state (substantially zero delay amount) before the delay unit 125 is adjusted. In this example, when the H / L toggle signal HLT is used, an average phase advance of about 100 psec (10 ⁻¹⁰ seconds) occurs with respect to the clock signal CLK. Further, it can be seen that a phase delay of 20 to 180 psec occurs in the case of the data signals DATA of the bit patterns P1 and P3, and a phase advance of 150 to 300 psec occurs in the case of the data signals DATA of the bit patterns P2 and P4. .

  FIG. 5B is an example of a result of measuring the skew amount after adjusting the delay amount of the delay unit 125 in the same signal transmission circuit 100. In the present embodiment, based on the measurement result before the delay unit 125 is adjusted (FIG. 5A), the average skew amount of the H / L toggle signal HLT is 100 psec as the delay amount of the delay unit 125. Selected. Note that when measuring the average value of the skew amount for adjusting the delay amount of the delay unit 125, it is desirable to sample a number that is sufficiently reliable in terms of statistics.

  The delay unit 125 adjusts the delay amount (delay time) based on the length of the data line by trimming the short-circuited portion of the meandering wiring pattern as shown in FIG. 2 with a laser or the like. By the delay unit 125 in which the delay amount is adjusted, the data signal DATA transmitted in various bit patterns is uniformly delayed by the delay time. As a result, as shown in FIG. 5B, the balance between the skew advance and the delay offset generated in the data signal DATA of each pattern is adjusted as a whole. Therefore, no matter what bit pattern of the data signal DATA is transmitted after the delay amount is adjusted, the correction amount of the skew correction performed in the subsequent synchronization adjustment unit 123 can be made smaller than in the past.

  Note that the skew amount (Td1, T11, Td2, Td2, Td2, Td2, Dd2 in the signal transmission circuit 100 using the dummy data signals DATA of the bit patterns P1 to P4 in which the phase delay or the phase advance with respect to the clock signal CLK shown in FIG. The average of Tl2) may be measured, and the average value may be selected as the delay amount of the delay unit 125.

[Second Embodiment]
FIG. 6 is a block diagram showing a circuit configuration of the receiving unit 120 according to the second embodiment of the present invention. In the second embodiment, a delay unit 126 in which a plurality of delay elements are arranged in series is provided at the output stage of the data input buffer 122.

  The delay unit 126 is initially formed in a state where all the delay elements are short-circuited (the delay amount is substantially zero), and can be adjusted in a direction in which the short-circuit portion is cut for each delay element by trimming such as a laser and the delay amount is increased. It is said that. In adjusting the delay amount of the delay unit 126, first, the H / L toggle signal HLT is received in a state where the delay amount of the delay unit 126 is substantially zero, and the time difference (advance of the H / L toggle signal HLT with respect to the clock signal CLK) Phase). Then, the average value of the time differences is selected as the delay amount of the delay unit 126.

  Next, the delay amount of the delay unit 126 is adjusted by trimming and cutting the short-circuit portions of the delay unit 126 for each delay element by the number corresponding to the selected delay amount. Similar to the first embodiment, the skew amount (Td1, Tl1) using the dummy data signals DATA of the bit patterns P1 to P4 in which the phase delay or the phase advance with respect to the clock signal CLK shown in FIG. , Td2, Tl2) may be measured, and the average value may be selected as the delay amount of the delay unit 126.

[Third Embodiment]
FIG. 7 is a block diagram showing a configuration of a signal transmission circuit 100 according to the third embodiment of the present invention. In the third embodiment, a delay unit 127 is provided in the middle of the data line 132 connecting the data output buffer 115 and the data input buffer 122.

  The delay unit 127 can be formed as, for example, a wiring provided on the data line 132 or an extension of a signal cable. Further, the delay unit 127 may be configured as a wiring pattern that can be trimmed on a chip as in the first or second embodiment. The length of the extended portion of the wiring constituting the delay unit 127 is measured by the H / L toggle signal HLT or the data signals DATA of the bit patterns P1 to P4 shown in FIG. 3 as in the first embodiment. Selected based on the average value of the skew amount (Td1, Tl1, Td2, Tl2).

[Fourth Embodiment]
FIG. 8 is a diagram showing a configuration example of the image reading apparatus 1 according to the fourth embodiment of the present invention. The image reading apparatus 1 includes a document conveying unit 2 that conveys a document 20, a front image reading unit 3 that reads an image on a front surface 20a of the document 20, and a back surface that is provided in the document conveying unit 2 and reads an image on a back surface 20b of the document 20. And an image reading unit 4.

(Original transport section)
The document transport unit 2 includes a paper feed tray 21 on which a document 20 on which an image is recorded is disposed, a paper discharge tray 22 from which the transported original 20 is discharged, and a document 20 from the paper feed tray 21 to a paper discharge tray 22. And a transport mechanism 23 for transporting to.

  The transport mechanism 23 includes a separation roll 230 that separates the originals 20 one by one from a bundle of the plurality of originals 20 disposed on the paper feed tray 21, a transport roll 231 that transports the separated originals 20, and the original 20 on the surface image. A reading roll 232 that conveys the original 20 to the reading unit 3, a guide roll 233 that guides the original 20 to the back image reading unit 4, and a discharge roll 234 that discharges the original 20 to the paper discharge tray 22.

(Surface image reading unit)
The surface image reading unit 3 includes a light source 30 that generates illumination light, a light guide 31 that guides the illumination light from the light source 30 to the first or second reading regions 3a and 3b, and illumination light from the light source 30 that is The first or third mirror 32A to 32C that reflects the reflected light reflected by the surface 20a of the document 20 in the first or second reading area 3a or 3b and the first to third mirrors 32A to 32C are guided. A reduction optical system lens 33 that collects the reflected light and a CCD (Charge Coupled Device) sensor 34 that is an example of a light receiving unit that receives the light collected by the lens 33 are provided.

  The surface image reading unit 3 includes a housing 35 that houses a light source 30, a light guide 31, first to third mirrors 32 </ b> A to 32 </ b> C, a lens 33, and a CCD sensor 34. Is provided with a document placement table 36 made of a light-transmitting member such as platen glass.

  The light source 30, the light guide 31, and the first mirror 32A are fixed to the first carriage 37A that can move in the sub-scanning direction indicated by the arrow A, and the second mirror 32B and the third mirror 32C are the second It is fixed to the carriage 37B. The second carriage 37B has a sub-movement amount of 1/2 of the first carriage 37A so that the optical path length from the document surface on the document placement table 36 to the light receiving surface of the CCD sensor 34 is always kept constant. It is configured to be movable in the scanning direction A. The first and second carriages 37A and 37B are moved in the sub-scanning direction A by a drive unit 39 including a motor (not shown) when reading an image on the surface 20a of the document 20 placed on the document placement table 36. Configured.

  First and second white reference plates 38A and 38B are provided at both ends of the first reading area 3a of the document placement table 36, and along the main scanning direction B in the vicinity of the second reading area 3b. A third white reference plate 38C is provided. As the first to third white reference plates 38A to 38C, for example, a white resin plate, a white painted metal plate, or the like can be used.

(Back side image reader)
The back image reading unit 4 includes a fixed contact type image sensor (CIS: Compact Image Sensor) 40, and a white white reference plate 49 is provided facing the image sensor 40 at a reading position where the document is conveyed. . The white reference plate 49 is a reference plate for obtaining white reference data used for image shading correction or the like. For example, a white resin plate or a metal plate painted in white can be used.

  The image sensor 40 includes a light source 41 that irradiates illumination light onto the back surface 20b of the document 20, a rod lens array 42 that collects reflected light reflected by the illumination light from the light source 41 on the back surface 20b of the document 20, and a rod lens array. The line sensor 43 which receives the reflected light condensed by 42 and a substrate 45 on which the line sensor 43 is mounted are configured.

  As the light source 41 of the image sensor 40, a plurality of LEDs (Light Emitting Diodes) arranged along the main scanning direction are used. The rod lens array 42 includes imaging lenses in which a large number of cylindrical single lenses are arranged in a line in close contact with each other in the same radial direction.

  For example, 16 to 24 sensor chips 431 are mounted on the substrate 44 in the line sensor 43. Further, for example, 304 photoelectric conversion elements 431a are formed in one sensor chip 431 by the same CMOS (Complementary Metal-Oxide Semiconductor) process.

(Control system)
FIG. 9 is a block diagram illustrating the configuration of the control system of the image reading apparatus 1. Main operation control in the image reading apparatus 1 is performed by the image reading control apparatus 10. The image reading control apparatus 10 includes a front surface image reading control unit 300 that controls driving of the front surface image reading unit 3 and reading of the front surface 20a of the document 20, and a back surface that controls reading of the back surface 20b of the document 20 by the back surface image reading unit 4. An image reading control unit 400 and a controller 500 that controls the entire image reading apparatus 1 are provided.

  The controller 500 includes an operation panel 14 that receives an operation such as an image reading instruction by a user, and a separation roll 230, a conveyance roll 231, a reading roll 232, a guide roll 233, and a discharge roll 234 according to the reading instruction. A transport mechanism driving unit 24 for driving the like is connected.

  The front surface image reading control unit 300 is connected to the light source 30 of the front surface image reading unit 3, the driving unit 39 that drives the first and second carriages 37A and 37B, and the CCD sensor 34.

  A light source 41 and a line sensor 43 provided in the image sensor 40 of the back image reading unit 4 are connected to the back image reading control unit 400.

  In the fourth embodiment, the signal transmission circuit 100 according to the first to third embodiments described above is applied to the internal buses of the front surface image reading control unit 300 and the back surface image reading control unit 400. Further, between the front surface image reading unit 3 and the front surface image reading control unit 300, between the back surface image reading unit 4 and the back surface image reading control unit 400, or between the controller 500 and the front surface image reading control unit 300 or the back surface image reading control unit. The signal transmission circuit 100 according to the first to fourth embodiments can also be applied to a data transmission system between 400 and 400.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to these embodiments, and various modifications and applications are possible without departing from the scope of the present invention. For example, the present invention can be applied to a case where data of RGB image data generated by the image reading unit is transmitted to an image processing apparatus provided outside the image reading apparatus, or a data transmission system from the image reading apparatus to the image forming apparatus.

DESCRIPTION OF SYMBOLS 1 ... Image reading apparatus, 2 ... Document conveyance part, 3 ... Front image reading part, 3a ... 1st reading area, 3b ... 2nd reading area, 4 ... Back surface image reading part, 5 ... Image forming apparatus, 5A ... Main unit, 6 ... Image forming unit, 7 ... Tray unit, 10 ... Image reading control device, 14 ... Operation panel, 17 ... Document cover, 20 ... Document, 20a ... Front side, 20b ... Back side, 21 ... Paper feed table, 22 DESCRIPTION OF SYMBOLS ... Paper discharge stand, 23 ... Conveyance mechanism, 24 ... Conveyance mechanism drive part, 30 ... Light source, 31 ... Light guide, 32A ... First mirror, 32B ... Second mirror, 32C ... Third mirror, 33 ... Lens 34... CCD sensor 35. Case 36. Document placement table 37 A First carriage 37 B Second carriage 38 A to 38 C White reference plate 39 Drive unit 40 Image sensor 41 ... light source, 42 ... rod lens array, 43 ... line Sensor 44 44 substrate 49 white reference plate 100 signal transmission circuit 110 transmission unit 111 clock source 112 frequency dividing unit 113 clock output buffer 114 data modulation unit 115 data output Buffer 120, receiving unit 121 121 clock input buffer 122 data input buffer 123 synchronization adjusting unit 124 data demodulating unit 125, 126, 127 delay unit 131 clock line 132 data line 230 ... Separation roll, 231 ... Conveying roll, 232 ... Reading roll, 233 ... Guiding roll, 234 ... Discharging roll, 300 ... Front image reading control unit, 400 ... Back image reading control unit, 431 ... Sensor chip, 431a ... Photoelectric conversion Element, 500 ... Controller, CLK ... Clock signal, DATA ... Data signal, HLT ... H / L Guru signal, P1, P2, P3, P4 ... bit pattern of the data signal, SCLK ... reference clock, Td1, Td2 ... delay time, Tl1, Tl2 ... time advance

Claims (6)

A transmission unit for individually transmitting a clock signal and a data signal via parallel signal lines;
A receiver for receiving the clock signal and the data signal transmitted from the transmitter;
A signal transmission circuit comprising: a delay unit provided in the signal line through which the data signal is transmitted between the transmission unit and the reception unit, the delay amount of which is adjustable.   The signal transmission circuit according to claim 1, wherein the delay amount of the delay unit is determined based on an average time difference of the data signal with respect to the clock signal.   The signal transmission circuit according to claim 1, wherein the delay unit includes an extension unit in which a length of the data signal is extended from the signal line to which the clock signal is transmitted. A first step of measuring in advance a time difference between a clock signal and a data signal that are individually transmitted via a parallel signal line and received by a receiving unit;
A second step of adjusting a delay amount of a delay unit provided in the signal line to which the data signal is transmitted, based on the measured time difference;
A skew correction method comprising: a third step of synchronizing a clock signal received by the receiving unit and a data signal delayed through the delay unit.   The skew correction method according to claim 4, wherein in the first step, the time difference is measured by the reception unit receiving a toggle signal in which a high potential and a low potential are alternately repeated as a temporary data signal. An image reading unit that reads an image of a document; and an image reading control unit that controls the image reading unit and processes an image read by the image reading unit;
4. An image reading apparatus in which the signal transmission circuit according to claim 1 is arranged on an internal bus of the image reading control unit.

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